Method for processing integrated circuit layout, electronic device and storage medium

Abstract

Embodiments of this disclosure provide a method, electronic device, and storage medium for processing an integrated circuit layout. The integrated circuit layout includes multiple patterns. The method includes determining a first grouped region based on the integrated circuit layout. The first grouped region includes multiple first grouped unit regions. The multiple first grouped unit regions include multiple rectangular regions covered by corresponding geometric vertices of the multiple patterns as geometric centers. The method further includes identifying regions in the integrated circuit layout not covered by the first grouped region as omitted regions. The method further includes generating multiple grouping center points based on the omitted regions. The method further includes using the multiple grouping center points to determine a second grouped region. The combination of the second grouped region and the first grouped region covers the multiple patterns of the integrated circuit layout. This method can avoid the problem of pattern omissions that occur when only the first grouped region is used to divide the integrated circuit layout into regions.

Description

Technical Field

[0001] This disclosure relates primarily to the field of integrated circuits, and more particularly to a method for processing integrated circuit layouts comprising multiple graphics, an electronic device, and a computer-readable storage medium. Background Technology

[0002] In the field of electronic design automation (EDA), integrated circuit layouts are used to describe the geometric arrangement of transistors, capacitors, resistors, and other devices, as well as multilayer interconnect structures, within a chip. As the integration density of integrated circuits continues to increase, the number of geometric shapes contained in the integrated circuit layout grows exponentially, leading to a continuous expansion of layout data and placing significant computational and storage pressure on subsequent layout verification, physical design optimization, and related data processing.

[0003] Therefore, to improve layout processing efficiency and shorten design cycles, the graphic data in the layout is appropriately simplified. However, how to ensure the integrity of layout information while reducing data processing complexity during layout simplification has become a pressing technical problem. Summary of the Invention

[0004] This disclosure provides a method, electronic device, and computer-readable storage medium for processing integrated circuit layouts that include multiple graphics.

[0005] According to a first aspect of this disclosure, a method for processing an integrated circuit layout comprising multiple graphics is provided. The method includes determining a first grouping region based on the integrated circuit layout. The first grouping region includes multiple first grouping unit regions. The multiple first grouping unit regions include multiple rectangular regions covered by corresponding geometric vertices of the multiple graphics as geometric centers. The method further includes identifying regions in the integrated circuit layout not covered by the first grouping region as missing regions. The method further includes generating multiple grouping center points based on the missing regions. The method further includes using the multiple grouping center points to determine a second grouping region. The combination of the second grouping region and the first grouping region covers the multiple graphics of the integrated circuit layout. This method effectively supplements and covers the missing regions by generating multiple grouping center points for the missing regions not covered by the first grouping region and generating the second grouping region based on the multiple grouping center points, thus avoiding the problem of graphics omission when only the first grouping region is used to divide the integrated circuit layout into regions. While ensuring complete coverage of multiple graphics in the integrated circuit layout, it achieves an optimized balance between the number of groups, grouping regularity, and grouping processing efficiency.

[0006] In some implementations of the first aspect, during the process of generating multiple group center points based on the missing region, multiple squares are generated based on the missing region, and the multiple geometric centers corresponding to the multiple squares are respectively determined as the multiple group center points.

[0007] In some implementations of the first aspect, the first grouping unit region includes a first side extending along a first direction and a second side extending along a second direction. The first direction and the second direction are perpendicular to each other in the plane where the integrated circuit layout is located. The plurality of patterns includes a first pattern. The first pattern includes a third side extending along the first direction and a fourth side extending along the second direction. The plurality of squares includes at least one of a first square and a second square. In the process of generating the plurality of squares based on the missing region, if the length of the third side is greater than the length of the first side, a first square is generated within the first pattern, and / or if the length of the fourth side is greater than the length of the second side, a second square is generated within the first pattern.

[0008] In some implementations of the first aspect, the second grouping region includes a first supplementary grouping region and a second supplementary grouping region. The plurality of squares also includes a third square. During the generation of the plurality of squares based on the missing regions, the first supplementary grouping region is generated based on at least one of the first square and the second square. The first supplementary grouping region includes a plurality of second grouping unit regions. The first square or the second square has the same geometric center as the corresponding second grouping unit region. The second grouping unit regions have the same dimensions as the first grouping unit regions. During the generation of the plurality of squares based on the missing regions, the region in the missing regions not covered by the first supplementary grouping region is determined as an intermediate missing region, and the third square is generated based on the intermediate missing region.

[0009] In some implementations of the first aspect, during the process of generating the third square based on the intermediate missing region, a layout boundary rectangle is generated based on the integrated circuit layout. The layout boundary rectangle is the smallest rectangle covering the integrated circuit layout. During the process of generating the third square based on the intermediate missing region, multiple cutting lines are used to divide the layout boundary rectangle into multiple segmented regions, and the third square is determined based on at least one of these segmented regions.

[0010] In some implementations of the first aspect, during the process of dividing a layout boundary rectangle into multiple segmented regions using multiple cutting lines, starting from a vertex of the layout boundary rectangle, multiple first cutting lines are generated along a first direction with a first spacing, and multiple second cutting lines are generated along a second direction with a second spacing, thereby dividing the layout boundary rectangle into multiple segmented regions. The line width of either the first or second cutting line is equal to the side length of one of the multiple squares. The first spacing is equal to the length of the first side. The second spacing is equal to the length of the second side. The first cutting line extends along the second direction, and the second cutting line extends along the first direction.

[0011] In some implementations of the first aspect, in the process of determining the third square based on at least one of the plurality of segmented regions, the center position of the segmented region covering at least a portion of the intermediate missing region within the layout boundary rectangle is determined, and the third square is generated using the center position as the geometric center.

[0012] In some implementations of the first aspect, if the length of the third side is greater than the length of the first side, the process of generating the first square within the first pattern includes generating a layout boundary rectangle based on the integrated circuit layout. The layout boundary rectangle is the smallest rectangle covering the integrated circuit layout. If the length of the third side is greater than the length of the first side, the process of generating the first square within the first pattern also includes dividing the layout boundary rectangle using multiple cutting lines, and determining the first square based on these multiple cutting lines.

[0013] In some implementations of the first aspect, during the process of dividing the layout boundary rectangle using multiple cutting lines, starting from a vertex of the layout boundary rectangle, multiple first cutting lines are generated along a first direction with a first spacing to divide the layout boundary rectangle. The line width of the first cutting line is equal to the side length of one of the multiple squares. The first spacing is equal to the length of the first side. The first cutting lines extend along a second direction.

[0014] In some implementations of the first aspect, during the process of determining the first square based on the plurality of cutting lines, a first rectangle with a predetermined width is generated within the first shape, based on the fact that the length of the third side is greater than the length of the first side. This predetermined value is equal to the side length of the square among the plurality of squares. During the process of determining the first square based on the plurality of cutting lines, the first square is determined based on multiple intersection areas between the first rectangle and the plurality of first cutting lines.

[0015] In some implementations of the first aspect, in the process of determining the first square based on multiple intersection regions of the first rectangle and multiple first cutting lines, the first square is determined based on the intersection region covered by the omitted region among the multiple intersection regions.

[0016] In some implementations of the first aspect, if the length of the fourth side is greater than the length of the second side, the process of generating a second square within the first pattern includes generating a layout boundary rectangle based on the integrated circuit layout. The layout boundary rectangle is the smallest rectangle covering the integrated circuit layout. If the length of the fourth side is greater than the length of the second side, the process of generating a second square within the first pattern also includes dividing the layout boundary rectangle using multiple cutting lines, and determining the second square based on these multiple cutting lines.

[0017] In some implementations of the first aspect, during the process of dividing the layout boundary rectangle using multiple cutting lines, multiple second cutting lines are generated along a second direction with a second spacing, starting from a vertex of the layout boundary rectangle, to divide the layout boundary rectangle. The line width of the second cutting line is equal to the side length of one of the multiple squares. The second spacing is equal to the length of the second side. The second cutting lines extend along the first direction.

[0018] In some implementations of the first aspect, during the process of determining the second square based on the plurality of cutting lines, a second rectangle with a predetermined width is generated within the first shape, based on the fact that the length of the fourth side is greater than the length of the second side. This predetermined value is equal to the side length of the square among the plurality of squares. During the process of determining the second square based on the plurality of cutting lines, the second square is determined based on multiple intersection areas between the second rectangle and the second cutting lines.

[0019] In some implementations of the first aspect, in the process of determining the second square based on multiple intersection regions of the second rectangle and the second cutting line, the second square is determined based on the intersection region covered by the omitted region among the multiple intersection regions.

[0020] According to a second aspect of this disclosure, an electronic device is provided. The electronic device includes a storage device and at least one processor. The storage device is coupled to the at least one processor and has instructions stored thereon that, when executed by the at least one processor, cause the electronic device to perform the method according to the first aspect of this disclosure.

[0021] According to a third aspect of this disclosure, a computer-readable storage medium is provided on which a computer program is stored. When executed by a processor, the program implements the method described according to a first aspect of this disclosure.

[0022] It is understood that the electronic device of the second aspect and the computer-readable storage medium of the third aspect provided above have the same beneficial effects as the method of the first aspect. Therefore, the explanations or descriptions of the first aspect also apply to the second and third aspects. Attached Figure Description

[0023] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements.

[0024] Figure 1 An exemplary flowchart of a method for processing an integrated circuit layout including multiple patterns according to an embodiment of the present disclosure is shown.

[0025] Figure 2A An exemplary schematic diagram of an integrated circuit layout according to an embodiment of the present disclosure is shown.

[0026] Figure 2B An exemplary schematic diagram of determining a first grouping region according to an embodiment of the present disclosure is shown.

[0027] Figure 3 An exemplary schematic diagram illustrating the determination of a missing region according to an embodiment of the present disclosure is shown.

[0028] Figure 4 An exemplary schematic diagram of a generated layout boundary rectangle according to an embodiment of the present disclosure is shown.

[0029] Figures 5A to 5D An exemplary schematic diagram is shown illustrating the division of a layout boundary rectangle into multiple segmented regions according to an embodiment of the present disclosure.

[0030] Figures 6A to 6E An exemplary schematic diagram of generating a first square and a second square according to an embodiment of the present disclosure is shown.

[0031] Figure 7 An exemplary schematic diagram illustrating the determination of a first supplementary grouping region according to an embodiment of the present disclosure is shown.

[0032] Figure 8 An exemplary schematic diagram illustrating the determination of intermediate missing regions according to embodiments of the present disclosure is shown.

[0033] Figure 9 An exemplary schematic diagram illustrating the determination of a second supplementary grouping region according to an embodiment of the present disclosure is shown.

[0034] Figure 10 An exemplary block diagram of an apparatus for processing an integrated circuit layout including multiple patterns, according to an embodiment of the present disclosure, is shown.

[0035] Figure 11 A schematic block diagram of an electronic device suitable for implementing embodiments of the present disclosure is shown. Detailed Implementation

[0036] The technical solutions of this disclosure will now be described with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of this disclosure, and not all embodiments.

[0037] The technical solutions of the embodiments of this disclosure will now be described with reference to the accompanying drawings. In the description of the embodiments of this disclosure, unless otherwise stated, " / " signifies "and / or," for example, A / B can mean A or B, or A and B. "And / or" in this text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, in the description of the embodiments of this disclosure, "plural" or "multiple" refers to two or more than two.

[0038] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature.

[0039] The terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. As used in the specification and appended claims of this disclosure, the singular expressions “a,” “an,” “the,” “the,” “the,” and “this” are intended to also include expressions such as “one or more,” unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this disclosure, “at least one,” “one or more” means one, two, or more than two.

[0040] References to "one embodiment" or "some embodiments" as used in this specification mean that one or more embodiments of this disclosure include a particular feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "one embodiment," "some embodiments," "another embodiment," "other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0041] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of this specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise expressly defined herein. Numbers or numerical values ​​used in this specification are illustrative and intended only to facilitate understanding of the techniques of embodiments of this disclosure, and are in no way intended to limit the scope of this disclosure.

[0042] To reduce the data size of integrated circuit layouts and improve subsequent processing efficiency, the layout can be simplified. One such simplification method involves using the geometric vertices of each graphic in the layout as center points, dividing it into multiple regions based on these center points, merging and grouping these regions, and finally selecting representative graphics from each group for analysis. This method can reduce the amount of layout data while preserving key geometric features, thereby improving layout processing efficiency.

[0043] However, in actual integrated circuit design, integrated circuit layouts contain a large number of elongated shapes with high aspect ratios. Since the geometric vertices of these elongated shapes are usually only located at both ends, the regions generated based on these vertices are insufficient to cover the entire area of ​​the elongated shape, resulting in some regions not being assigned to their corresponding groupings. These uncovered areas may be missed during integrated circuit layout simplification, leading to lost layout information and potentially affecting subsequent design analysis, such as causing deviations in electrical characteristic characterization or inaccurate parasitic parameter extraction. Therefore, to address the problem of missing regions due to special geometric shapes in the layout, a layout processing method is needed to identify and supplement these missing regions, thereby reducing the complexity of layout data processing while ensuring the integrity of layout information and the reliability of processing results.

[0044] To this end, this disclosure provides a method for processing an integrated circuit layout comprising multiple patterns. The method includes determining a first grouped region based on the integrated circuit layout. The first grouped region includes multiple first grouped unit regions. The multiple first grouped unit regions include multiple rectangular regions covered by corresponding geometric vertices of the multiple patterns as geometric centers. The method further includes determining regions in the integrated circuit layout not covered by the first grouped region as missing regions. The method further includes generating multiple grouping center points based on the missing regions. The method further includes using the multiple grouping center points to determine a second grouped region. The combination of the second grouped region and the first grouped region covers the multiple patterns of the integrated circuit layout.

[0045] This method generates multiple group center points for missing areas not covered by the first group region, and then generates a second group region based on these multiple group center points. This effectively supplements and covers the missing areas, avoiding the graphic omission problem that occurs when only the first group region is used to divide the integrated circuit layout. While ensuring complete coverage of multiple graphics in the integrated circuit layout, it achieves an optimized balance between the number of groups, group regularity, and group processing efficiency.

[0046] Various embodiments of this disclosure will now be described in further detail with reference to the accompanying drawings. Figure 1 An exemplary flowchart of a method 100 for processing an integrated circuit layout including multiple patterns according to an embodiment of the present disclosure is shown. This method can be performed by an apparatus for processing an integrated circuit layout including multiple patterns. The apparatus can be an EDA apparatus with layout processing capabilities, such as an EDA tool for performing operations such as layout analysis, layout simplification, or layout verification. In the following description, method 100 is executor-specifically described using an EDA apparatus as the execution subject.

[0047] At box 102, the EDA device determines a first grouping region based on the integrated circuit layout. The first grouping region includes multiple first grouping unit regions. These multiple first grouping unit regions include multiple rectangular regions covered by corresponding geometric vertices of the multiple patterns as geometric centers.

[0048] At box 104, the EDA device identifies the area in the integrated circuit layout that is not covered by the first grouped area as the missing area.

[0049] At box 106, the EDA device generates multiple grouping center points based on the missing regions.

[0050] At box 108, the EDA device uses multiple group center points to determine the second group region. The combination of the second group region and the first group region covers multiple patterns of the integrated circuit layout.

[0051] Figure 2A An exemplary schematic diagram of an integrated circuit layout 200 according to an embodiment of the present disclosure is shown. Figure 2A As shown, the integrated circuit layout 200 may include a plurality of patterns, such as patterns 201 to 213. In some embodiments, at least one of the plurality of patterns may have a rectangular shape. For ease of illustration, Figure 2AThe illustration uses figures 201 to 213 as an example, all of which are rectangles. For example, any one of figures 201 to 213 may include a side extending in a first direction (i.e., the x-direction) and a side extending in a second direction (i.e., the y-direction). The first and second directions are perpendicular to each other. For example, the first and second directions are perpendicular to each other in the plane containing the integrated circuit layout 200. For example, the first and second directions are perpendicular to each other in the xy plane. However, it should be understood that the figures included in the integrated circuit layout 200 of the embodiments of this disclosure are not limited to rectangular shapes, and the number of such figures is not limited. These figures may also have other geometric shapes, such as polygons, figures with irregular boundaries, or figures formed by combining multiple geometric figures.

[0052] In some embodiments, patterns 201 to 213 in the integrated circuit layout 200 can represent various layout structures in the integrated circuit design, such as active regions, gate structures, metal interconnect structures, via structures, or other geometric patterns used to define the structure and interconnection relationships of semiconductor devices. Patterns 201 to 213 can be subsequently processed based on their location, size, shape, or other geometric features, such as region partitioning, grouping, analysis, or simplification.

[0053] Figure 2B An exemplary schematic diagram illustrating the determination of a first grouping region according to an embodiment of the present disclosure is shown. Figure 2B As shown, multiple rectangular regions are generated, each covering a corresponding geometric vertex of shapes 201 to 213 as its geometric center. For example, multiple rectangular regions are generated, each covering all geometric vertices of each shape in shapes 201 to 213 as its geometric center. Here, a geometric vertex can refer to the vertices that form the boundary of a shape. For example, for a rectangular shape, a geometric vertex can refer to the four corner points of the rectangle; that is, a rectangle includes four geometric vertices. Figure 2B As shown, four corresponding first grouping unit regions A1 can be generated based on the four geometric vertices of each of the figures 201 to 213. For example, the first grouping unit region A1 can be a rectangular region. Each first grouping unit region A1 can include a first side extending along the x-direction and a second side extending along the y-direction. For example, the length of the first side can be wx, and the length of the second side can be wy. Figure 2B As shown, the region covered by all the first grouping unit regions A1 generated by all the geometric vertices in Figures 201 to 213 in the xy plane can be regarded as the first grouping region.

[0054] Figure 3 An exemplary schematic diagram of determining the missing region A2 according to an embodiment of the present disclosure is shown. Figure 3As shown, the region in the integrated circuit layout 200 not covered by the first group region is identified as the missing region A2. For example, the regions in patterns 201 to 213 not covered by the first group region are identified as missing regions A2. The process of determining the second group region based on the missing region A2 will be further described below. The combination of the second group region and the first group region can cover patterns 201 to 213 of the integrated circuit layout 200.

[0055] Figure 4 An exemplary schematic diagram of a generated layout boundary rectangle B1 according to an embodiment of the present disclosure is shown. Figure 4 As shown, a layout boundary rectangle B1 is generated based on the integrated circuit layout 200. For example, the layout boundary rectangle B1 can be the smallest rectangle covering the integrated circuit layout 200.

[0056] Figures 5A to 5D An exemplary schematic diagram is shown illustrating the division of a layout boundary rectangle B1 into multiple segmented regions according to an embodiment of the present disclosure. Figure 5A As shown, the layout boundary rectangle B1 includes a first vertex C1, a second vertex C2, a third vertex C3, and a fourth vertex C4. The first vertex C1, the second vertex C2, the third vertex C3, and the fourth vertex C4 are located at the lower left, lower right, upper right, and upper left corners of the layout boundary rectangle B1, respectively. As an example, the layout boundary rectangle B1 can be divided using multiple cutting lines. For instance, multiple cutting lines can be used to divide the layout boundary rectangle B1 into multiple segmented regions. Figure 5A As shown, the multiple cutting lines may include one or more first cutting lines and one or more second cutting lines. For example, starting from a vertex of the layout boundary rectangle B1, multiple first cutting lines are generated along the x-direction at a first spacing, and multiple second cutting lines are generated along the y-direction at a second spacing, to divide the layout boundary rectangle B1 into multiple segmented regions. The embodiments of this disclosure illustrate the case where the layout boundary rectangle B1 is divided into multiple segmented regions based on a first vertex C1. Figure 5A As shown, starting from the first vertex C1 of the layout boundary rectangle B1, multiple first cutting lines L1 are generated along the x-direction from left to right at a first spacing, and multiple second cutting lines L2 are generated along the y-direction from bottom to top at a second spacing, thereby dividing the layout boundary rectangle B1 into multiple segmented regions. It should be understood that dividing the layout boundary rectangle B1 based on the second vertex C2, the third vertex C3, or the fourth vertex C4 to obtain multiple segmented regions is similar to the case based on the first vertex C1, and will not be elaborated further in this disclosure.

[0057] Figure 5BAn embodiment according to this disclosure is shown. Figure 5A An enlarged view of region A3 in the diagram. (See attached image.) Figure 5B As shown, either the first cutting line L1 or the second cutting line L2 has a predetermined linewidth. Here, the predetermined linewidth can refer to the width of the cutting line in the xy plane along a direction perpendicular to its extension direction. For example, the predetermined linewidth can be in the range of 1 nm to 5 nm, including endpoints. The first spacing can be equal to the length of the first side of the first grouping unit region A1. The second spacing can be equal to the length of the second side of the first grouping unit region A1. The first cutting line L1 extends along the y-direction, and the second cutting line L2 extends along the x-direction. Here, the spacing between the two cutting lines refers to the distance between the two center lines corresponding to the two cutting lines. The center line refers to a virtual line located at the middle of the cutting line in the width direction and extending along the extension direction of the cutting line.

[0058] Figure 5C An exemplary schematic diagram is shown showing a layout boundary rectangle B1 divided into multiple segmented regions according to an embodiment of the present disclosure. Figure 5C As shown, the difference between the layout boundary rectangle B1 and the area covered by cutting lines L1 and L2 is used to generate multiple segmented regions A4. For example, multiple spaced-apart segmented regions A4 can be obtained by removing the area covered by cutting lines L1 and L2 from the area covered by the layout boundary rectangle B1. Figure 5D An embodiment according to this disclosure is shown. Figure 5C An enlarged view of region A5 in the diagram. (See attached image.) Figure 5D As shown, the spacing between adjacent edges of adjacent segmented regions A4 in region A5 is the line width of the cutting line. Because the size of the layout boundary rectangle B1 may not be equally divided by the predetermined spacing between the cutting lines (i.e., the first spacing and / or the second spacing), the area covered by segmented region A4 located at a portion of the boundary of the layout boundary rectangle B1 may be smaller than the area covered by other segmented regions A4. For example, as... Figure 5C As shown, the area covered by the segmented region A4 at the right and top boundaries of the map boundary rectangle B1 is smaller than the area covered by other segmented regions A4 within the map boundary rectangle B1.

[0059] Figures 6A to 6EAn exemplary schematic diagram illustrating the generation of a first square and a second square according to embodiments of the present disclosure is shown. Any of the graphics 201 to 213 may include a side extending along the x-direction (also referred to as a third side) and a side extending along the y-direction (also referred to as a fourth side). In some embodiments, if the length of the third side of a graphic in graphics 201 to 213 is greater than the length of the first side of the first grouping unit region A1, a first rectangle with a predetermined width is generated within that graphic. For example, based on the fact that the length of the third side of a graphic in graphics 201 to 213 is greater than the length of the first side of the first grouping unit region A1, a first rectangle is generated within that graphic along the third side, the first rectangle having a width equal to the line width of a cutting line in a direction perpendicular to the extension direction of the third side. For example, the side of the first rectangle extending along the third side may overlap with the third side. Figure 6B An embodiment according to this disclosure is shown. Figure 6A Enlarged schematic diagrams of regions A6, A7, and A8 in the diagram. One or more first rectangles can be generated within the integrated circuit layout 200. For example... Figure 6B As shown, the rectangle indicated by label R1 (i.e., the black rectangle) can be a part of the first rectangle within region A6.

[0060] In some embodiments, if the length of the fourth side of a graphic in graphics 201 to 213 is greater than the length of the second side of the first grouping unit region A1, a second rectangle with a predetermined width is generated within that graphic. For example, based on the fact that the length of the fourth side of a graphic in graphics 201 to 213 is greater than the length of the second side of the first grouping unit region A1, a second rectangle is generated within that graphic along the fourth side, and this second rectangle has a width equal to the line width of the cutting line in a direction perpendicular to the extension direction of the fourth side. For example, the side of the second rectangle extending along the fourth side may overlap with the fourth side. One or more second rectangles may be generated within the integrated circuit layout 200. Figure 6B As shown, the rectangle indicated by label R2 (i.e., the black rectangle) can be a part of the second rectangle within region A7 or region A8.

[0061] In some embodiments, such as Figure 6C As shown, one or more first squares can be determined based on multiple cutting lines. For example, a first square can be determined based on multiple intersection regions of a first rectangle and multiple first cutting lines L1. For example, the intersection regions of the first rectangle and the first cutting lines L1 may include multiple squares. For example, one of these multiple squares can be referred to as the first square. A first square can also be determined based on the intersection region covered by the omitted region A2 among the multiple intersection regions (i.e., multiple square regions) of the first rectangle and the first cutting lines L1. For example, the intersection region covered by the omitted region A2 among the multiple intersection regions of the first rectangle and the first cutting lines L1 is referred to as the first square. Figure 6D An embodiment according to this disclosure is shown. Figure 6C Enlarged schematic diagrams of regions A9 and A10 in the image. Figure 6D As shown, the rectangle indicated by label S1 (i.e., the white rectangle) can be the first square. Figure 6C As shown, one or more second squares can be determined based on multiple cutting lines. For example, a second square can be determined based on multiple intersection regions of a second rectangle and multiple second cutting lines L2. For example, the intersection regions of the second rectangle and the second cutting lines L2 can include multiple squares. For example, one of these multiple squares can be referred to as the second square. A second square can also be determined based on the intersection region covered by the omitted region A2 among the multiple intersection regions (i.e., multiple square regions) of the second rectangle and the second cutting lines L2. For example, the intersection region covered by the omitted region A2 among the multiple intersection regions of the second rectangle and the second cutting lines L2 is referred to as the second square. Figure 6D As shown, the rectangle indicated by label S2 (i.e., the white rectangle) can be a second square.

[0062] Figure 6E An exemplary schematic diagram of a first square and a second square of an integrated circuit layout 200 according to an embodiment of the present disclosure is shown. Figure 6E As shown, an "×" can indicate a first square or a second square formed by the intersection of the cutting line and the first rectangle and the second rectangle. For example, an "×" can indicate a square formed by the intersection of the cutting line and the first rectangle or the second rectangle.

[0063] In some embodiments, the second grouping area may include a first supplementary grouping area. Figure 7 An exemplary schematic diagram illustrating the determination of a first supplementary grouping region according to embodiments of the present disclosure is shown. In some embodiments, the first supplementary grouping region is generated based on at least one of a first square and a second square. The first supplementary grouping region includes a plurality of second grouping unit regions A11. For example, a corresponding second grouping unit region A11 is generated based on each first square in the integrated circuit layout 200. A corresponding second grouping unit region A11 is generated based on each second square in the integrated circuit layout 200. Figure 7As shown, the first supplementary grouping region can be the area jointly covered by the second grouping unit region A11 generated by all the first squares and the second grouping unit region A11 generated by all the second squares. The first square or the second square has the same geometric center as the corresponding second grouping unit region A11. For example, the second grouping unit region A11 can have the same size as the first grouping unit region A1. For example, each second grouping unit region A11 can include a side extending along the x-direction and a side extending along the y-direction. For example, the length of the side extending along the x-direction of the second grouping unit region A11 can be wx, and the length of the side extending along the y-direction of the second grouping unit region A11 can be wy.

[0064] In some embodiments, the second grouping region may further include a second supplementary grouping region. The process for determining the second supplementary grouping region will be further described below. Figure 8 An exemplary schematic diagram of determining the intermediate missing region A12 according to an embodiment of the present disclosure is shown. Figure 8 As shown, the area in the missing area A2 that is not covered by the first supplementary grouping area is determined as the intermediate missing area A12. Figure 9 An exemplary schematic diagram illustrating the determination of a second supplementary grouping region according to an embodiment of the present disclosure is shown. As an example, one or more third squares can be determined based on a plurality of segmented regions A4 of the layout boundary rectangle B1. For example, one or more third squares can be determined based on at least one of the plurality of segmented regions A4. The center position of the segmented region A4 in the layout boundary rectangle B1 that covers at least a portion of the intermediate missing region A12 is determined. Figure 9 As shown, there are four segmented regions A4 within the bounding rectangle B1 that cover at least a portion of the missing intermediate region A12, and at least a portion of each of these four segmented regions A4 overlaps with the missing intermediate region A12. For example, the area commonly covered by these four segmented regions A4 could be a second supplementary grouping region. A third square is generated using the center position (i.e., geometric center) of each segmented region A4 that covers at least a portion of the missing intermediate region A12 as its geometric center. Figure 9 An "×" symbol in the diagram can indicate a third square. The third square can have the same dimensions as the first or second square. For example, the third square can include sides extending in the x-direction and sides extending in the y-direction.

[0065] In some embodiments, the geometric centers corresponding to all the first squares, all the second squares, and all the third squares generated based on the missing region A2 are respectively determined as multiple grouping center points. For example, the geometric center corresponding to each of the first squares, all the second squares, and all the third squares is determined as a grouping center point to obtain multiple grouping center points. These multiple grouping center points are used to determine a second grouping region. For example, the second grouping region may be the region jointly covered by the first supplementary grouping region and the second supplementary grouping region.

[0066] It should be understood that although the embodiments of this disclosure illustrate examples of generating a first square, a second square, and a third square based on the omitted region A2, the embodiments of this disclosure are not limited thereto. In some embodiments, depending on the specific circumstances of the omitted region A2, only one or more of the first square, the second square, and the third square may be generated. For example, the number and type of squares generated based on the omitted region A2 may be determined based on the number, size, and shape of images in the actual integrated circuit layout. For example, only at least one of the first square and the second square may be generated based on the omitted region A2. For example, any one of the first square, the second square, and the third square may have the same side length. This side length is equal to the line width of either the first cutting line L1 or the second cutting line L2.

[0067] This disclosure processes long-side regions (i.e., graphic regions corresponding to long sides) in the integrated circuit layout 200 that exceed a predetermined length by regularly generating group center points. The generated candidate group center points are then intersected with the missing regions to obtain valid group center points located within the actual missing regions, effectively preventing omissions due to insufficient coverage of long-side regions. For intermediate missing regions within the graphic, this disclosure uses a regularized cutting of the layout and intersecting with the intermediate missing regions to obtain the corresponding group center points. Through this layered processing strategy (i.e., processing long-side regions first, then processing regions within the graphic), while ensuring that all graphics in the integrated circuit layout are covered, the generation of invalid group regions is reduced, the number of redundant groups is decreased, and a balance is achieved between the regular distribution and quantity reduction of group center points.

[0068] Furthermore, by using a regularized cutting method to generate group center points, the missing areas within the graphic can be divided according to uniform rules, making it easier for regions with the same or similar geometric features to be grouped into the same group. Compared to cutting based on the missing area itself, this disclosure reduces redundant grouping caused by irregular distribution of center points, thereby reducing the final number of groups. Further, the grouping unit regions in the first grouping region generated by regularized dot notation and the second grouping region generated based on the missing areas can use the same size. By using grouping unit regions of uniform size for different grouping regions, overlap between different grouping regions can be reduced, and repeated processing of the same areas can be suppressed, thereby reducing computational resource consumption during the grouping process. Moreover, by generating rectangular regions based on the boundaries of the graphic and finding the intersection of these rectangular regions with the cutting line regions to obtain the group center points corresponding to the missing areas, the generated group center points can be associated with the actual graphic regions. This method avoids generating a large number of grouping regions that do not contain graphics or contain only a few graphics, thereby reducing the generation of invalid groups and decreasing the final number of groups.

[0069] Figure 10 An exemplary block diagram of an apparatus 1000 for processing an integrated circuit layout including multiple patterns, according to an embodiment of the present disclosure, is shown. The apparatus 1000 includes a first determining module 1002, a second determining module 1004, a generating module 1006, and a third determining module 1008. The first determining module 1002 is configured to determine a first grouping region based on the integrated circuit layout. The first grouping region includes a plurality of first grouping unit regions. The plurality of first grouping unit regions include a plurality of rectangular regions covered by corresponding geometric vertices of the plurality of patterns as geometric centers. The second determining module 1004 is configured to determine regions in the integrated circuit layout not covered by the first grouping region as missing regions. The generating module 1006 is configured to generate a plurality of grouping center points based on the missing regions. The third determining module 1008 is configured to use the plurality of grouping center points to determine a second grouping region. The combination of the second grouping region and the first grouping region covers the plurality of patterns of the integrated circuit layout.

[0070] The device 1000 generates multiple group center points for the missing areas not covered by the first group region, and generates a second group region based on these multiple group center points, thereby effectively supplementing and covering the missing areas. This avoids the graphic omission problem that occurs when only the first group region is used to divide the integrated circuit layout. While ensuring that multiple graphics in the integrated circuit layout are completely covered, an optimized balance is achieved between the number of groups, the regularity of grouping, and the efficiency of grouping processing.

[0071] The apparatus 1000 of this disclosure for processing an integrated circuit layout including multiple patterns can be used to perform some or all of the aforementioned methods for processing an integrated circuit layout including multiple patterns. The description of the methods for processing an integrated circuit layout including multiple patterns according to embodiments of this disclosure also applies to the apparatus 1000. Therefore, the apparatus 1000 will not be described in detail here.

[0072] Figure 11 A schematic block diagram of an example device 1100 suitable for implementing embodiments of the present disclosure is shown. As shown, device 1100 includes a computing unit 1101. The computing unit 1101 is, for example, a CPU, a graphics processing unit (GPU), or a neural processing unit (NPU), which can perform various appropriate actions and processes according to computer program instructions stored in read-only memory (ROM) 1102 or loaded from storage unit 1108 into random access memory (RAM) 1103. Various programs and data required for the operation of device 1100 may also be stored in RAM 1103. The computing unit 1101, ROM 1102, and RAM 1103 are interconnected via bus 1104. Input / output (I / O) interface 1105 is also connected to bus 1104.

[0073] Multiple components in device 1100 are connected to I / O interface 1105, and may include, for example: input unit 1106, such as a keyboard, mouse, etc.; output unit 1107, such as various types of displays, speakers, etc.; storage unit 1108, such as a disk, optical disk, etc.; and communication unit 1109, such as a network card, modem, wireless transceiver, etc. Communication unit 1109 allows device 1100 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks. Communication unit 1109 may, for example, communicate with an external server to obtain various data required, for example, for processing integrated circuit layouts.

[0074] The various processes and procedures described above can be executed by computing unit 1101. For example, in some embodiments, method 100 can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1108. In some embodiments, part or all of the computer program can be loaded and / or installed on device 1100 via ROM 1102 and / or communication unit 1109. When the computer program is loaded into RAM 1103 and executed by computing unit 1101, one or more actions of method 100 described above can be performed.

[0075] This disclosure can be a method, apparatus, system, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of this disclosure.

[0076] Computer-readable storage media can be tangible devices capable of holding and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM) (or flash memory), static random-access memory (SRAM), and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0077] The computer-readable program instructions described herein can be downloaded from computer-readable storage media to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage media in the respective computing / processing device.

[0078] The computer program instructions used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information of computer-readable program instructions. These electronic circuits can execute computer-readable program instructions to implement various aspects of this disclosure.

[0079] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0080] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processing unit of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0081] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions that execute on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0082] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0083] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or pervasive.

[0084] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with at least one other aspect. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0085] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for processing an integrated circuit layout, the integrated circuit layout comprising a plurality of patterns, the method comprising: A first grouping region is determined based on the integrated circuit layout. The first grouping region includes multiple first grouping unit regions, and the multiple first grouping unit regions include multiple rectangular regions covered by the corresponding geometric vertices of the multiple graphics as geometric centers. The regions in the integrated circuit layout that are not covered by the first grouped region are identified as missing regions. Multiple grouping center points are generated based on the omitted regions; as well as The plurality of grouping center points are used to determine a second grouping region, wherein the combination of the second grouping region and the first grouping region covers the plurality of patterns of the integrated circuit layout.

2. The method according to claim 1, wherein generating multiple grouping center points based on the omitted region includes: Multiple squares are generated based on the missing area; as well as The geometric centers corresponding to the multiple squares are respectively determined as the multiple grouping center points.

3. The method according to claim 2, wherein the first grouping unit region includes a first side extending along a first direction and a second side extending along a second direction, the first direction and the second direction being perpendicular to each other in the plane where the integrated circuit layout is located, the plurality of graphics includes a first graphic, the first graphic including a third side extending along the first direction and a fourth side extending along the second direction, the plurality of squares including at least one of a first square and a second square, and generating the plurality of squares based on the missing region includes: If the length of the third side is greater than the length of the first side, then the first square is generated within the first shape; and / or If the length of the fourth side is greater than the length of the second side, then the second square is generated within the first shape.

4. The method according to claim 3, wherein the second grouping region includes a first supplementary grouping region and a second supplementary grouping region, the plurality of squares further includes a third square, and generating the plurality of squares based on the omitted region further includes: A first supplementary grouping region is generated based on at least one of the first square and the second square. The first supplementary grouping region includes a plurality of second grouping unit regions. The first square or the second square has the same geometric center as the corresponding second grouping unit region, and the second grouping unit region has the same size as the first grouping unit region. The regions within the omitted regions that are not covered by the first supplementary grouping region are identified as intermediate omitted regions; and The third square is generated based on the missing intermediate region.

5. The method according to claim 4, wherein generating the third square based on the intermediate missing region comprises: A layout boundary rectangle is generated based on the integrated circuit layout, wherein the layout boundary rectangle is the smallest rectangle covering the integrated circuit layout; The layout boundary rectangle is divided into multiple segmented regions using multiple cutting lines; as well as The third square is determined based on at least one of the plurality of segmented regions.

6. The method according to claim 5, wherein dividing the layout boundary rectangle into multiple segmented regions using multiple cutting lines comprises: Starting from a vertex of the bounding rectangle of the layout, multiple first cutting lines are generated along a first direction with a first spacing, and multiple second cutting lines are generated along a second direction with a second spacing, to divide the bounding rectangle of the layout into multiple segmented regions. The line width of either the first cutting line or the second cutting line is equal to the side length of the square among the multiple squares. The first spacing is equal to the length of the first side, and the second spacing is equal to the length of the second side. The first cutting line extends along the second direction, and the second cutting line extends along the first direction.

7. The method of claim 6, wherein determining the third square based on at least one of the plurality of segmented regions comprises: Determine the center position of the segmented region within the bounded rectangle of the map, which covers at least a portion of the intermediate omitted region; as well as The third square is generated using the central position as the geometric center.

8. The method of claim 3, wherein generating the first square within the first shape if the length of the third side is greater than the length of the first side comprises: A layout boundary rectangle is generated based on the integrated circuit layout, wherein the layout boundary rectangle is the smallest rectangle covering the integrated circuit layout; The layout boundary rectangle is divided using multiple cutting lines; as well as The first square is determined based on the multiple cutting lines.

9. The method of claim 8, wherein dividing the layout boundary rectangle using multiple cutting lines comprises: Starting from a vertex of the layout boundary rectangle, multiple first cutting lines are generated along a first direction with a first spacing to divide the layout boundary rectangle. The line width of the first cutting line is equal to the side length of the square among the multiple squares, the first spacing is equal to the length of the first side, and the first cutting line extends along a second direction.

10. The method of claim 9, wherein determining the first square based on the plurality of cutting lines comprises: Based on the fact that the length of the third side is greater than the length of the first side, a first rectangle with a predetermined width is generated within the first shape, the predetermined value being equal to the side length of one of the plurality of squares; and The first square is determined based on the multiple intersection areas of the first rectangle and the multiple first cutting lines.

11. The method of claim 10, wherein determining the first square based on a plurality of intersection regions of the first rectangle and the plurality of first cutting lines comprises: The first square is determined based on the intersection region covered by the omitted region among the plurality of intersection regions.

12. The method of claim 3, wherein generating the second square within the first shape if the length of the fourth side is greater than the length of the second side comprises: A layout boundary rectangle is generated based on the integrated circuit layout, wherein the layout boundary rectangle is the smallest rectangle covering the integrated circuit layout; The layout boundary rectangle is divided using multiple cutting lines; as well as The second square is determined based on the multiple cutting lines.

13. The method of claim 12, wherein dividing the layout boundary rectangle using multiple cutting lines comprises: Starting from one vertex of the layout boundary rectangle, multiple second cutting lines are generated along a second direction at a second spacing to divide the layout boundary rectangle. The line width of the second cutting line is equal to the side length of one of the multiple squares, the second spacing is equal to the length of the second side, and the second cutting line extends along a first direction.

14. The method of claim 13, wherein determining the second square based on the plurality of cutting lines comprises: Based on the fact that the length of the fourth side is greater than the length of the second side, a second rectangle with a predetermined width is generated within the first shape, the predetermined value being equal to the side length of one of the plurality of squares; and The second square is determined based on multiple intersection areas between the second rectangle and the second cutting line.

15. The method of claim 14, wherein determining the second square based on a plurality of intersection regions of the second rectangle and the second cutting line comprises: The second square is determined based on the intersection region covered by the omitted region among the plurality of intersection regions.

16. An electronic device comprising: At least one processor; as well as A storage device coupled to the at least one processor and having instructions stored thereon, which, when executed by the at least one processor, cause the electronic device to perform the method according to any one of claims 1-15.

17. A storage medium, said storage medium being a computer-readable storage medium having a computer program stored thereon, said program, when executed by a processor, implementing the method as described in any one of claims 1-15.

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