A spiking transmission method and device for brain-like computing and a medium

Abstract

This invention discloses a pulse transmission method, device, and medium for neuromorphic computing, relating to the field of neuromorphic computing technology. The method includes: accumulating the membrane potential of input pulse values ​​to neurons to obtain accumulated membrane potential values; generating trigger pulses based on pulse generation instructions in the spiking neural network (SNN) source code script and the accumulated membrane potential values; and transmitting the trigger pulses to downstream neurons. The technical solution of this invention can be adapted to distributed computing in SNNs, optimizing pulse generation instructions and improving SNN computational performance.

Description

Technical Field

[0001] This invention relates to the field of neuromorphic computing technology, and in particular to a pulse transmission method, device and medium for neuromorphic computing. Background Technology

[0002] Neuromorphic computing is an intelligent computing technology inspired by the workings of the brain. Based on research findings in neuroscience, cognitive science, and computational neuroscience, it learns from and draws upon the information processing mechanisms, physiological structures, and main functions of biological nervous systems. It aims to simulate and realize the processing power and efficiency of the biological brain in artificial computing systems, offering advantages such as high energy efficiency, high speed, high fault tolerance, and strong scalability. In the field of neuromorphic computing, Spiking Neural Networks (SNNs), as a typical representative capable of efficiently representing the information processing mechanisms, structures, and functions of biological nervous systems, have gradually become a focus of academic research and engineering applications, and are one of the most commonly used artificial neural network models in current neuromorphic computing research. Spiking neural networks possess both high biological reliability and computational efficiency, transmitting information by mimicking the pulse release behavior of biological neurons. Due to their sparse event-driven nature, SNN networks are highly energy efficient and have strong real-time performance, making them very suitable for power- and latency-sensitive applications such as high-performance processors, edge computing, and terminal devices. Therefore, neuromorphic computing technology can significantly improve the overall performance of edge-cloud collaborative computing systems.

[0003] The benefits of using neuromorphic computing technology in distributed computing systems mainly include: the event-driven mechanism of neuromorphic computing enables rapid response to local events initiated by terminal devices, thereby significantly improving the real-time processing capabilities of distributed edge-cloud systems; the data processing objects of neuromorphic computing are easily coded pulse sequences, which can reduce the amount of data that needs to be transmitted, thereby improving the utilization efficiency of network bandwidth and alleviating the bandwidth pressure on terminal devices and edge networks; the sparse neuronal pulse firing of neuromorphic computing brings low power consumption advantages, which can significantly improve the energy efficiency of various computing nodes in collaborative computing systems, especially edge computing and terminal devices.

[0004] However, most existing distributed computing systems only provide hardware and software support for common artificial neural networks such as deep neural networks (DNNs), and have not achieved integration and compatibility with SNN network computing functions. For example, the neuromorphic instruction set based on the HiPU (High-performance Intelligent Processing Unit) series chips contains only one pulse sequence operation GP instruction, which is somewhat lacking in flexibility and parameter configurability, making it difficult to achieve a trade-off between instruction-level resource consumption and computing performance. The GSPRS instruction (pulse generation operation instruction) of the Darwin 3 chip is an encoding with only 4 bits of effective information. Its purpose is to indicate whether four operations need to be performed: pulse generation, threshold comparison, adaptive update, and membrane potential value reset. However, this instruction still needs to call other arithmetic instructions to calculate the pulse value. Therefore, the instruction code density is insufficient, which seriously restricts the further development and application of neuromorphic intelligent processors.

[0005] In the entire SNN computation process, pulse generation serves as a crucial link between membrane potential accumulation and pulse propagation, and the quality of its instruction-level implementation directly impacts the overall efficiency of SNN inference. Therefore, a systematic technical solution is urgently needed to improve the instruction-level efficiency of SNN pulse generation operations, thereby promoting the practical application of neuromorphic computing in distributed systems. Summary of the Invention

[0006] This invention provides a pulse transmission method, device, and medium for neuromorphic computing, to solve the problem that the pulse generation instructions in existing SNN calculations need to be optimized, which seriously restricts the performance of SNN calculations.

[0007] According to one aspect of the present invention, a pulse transmission method for neuromorphic computing is provided, comprising: The membrane potential is accumulated based on the input pulse values ​​of the neuron to obtain the accumulated membrane potential value; Based on the pulse generation instructions and the accumulated membrane potential value in the spiking neural network source code script, a trigger pulse is generated and transmitted to the downstream neurons; wherein, the pulse generation instructions include single pulse generation instructions or pulse batch generation instructions.

[0008] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: At least one neuromorphic processor; and a memory communicatively connected to the at least one neuromorphic processor; The memory stores a computer program that can be executed by the at least one neuromorphic processor, and the computer program is executed by the at least one neuromorphic processor to enable the at least one neuromorphic processor to execute the pulse transmission method for neuromorphic computing as described in any embodiment of the present invention.

[0009] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a neuromorphic processor to execute and implement the pulse transmission method for neuromorphic computing as described in any embodiment of the present invention.

[0010] According to another aspect of the present invention, a computer program product is provided, the computer program product comprising a computer program that, when executed by a neuromorphic processor, implements the pulse transmission method for neuromorphic computing as described in any embodiment of the present invention.

[0011] The technical solution of this invention accumulates membrane potential values ​​from the input pulse values ​​of neurons to obtain accumulated membrane potential values. Based on the pulse generation instructions in the spiking neural network source code script and the accumulated membrane potential values, a trigger pulse is generated and transmitted to downstream neurons. This solution generates pulses based on single-pulse generation instructions or batch pulse generation instructions, without relying on other computational instructions. Batch pulse generation instructions have higher code density and can generate trigger pulses in batches, improving the overall computational performance of the SNN. Single-pulse generation instructions have lower performance requirements for the neuromorphic processor. Both pulse generation instructions are adaptable to distributed computing in SNNs and can be flexibly selected by technicians as needed. This solves the problem that existing SNN computations require optimization of pulse generation instructions, which severely restricts SNN computational performance. It can adapt to distributed SNN computing, optimize pulse generation instructions, and improve SNN computational performance.

[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 The flowchart shows a pulse transmission method for neuromorphic computing provided in Embodiment 1 of the present invention. Figure 2 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. Detailed Implementation

[0015] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] Example 1 Figure 1 This is a flowchart of a pulse delivery method for neuromorphic computing provided in Embodiment 1 of the present invention. This embodiment is applicable to SNN distributed computing. The method can be executed by a pulse delivery device for neuromorphic computing, which can be implemented in hardware and / or software and can be configured in an electronic device. The pulse delivery device for neuromorphic computing can be a virtual device executing the pulse delivery method for neuromorphic computing. Figure 1 As shown, the method includes: Step 110: Accumulate the membrane potential of the neuron input pulse value to obtain the accumulated membrane potential value.

[0018] Among them, the cumulative membrane potential is the accumulated state quantity of the neuron's membrane potential, representing the sum of potentials continuously superimposed after the neuron receives synaptic input currents. The neuron's input pulse value can be the pulse value input to the neuron in a spiking neural network.

[0019] In this embodiment of the invention, the membrane potential accumulation value can be obtained by accumulating the input pulse value of the neuron based on the membrane potential input accumulation instruction in the spiking neural network source code script.

[0020] The spiking neural network (SNN) source code script can be the code execution script for an SNN network inference task. For example, an SNN network inference task can include object detection, image recognition, image segmentation, etc. The membrane potential input accumulation instruction can include a single-input membrane potential accumulation instruction or a multi-input membrane potential accumulation instruction. A single-input membrane potential accumulation instruction can be a membrane potential update instruction for a single-input neuron. A multi-input membrane potential accumulation instruction can be a membrane potential update instruction for a multi-input neuron.

[0021] For example, a neuron can have two inputs, i.e., two input paths. The neuron's inputs can also be a single set or two sets. When the neuron has two sets of inputs, the membrane potential needs to be accumulated from both sets of pulse values ​​for determination. When the neuron has a single set of inputs, the membrane potential needs to be accumulated from only one set of pulse values ​​for determination.

[0022] Step 120: Generate a trigger pulse based on the pulse generation instructions and the accumulated membrane potential value in the spiking neural network source code script, and transmit the trigger pulse to the downstream neuron.

[0023] The pulse generation instruction can include a single pulse generation instruction or a batch pulse generation instruction. A single pulse generation instruction can be a control instruction that generates a single trigger pulse. A batch pulse generation instruction can be a control instruction that generates a batch of trigger pulses.

[0024] In this embodiment of the invention, according to the single pulse generation instruction in the spiking neural network source code script, the accumulated membrane potential value of only one neuron is compared with the pulse triggering threshold. If the accumulated membrane potential value is greater than the pulse triggering threshold, a single trigger pulse is generated. Alternatively, according to the pulse batch generation instruction in the spiking neural network source code script, the accumulated membrane potential values ​​of multiple neurons are compared with the pulse triggering threshold. If the accumulated membrane potential values ​​of multiple neurons are greater than the pulse triggering threshold, trigger pulses are generated in batches and then transmitted to downstream neurons.

[0025] It's important to understand that, assuming the SNN network inference task is an image recognition task, and the data input to the neuromorphic processor is a 0-1 sequence (a binary sequence composed of 0s and 1s), then the 0-1 sequence represents the binary sequence of the image to be recognized. Based on the membrane potential accumulation instructions (single-input or multi-input) in the spiking neural network source code script, the membrane potential of the neuron input pulse value is accumulated to obtain the accumulated membrane potential value. Then, based on the pulse generation instructions (single-pulse or batch-pulse) in the spiking neural network source code script, when the accumulated membrane potential value is greater than the pulse triggering threshold, a trigger pulse is generated and transmitted to the downstream neurons, forming the basic loop of SNN inference. This loop is executed iteratively until the forward inference of the entire network is completed, and the binary sequence representing the image recognition result is output by the terminal neurons as the output of the neuromorphic processor.

[0026] The technical solution of this invention accumulates membrane potential values ​​from the input pulse values ​​of neurons to obtain accumulated membrane potential values. Based on the pulse generation instructions in the spiking neural network source code script and the accumulated membrane potential values, a trigger pulse is generated and transmitted to downstream neurons. This solution generates pulses based on single-pulse generation instructions or batch pulse generation instructions, without relying on other computational instructions. Batch pulse generation instructions have higher code density and can generate trigger pulses in batches, improving the overall computational performance of the SNN. Single-pulse generation instructions have lower performance requirements for the neuromorphic processor. Both pulse generation instructions are adaptable to distributed computing in SNNs and can be flexibly selected by technicians as needed. This solves the problem that existing SNN computations require optimization of pulse generation instructions, which severely restricts SNN computational performance. It can adapt to distributed SNN computing, optimize pulse generation instructions, and improve SNN computational performance.

[0027] Example 2 This invention provides an optional implementation of a pulse transmission method for neuromorphic computing, as shown in Embodiment 2.

[0028] It should be noted that, for ease of register naming, the register names are determined based on the order of registers in the operands of instructions (membrane potential input accumulation instruction, pulse generation instruction), namely, first register, second register, ... This is a logical naming of registers within the instruction; that is, the first register in different instructions does not refer to a specific physical register. Similarly, for ease of vector register naming, the vector register names are determined based on the order of vector registers in the operands of instructions (membrane potential input accumulation instruction, pulse generation instruction), namely, first vector register, second vector register, ... This is a logical naming of vector registers within the instruction; that is, the first vector register in different instructions does not refer to a specific physical register.

[0029] In an optional embodiment of the present invention, the neuron input pulse value includes the current neuron's first input pulse value and the current neuron's second input pulse value; accumulating the neuron input pulse values ​​to obtain a membrane potential accumulation value may include: when the membrane potential multi-input accumulation instruction in the spiking neural network source script is a membrane potential dual-input accumulation instruction, writing the current neuron's first input pulse value and the current neuron's second input pulse value into a first register according to the membrane potential dual-input accumulation instruction; when both the current neuron's first input pulse value and the current neuron's second input pulse value are 0, no membrane potential accumulation is performed, and the membrane potential accumulation value is the historical accumulation value of the membrane potential; when the current neuron's first input pulse value and / or the current neuron's second input pulse value are not 0, adding the current neuron's first input synaptic weight value and / or the current neuron's second input synaptic weight value to the historical accumulation value of the membrane potential to obtain the membrane potential accumulation value.

[0030] The membrane potential dual-input accumulation instruction can be a multi-input accumulation instruction for membrane potential, which performs accumulation judgment and calculation of the accumulated value based on two input pulse values. The first and second input pulse values ​​of the current neuron are the pulse values ​​of the two forward input pulses of the current neuron, respectively. The first and second input pulse values ​​of the current neuron can be 0 or 1. The first and second input synaptic weight values ​​are the synaptic weights of the two forward input pulses of the current neuron, respectively. The synaptic weight values ​​are signed fixed-point numbers, with positive values ​​indicating excitatory synapses and negative values ​​indicating inhibitory synapses.

[0031] In this embodiment of the invention, if the membrane potential multi-input accumulation instruction in the spiking neural network source code script is a membrane potential dual-input accumulation instruction, then based on the membrane potential dual-input accumulation instruction, the first input pulse value of the current neuron and the second input pulse value of the current neuron are respectively written into two storage data bits of the first register. When both the first and second input pulse values ​​of the current neuron are 0, no membrane potential accumulation is performed, and the accumulated membrane potential value of the current neuron remains the historical accumulated membrane potential value. When the first input pulse value of the current neuron and / or the second input pulse value of the current neuron are 1, the synaptic weight value of the input pulse with an input pulse value of 1 (the synaptic weight value of the first input pulse of the current neuron and / or the synaptic weight value of the second input pulse of the current neuron) is added to the historical accumulated membrane potential value to obtain the accumulated membrane potential value.

[0032] In an optional embodiment of the present invention, accumulating membrane potentials from neuron input pulse values ​​to obtain a cumulative membrane potential value may include: when the membrane potential multi-input accumulation instruction in the spiking neural network source code script is a membrane potential single-group input accumulation instruction, reading the current neuron input pulse vector in the first vector register according to the membrane potential single-group input accumulation instruction; wherein, the membrane potential single-group input accumulation instruction includes multiple neuron input pulse values; when at least one word element in the current neuron input pulse vector has a non-zero last bit value, determining the cumulative membrane potential value based on the historical cumulative membrane potential value corresponding to the word element with a non-zero last bit value in the current neuron input pulse vector and the synaptic weight value.

[0033] The single-group membrane potential accumulation instruction can be a multi-input membrane potential accumulation instruction that performs membrane potential accumulation judgment and accumulation value calculation for a group of input pulse values. The current neuron input pulse vector can be a vector describing the current neuron's input pulse values, with words as vector elements, representing a group of inputs from feedforward neurons. For example, the current neuron input pulse vector can include 8 words. The group membrane potential accumulation instruction includes both single-group and double-group input accumulation instructions. A value of 0 at the end of a word element indicates that the corresponding input pulse value is 0; a value of 1 at the end of a word element indicates that the corresponding input pulse value is 1.

[0034] In an embodiment of the present invention, for example, the input pulse of the current neuron has a one-to-one mapping relationship with the word-format input pulse value stored in the current neuron's input pulse vector (i.e., the word element stored in the current neuron's input pulse vector), and the synaptic weight value of the input pulse of the current neuron has a one-to-one mapping relationship with the word-format input pulse value stored in the current neuron's input pulse vector.

[0035] In this embodiment of the invention, if the membrane potential multi-input accumulation instruction in the spiking neural network source code script is a membrane potential single-input accumulation instruction, then based on the membrane potential single-input accumulation instruction, the current neuron input pulse vector in the first vector register is read, and based on the last word element of the current neuron input pulse vector, it is determined whether the corresponding input pulse value is 0 or 1. For the membrane potential accumulation value corresponding to the word element with a last word value of 0, it is the historical accumulation value of the membrane potential corresponding to that word element. For the membrane potential accumulation value corresponding to the word element with a last word value of 1, it is the sum of the historical accumulation value of the membrane potential corresponding to that word element and the synaptic weight value of the pulse input corresponding to that word element.

[0036] In an optional embodiment of the present invention, processing the neuron input pulse value to obtain the membrane potential accumulation value may include: when the operand in the single input accumulation instruction for membrane potential is three, storing the current neuron input pulse value into the first register according to the single input accumulation instruction for membrane potential in the spiking neural network source code script; when the current neuron input pulse value is 0, no membrane potential accumulation is performed, and the membrane potential accumulation value is the historical accumulation value of membrane potential; when the current neuron input pulse value is not 0, the sum of the historical accumulation value of membrane potential stored in the second register and the synaptic weight value stored in the third register is used as the membrane potential accumulation value, and the membrane potential accumulation is updated to the second register.

[0037] The historical cumulative value of membrane potential is the cumulative value of membrane potential before the 0 / 1 judgment of the current neuron's input pulse value. Membrane potential non-group input accumulation instructions can include single-input accumulation instructions and dual-input accumulation instructions.

[0038] For example, the operand description format in the membrane potential single-input accumulation instruction is <register name>.<access type>. Assume the membrane potential single-input accumulation instruction is CMPEQ_SRa.r, Rb.r, Rc.w, where Ra is the register name of the first register, Rb is the register name of the second register, and Rc is the register name of the third register. r indicates read type, and w indicates write type.

[0039] In this embodiment of the invention, when the operand in the single-input accumulation instruction for membrane potential is three, the operation of storing the current neuron's input pulse value into the first register can be executed according to the single-input accumulation instruction in the spiking neural network source code script. This allows it to determine whether the current neuron's input pulse value is 0. If the current neuron's input pulse value is 0, then there is no need to perform membrane potential accumulation, and the accumulated membrane potential value is the historical accumulated value of the membrane potential. When the current neuron's input pulse value is not 0, based on the single-input accumulation instruction for membrane potential, the historical accumulated value of the membrane potential stored in the second register is summed with the synaptic weight value stored in the third register, and the sum of the historical accumulated value of the membrane potential and the synaptic weight value is used as the accumulated membrane potential value. The accumulated membrane potential is then updated to the second register to complete the update of the accumulated membrane potential value.

[0040] In an optional embodiment of the present invention, processing the neuron input pulse value to obtain the membrane potential accumulation value may further include: when the operand in the single input accumulation instruction of the membrane potential is four and the current neuron input pulse value is 0, storing the current neuron input pulse value in the first register and writing the historical accumulation value of the membrane potential stored in the second register into the fourth register; when the current neuron input pulse value is not 0, using the sum of the historical accumulation value of the membrane potential stored in the second register and the synaptic weight value stored in the third register as the membrane potential accumulation value, and updating the membrane potential accumulation to the second memory.

[0041] In this embodiment of the invention, when the operand in the single-input accumulation instruction for membrane potential is four, according to the single-input accumulation instruction for membrane potential in the spiking neural network source code script, if the current neuron input pulse value is identified as 0, then the current neuron input pulse value is stored in the first register, and the historical accumulation value of membrane potential stored in the second register is written to the fourth register. If the current neuron input pulse value is identified as 1, then the historical accumulation value of membrane potential stored in the second register is added to the synaptic weight value stored in the third register, and the sum of the historical accumulation value of membrane potential and the synaptic weight value is used as the accumulated value of membrane potential and updated to the second memory.

[0042] In an optional embodiment of the present invention, processing the current neuron input pulse value based on the membrane potential multi-input accumulation instruction in the spiking neural network source script to obtain the membrane potential accumulation value may include: when the membrane potential multi-input accumulation instruction in the spiking neural network source script is a membrane potential dual-input accumulation instruction, reading the dual-group neuron input pulse vector according to the membrane potential dual-input accumulation instruction; wherein, the dual-group neuron input pulse vector includes multiple current neuron input pulse values; when the last and second-last bits of each word element of the dual-group neuron input pulse vector are 0, determining the membrane potential accumulation value based on the membrane potential historical accumulation vector corresponding to the dual-group neuron input pulse vector.

[0043] The membrane potential dual-input accumulation instruction can be a multi-input accumulation instruction for membrane potential, which performs accumulation judgment and calculation of the accumulated value for two sets of input pulse values. The membrane potential history accumulation vector can be a vector that stores the historical accumulated values ​​of membrane potentials corresponding to each word element in the dual-group neuron input pulse vector. The dual-group neuron input pulse vector can be understood as a vector describing the current neuron's input pulse value, with words as vector elements, representing the input pulse values ​​from two feedforward neurons to the current neuron.

[0044] In the input pulse vector of the two groups of neurons, the last word of the word element indicates the type (0 or 1) of the input pulse value of one group of feedforward neurons of the current neuron, and the second last word of the word element indicates the type (0 or 1) of the input pulse value of the other group of feedforward neurons of the current neuron.

[0045] In this embodiment of the invention, if the membrane potential multi-input accumulation instruction in the spiking neural network source code script is a membrane potential dual-input accumulation instruction, then the dual-group neuron input pulse vector is read from the first vector register corresponding to the first operand in the dual-group neuron input pulse vector. When the last bit and the second last bit of each word element of the dual-group neuron input pulse vector are 0, the membrane potential historical accumulation vector corresponding to the dual-group neuron input pulse vector is the membrane potential accumulation value corresponding to each word element in the dual-group neuron input pulse vector.

[0046] In an optional embodiment of the present invention, after reading the input pulse vectors of the two groups of neurons, the method may further include: determining the last word element and / or the second-to-last word element of the input pulse vectors of the two groups of neurons that are 1; and calculating the cumulative membrane potential value based on the historical cumulative value of the membrane potential corresponding to the keyword element and the synaptic weight of the target neuron.

[0047] The keyword element can be the last word element and / or the second-to-last word element in the input pulse vector of the two sets of neurons, where the keyword element is 1. The target neuron synaptic weight can be the synaptic weight value corresponding to the pulse input of the target word element.

[0048] Accordingly, when the last and / or second-to-last word of a word element in the input pulse vector of the two groups of neurons is 1, the keyword element with the last and / or second-to-last word element being 1 is determined. Then, based on the membrane potential dual-group input accumulation instruction, the target neuron synaptic weight corresponding to the keyword element is read from the third vector register corresponding to its third operand. Further, the historical accumulated membrane potential value corresponding to the keyword element and the target neuron synaptic weight are summed to obtain the accumulated membrane potential value corresponding to the keyword element; that is, the accumulated membrane potential value corresponding to the keyword element is updated. The accumulated membrane potential values ​​corresponding to other word elements in the input pulse vector of the two groups of neurons, excluding the keyword element, are historical values ​​and are not updated.

[0049] In an optional embodiment of the present invention, generating a trigger pulse based on the single pulse generation instruction and the accumulated membrane potential value in the spiking neural network source code script may include: when the operand in the single pulse generation instruction in the spiking neural network source code script is five, calculating the target difference between the accumulated membrane potential value and the membrane potential threshold stored in the second register according to the single pulse generation instruction; when the target difference is greater than 0, writing the membrane potential reset value into the fourth register and setting the pulse value in the fifth register to 1; and generating a trigger pulse when the pulse value is 1.

[0050] The target difference can be the difference between the current cumulative membrane potential of the neuron and the membrane potential threshold. The membrane potential threshold can be a pre-set critical value for membrane potential, equivalent to the impulse triggering threshold.

[0051] When the operand in the single pulse generation instruction in the spiking neural network source code script is five, the first register stores the accumulated membrane potential value, the second register stores the membrane potential threshold, and the third register stores the membrane potential reset value.

[0052] Accordingly, when the operand in the single-pulse generation instruction in the spiking neural network source code script is five, the target difference can be obtained by subtracting the accumulated membrane potential value stored in the first register from the membrane potential threshold value stored in the second register based on the single-pulse generation instruction. When the target difference is greater than 0, the membrane potential reset value is written to the fourth register, and the pulse value in the fifth register is set to 1, so that when the pulse value is 1, a single trigger pulse is generated, that is, the current neuron outputs a pulse.

[0053] In an optional embodiment of the present invention, generating a trigger pulse based on the single pulse generation instruction and the accumulated membrane potential value in the spiking neural network source code script may include: when the operand in the single pulse generation instruction in the spiking neural network source code script is four, calculating the target difference between the accumulated membrane potential value and the membrane potential threshold stored in the second register according to the single pulse generation instruction; when the target difference is greater than 0, writing the membrane potential reset value into the first register and setting the pulse value in the fourth register to 1; and generating a trigger pulse when the pulse value is 1.

[0054] Specifically, when the operand of the single-pulse generation instruction in the spiking neural network source code script is four, the difference between the accumulated membrane potential value stored in the first register and the membrane potential threshold value stored in the second register is obtained to obtain the target difference value. When the target difference value is greater than 0, the membrane potential reset value stored in the third register is written to the first register, and the pulse value in the fourth register is set to 1, thereby generating a single trigger pulse when the pulse value is 1.

[0055] In an optional embodiment of the present invention, generating trigger pulses according to the pulse batch generation instruction in the spiking neural network source code script may include: when the operand in the pulse batch generation instruction in the spiking neural network source code script is five, calculating the difference between the membrane potential threshold stored in the second vector register and the membrane potential accumulation vector composed of the membrane potential accumulation value stored in the first vector register according to the pulse batch generation instruction to obtain a target difference vector; writing the membrane potential reset value stored in the third vector register to the fourth vector register according to the word element in the target difference vector, or writing the membrane potential reset value stored in the first vector register to the fourth vector register; setting the last bit of the target word element in the fifth vector register to 1 according to the word element with the last bit set to 1, and generating trigger pulses in batches based on the word element with the last bit set to 1.

[0056] The membrane potential accumulation vector can be a vector composed of the current accumulated membrane potential values ​​of multiple neurons. Optionally, the first, second, third, and fourth vector registers are all vector registers storing 8 integer words. The target difference vector can be a vector composed of the differences between the elements in the membrane potential accumulation vector and the membrane potential threshold. The target word element can be a word element that controls the generation of a trigger pulse by setting its last bit to 1. The neuron that generates the trigger pulse corresponding to the target word element is connected to the neuron corresponding to the word element in the target difference vector that is less than 0.

[0057] In this embodiment of the invention, when the operand in the pulse batch generation instruction in the spiking neural network source code script is five, the difference between the membrane potential threshold stored in the second vector register and the membrane potential accumulation vector composed of the membrane potential accumulation values ​​stored in the first vector register can be calculated according to the pulse batch generation instruction to obtain the target difference vector. Then, for word elements in the target difference vector that are less than 0, the membrane potential reset value stored in the third vector register is written to the corresponding position in the fourth vector register (the data storage bit corresponding to the word element less than 0 in the target difference vector), and the last bit of the target word element in the fifth vector register is set to 1, so that the neurons corresponding to the word elements whose last bit is set to 1 can generate trigger pulses in batches. For word elements in the target difference vector that are greater than 0, the membrane potential reset value stored in the first vector register is written to the corresponding position in the fourth vector register (the data storage bit corresponding to the word element greater than 0 in the target difference vector), and the last bit of the non-target word element in the fifth vector register is set to 0, so that the neurons corresponding to the word elements whose last bit is set to 0 do not output trigger pulses.

[0058] For example, the neurons corresponding to the word elements stored sequentially in the fifth vector register have a one-to-one correspondence with the neurons corresponding to the word elements stored sequentially in the target difference vector. Assuming that there are word elements less than 0 in the target difference vector as the first and second-to-first word elements, and neuron a corresponds to the first word element and neuron b corresponds to the second-to-first word element, then the target word elements in the fifth vector register are also the first and second word elements. That is, the word elements in the fifth vector register that need to be set to 1 at the end are located at the first and second-to-first positions of the entire stored vector, and neurons a and b generate trigger pulses.

[0059] In an optional embodiment of the present invention, generating trigger pulses according to the pulse batch generation instruction in the spiking neural network source code script may include: when the operand in the pulse batch generation instruction in the spiking neural network source code script is four, calculating the difference between the membrane potential threshold stored in the second vector register and the membrane potential accumulation vector composed of the membrane potential accumulation value stored in the first vector register according to the pulse batch generation instruction to obtain a target difference vector; writing the membrane potential reset value stored in the third vector register into the first vector register; setting the last bit of the target word element in the fourth vector register to 1 according to the word element with the last bit set to 1, and generating trigger pulses in batches based on the word element with the last bit set to 1.

[0060] Correspondingly, when the operand in the pulse batch generation instruction in the spiking neural network source code script is four, according to the pulse batch generation instruction, the membrane potential threshold stored in the second vector register is calculated with the membrane potential accumulation vector composed of the membrane potential accumulation value stored in the first vector register to obtain the target difference vector. Then, for the word elements in the target difference vector that are less than 0, the membrane potential reset value stored in the third vector register is written to the corresponding position in the first vector register (the data storage bit corresponding to the word element less than 0 in the target difference vector), and the last bit of the target word element in the fourth vector register is set to 1, so that the neurons corresponding to the word elements with the last bit set to 1 can generate trigger pulses in batches.

[0061] Example 3 Embodiment 3 of the present invention provides an optional embodiment of the pulse generation instruction, the specific implementation of which can be found in the following embodiments. Technical terms that are the same as or corresponding to those in the above embodiments will not be repeated here.

[0062] SNN networks use pulses for information encoding. A pulse signal is a binary signal: a value of 1 indicates that a neuron is activated (generating an event) and the signal is transmitted to the neurons connected to its back end; a value of 0 indicates that the neuron is not activated and no pulse event is generated. The pulse generation mechanism of the SNN neuron model is reflected in the cell body dynamics of the neuron: when the accumulated membrane potential of the neuron exceeds a certain threshold, the cell body fires a pulse; otherwise, no pulse is fired.

[0063] The single-pulse generation instruction (equivalent to a basic instruction) can be implemented by manipulating either four or five integer registers. The single-pulse generation instruction determines whether to fire a pulse based on a comparison between the accumulated membrane potential and the membrane potential threshold. If the accumulated membrane potential exceeds the threshold, a pulse is fired, and the membrane potential value is reset; otherwise, the previous accumulated membrane potential value is maintained, and no pulse is fired.

[0064] A single pulse generation instruction with five operands can be denoted as SELGT_S5R and defined as follows: SELGT_S5RRa.r, Rb.r, Rc.r, Rd.w, Re.w The naming convention for the SELGT_S5R instruction mnemonic follows the general naming rules of domestic instruction sets. The operand description format in the instruction is "<name>.<access type>". Here, Ra, Rb, Rc, Rd, and Re all represent integer registers; the operand access types r and w represent "operand is read-only" and "operand is write-only", respectively; the operand data type can be selected according to the specific implementation.

[0065] A single pulse generation instruction with five operands can be denoted as SELGT_S4R and defined as follows: SELGT_S4RRa.m, Rb.r, Rc.r, Rd.w Here, the operand access type m indicates that "the operand is readable and writable". In this case, the integer register Ra is both the source register and the destination register.

[0066] The single-pulse generation instructions SELGT_S5R and SELGT_S4R have the same function, but their main difference lies in their implementation: using four registers improves hardware resource utilization, avoids unnecessary data copying, and reduces power consumption; however, this increases the complexity of data dependency judgment in some cases, leading to more potential resource conflicts and thus impacting pipeline execution efficiency. The specific instruction generation and invocation can be flexibly selected based on computational performance requirements through compiler optimization.

[0067] In the domestic instruction set, multiple vector registers are set up, each with a width of 256 bits. Vector registers can store eight-element word integer vectors, four-element single-precision floating-point vectors, or four-element double-precision floating-point vectors. Data transfer between vector registers and memory can be achieved through SIMD extension instructions. SIMD extensions represent enhanced processing methods for single-instruction-multiple-data (SIMD) instructions with short vector characteristics.

[0068] To improve the density of neuromorphic instructions and increase the efficiency of SNN operations, a new SIMD extension instruction is added to enable batch processing of SNN neuron spiking.

[0069] The pulse batch generation SIMD instruction designed in this invention has the following main function: It stores an eight-element word integer vector in a vector register. Based on the comparison result of the corresponding word elements of the membrane potential accumulation vector and the membrane potential threshold vector, it determines whether a pulse needs to be issued. When the value of a word element in the membrane potential accumulation vector exceeds the value of the corresponding word element in the membrane potential threshold vector, the corresponding pulse is issued, and the corresponding word element of the membrane potential accumulation vector is reset; otherwise, the previous value of the corresponding word element in the membrane potential accumulation vector is maintained, and the corresponding pulse is not issued.

[0070] The pulse batch generation SIMD instruction can be implemented by manipulating either four or five vector registers. The pulse batch generation instruction with five operands can be denoted as VSELLTW_S5R and defined as follows: VSELLTW_S5R Va.r, Vb.r, Vc.r, Vd.w, Ve.w Among them, Va, Vb, Vc, Vd, and Ve all represent vector registers.

[0071] A pulse batch generation instruction with four operands is denoted as VSELLTW_S4R and is defined as follows: VSELLTW_S4R Va.m, Vb.r, Vc.r, Vd.w At this point, the vector register Va is both the source vector register and the destination vector register.

[0072] VSELLTW_S5R and VSELLTW_S4R have the same function; the main difference in their implementation is similar to the difference between the single pulse generation instructions SELGT_S5R and SELGT_S4R, and will not be elaborated further.

[0073] The pulse generation instruction design based on the domestic instruction set proposed in this solution achieves specific support and high-efficiency compatibility for SNN computation. The design of the neuromorphic dedicated instructions conforms to the existing design principles of the domestic instruction set and maintains forward compatibility with existing instruction set versions. It can realize flexible (selectable number of registers used), on-demand (supports basic instructions and SIMD extended instructions), and efficient (directly obtains the operation result) instruction operation, which facilitates the targeted selection of specific implementation methods according to different network scales, domain tasks and other specific application situations, and provides key technical support for the development of an independent and controllable neuromorphic intelligent processor.

[0074] In this embodiment, all instructions are 32 bits long, with the opcode being 6 bits long and each register field occupying 5 bits (corresponding to 32 integer, floating-point, or vector registers). The register types involved are 64-bit integer registers, 64-bit floating-point registers, or 256-bit vector registers.

[0075] SELGT_S5R is implemented by operating on five integer registers (including two source registers and three destination registers). The domestic instruction set used has a total of 64 opcodes. If one of the opcodes is dedicated to neuromorphic computing, it can achieve dedicated and efficient support for pulse generation operations.

[0076] Based on the existing domestic instruction system, this implementation method needs to define a new basic instruction format, called the "brain-like computing instruction format", which uses a total of 5 registers, as shown in Table 1.

[0077] Table 1. Neuromorphic computing instruction format The instruction length of the neuromorphic arithmetic instruction format remains 32 bits, with the opcode being 6 bits long and each of the five register fields occupying 5 bits, totaling 31 bits. Therefore, only 1 bit remains for function code encoding.

[0078] In this embodiment, the

[15] th bit of the instruction is defined as the function code: when the

[15] th bit is 0x0, it indicates a single pulse generation instruction containing five operands, as shown in Table 2.

[0079] Table 2 Description of SELGT_S5R Instructions Therefore, the relevant definition of SELGT_S5R, which occupies an opcode specifically for neuromorphic computing, is as follows: Mnemonic: SELGT_S5R / / Integer greater than "0" selects to generate pulse (including 5 operands); Format: SELGT_S5RRa.rl, Rb.rl, Rc.rl, Rd.wl, Re.wl; Operation: IFTEST(Rav-Rbv, GT); THENRd ← Rcv, Re ← 1; ELSERd ← Rav, Re ← 0.

[0080] Instruction description: Perform a conditional test on Ra-Rb. If Ra-Rb > 0, write the value of Rc to Rd and set the value of Re to 1; otherwise, write the value of Ra to Rd and set the value of Re to 0. An integer overflow will occur in case of an exception.

[0081] The SELGT_S5R instruction means: Ra stores the accumulated membrane potential value, Rb stores the membrane potential threshold, and Rc stores the membrane potential reset value. If the accumulated membrane potential value exceeds the threshold, the membrane potential is reset, i.e., the membrane potential reset value (the value of Rc) is written to Rd, and a pulse is emitted, i.e., the pulse value (the value of Re) is set to 1; otherwise, the membrane potential does not need to be reset, the accumulated membrane potential value (the value of Ra) is written to Rd, and no pulse is emitted, i.e., the pulse value (the value of Re) is set to 0. After the instruction is executed, the value of Rd represents the current accumulated membrane potential value, and the value of Re represents the current pulse generation status.

[0082] The operand description format in the instruction is "<name>.<access type><data type>". The data type "l" of the operand indicates a long word, which is 8 bytes (64 bits) starting at any byte boundary. The operator TEST(x,cond) indicates that the contents of register x are accessed. The test is performed according to the condition cond. If the specified relationship is true, TEST returns a boolean value of "true"; otherwise, it returns "false". The test condition GT indicated in the instruction means that the test is performed on "greater than 0".

[0083] The SELGT_S4R instruction does not require a dedicated opcode for neuromorphic computing. Although it cannot provide specific support for pulse generation operations, it can maintain the openness and flexibility of the instruction set. Based on the existing domestic instruction set, a new integer compound arithmetic instruction format suitable for neuromorphic computing needs to be defined, as shown in Table 3.

[0084] Table 3 Integer compound arithmetic instruction format In general-purpose function instructions using this instruction format, bits [15:13] are always all "0" (i.e., the SBZ field). In contrast, this scheme encodes bits [15:13] as part of the function code, and the encoding of this region [15:13] for newly added neuromorphic function instructions must not be 0x0 (thus avoiding conflicts with existing instructions and ensuring backward compatibility of the instruction set). A new integer conditional selection instruction, designated as the dedicated SELGT_S4R, is added, as shown in Table 4.

[0085] Table 4 Description of SELGT_S4R Instructions The relevant definition of this instruction is as follows: Mnemonic: SELGT_S4R / / Integer greater than "0" selects to generate pulse (containing 4 operands); Format: SELGT_S4RRa.ml, Rb.rl, Rc.rl, Rd.wl; Operation: IFTEST(Rav-Rbv, GT); THENRa ← Rcv, Rd ← 1; ELSERd ← 0.

[0086] Instruction description: Perform a conditional test on Ra-Rb. If Ra-Rb > 0, write the value of Rc to Ra and set the value of Re to 1. Otherwise, set the value of Re to 0. In case of an exception, integer overflow will occur.

[0087] The meaning of SELGT_S4R is as follows: Ra stores the accumulated membrane potential value, Rb stores the membrane potential threshold, and Rc stores the membrane potential reset value. If the accumulated membrane potential value exceeds the threshold, the membrane potential is reset, i.e., the membrane potential reset value (the value of Rc) is written to Ra, and a pulse is emitted, i.e., the pulse value (the value of Rd) is set to 1; otherwise, the membrane potential does not need to be reset, and no pulse is emitted, i.e., the pulse value (the value of Rd) is set to 0. After the instruction is executed, the value of Ra (which is both the source and destination operand register) represents the current accumulated membrane potential value, and the value of Rd represents the current pulse generation status.

[0088] Due to the sparsity of SNN pulses, neurons are not activated most of the time. Therefore, the resetting of the membrane potential (i.e., the resetting of Ra) is a low-probability event.

[0089] By manipulating five vector registers, a SIMD instruction for batch pulse generation is implemented, denoted as VSELLTW_S5R.

[0090] Based on the existing domestic instruction set, this implementation requires defining a new floating-point composite arithmetic instruction format, called the "Neuro-like SIMD arithmetic instruction format", which uses 5 registers, as shown in Table 5.

[0091] Table 5. Neuromorphic SIMD Operation Instruction Format In this embodiment, the

[15] th bit of the instruction is defined as the function code: when the

[15] th bit is 0x1, it indicates a pulse batch generation SIMD instruction containing five operands, namely the VSELLTW_S5R instruction, as shown in Table 6.

[0092] Table 6 Description of VSELLTW_S5R Instructions The relevant definitions of the VSELLTW_S5R instruction are as follows: Mnemonic: VSELLTW_S5R / / Word integer vector less than 0 selects to generate pulse (containing 5 operands); Format: VSELLTW_S5R Va.rw, Vb.rw, Vc.rw, Vd.ww, Ve.ww; Operation: FOR (i=0; i<8; i++); BEGIN; IF TEST (Vb[32×i+31 : 32×i]-Va[32×i+31 : 32×i], LT); THEN Vd[32×i+31 : 32×i]←Vcv[32×i+31 : 32×i], Ve[32×i]←1; ELSE Vd[32×i+31 : 32×i]←Vav[32×i+31 : 32×i], Ve[32×i]←0; END.

[0093] VSELLTW_S5R instruction description: Va, Vb, Vc, and Vd are all vector registers storing 8 words of integers. It tests each word element in Vb-Va. If each word element in Vb-Va is less than 0, the word element corresponding to vector Vb is written to the corresponding position in Vd, and the least significant bit of the word element corresponding to Ve is set to 1; otherwise, the word element corresponding to vector Vc is written to the corresponding position in Vd, and the least significant bit of the word element corresponding to Ve is set to 0.

[0094] The VSELLTW_S5R instruction means: Va stores 8 accumulated membrane potential values, Vb stores 8 membrane potential threshold values, and Vc stores 8 membrane potential reset values. If the accumulated membrane potential value exceeds the threshold, the membrane potential is reset, i.e., the membrane potential reset value (the value of Vc) is written to Vd, and a pulse is issued, i.e., the pulse value (the value of Ve) is set to 1; otherwise, the membrane potential does not need to be reset, the accumulated membrane potential value (the value of Va) is written to Vd, and no pulse is issued, i.e., the pulse value (the value of Ve) is set to 0. After the instruction is executed, the value of vector Vd represents the current 8 accumulated membrane potential values, and the value of vector Ve represents the current 8 pulse generation status.

[0095] The test condition LT indicated in the instruction means that the test is performed on "less than 0".

[0096] By manipulating four integer registers, a SIMD instruction for batch pulse generation is implemented, denoted as VSELLTW_S4R.

[0097] This implementation does not require a dedicated opcode for neuromorphic computing. Although it cannot provide specific support for spike generation operations, it maintains the openness and flexibility of the instruction set and can still achieve batch processing of spike generation for SNN neuron models. Its instruction format can adopt the floating-point compound arithmetic instruction format of domestic instruction sets, as shown in Table 7.

[0098] Table 7 Floating-point compound arithmetic instruction format By manipulating five vector registers, a SIMD instruction for batch pulse generation is implemented, denoted as VSELLTW_S4R. The instruction description of VSELLTW_S4R is shown in Table 8.

[0099] Table 8 Description of VSELLTW_S4R Commands The relevant definitions of the VSELLTW_S4R instruction are as follows: Mnemonic: VSELLTW_S4R / / Word integer vector less than 0 selects to generate pulse (containing 4 operands); Format: VSELLTW_S4R Va.rw, Vb.rw, Vc.rw, Vd.ww; Operation: FOR (i=0; i<8; i++); BEGIN; IF TEST (Vb[32×i+31 : 32×i]-Va[32×i+31 : 32×i], LT); THEN Va[32×i+31 : 32×i]←Vcv[32×i+31 : 32×i], Vd[32×i]←1; ELSE Vd[32×i]←1; END.

[0100] VSELLTW_S4R instruction description: Va, Vb, Vc, and Vd are all vector registers storing 8 words of integers. It tests each word element in Vb-Va. If each word element in Vb-Va is less than 0, the word element corresponding to vector Vc is written to the corresponding position in Va and the least significant bit of the word element corresponding to Vd is set to 1; otherwise, the least significant bit of the word element corresponding to Vd is set to 0.

[0101] VSELLTW_S4R Explanation: Va stores 8 accumulated membrane potential values, Vb stores 8 membrane potential threshold values, and Vc stores 8 membrane potential reset values. If the accumulated membrane potential value exceeds the threshold, the membrane potential is reset (the reset value of Vc is written to Va), and a pulse is emitted (the pulse value of Vd is set to 1); otherwise, the membrane potential does not need to be reset, and no pulse is emitted (the pulse value of Vd is set to 0). After the instruction is executed, the value of vector Va (which is both the source and destination operand register) represents the current 8 accumulated membrane potential values, and the value of vector Vd represents the current 8 pulse generation status.

[0102] Example 4 Figure 2 A schematic diagram of an electronic device that can be used to implement embodiments of the present invention is shown. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0103] like Figure 2 As shown, the electronic device 10 includes at least one neuromorphic processor 11 and a memory, such as ROM 12 or RAM 13, communicatively connected to the at least one neuromorphic processor 11. The memory stores computer programs executable by the at least one neuromorphic processor. The neuromorphic processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from the storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The neuromorphic processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An I / O interface 15 is also connected to the bus 14. The ROM 12 is a read-only memory, the RAM 13 is a random access memory, and the I / O interface 15 is an input / output interface.

[0104] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0105] The neuromorphic processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the neuromorphic processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various neuromorphic processors running machine learning model algorithms, digital signal neuromorphic processors (DSPs), and any suitable neuromorphic processor, controller, microcontroller, etc. The neuromorphic processor 11 performs the various methods and processes described above, such as the pulse delivery method for neuromorphic computing.

[0106] In some embodiments, the pulse delivery method for neuromorphic computing can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or mounted on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by neuromorphic processor 11, one or more steps of the pulse delivery method for neuromorphic computing described above can be performed. Alternatively, in other embodiments, neuromorphic processor 11 can be configured to perform the pulse delivery method for neuromorphic computing by any other suitable means (e.g., by means of firmware).

[0107] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable neuromorphic processor, which may be a dedicated or general-purpose programmable neuromorphic processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0108] Computer programs used to implement the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a neuromorphic processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the neuromorphic processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer programs can be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0109] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0110] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0111] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0112] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS servers, such as high management difficulty and weak business scalability.

[0113] This application also discloses a computer program product, which includes a computer program that, when executed by a neuromorphic processor, implements the pulse transfer method for neuromorphic computing provided in any embodiment of this application. This program product shares the same inventive concept as the pulse transfer method for neuromorphic computing disclosed in the embodiments of this application, and therefore will not be described further here.

[0114] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0115] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pulse transmission method for neuromorphic computing, characterized in that, include: The membrane potential is accumulated based on the input pulse values ​​of the neuron to obtain the accumulated membrane potential value; Based on the pulse generation instructions in the spiking neural network source code script and the accumulated membrane potential value, a trigger pulse is generated and transmitted to the downstream neuron; wherein, the pulse generation instructions include single pulse generation instructions or pulse batch generation instructions.

2. The method according to claim 1, characterized in that, Based on the single-pulse generation instructions in the spiking neural network source code script and the accumulated membrane potential value, a trigger pulse is generated, including: When the operand in the single pulse generation instruction in the spiking neural network source code script is five, the target difference between the accumulated membrane potential value and the membrane potential threshold stored in the second register is calculated according to the single pulse generation instruction. When the target difference is greater than 0, the membrane potential reset value is written to the fourth register, and the pulse value in the fifth register is set to 1; When the pulse value is 1, a trigger pulse is generated.

3. The method according to claim 1, characterized in that, Based on the single-pulse generation instructions in the spiking neural network source code script and the accumulated membrane potential value, a trigger pulse is generated, including: When the operand in the single pulse generation instruction in the spiking neural network source code script is four, the target difference between the accumulated membrane potential value and the membrane potential threshold stored in the second register is calculated according to the single pulse generation instruction. When the target difference is greater than 0, the membrane potential reset value is written to the first register, and the pulse value in the fourth register is set to 1; When the pulse value is 1, a trigger pulse is generated.

4. The method according to claim 1, characterized in that, Based on the pulse batch generation instructions in the spiking neural network source code script, trigger pulses are generated, including: When the operand in the pulse batch generation instruction in the pulse neural network source code script is five, according to the pulse batch generation instruction, the difference between the membrane potential threshold stored in the second vector register and the membrane potential accumulation vector composed of the membrane potential accumulation value stored in the first vector register is calculated to obtain the target difference vector. Based on the word element in the target difference vector, the membrane potential reset value stored in the third vector register is written to the fourth vector register, or the membrane potential reset value stored in the first vector register is written to the fourth vector register. Based on the word elements less than 0 in the target difference vector, set the last bit of the target word element in the fifth vector register to 1, and generate trigger pulses in batches based on the word elements with the last bit set to 1.

5. The method according to claim 1, characterized in that, Based on the pulse batch generation instructions in the spiking neural network source code script, trigger pulses are generated, including: When the operand in the pulse batch generation instruction in the pulse neural network source code script is four, according to the pulse batch generation instruction, the difference between the membrane potential threshold stored in the second vector register and the membrane potential accumulation vector composed of the membrane potential accumulation value stored in the first vector register is calculated to obtain the target difference vector. Write the membrane potential reset value stored in the third vector register into the first vector register; Based on the word elements less than 0 in the target difference vector, set the last bit of the target word element in the fourth vector register to 1, and generate trigger pulses in batches based on the word elements with the last bit set to 1.

6. The method according to claim 1, characterized in that, Neuron input pulse values, including the first input pulse value of the current neuron and the second input pulse value of the current neuron; The membrane potential is accumulated from the input impulse values ​​of the neuron to obtain the accumulated membrane potential value, including: When the membrane potential multi-input accumulation instruction in the spiking neural network source code script is a membrane potential dual-input accumulation instruction, the first input pulse value of the current neuron and the second input pulse value of the current neuron are written into the first register according to the membrane potential dual-input accumulation instruction; When both the first input pulse value and the second input pulse value of the current neuron are 0, no membrane potential accumulation is performed, and the accumulated membrane potential value is the historical accumulated value of the membrane potential. When the first input pulse value of the current neuron and / or the second input pulse value of the current neuron are not 0, the synaptic weight value of the first input of the current neuron and / or the synaptic weight value of the second input of the current neuron are added to the historical cumulative value of the membrane potential to obtain the cumulative value of the membrane potential.

7. The method according to claim 1, characterized in that, The membrane potential is accumulated from the input impulse values ​​of the neuron to obtain the accumulated membrane potential value, including: When the membrane potential multi-input accumulation instruction in the spiking neural network source code script is a membrane potential single-input accumulation instruction, the current neuron input pulse vector in the first vector register is read according to the membrane potential single-input accumulation instruction; wherein, the membrane potential single-input accumulation instruction includes multiple neuron input pulse values; When at least one word element in the current neuron input pulse vector has a non-zero last value, the accumulated membrane potential value is determined based on the historical accumulated membrane potential value corresponding to the word element with a non-zero last value in the current neuron input pulse vector and the synaptic weight value.

8. An electronic device, characterized in that, The electronic device includes: At least one neuromorphic processor, and a memory communicatively connected to said at least one neuromorphic processor; The memory stores a computer program that can be executed by the at least one neuromorphic processor, the computer program being executed by the at least one neuromorphic processor to enable the at least one neuromorphic processor to perform the pulse transmission method for neuromorphic computing as described in any one of claims 1-7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause the neuromorphic processor to execute the pulse transmission method for neuromorphic computing as described in any one of claims 1-7.

10. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a neuromorphic processor, implements the pulse transmission method for neuromorphic computing according to any one of claims 1-7.

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