A bidirectional resistive complementary self-selecting memristor and cross array thereof

Abstract

This invention provides a bidirectional resistive switching complementary self-selecting memristor and its cross-array, relating to the fields of semiconductor devices and non-volatile memory technology. The device includes a first electrode layer, a first semiconductor functional layer, a high-dielectric-constant resistive switching barrier layer, a second semiconductor functional layer, and a second electrode layer arranged sequentially along the stacking direction. By setting the first and second electrode layers with different work functions, an asymmetric interface barrier is formed. Combined with the high-dielectric-constant resistive switching barrier layer, the memristor maintains a high-resistance state under half-selection voltage and forms a positive low-resistance state and a negative low-resistance state under positive and negative programming voltages, respectively. By adjusting the difference between the positive and negative conductances, a single memristor can characterize multiple levels of signed weights. The memristor itself possesses half-selection high-resistance characteristics. Memristor units in a cross-array constructed using this memristor do not require additional series-connected independent selection devices, reducing the number of devices, simplifying the array structure, and increasing integration density.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices and non-volatile memory technology, and in particular to a bidirectional resistive-switching complementary self-selective memristor and its cross array. Background Technology

[0002] With the development of data-intensive applications such as artificial intelligence and neuromorphic computing, the traditional von Neumann computing architecture, which separates storage and computing units, requires frequent data transfer between them, easily creating bottlenecks in storage bandwidth and data movement. In-memory computing technology reduces data transfer overhead by performing some computations directly within the storage array. Memristors, with their non-volatility, adjustable resistance, and ease of constructing cross-arrays, can be used to perform parallel multiply-accumulate operations by utilizing the relationship between the conductance of a memristor cross-array and the input voltage. Therefore, they are used to build in-memory computing and neuromorphic computing hardware.

[0003] Existing memristor cross-arrays typically include multiple word lines and bit lines that intersect each other, with memristor cells positioned at the intersections of word lines and bit lines. When programming or reading a selected memristor cell, other cells sharing word lines or bit lines with the selected cell may be in a half-selected state, and current may also form unintended conductive paths through multiple unselected cells. To limit the current in these unselected paths, some existing solutions use a gating device connected in series in each memristor cell, such as a 1T1R structure consisting of a transistor and a memristor, a 1D1R structure consisting of a diode and a memristor, or a 1S1R structure consisting of a gating device and a memristor. Furthermore, in neuromorphic memory systems built on memristors, to implement positive and negative signed synaptic weights, common existing solutions use two independent memristors to store the positive and negative weight components respectively, using the difference in their conductances as the equivalent synaptic weight. A typical implementation uses a dual-device differential structure to complete the readout and differential operation of the two conductances. However, the two independent devices each have their own conductance drift and random fluctuations. The parameter mismatch and drift differences between the devices will continuously introduce weighting errors, which will seriously reduce the calculation accuracy.

[0004] In the aforementioned array crosstalk suppression scheme, since the independent gating devices are connected in series with the memristors, each crossover position requires additional devices and corresponding connection structures in addition to the memristors. This increases the cell area, fabrication steps, and array driving complexity, which is not conducive to further improving the integration density of passive crossover arrays. In the aforementioned signed weight representation scheme, since a weight needs to be represented by two independent memristors, it not only increases the number of memristors and array wiring resources, but also the two devices may have differences in initial conductance, resistance-state adjustment characteristics, and conductance drift over time. These differences will be directly reflected in the difference between the two conductances, forming a weight representation error. At the same time, programming, reading, and differential processing of the two devices separately will also increase the burden on the peripheral control and reading circuits. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of the prior art by providing a bidirectional resistive switching complementary self-selection memristor and its cross array. The aim is to solve the problems of existing memristor cross arrays relying on independent gating devices to suppress half-selection crosstalk and using a dual-device differential structure to represent signed weights by constructing a bidirectional resistive switching complementary self-selection memristor with an asymmetric interface barrier and a high dielectric constant resistive switching barrier layer.

[0006] To achieve the above objectives, the main technical solution adopted by the present invention is as follows: In a first aspect of the present invention, a bidirectional resistive switching complementary self-selective memristor is provided, comprising a first electrode layer, a first semiconductor functional layer, a high dielectric constant resistive switching barrier layer, a second semiconductor functional layer and a second electrode layer disposed sequentially along the stacking direction. The first electrode layer and the first semiconductor functional layer form a first interface barrier, and the second electrode layer and the second semiconductor functional layer form a second interface barrier. The first electrode layer and the second electrode layer have different work functions, and the first interface barrier and the second interface barrier are asymmetrical. The first interface barrier, the second interface barrier, and the high dielectric constant resistive switching barrier layer together enable the memristor to form a positive low-resistance state under the action of a positive programming voltage where the first electrode layer is at a positive potential relative to the second electrode layer, and a negative low-resistance state under the action of a negative programming voltage where the first electrode layer is at a negative potential relative to the second electrode layer. In the positive low-resistance state, the dominant conduction direction of the memristor is positive, and in the negative low-resistance state, the dominant conduction direction of the memristor is negative, causing the memristor to be in a high-resistance state under the action of half-select voltage.

[0007] Preferably, one of the first electrode layer and the second electrode layer is an inert metal electrode layer, and the other is a metal or alloy electrode layer.

[0008] Preferably, the high dielectric constant resistive switching barrier layer is an insulating or semi-insulating dielectric layer used to form a carrier transport barrier; the carrier transport barrier restricts carrier transport under half-selection voltage and generates field-assisted carrier transport under programming voltage.

[0009] Preferably, both the first semiconductor functional layer and the second semiconductor functional layer are wide bandgap semiconductor oxide layers containing defects, and the defects are used to regulate carrier injection and carrier transport at the corresponding interfaces.

[0010] Preferably, the defects in the wide bandgap semiconductor oxide layer include at least one of oxygen vacancies and lattice defects.

[0011] Preferably, the read voltage when the first electrode layer is at a positive potential relative to the second electrode layer is defined as the positive read voltage, and the read voltage when the first electrode layer is at a negative potential relative to the second electrode layer is defined as the negative read voltage; the conductance of the memristor under the positive read voltage is the positive conductance, and the conductance under the negative read voltage is the negative conductance; In the forward low-resistance state, the forward conductance is greater than the negative conductance; in the negative low-resistance state, the negative conductance is greater than the forward conductance.

[0012] Preferably, at least one of the positive conductance and the negative conductance can be adjusted to multiple conductance values ​​under the action of a programmed pulse sequence to adjust the difference between the positive conductance and the negative conductance; the difference is used to characterize the signed weight.

[0013] In another aspect of the present invention, a bidirectional resistive-switching complementary self-selective memristor cross array is provided, comprising a plurality of first wires, a plurality of second wires, and a plurality of memristor units respectively disposed at the intersection of each of the first wires and each of the second wires; Each memristor unit is a bidirectional resistive-switching complementary self-selecting memristor. The first electrode layer and the second electrode layer of the memristor unit are electrically connected to the corresponding first wire and the second wire, respectively, and each memristor unit is not connected in series with an independent selection device.

[0014] Preferably, the read voltage when the first electrode layer is at a positive potential relative to the second electrode layer is defined as the positive read voltage, and the read voltage when the first electrode layer is at a negative potential relative to the second electrode layer is defined as the negative read voltage; each memristor cell has a positive conductance and a negative conductance under the positive read voltage and the negative read voltage, respectively, and the difference between the positive conductance and the negative conductance is used to characterize the signed weight.

[0015] Preferably, when programming or reading a selected memristor cell, the selected memristor cell is subjected to a full-select voltage across its terminals, while the non-selected memristor cells that share the first or second wire with the selected memristor cell are subjected to a half-select voltage across their terminals. The absolute value of the half-selection voltage is lower than the absolute value of the resistive switching threshold voltage corresponding to its polarity.

[0016] The beneficial effects of this invention are: 1. This invention sets up a first electrode layer and a second electrode layer with different work functions and forms an asymmetric interface barrier. Combined with a high dielectric constant resistive switching barrier layer, it restricts carrier transport under half-select voltage, thereby keeping the half-select memristor unit in a high-resistivity state and suppressing array leakage current and crosstalk current.

[0017] 2. This invention enables memristors to have half-select high impedance characteristics, so that memristor units in the cross array do not need to be connected in series with independent selection devices, thereby reducing the number of devices, simplifying the array structure and increasing the integration density.

[0018] 3. This invention forms positive and negative low-resistance states with opposite dominant conduction directions under the action of programming voltages with opposite polarities, and uses the difference between positive and negative conductance to characterize the signed weight, thereby achieving the effect of storing the signed weight by a single memristor, reducing the number of memristors and peripheral control resources.

[0019] 4. This invention adjusts at least one of the positive and negative conductances to multiple conductance values ​​by programming pulse sequences, thereby adjusting the conductance difference between the two, realizing multi-level signed weighted control and reducing the influence of parameter differences between the two devices. Attached Figure Description

[0020] Figure 1 This is a diagram showing the bidirectional resistive-variable current-voltage characteristic curve of a bidirectional resistive-variable complementary self-selective memristor according to the present invention. Figure 2 This is a current-voltage characteristic curve of a bidirectional resistive-variable complementary self-selective memristor after 100 consecutive cycles according to the present invention. Figure 3 This is a schematic diagram of the carrier transport mechanism of a bidirectional resistive-switched complementary self-selective memristor under different bias voltages and resistive states according to the present invention. Figure 4 This is a Poul-Frank emission fitting result diagram of a bidirectional resistive-switched complementary self-selective memristor according to the present invention; Figure 5 This is a Schottky emitter fitting result diagram of a bidirectional resistive-switched complementary self-selective memristor according to the present invention; Figure 6This is a graph showing the positive low resistance state, negative low resistance state, and differential conductance retention characteristics of a bidirectional resistive-variable complementary self-selective memristor at different temperatures. Figure 7 This is a graph showing the conductivity drift rate of a bidirectional resistive-variable complementary self-selective memristor at different temperatures over time. Figure 8 This is a schematic diagram comparing the structure and working principle of a traditional dual-device differential unit and the single-device differential unit of this invention; Figure 9 This is a distribution diagram of the target differential conductance in a bidirectional resistive-variable complementary self-selective memristor cross array according to the present invention; Figure 10 This is a distribution diagram of the actual differential conductance in a bidirectional resistive-variable complementary self-selective memristor cross array according to the present invention. Figure 11 This invention relates to the differential conductance error probability distribution and fitting curve of a bidirectional resistive-variable complementary self-selective memristor cross array. Detailed Implementation

[0021] To better explain and facilitate understanding of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The present invention provides a bidirectional resistive switching complementary self-selection memristor, which includes a first electrode layer, a first semiconductor functional layer, a high dielectric constant resistive switching barrier layer, a second semiconductor functional layer, and a second electrode layer arranged sequentially along the stacking direction, forming a five-layer structure in which the electrode layer, semiconductor functional layer, high dielectric constant resistive switching barrier layer, semiconductor functional layer, and electrode layer are stacked sequentially.

[0023] The first electrode layer is in direct contact with the first semiconductor functional layer, forming a first interface barrier at their interface. The second electrode layer is in direct contact with the second semiconductor functional layer, forming a second interface barrier at their interface. The first and second electrode layers are made of conductive materials with different work functions, creating an asymmetric relationship between the first and second interface barriers. This asymmetry can manifest as differences in barrier height, barrier width, carrier injection capability, or transport response under opposite bias. One of the first and second electrode layers is made of an inert metal, while the other is made of a metal or alloy with a significantly different work function from the inert metal. The inert metal can be a noble metal such as platinum, gold, palladium, rhodium, or iridium, or an inert alloy; the other electrode can be tantalum, or other metals or alloys capable of forming an asymmetric interface barrier with the inert metal. Both the first and second semiconductor functional layers are made of wide-bandgap semiconductor oxides containing defects, such as indium gallium zinc oxide (IGZO), indium zinc oxide, gallium zinc oxide, zinc oxide, indium oxide, or multi-component composite metal oxide semiconductor materials. Two semiconductor functional layers, made of the same material, are symmetrically disposed on either side of a high-dielectric-constant resistive switching barrier layer with similar or identical thicknesses. Each semiconductor functional layer contains at least one of oxygen vacancies and lattice defects. These defects can form carrier trapping sites and alter carrier concentration, interfacial charge distribution, and carrier injection conditions. The defect concentration and distribution can be adjusted by regulating the oxygen partial pressure, working gas pressure, and deposition power during the deposition process. The two semiconductor functional layers also passivate, screen, and regulate carrier transport at the interface on either side of the high-dielectric-constant resistive switching barrier layer. The high-dielectric-constant resistive switching barrier layer is disposed between and in contact with the two semiconductor functional layers. This high-dielectric-constant resistive switching barrier layer is an insulating or semi-insulating dielectric layer used to form a carrier transport barrier. The high-dielectric-constant resistive switching barrier layer can be made of non-stoichiometric hafnium oxide (HfOx), where x represents the non-stoichiometric coefficient of oxygen, or it can be made of zirconium oxide, aluminum oxide, titanium oxide, tantalum oxide, lanthanide metal oxides, zirconium-hafnium composite oxides, or modified high-dielectric-constant dielectric materials. Under half-select voltage or lower readout voltage, the carrier transport barrier restricts carriers from passing through the device; under the strong electric field generated by the programming voltage, carriers are transported through defect-assisted or field-assisted methods, causing the device to undergo reversible resistive state switching. A specific device structure is a five-layer structure of platinum (Pt) / indium gallium zinc oxide IGZO / hafnium oxide HfOx / indium gallium zinc oxide IGZO / tantalum (Ta), wherein the first electrode layer is made of Pt, the first semiconductor functional layer is made of IGZO, the high-dielectric-constant resistive switching barrier layer is made of HfOx, the second semiconductor functional layer is made of IGZO, and the second electrode layer is made of Ta. Pt forms a metal-semiconductor interface with IGZO, and Ta forms another metal-semiconductor interface with IGZO. The difference in work function between Pt and Ta causes the two interfaces to form an asymmetric potential barrier.

[0024] During fabrication, a single-crystal silicon substrate with an oxide layer was selected. The RCA standard cleaning process was used to remove particulate matter, organic matter, and metallic impurities from the substrate surface. After cleaning, the substrate was dried in a vacuum oven and then transferred to a magnetron sputtering apparatus. Each functional thin film was deposited under vacuum and room temperature conditions. The stack, from bottom to top, consisted of a Ta bottom electrode, a lower IGZO functional layer, an HfOx resistive switching barrier layer, an upper IGZO functional layer, and a Pt top electrode.

[0025] The Ta bottom electrode is formed using DC magnetron sputtering, and then etched into a strip shape using photolithography and dry etching. The lower IGZO functional layer is formed using RF magnetron sputtering, the HfOx resistive switching barrier layer is also formed using RF magnetron sputtering, and the upper IGZO functional layer is formed using the same RF magnetron sputtering process as the lower IGZO functional layer, so that the two IGZO functional layers are symmetrically arranged on both sides of the HfOx resistive switching barrier layer. The Pt top electrode is formed using DC magnetron sputtering, and then etched into a strip shape using photolithography and dry etching. The top and bottom electrodes are arranged perpendicularly and alternately, and their intersection area constitutes the effective working cell of the memristor.

[0026] The device initially operates in a high-resistance state. When the voltage is within the half-selection range of -0.6V to +0.6V, the first interface barrier, the second interface barrier, and the HfOx resistive switching barrier layer collectively restrict carrier injection and transport, maintaining the device in a high-resistance state. When the forward voltage reaches +3.0V to +3.4V, the device switches from a high-resistance state to a positive low-resistance state; applying a negative voltage of -0.8V to -1.2V resets the device from the positive low-resistance state to a high-resistance state. When the negative voltage reaches -3.0V to -3.4V, the device switches from a high-resistance state to a negative low-resistance state; applying a positive voltage of +0.8V to +1.2V resets the device from the negative low-resistance state to a high-resistance state. For example... Figure 1 and Figure 2 As shown, the device can achieve bidirectional resistive switching and maintain stable current-voltage characteristics during 100 consecutive cycle tests. Figure 1 The numbers 1 through 6 in the code represent the sequence of a complete bidirectional voltage scan. Figure 2 The numbers 1-4 in the diagram indicate the order of cyclic scanning, and the arrows indicate the direction of voltage scanning. The hollow circles in the diagram represent selected characteristic operating points, and the dashed lines represent the corresponding auxiliary reading lines. The forward self-rectification ratio is the ratio of the read current in the dominant conduction direction to the suppressed current in the opposite direction when the device is in a forward low-resistance state. The negative self-rectification ratio is the ratio of the read current in the dominant conduction direction to the suppressed current in the opposite direction when the device is in a negative low-resistance state.

[0027] The positive low-resistance state and the negative low-resistance state have opposite dominant conduction directions. When reading a positive low-resistance state, a positive read voltage is used, consistent with the dominant conduction direction of the positive low-resistance state; the reset of a positive low-resistance state uses a negative voltage. Similarly, when reading a negative low-resistance state, a negative read voltage is used; the reset of a negative low-resistance state uses a positive voltage. Therefore, the reading and reset processes are distinguished by the applied polarity, the current resistance state of the device, and the pulse duration. The positive and negative read voltages preferably have the same absolute value, and the reading condition is sufficient to trigger a resistance state switch. Both positive and negative low-resistance states are state categories, and each category can contain multiple low-resistance states with different conductance values.

[0028] like Figures 3 to 5 As shown, when the bias voltage is in the low voltage range of ±0.8V to ±1.3V, carrier transport is dominated by Schottky emission, the device maintains high resistance and exhibits self-selection; when the bias voltage is in the higher voltage range of ±1.5V to ±3.2V, carrier transport is dominated by Purle-Frank emission, and the device undergoes resistive state switching. The interface barrier confinement in the low voltage range and the field-assisted transport in the higher voltage range together form the half-select high resistance, bidirectional resistive switching, and complementary conductivity characteristics. Figure 3 The band structure shown is relative to the vacuum level. The work functions of platinum and tantalum are 5.3 eV and 4.3 eV, respectively; the electron affinity and band gap of indium gallium zinc oxide are 4.2 eV and 3.0 eV, respectively; and the electron affinity and band gap of hafnium oxide are 2.1 eV and 5.5 eV, respectively. In the figure, red solid dots represent electrons, short horizontal lines represent defect or trap levels, arrows indicate carrier migration directions, and red crosses indicate that the corresponding carrier transport path is suppressed. Figure 4 and Figure 5 In the fitting process, the horizontal axis represents the square root of the absolute value of the voltage, the vertical axis represents the natural logarithm of the absolute value of the ratio of current to voltage, the blue data points represent positive bias experimental data, the red data points represent negative bias experimental data, and the black line represents the corresponding fitting result.

[0029] The read voltage when the first electrode layer is at a positive potential relative to the second electrode layer is defined as the positive read voltage, and the read voltage when the first electrode layer is at a negative potential relative to the second electrode layer is defined as the negative read voltage. The conductance of the memristor under the positive read voltage is the positive conductance G+, and the conductance under the negative read voltage is the negative conductance G. Differential conductance ΔG = G+ - G Used to characterize signed weights. A positive weight is associated with a value greater than zero, a negative weight with a value less than zero, and a zero weight is associated with a value equal to zero or located in a preset zero range.

[0030] When using pulse signal control devices, the programming pulse width is 80μs to 120μs, the absolute value of the read voltage is 0.8V to 1.2V, and the read duration is 40μs to 60μs. Through positive and negative pulse sequences, the conductance can be continuously increased and decreased, allowing at least one of the positive and negative conductances to be adjusted to multiple conductance values, thereby forming multiple differential conductance states and achieving multi-level signed weighted adjustment.

[0031] like Figure 6 and Figure 7 As shown, during hold tests at room temperature for 1500s–2500s, there is a certain conductance drift in both the single positive and negative low-resistance states, while the differential conductance drift formed by the positive and negative conductances of the same device is smaller. Using the difference in conductance in the two directions of the same device to characterize the weight can reduce the impact of differences in initial conductance, resistance-state adjustment characteristics, and conductance drift between two independent memristors on the accuracy of the weight.

[0032] The cross array includes multiple first conductors, multiple second conductors, and multiple memristor units respectively disposed at the intersections of each first conductor and each second conductor. Each memristor unit adopts the aforementioned five-layer structure, with the first electrode layer electrically connected to the corresponding first conductor and the second electrode layer electrically connected to the corresponding second conductor. One memristor unit is disposed at each intersection position, and the memristor unit is not connected in series with an independent selection transistor, an independent selection diode, or other independent selection device.

[0033] When programming or reading a selected memristor cell, the selected memristor cell is subjected to a full-select voltage across its terminals, while the non-selected memristor cell, which shares a first or second conductor with the selected memristor cell, is subjected to a half-select voltage across its terminals. The absolute value of the half-select voltage is lower than the absolute value of the resistance-state switching threshold voltage corresponding to its polarity, and therefore insufficient to trigger a resistance-state switching in the non-selected memristor cell, keeping the non-selected memristor cell in a high-resistance state, thereby reducing leakage current and crosstalk current in the non-selected conductive path.

[0034] During array reading, positive and negative read voltages of opposite polarities with the same absolute value are applied sequentially to the same memristor cell to obtain the positive and negative read conductances, respectively. The difference between these two conductances represents the signed weight of the corresponding memristor cell. The array completes the reading of the two polarities according to a predetermined timing sequence and obtains differential outputs. It is not necessary to set two memristors at each crossover position, nor is it necessary to set independent subtraction structures inside the cell.

[0035] like Figures 8 to 11As shown, after constructing a 32×32 passive cross array using memristors, the quantized weight gradients of a convolutional neural network can be mapped to the array cells. Parallel weight updates and differential operations are achieved through bidirectional conductance adjustment of the device. The error between the actual array weights and the target weights can be controlled within ±0.03μS. The cross array can be used for storage, in-memory computing, and neuromorphic computing, and multiplication-accumulation operations are achieved by summing the currents in each row or column. Figure 8 In this context, W represents the signed weight characterized by the differential conductance, i.e., W = ΔG = G+ G . This represents the set voltage of a traditional differential unit. and These represent the positive and negative set voltages of the differential unit of a single device in this invention, respectively. This indicates the voltage being read. This indicates leakage current formed through a non-selected conductive path; a red cross indicates that the corresponding leakage path is suppressed. A multiplexer (MUX) is used to select the appropriate bit line read channel; the triangular circuit symbol in a traditional dual-device differential unit represents a differential read or differential amplifier circuit. Figure 9 and Figure 10 In the diagram, the horizontal axis represents the bit line number, and the vertical axis represents the word line number. Each color block corresponds to a memristor cell in a 32×32 cross array. The color of the color block represents the differential conductance value of that cell, in micro-Siemens (μS); red indicates positive differential conductance, blue indicates negative differential conductance, and white indicates differential conductance close to zero. Figure 11 The weighted error in the diagram is represented by differential conductance, with units of μS. The vertical axis percentage represents the proportion of array elements within the corresponding error interval to the total number of array elements.

[0036] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make modifications, alterations, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A bidirectional resistive-variable complementary self-selective memristor, characterized in that, It includes a first electrode layer, a first semiconductor functional layer, a high dielectric constant resistive switching barrier layer, a second semiconductor functional layer, and a second electrode layer arranged sequentially along the stacking direction. The first electrode layer and the first semiconductor functional layer form a first interface barrier, and the second electrode layer and the second semiconductor functional layer form a second interface barrier. The first electrode layer and the second electrode layer have different work functions, and the first interface barrier and the second interface barrier are asymmetrical. The first interface barrier, the second interface barrier, and the high dielectric constant resistive switching barrier layer together enable the memristor to form a positive low-resistance state under the action of a positive programming voltage in which the first electrode layer is at a positive potential relative to the second electrode layer, and a negative low-resistance state under the action of a negative programming voltage in which the first electrode layer is at a negative potential relative to the second electrode layer. In the positive low-resistance state, the dominant conduction direction of the memristor is positive, and in the negative low-resistance state, the dominant conduction direction of the memristor is negative, causing the memristor to be in a high-resistance state under the action of half-select voltage.

2. The bidirectional resistive-variable complementary self-selective memristor according to claim 1, characterized in that, One of the first electrode layer and the second electrode layer is an inert metal electrode layer, and the other is a metal or alloy electrode layer.

3. The bidirectional resistive-variable complementary self-selective memristor according to claim 1, characterized in that, The high dielectric constant resistive switching barrier layer is an insulating or semi-insulating dielectric layer used to form a carrier transport barrier; the carrier transport barrier restricts carrier transport under half-selection voltage and generates field-assisted carrier transport under programming voltage.

4. The bidirectional resistive-variable complementary self-selective memristor according to claim 1, characterized in that, Both the first semiconductor functional layer and the second semiconductor functional layer are wide bandgap semiconductor oxide layers containing defects, which are used to regulate carrier injection and carrier transport at the corresponding interfaces.

5. The bidirectional resistive-variable complementary self-selective memristor according to claim 4, characterized in that, The defects in the wide bandgap semiconductor oxide layer include at least one of oxygen vacancies and lattice defects.

6. The bidirectional resistive-variable complementary self-selective memristor according to claim 1, characterized in that, The read voltage when the first electrode layer is at a positive potential relative to the second electrode layer is defined as the positive read voltage, and the read voltage when the first electrode layer is at a negative potential relative to the second electrode layer is defined as the negative read voltage; the conductance of the memristor under the positive read voltage is the positive conductance, and the conductance under the negative read voltage is the negative conductance; In the forward low-resistance state, the forward conductance is greater than the negative conductance; in the negative low-resistance state, the negative conductance is greater than the forward conductance.

7. The bidirectional resistive-variable complementary self-selective memristor according to claim 6, characterized in that, At least one of the positive conductance and the negative conductance can be adjusted to multiple conductance values ​​under the action of a programmed pulse sequence to adjust the difference between the positive conductance and the negative conductance; the difference is used to characterize the signed weight.

8. A bidirectional resistive-variable complementary self-selective memristor cross array, characterized in that, It includes multiple first wires, multiple second wires, and multiple memristor units respectively disposed at the intersection of each first wire and each second wire; Each memristor unit is a bidirectional resistive-switching complementary self-selecting memristor as described in claim 1, wherein the first electrode layer and the second electrode layer of the memristor unit are electrically connected to the corresponding first wire and the second wire, respectively, and each memristor unit is not connected in series with an independent selection device.

9. The bidirectional resistive-variable complementary self-selective memristor cross array according to claim 8, characterized in that, The read voltage when the first electrode layer is at a positive potential relative to the second electrode layer is defined as the positive read voltage, and the read voltage when the first electrode layer is at a negative potential relative to the second electrode layer is defined as the negative read voltage. Each memristor cell has a positive conductance and a negative conductance under the positive read voltage and the negative read voltage, respectively, and the difference between the positive conductance and the negative conductance is used to characterize the signed weight.

10. The bidirectional resistive-variable complementary self-selective memristor cross array according to claim 8, characterized in that, When programming or reading a selected memristor cell, the selected memristor cell is subjected to a full selection voltage across its terminals, while the non-selected memristor cells that share the first or second wire with the selected memristor cell are subjected to a half selection voltage across their terminals. The absolute value of the half-selection voltage is lower than the absolute value of the resistive switching threshold voltage corresponding to its polarity.

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