Error mitigation method and related apparatus

Abstract

This invention discloses an error mitigation method and related apparatus. The method includes: constructing a quantum detection circuit containing a target quantum logic gate; obtaining the probability distribution value of the quantum state of the target quantum bit corresponding to each rotation angle by changing the rotation angle of the single-qubit rotation gate applied to the target quantum bit in the quantum detection circuit; fitting the relationship between the probability distribution value affected by phase deviation and the rotation angle using all probability distribution values; determining the phase deviation angle value of the target quantum logic gate using the fitted relationship; constructing a quantum circuit for execution on a quantum chip, and applying a target quantum rotation gate with a rotation angle value opposite to the determined phase deviation angle value after the target quantum logic gate of the quantum circuit. This application further improves the overall reliability of quantum computing by measuring and mitigating the phase angle deviation generated by the target quantum logic gate executed on the quantum circuit.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically an error mitigation method and related apparatus. Background Technology

[0002] In quantum computing, the gate bias problem refers to the deviation between the actual operation and the ideal operation during quantum gate operation, which affects the overall accuracy of quantum computing. Ideally, quantum gate operation should precisely realize a specific quantum state transformation. However, in actual execution, due to various factors, the operation effect is difficult to completely match the theoretical expectation, resulting in deviations in the evolution of quantum states. The specific reasons for this may be due to the non-ideal characteristics of qubits and the imprecision of quantum gate operation, or environmental noise and quantum decoherence phenomena generated by the interaction between the quantum system and its surrounding environment. Gate bias causes the evolution of quantum states to deviate from the ideal path, resulting in errors in the output results of quantum algorithms. As the scale of quantum computing increases and the depth of quantum circuits increases, gate bias will continue to accumulate and amplify, ultimately reducing the overall reliability of quantum computing.

[0003] In existing technologies, solutions to the gate bias problem, such as dynamic decoupling, can suppress the interaction between qubits and the environment, reducing decoherence and gate bias. However, its sequence design is complex, requiring precise control of pulse parameters, which may introduce new errors and increase system complexity and computation time. Readout error mitigation techniques can correct errors in the measurement process, improve measurement accuracy, and indirectly reduce the impact of gate bias. However, the accuracy of obtaining the calibration matrix is ​​difficult to guarantee, and the application of the calibration matrix for correction may introduce new errors. Therefore, for the gate bias problem in quantum computing, there is an urgent need for a solution that can efficiently solve the gate bias problem to improve the overall reliability of quantum computing. Summary of the Invention

[0004] The purpose of this invention is to provide an error mitigation method and related apparatus, which aims to measure and mitigate the phase angle deviation generated by the target quantum logic gate executed on the quantum circuit, thereby further improving the overall reliability of quantum computing.

[0005] One embodiment of the present invention provides an error mitigation method, the method comprising:

[0006] Construct a quantum detection circuit containing a target quantum logic gate; wherein the target quantum logic gate is a two-qubit quantum logic gate that generates a phase deviation, and the quantum detection circuit is a quantum circuit used to determine the phase deviation of the target quantum logic gate;

[0007] By changing the rotation angle of the single-qubit rotation gate applied to the target qubit in the quantum detection circuit, the probability distribution value of the quantum state of the target qubit corresponding to each rotation angle is obtained;

[0008] Using all probability distribution values, the relationship between the probability distribution values ​​affected by phase deviation and the rotation angle is obtained by fitting.

[0009] The phase deviation angle value of the target quantum logic gate is determined by using the fitted variation relationship;

[0010] Construct a quantum circuit for execution on a quantum chip, and apply a target quantum rotation gate after the target quantum logic gate of the quantum circuit with a rotation angle value opposite to a determined phase deviation angle value.

[0011] Optionally, the quantum detection circuit is a two-qubit qubit, comprising, in sequence:

[0012] A quantum rotation gate applied to each qubit, a target quantum logic gate applied to two qubits, and a quantum rotation gate applied to the target qubit.

[0013] Optionally, the step of fitting the relationship between the probability distribution values ​​affected by the phase deviation and the rotation angle using all probability distribution values ​​includes:

[0014] Based on the quantum detection circuit structure, the probability distribution function of the quantum state of the target qubit affected by phase deviation is determined;

[0015] Based on the probability distribution function, using all the probability distribution values, the relationship between the probability distribution values ​​affected by the phase deviation and the rotation angle is fitted.

[0016] Optionally, the step of fitting the relationship between the probability distribution value affected by the phase deviation and the rotation angle based on the probability distribution function and all probability distribution values ​​includes:

[0017] The probability distribution function is subjected to parameter fixing, and all probability distribution values ​​are used to fit the processed probability distribution function to obtain the relationship between the probability distribution value of a quantum state of the target qubit and the rotation angle.

[0018] Optionally, the fitted variation relationship includes the fitted value of the phase deviation angle parameter;

[0019] Determining the phase deviation angle of the target quantum logic gate by utilizing the fitted variation relationship includes:

[0020] By fitting the relationship of change, the fitted values ​​of the parameter terms including the phase deviation angle are determined;

[0021] The phase deviation angle value of the target quantum logic gate is determined by using the determined fitted value and the relationship between the fitted value and the phase deviation angle.

[0022] Optionally, the target quantum logic gate is a CZ gate; the target quantum rotation gate is an RZ gate.

[0023] Another embodiment of the present invention provides an error mitigation device, characterized in that the device comprises:

[0024] A construction unit is used to construct a quantum detection circuit containing a target quantum logic gate; wherein the target quantum logic gate is a two-qubit quantum logic gate that generates a phase deviation, and the quantum detection circuit is a quantum circuit used to determine the phase deviation of the target quantum logic gate;

[0025] The acquisition unit is used to obtain the probability distribution value of the quantum state of the target quantum bit corresponding to each rotation angle by changing the rotation angle of the single-qubit rotation gate applied to the target quantum bit in the quantum detection circuit;

[0026] The fitting unit is used to fit the relationship between the probability distribution values ​​affected by the phase deviation and the rotation angle using all probability distribution values;

[0027] A determining unit is used to determine the phase deviation angle value of the target quantum logic gate by utilizing the fitted variation relationship;

[0028] A mitigation unit is used to construct a quantum circuit for execution on a quantum chip, applying a target quantum rotation gate with a rotation angle value opposite to a determined phase deviation angle value after the target quantum logic gate of the quantum circuit.

[0029] Another embodiment of the present invention provides an electronic device, wherein the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, perform the methods described in any of the above embodiments.

[0030] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, perform the methods described in any of the above embodiments.

[0031] Another embodiment of the present invention provides a quantum computer operating system, which mitigates phase deviation errors in quantum computing according to the method described in any of the above embodiments.

[0032] Compared with existing technologies, this invention provides an error mitigation method. First, a quantum detection circuit containing a target quantum logic gate is constructed. The target quantum logic gate is a two-qubit quantum logic gate that generates a phase deviation, and the quantum detection circuit is a quantum circuit used to determine the phase deviation of the target quantum logic gate. Then, by changing the rotation angle of the single-qubit rotation gate applied to the target qubit in the quantum detection circuit, the probability distribution value of the quantum state of the target qubit corresponding to each rotation angle is obtained. Next, using all probability distribution values, the relationship between the probability distribution value affected by the phase deviation and the rotation angle is fitted. Then, using the fitted relationship, the phase deviation angle value of the target quantum logic gate is determined. Finally, a quantum circuit for execution on a quantum chip is constructed, and a rotation angle value opposite to the determined phase deviation angle value is applied after the target quantum logic gate of the quantum circuit. This application proposes a target quantum rotation gate. By constructing a quantum detection circuit, it provides a concrete way to obtain phase deviation information through the measurement of quantum states. By changing the rotation angle of a single-qubit rotation gate, the probability distribution values ​​of the quantum states of the target qubit at different rotation angles are obtained. The probability distribution values ​​at different rotation angles reflect the degree and manner in which the phase deviation of the target quantum logic gate affects the quantum states. The relationship between the obtained different rotation angles and the probability distribution of quantum states provides a basis for subsequent fitting of the change relationship. By fitting the change relationship, the phase deviation angle value of the target quantum logic gate can be determined. Finally, by applying a target quantum rotation gate with a rotation angle value opposite to the measured phase deviation angle value after the target quantum logic gate of the quantum circuit to be executed, the phase deviation generated by the target quantum logic gate can be canceled, thereby effectively mitigating errors and improving the overall accuracy of quantum computing. Attached Figure Description

[0033] Figure 1 This is a network block diagram of an error mitigation system provided in an embodiment of the present invention.

[0034] Figure 2 A flowchart of an error mitigation method provided in an embodiment of the present invention.

[0035] Figure 3(a) is a schematic diagram of a quantum detection circuit provided in an embodiment of the present invention.

[0036] Figure 3(b) is a schematic diagram of a quantum circuit actually executed by a CZ gate according to an embodiment of the present invention.

[0037] Figure 4 This is a flowchart for obtaining a fitting change relationship according to an embodiment of the present invention.

[0038] Figure 5 This is a flowchart of a method for determining a phase deviation angle provided in an embodiment of the present invention.

[0039] Figure 6 This is a structural diagram of an error mitigation device provided in an embodiment of the present invention.

[0040] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0041] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0042] Figure 1 This is a network block diagram of an error mitigation system provided in an embodiment of the present invention. The error mitigation system may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0043] Network 110 is a medium used to provide communication links between various devices and computers connected together within a fault mitigation system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof, and the connection method can be wired, wireless communication links, or fiber optic cables.

[0044] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0045] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled according to the error mitigation method provided in the embodiments of the present invention.

[0046] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0047] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0048] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0049] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0050] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0051] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0052] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0053] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0054] In the field of quantum computing, the gate bias problem refers to the deviation between the actual operation and the ideal operation during quantum gate operations, which affects the overall accuracy of quantum computing. Ideally, quantum gate operations should precisely realize specific quantum state transformations, but in actual execution...

[0055] Due to various factors, the operational results are difficult to fully meet theoretical expectations, leading to deviations in the evolution of quantum states. The specific reasons for this may be due to the non-ideal characteristics of qubits and the imprecision of quantum gate operations, or environmental noise and quantum decoherence phenomena generated by the interaction between the quantum system and its surrounding environment. Gate deviations cause the evolution of quantum states to deviate from the ideal path, resulting in errors in the output of quantum algorithms. As the scale of quantum computing increases and the depth of quantum circuits increases, gate deviations will continue to accumulate and amplify, ultimately reducing the overall reliability of quantum computing.

[0056] In existing technologies, solutions to the gate bias problem, such as dynamic decoupling, can suppress the interaction between qubits and the environment, reducing decoherence and gate bias. However, its sequence design is complex, requiring precise control of pulse parameters, which may introduce new errors and increase system complexity and computation time. Readout error mitigation techniques can correct errors in the measurement process, improve measurement accuracy, and indirectly reduce the impact of gate bias. However, the accuracy of obtaining the calibration matrix is ​​difficult to guarantee, and the application of the calibration matrix for correction may introduce new errors. Therefore, for the gate bias problem in quantum computing, there is an urgent need for a solution that can efficiently solve the gate bias problem to improve the overall reliability of quantum computing.

[0057] See Figure 2 , Figure 2 An error mitigation method provided in this embodiment of the invention includes the following steps:

[0058] Step S201: Construct a quantum detection circuit containing a target quantum logic gate; wherein, the target quantum logic gate is a two-bit quantum logic gate that generates a phase deviation, and the quantum detection circuit is a quantum circuit used to determine the phase deviation of the target quantum logic gate.

[0059] Specifically, a quantum detection circuit containing a target quantum logic gate is constructed. The target quantum logic gate, as the research object of this application, is characterized as a two-qubit quantum logic gate that will produce a phase deviation. The quantum detection circuit is a quantum circuit used to determine the phase deviation value of the target quantum logic gate.

[0060] For example, see Figure 3(a), which is a schematic diagram of a quantum detection circuit provided in an embodiment of the present invention.

[0061] Step S202: By changing the rotation angle of the single-qubit rotating gate applied to the target qubit in the quantum detection circuit, the probability distribution value of the quantum state of the target qubit corresponding to each rotation angle is obtained.

[0062] Specifically, by changing the rotation angle of the single-qubit rotation gate of the target qubit in the quantum detection circuit, the probability distribution value of the quantum state of the target qubit corresponding to each rotation angle is obtained.

[0063] For example, in Figure 3(a), the probability distribution of the quantum state of the target qubit is obtained by changing the rotation angle in the RY gate in the upper left corner.

[0064] Step S203: Using all probability distribution values, fit the relationship between the probability distribution values ​​affected by phase deviation and the rotation angle.

[0065] Specifically, the probability distribution value of the quantum state of the target qubit corresponding to each rotation angle is fitted to obtain the relationship between the fitted probability distribution value affected by the phase deviation and the rotation angle.

[0066] Step S204: Determine the phase deviation angle value of the target quantum logic gate using the fitted change relationship.

[0067] Specifically, the phase deviation angle value of the target quantum logic gate can be obtained by fitting the change relationship.

[0068] Step S205: Construct a quantum circuit for execution on a quantum chip, and apply a target quantum rotation gate with a rotation angle value opposite to the determined phase deviation angle value after the target quantum logic gate of the quantum circuit.

[0069] Specifically, a quantum circuit is constructed for execution on a quantum chip, and a target quantum rotation gate with a rotation angle value opposite to the phase deviation angle value obtained through the quantum detection circuit is applied after the target quantum logic gate that generates phase deviation, in order to mitigate the generated phase deviation error.

[0070] For example, see Figure 3(b). Figure 3(b) is a schematic diagram of a quantum circuit of a CZ gate in actual execution according to an embodiment of the present invention. A target quantum rotation gate RZ' with a rotation angle value opposite to the determined phase deviation angle value is applied after the target quantum logic gate CZ gate that generates phase deviation, so as to cancel the phase deviation error generated by the CZ gate.

[0071] In summary, this invention first constructs a quantum detection circuit containing a target quantum logic gate; wherein the target quantum logic gate is a two-qubit quantum logic gate that generates a phase deviation, and the quantum detection circuit is a quantum circuit used to determine the phase deviation of the target quantum logic gate; then, by changing the rotation angle of the single-qubit rotation gate applied to the target qubit in the quantum detection circuit, the probability distribution value of the quantum state of the target qubit corresponding to each rotation angle is obtained; next, using all probability distribution values, the relationship between the probability distribution value affected by the phase deviation and the rotation angle is fitted; secondly, the phase deviation angle value of the target quantum logic gate is determined using the fitted relationship; finally, a quantum circuit for execution on a quantum chip is constructed, and a target quantum rotation gate with a rotation angle value opposite to the determined phase deviation angle value is applied after the target quantum logic gate of the quantum circuit. This application provides a concrete way to obtain phase deviation information through quantum state measurement by constructing a quantum detection circuit. By changing the rotation angle of the single-qubit rotation gate, the probability distribution values ​​of the quantum state of the target qubit under different rotation angles are obtained. The probability distribution values ​​under different rotation angles reflect the degree and manner of the influence of the phase deviation of the target quantum logic gate on the quantum state. The relationship between the obtained different rotation angles and the quantum state probability distribution provides a basis for subsequent fitting of the change relationship. By fitting the change relationship, the phase deviation angle value of the target quantum logic gate can be determined. Finally, by applying the target quantum rotation gate with a rotation angle value opposite to the measured phase deviation angle value after the target quantum logic gate of the quantum circuit to be executed, the phase deviation generated by the target quantum logic gate can be canceled, thereby effectively mitigating errors and improving the overall accuracy of quantum computing.

[0072] In one embodiment of the present invention, the quantum detection circuit is a two-qubit qubit, comprising:

[0073] A quantum rotation gate applied to each qubit, a target quantum logic gate applied to two qubits, and a quantum rotation gate applied to the target qubit.

[0074] Specifically, the construction of a quantum detection circuit includes, in sequence, a quantum rotation gate applied to each qubit in the same execution sequence, a target quantum logic gate applied to the two qubits, and a quantum rotation gate applied to the target qubit.

[0075] For example, in Figure 3(a), which is a schematic diagram of a quantum detection circuit provided by an embodiment of the present invention, the construction of the quantum detection circuit includes, in sequence, two RY gates applied to each qubit in the same execution time sequence, a target quantum logic gate CZ gate applied to the two qubits, and an RY gate applied to the target qubit.

[0076] See Figure 4 , Figure 4 A flowchart for obtaining a fitting change relationship provided in an embodiment of the present invention includes the following steps:

[0077] Step S401: Based on the quantum detection circuit structure, determine the probability distribution function of the quantum state of the target qubit affected by the phase deviation.

[0078] Specifically, based on the structure of the quantum detection circuit designed in this application, the probability distribution function of the quantum state of the target qubit affected by phase deviation can be determined.

[0079] For example, based on the schematic diagram of a quantum detection circuit shown in Figure 3(a), the probability distribution function of the quantum state of the target qubit affected by phase deviation can be obtained. That is, let the rotation angles of the two RY gates on the left be a and b, let the phase deviation angle generated by the CZ gate be c, and let the angle of the last RY gate be d. The probability distribution of the 0 state of qubit q0 can be calculated as follows:

[0080]

[0081] Step S402: Based on the probability distribution function, use all the probability distribution values ​​to fit the relationship between the probability distribution values ​​affected by the phase deviation and the rotation angle.

[0082] Specifically, based on the probability distribution function and by changing the rotation angle of the single-qubit rotation gate of the target qubit, all probability distribution values ​​are obtained. By fitting all the probability distribution values, the relationship between the probability distribution values ​​affected by the phase deviation and the rotation angle can be obtained.

[0083] For example, based on the probability distribution function in step S401 above, by fixing angles b and d and assuming that the phase deviation angle c is also constant, a series of probability distribution values ​​of the 0 state of quantum bit q0 can be obtained by continuously changing the value of the rotation angle a. By fitting this series of probability distribution values, the relationship between the probability distribution value affected by the phase deviation and the rotation angle can be obtained.

[0084] In one embodiment of this application, the step of fitting the relationship between the probability distribution value affected by the phase deviation and the rotation angle based on the probability distribution function and all probability distribution values ​​includes:

[0085] The probability distribution function is subjected to parameter fixing, and all probability distribution values ​​are used to fit the processed probability distribution function to obtain the relationship between the probability distribution value of a quantum state of the target qubit and the rotation angle.

[0086] Specifically, by fixing the parameters of the probability distribution function obtained in step S401 above, the functional transformation relationship of the probability distribution of the quantum state of the target qubit can be obtained. Based on this functional transformation relationship, by fitting a series of probability distribution values ​​obtained by changing the rotation angle, the change relationship of the probability distribution value of a quantum state of the target qubit with the rotation angle can be obtained.

[0087] For example, the probability distribution function obtained in step S401 above... By fixing parameters b, d, and c, the mathematical function transformation relationship of the probability distribution of the quantum states of the target qubit can be obtained. The trigonometric function relationship can be obtained by changing the values ​​of multiple rotation angles 'a'. By fitting the Bcos(a+t)+m function to it, the probability distribution value of a quantum state of the target qubit can be obtained as a function of rotation angle.

[0088] In summary, by determining the quantum state probability distribution function of the target qubit affected by phase deviation based on a specific quantum detection circuit structure, an accurate theoretical model is provided for subsequent fitting operations, giving the fitting process a clear mathematical basis. Then, by using this function and the actual measured probability distribution values, the relationship between the probability distribution value affected by phase deviation and the rotation angle is obtained, intuitively presenting the influence law of phase deviation on the probability distribution. This allows for the effective application of a compensating rotation gate in subsequent steps to mitigate errors caused by phase deviation, improving the accuracy and reliability of error mitigation methods in quantum computing.

[0089] In one embodiment of this application, the fitted variation relationship includes the fitted value of the phase deviation angle parameter;

[0090] Specifically, in the previous embodiment, the mathematical function transformation relationship of obtaining the probability distribution of the quantum state of the target qubit is described. This is a trigonometric function that varies with the rotation angle 'a'. Different values ​​of 'c' will change the corresponding amplitude 'A' and phase 't'. Through function derivation, we can obtain... t = arctan(tan dcosb cosc), after obtaining a series of probability distribution values, and fitting them with the Bcos(a+t)+m function, where t is the fitted value of the parameter including the phase deviation angle.

[0091] See Figure 5 , Figure 5 A flowchart of a phase deviation angle determination method provided in an embodiment of the present invention includes the following steps:

[0092] Step S501: By fitting the change relationship, determine the fitted value of the parameter including the phase deviation angle.

[0093] Specifically, by fitting the relationship of change, the fitted value t of the parameter including the phase deviation angle can be determined.

[0094] Step S502: Using the determined fitting value and the relationship between the fitting value and the phase deviation angle, determine the phase deviation angle value of the target quantum logic gate.

[0095] Specifically, by using the determined fitted value and the relationship between the fitted value and the phase deviation angle, the phase deviation angle value of the target quantum logic gate can be determined.

[0096] For example, using the determined fitted value t and the relationship between the fitted value and the phase deviation angle t = arctan(tandcosb cosc), the phase deviation angle value of the target quantum logic gate can be obtained. Here, b and d are preset constants.

[0097] In summary, by extracting key information from the fitted variation relationship and accurately calculating the phase deviation angle value, crucial support is provided for error mitigation in quantum computing, which helps improve the accuracy and reliability of quantum computing.

[0098] In one embodiment of the present invention, the target quantum logic gate is a CZ gate; the target quantum rotation gate is an RZ gate.

[0099] The target quantum logic gate is a CZ gate. In reality, the physical implementation of a CZ gate is not ideal. The actual quantum gate deviates from the ideal quantum logic gate by a certain phase. It can be understood that the actual CZ gate is the ideal CZ gate plus two extra RZ gates.

[0100] See Figure 6 , Figure 6 An error mitigation device provided in an embodiment of the present invention may include a construction unit 601, an acquisition unit 602, a fitting unit 603, a determination unit 604, and a mitigation unit 605, wherein:

[0101] Construction unit 601 is used to construct a quantum detection circuit containing a target quantum logic gate; wherein, the target quantum logic gate is a two-bit quantum logic gate that generates a phase deviation, and the quantum detection circuit is a quantum circuit used to determine the phase deviation of the target quantum logic gate.

[0102] Specifically, the quantum detection circuit is a two-qubit qubit, comprising:

[0103] A quantum rotation gate applied to each qubit, a target quantum logic gate applied to two qubits, and a quantum rotation gate applied to the target qubit.

[0104] The obtaining unit 602 is used to obtain the probability distribution value of the quantum state of the target quantum bit corresponding to each rotation angle by changing the rotation angle of the single-qubit rotation gate applied to the target quantum bit in the quantum detection circuit.

[0105] Fitting unit 603 is used to fit the relationship between the probability distribution value affected by phase deviation and the rotation angle using all probability distribution values.

[0106] Specifically, the step of fitting the relationship between the probability distribution values ​​affected by phase deviation and the rotation angle using all probability distribution values ​​includes:

[0107] Based on the quantum detection circuit structure, the probability distribution function of the quantum state of the target qubit affected by phase deviation is determined.

[0108] Based on the probability distribution function, using all the probability distribution values, the relationship between the probability distribution values ​​affected by the phase deviation and the rotation angle is fitted.

[0109] Specifically, the step of fitting the relationship between the probability distribution value affected by the phase deviation and the rotation angle based on the probability distribution function and all probability distribution values ​​includes:

[0110] The probability distribution function is subjected to parameter fixing, and all probability distribution values ​​are used to fit the processed probability distribution function to obtain the relationship between the probability distribution value of a quantum state of the target qubit and the rotation angle.

[0111] The determining unit 604 is used to determine the phase deviation angle value of the target quantum logic gate by utilizing the fitted change relationship.

[0112] Specifically, the fitted relationship includes the fitted value of the phase deviation angle parameter.

[0113] Determining the phase deviation angle of the target quantum logic gate by utilizing the fitted variation relationship includes:

[0114] By fitting the changing relationship, the fitted values ​​of the parameter terms, including the phase deviation angle, are determined.

[0115] The phase deviation angle value of the target quantum logic gate is determined by using the determined fitted value and the relationship between the fitted value and the phase deviation angle.

[0116] The mitigation unit 605 is used to construct a quantum circuit for execution on a quantum chip, and to apply a target quantum rotation gate with a rotation angle value opposite to a determined phase deviation angle value after the target quantum logic gate of the quantum circuit.

[0117] Specifically, the target quantum logic gate is a CZ gate; the target quantum rotation gate is an RZ gate.

[0118] The specific functions and effects of the aforementioned error mitigation device can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the error mitigation device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in the computer device in hardware form, or it can be stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0119] Please see Figure 7 This specification also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the error mitigation method described in any of the above embodiments. Please refer to... Figure 7 The electronic device can be a classical computer or a quantum computer.

[0120] This specification also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the error mitigation method described in any of the above embodiments.

[0121] This specification also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the error mitigation method described in any of the above embodiments.

[0122] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0123] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0124] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0125] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0126] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0127] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0128] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0129] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0130] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0131] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0132] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0133] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0134] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. An error mitigation method, characterized in that, The method includes: Construct a quantum detection circuit containing a target quantum logic gate; wherein the target quantum logic gate is a two-qubit quantum logic gate that generates a phase deviation, and the quantum detection circuit is a quantum circuit used to determine the phase deviation of the target quantum logic gate; By changing the rotation angle of the single-qubit rotation gate applied to the target qubit in the quantum detection circuit, the probability distribution value of the quantum state of the target qubit corresponding to each rotation angle is obtained; Using all probability distribution values, the relationship between the probability distribution values ​​affected by phase deviation and the rotation angle is obtained by fitting. The phase deviation angle value of the target quantum logic gate is determined by using the fitted variation relationship; Construct a quantum circuit for execution on a quantum chip, and apply a target quantum rotation gate after the target quantum logic gate of the quantum circuit with a rotation angle value opposite to a determined phase deviation angle value.

2. The method according to claim 1, characterized in that, The quantum detection circuit consists of two qubits, comprising: A quantum rotation gate applied to each qubit, a target quantum logic gate applied to two qubits, and a quantum rotation gate applied to the target qubit.

3. The method according to claim 1, characterized in that, The process of fitting the relationship between the probability distribution values ​​affected by phase deviation and the rotation angle using all probability distribution values ​​includes: Based on the quantum detection circuit structure, the probability distribution function of the quantum state of the target qubit affected by phase deviation is determined; Based on the probability distribution function, using all the probability distribution values, the relationship between the probability distribution values ​​affected by the phase deviation and the rotation angle is fitted.

4. The method according to claim 3, characterized in that, The process of fitting the relationship between the probability distribution values ​​affected by phase deviation and the rotation angle based on the probability distribution function and all probability distribution values ​​includes: The probability distribution function is subjected to parameter fixing, and all probability distribution values ​​are used to fit the processed probability distribution function to obtain the relationship between the probability distribution value of a quantum state of the target qubit and the rotation angle.

5. The method according to claim 1, characterized in that, The fitted relationship includes the fitted value of the phase deviation angle parameter. Determining the phase deviation angle of the target quantum logic gate by utilizing the fitted variation relationship includes: By fitting the relationship of change, the fitted values ​​of the parameter terms including the phase deviation angle are determined; The phase deviation angle value of the target quantum logic gate is determined by using the determined fitted value and the relationship between the fitted value and the phase deviation angle.

6. The method according to claim 1, characterized in that, The target quantum logic gate is a CZ gate; the target quantum rotation gate is an RZ gate.

7. An error mitigation device, characterized in that, The device includes: A construction unit is used to construct a quantum detection circuit containing a target quantum logic gate; wherein, the target quantum logic gate is a two-qubit quantum logic gate that generates a phase deviation, and the quantum detection circuit is a quantum circuit used to determine the phase deviation of the target quantum logic gate; The acquisition unit is used to obtain the probability distribution value of the quantum state of the target quantum bit corresponding to each rotation angle by changing the rotation angle of the single-qubit rotation gate applied to the target quantum bit in the quantum detection circuit; The fitting unit is used to fit the relationship between the probability distribution values ​​affected by the phase deviation and the rotation angle using all probability distribution values; A determining unit is used to determine the phase deviation angle value of the target quantum logic gate by utilizing the fitted variation relationship; A mitigation unit is used to construct a quantum circuit for execution on a quantum chip, applying a target quantum rotation gate with a rotation angle value opposite to a determined phase deviation angle value after the target quantum logic gate of the quantum circuit.

8. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claims 1-6.

10. A quantum computer operating system, characterized in that, The quantum computer operating system is described in any one of claims 1-6 to mitigate phase deviation errors in quantum computing.

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