A quantum error correction code construction method based on address array symmetry constraint and a system thereof

Abstract

The application discloses a quantum error correction code construction method and system based on address array symmetry constraint. The method encodes logical quantum bits as address pairs which are symmetric about the central symmetry axis in the isosceles trapezoidal address array; detects errors by reading the offset direction and offset amplitude of the address pairs relative to the central symmetry axis once; diagnoses error types according to the symmetry breaking mode; and maps the deviated address pairs back to the central symmetric position through error correction rearrangement operation to complete error correction. The application can complete error detection and diagnosis by single reading, each layer can perform error correction in parallel, the error correction time is irrelevant to the number of quantum bits, and is suitable for superconducting, ion trap, photon and other quantum computing platforms.

Description

Technical Field

[0001] This invention relates to the fields of quantum information and quantum error correction technology, specifically to a method and system for constructing quantum error-correcting codes based on address array symmetry constraints. This invention can be applied to error-correcting coding in various quantum computing platforms, including superconducting qubits, ion trap qubits, and optical qubits. Background Technology

[0002] Quantum error-correcting codes are a core technology in fault-tolerant quantum computing. Current mainstream quantum error-correcting codes detect and correct errors through redundant coding. However, these schemes suffer from two fundamental problems: enormous measurement overhead—each logical qubit requires the measurement of a large number of physical qubits; and error type diagnosis requires repeated measurements across multiple measurement bases. For example, surface codes require hundreds of physical qubits and thousands of measurements per logical qubit, which severely limits the scalability of quantum computing. Existing quantum error correction schemes have the following shortcomings: (i) The measurement overhead is huge. Mainstream quantum error-correcting codes such as surface codes and color codes require frequent measurements of a large number of physical qubits. The physical resources required for each logical qubit increase with the square of the code distance, which is difficult to realize on a large scale under existing quantum hardware conditions. (ii) Error type diagnosis requires multiple measurements. Traditional error correction codes require repeated measurements on multiple measurement bases to determine the error type. Each measurement introduces additional errors and consumes a lot of measurement time. (iii) Delay in error correction. In existing solutions, error detection requires the collection of a large number of measurement results, and then the error location and type are determined by classical computation decoding. The decoding delay leads to untimely error correction. (iv) Separation of physical layer and logic layer. In the existing scheme, error detection in the physical layer and error correction in the logic layer are separated, and the physical layer lacks direct error diagnosis information feedback to the logic layer. Therefore, existing quantum error correction schemes suffer from high measurement overhead, slow error diagnosis, and disconnect between the physical and logic layers. There is still no error correction scheme that can achieve low-overhead error detection and diagnosis through geometric symmetry observation. To address the above problems, this invention provides a method and system for constructing quantum error-correcting codes based on address array symmetry constraints. Summary of the Invention

[0003] This invention aims to solve the technical problems of huge measurement overhead and repeated measurements required for error type diagnosis in existing quantum error correction schemes. It provides a quantum error correction code construction method and system based on address array symmetry constraints, which achieves low-overhead error detection and diagnosis through observation of geometric symmetry. (I) This invention provides a method for constructing quantum error-correcting codes based on address array symmetry constraints, comprising the following steps: Step 1: Encode the logical qubits into address pairs that are symmetrical about the central axis of symmetry in an isosceles trapezoidal address array. In the address array, the address pairs are symmetrical about the central axis of symmetry, and the same logical state is represented by a pair of symmetrical address pairs. Step 2: By reading the position of the current address pair in the address array, measure its offset direction and offset magnitude relative to the central axis of symmetry. Step 3: Diagnose the error type based on the symmetry breaking pattern of the address pair. When there is no error, the address pair is located on the central axis of symmetry, exhibiting perfect symmetry; a deviation of the address pair along the horizontal direction within the layer corresponds to a Type I error; a deviation of the address pair along the vertical direction across layers corresponds to a Type II error; and a simultaneous horizontal and vertical deviation corresponds to a Type III error. Step 4: The misaligned address pairs are mapped back to their centrosymmetric positions through an error correction and rearrangement operation, thus completing the error correction. This error correction and rearrangement operation is reversible and preserves the complete information of the quantum state. Step 5: For multi-qubit systems, each qubit is assigned to an independent layer of the address array, and error detection and correction operations are performed in parallel on each layer. (ii) The present invention also provides a quantum error-correcting code system based on address array symmetry constraints, comprising: A symmetry encoding unit encodes logical qubits into address pairs that are symmetrical about the central symmetry axis. An error detection unit measures the direction and magnitude of the address pair's offset relative to the central symmetry axis. An error diagnosis unit determines the error type based on the symmetry breaking mode of the address pair. An error correction execution unit maps the offset address pairs back to their central symmetry positions. An inter-layer synchronization unit maintains phase consistency between layers in a multi-qubit system. (III) The present invention has the following beneficial effects: (1) Compared with existing quantum error correction schemes that require repeated measurements, the present invention only needs to read the address pair position once to complete error detection and diagnosis, significantly reducing measurement overhead. (2) Error type diagnosis is directly determined through symmetry breaking mode, without the need for additional decoding calculations. (3) Error correction rearrangement operation is a pure geometric mapping, without introducing additional quantum gate errors. (4) Each layer detects and corrects errors independently, supports parallel error correction, and the error correction time is independent of the number of qubits. (5) It can work in conjunction with surface codes as physical layer error correction, while the logic layer is protected by surface codes. Detailed Implementation

[0004] Example 1: X / Z error detection and correction for a single quantum bit. This embodiment demonstrates the workflow of the error-correcting code of the present invention on a single quantum bit. S1. Symmetric Encoding. A single quantum bit is encoded into address pairs that are symmetrical about the central axis of symmetry. Logical state 0 corresponds to one pair of symmetrical address pairs, and logical state 1 corresponds to another pair of symmetrical address pairs. S2, Error Injection. Simulates injection of Type I errors, moving address pairs from symmetrical positions to horizontally offset positions. S3. Error Detection. Read the current address pair and detect its deviation direction and magnitude relative to the central axis of symmetry. S4. Error Diagnosis. Based on the symmetry breaking pattern, determine the error type: horizontal deviation corresponds to Type I error, vertical deviation corresponds to Type II error, and bidirectional deviation corresponds to Type III error. S5. Error Correction Execution. Perform error correction and rearrangement operations to map the deviated address pairs back to the centrally symmetrical positions. Error correction is complete. Implementation results: Error detection and diagnosis are completed in a single read, and error correction is completed within one time unit. Traditional solutions require at least three measurements and complex decoding calculations. Example 2: Multi-layer parallel error correction for 5-qubit logic states. This embodiment demonstrates the parallel error correction of the present invention on a 5-qubit logic state. S1. Encoding and Allocation. The 5 qubits are allocated to 5 independent layers, and each layer is independently encoded as a symmetric address pair. S2. Parallel error detection. Address pairs are read simultaneously across all 5 layers, and symmetric breaking patterns are detected in parallel across each layer. S3. Parallel error correction. Error correction and rearrangement operations are performed simultaneously across all 5 layers, mapping the offset address pairs from each layer back to the centrally symmetrical position. Implementation results: Error detection and correction of 5 qubits are completed within one time unit. Traditional methods require five times the serial measurement time. Example 3: Collaborative error correction with surface codes. In this embodiment, the error correction code of the present invention is used as physical layer error correction, and the surface code is used as logical layer error correction. S1. Physical layer protection. Each physical qubit is protected using the symmetric coding of this invention to detect and correct single-bit errors. S2, Logic Layer Protection. Surface codes detect and correct residual errors above the physical layer. S3. Collaborative Optimization. Error diagnosis results from the physical layer are directly passed to the surface code decoder, reducing the number of surface code measurements. Attached Figure Description

[0005] Figure 1 This is a schematic diagram of the symmetrical encoding of the present invention. Figure 2 This is a diagram showing the correspondence between error types and symmetry breaking modes. Figure 3This is a diagram illustrating the error correction and rearrangement operation. Figure 4 This is a block diagram of a multi-qubit parallel error correction architecture. Terminology Explanation

[0006] Symmetric encoding: Encode logical qubits into address pairs that are symmetrical about the central axis of symmetry, thereby achieving redundancy by utilizing symmetry. Symmetry breaking mode: The way and magnitude by which address pairs deviate from the central axis of symmetry, used to diagnose error types. Error correction and rearrangement operation: The operation of mapping off-center address pairs back to their centrally symmetric positions. Parallel error correction: Error detection and correction operations are performed simultaneously at each layer, and the error correction time is independent of the number of layers.

Claims

1. A method for constructing quantum error-correcting codes based on address array symmetry constraints, characterized in that, Includes the following steps: The logical qubits are encoded as address pairs that are symmetrical about the central axis of symmetry in an isosceles trapezoidal address array; Errors are detected by reading the offset direction and offset magnitude of the current address relative to the central axis of symmetry. Diagnose error types based on the symmetry breaking pattern of address pairs; Error correction is achieved by mapping the deviated address pairs back to the central symmetrical position through error correction and rearrangement operations.

2. The method according to claim 1, characterized in that: The correspondence between the error types and symmetry breaking modes is as follows: horizontal deviation corresponds to Type I error, vertical deviation corresponds to Type II error, and bidirectional deviation corresponds to Type III error.

3. The method according to claim 1, characterized in that: The error correction and rearrangement operation is reversible and preserves the complete information of the quantum state.

4. The method according to claim 1, characterized in that: The error detection only requires a single read of the address pair position, without the need for repeated measurements on multiple measurement bases.

5. The method according to claim 1, characterized in that: For multi-qubit systems, each qubit is assigned to an independent layer, and error detection and correction are performed in parallel on each layer.

6. A quantum error-correcting code system based on address array symmetry constraints, characterized in that, include: Symmetric encoding unit, used to encode logical qubits into address pairs that are symmetrical about the central axis of symmetry; An error detection unit is used to measure the offset direction and offset magnitude of an address pair relative to the central axis of symmetry. An error diagnosis unit is used to determine the error type based on the symmetry breaking mode. The error correction execution unit is used to map off-center address pairs back to the center-symmetric location; Inter-layer synchronization units are used to maintain phase consistency between layers in a multi-qubit system.

7. The system according to claim 6, characterized in that: The error detection unit has a detection frequency that is more than 10 times the quantum gate operation frequency.

8. The system according to claim 6, characterized in that: The system works in conjunction with surface code quantum error-correcting codes as a physical layer error correction mechanism.

9. The system according to claim 6, characterized in that: The error correction execution unit's error correction time is independent of the number of qubits, and a single error correction operation is completed within one time unit.

10. A quantum computing chip, characterized in that: The system comprises the quantum error correction code system according to any one of claims 6-9, wherein the system is integrated into a superconducting quantum processor or an ion trap quantum processor.

Images