Rendering processing method, graphics processing device, and electronic device

Abstract

This disclosure provides a rendering processing method, a graphics processing device, and an electronic device. The method is applied to any one of a plurality of processing cores in the graphics processing device. The method includes: in response to receiving a streaming output enable command from the graphics processing device, if the current processing core is an executing processing core when streaming output is disabled, determining first information of a data end marker received by the executing processing core during the period when streaming output is disabled; wherein the executing processing core is a processing core that is performing streaming output when streaming output is disabled and has not sent first address information to the next processing core; sending first routing information including the first information and the first address information to the next processing core of the current processing core; wherein the next processing core is used to determine whether to perform streaming output based on the first routing information. Embodiments of this disclosure can improve graphics processing efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a rendering method, graphics processing device, and electronic device. Background Technology

[0002] In computer graphics, the rendering pipeline is a stage in graphics processing (such as a graphics processing unit, GPU) that is responsible for processing and transforming graphics data for rendering. Its main task is to convert input geometric primitives (such as points, lines, triangles, etc.) into pixels visible on the screen.

[0003] Stream output is a stage in the rendering pipeline that occurs after the geometry shader and before rasterization. Stream output is used to output processed vertex or graph data from the rendering pipeline to the graphics processing device's memory (VRAM). Stream output can be enabled or disabled. Summary of the Invention

[0004] This disclosure provides a rendering method, a graphics processing device, and an electronic device.

[0005] In a first aspect, this disclosure provides a rendering processing method applied to any one of a plurality of processing cores in a graphics processing device; the method includes: in response to receiving a streaming output enable instruction from the graphics processing device, if the current processing core is an execution processing core when streaming output is disabled, determining first information of a data end marker received by the execution processing core during the period when streaming output is disabled; wherein the execution processing core is a processing core that is performing streaming output when streaming output is disabled and has not sent first address information to the next processing core; sending first routing information including the first information and the first address information to the next processing core of the current processing core; wherein the next processing core is configured to determine whether to perform streaming output based on the first routing information.

[0006] In a second aspect, this disclosure provides a graphics processing device, which includes multiple processing cores and an on-chip network, the on-chip network being configured to interact with data between the multiple processing cores and external data; wherein any processing core is configured to: in response to receiving a streaming output enable instruction from the graphics processing device, and when the current processing core is an execution processing core that is disabled when streaming output is disabled, determine first information of a data end marker received by the execution processing core during the period when streaming output is disabled; wherein the execution processing core is a processing core that is performing streaming output when streaming output is disabled and has not sent the first address information to the next processing core; and send first routing information including the first information and the first address information to the next processing core of the current processing core; wherein the next processing core is configured to determine whether to perform streaming output based on the first routing information.

[0007] Thirdly, this disclosure provides an electronic device that includes the aforementioned graphics processing device.

[0008] According to the rendering processing method of this disclosure, when the streaming output of the graphics processing device is enabled, the execution processing core when the streaming output is disabled can determine the first information of the data end marker received during the period when the streaming output is disabled, and send the first routing information, including the first information and the first address information, to the next processing core. The next processing core can determine whether to perform streaming output based on the first routing information. In this way, when the streaming output of the graphics processing device is enabled, the execution processing core when the streaming output is disabled can initiate an abnormal routing by sending the first routing information. Other non-execution processing cores determine whether to perform streaming output based on the first routing information, without relying on the routing of memory address offsets during the period when the streaming output is disabled, and therefore do not need to perform routing operations of memory address offsets during the period when the streaming output is disabled. Therefore, the rendering processing method of this disclosure can avoid routing operations between processing cores during the period when the streaming output of the graphics processing device is disabled, reduce the occupation of network-on-chip (NOC) bandwidth, reduce time waste, thereby reducing the number of interactions between processing cores during the period when the streaming output is disabled, and reducing the interference of the streaming output disabled time on the rasterization path, improving rendering processing efficiency, and thus improving graphics processing efficiency.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0010] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of detailed exemplary embodiments with reference to the accompanying drawings, which are described below.

[0011] Figure 1 This is a schematic diagram of a rendering pipeline provided in an embodiment of the present disclosure.

[0012] Figure 2 This is a schematic diagram of a stream output during the rendering process.

[0013] Figure 3 This is a flowchart of a rendering processing method provided in an embodiment of the present disclosure.

[0014] Figure 4 This is a schematic diagram of a rendering processing method provided in an embodiment of the present disclosure.

[0015] Figure 5 This is a block diagram of a graphics processing device provided in an embodiment of the present disclosure. Detailed Implementation

[0016] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0017] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0018] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0019] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0020] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0021] Before detailing the embodiments of this disclosure, some related concepts will be explained for clarity.

[0022] A render target can refer to an object to be rendered, which can be a part of a virtual scene to be rendered, or an image or video frame to be rendered.

[0023] A primitive can refer to the basic geometric shapes that make up a graphic, such as points, lines, and triangles. For example, a graphic drawn by an application can be represented in a computer by a combination of a large number of basic geometric shapes.

[0024] The rendering pipeline can generally be divided into two stages: the geometry stage (i.e., the geometry pipeline) and the pixel stage (also known as the fragment pipeline). The geometry stage is the first stage of the rendering pipeline, including input assembly, vertex shaders, geometry shaders, and stream output. The geometry pipeline primarily focuses on the processing and transformation of geometric data. It receives input geometric primitives (such as points, lines, triangles, etc.) and, after a series of stages, transforms them into geometric processing results mapped to pixel coordinates in screen space. The geometry pipeline is responsible for performing geometric calculations such as model transformations, view transformations, and projection transformations, as well as generating new geometric primitives and changing their shape, size, and position. The pixel stage generally includes rasterization, pixel shaders, and output processing, focusing on pixel-level processing. In short, the geometry pipeline converts geometric data into pixel data, while the fragment pipeline performs the final processing and calculations for each pixel. These two pipelines are interdependent and work closely together to ultimately generate a visualized image.

[0025] Figure 1 This is a schematic diagram of a rendering pipeline provided in an embodiment of this disclosure. (Refer to...) Figure 1 The rendering pipeline includes the following stages: Input-assembler stage (IA) 101, Vertex Shader Stage (VS) 102, Hull Shader Stage (HS) 103, Tessellator Stage (Tess) 104, Domain Shader Stage (DS) 105, Geometry Shader Stage (GS) 106, Stream Output stage (SO) 107, Rasterizer Stage (RS) 108, Pixel Shader Stage (PS) 109, and Output-Merger Stage (OM) 110. Except for the Stream Output stage 107, all other stages can obtain data from memory 100. The Stream Output stage 107, Pixel Shader stage 109, and Output-Merger stage 110 can also write data to memory 100. The memory 100 here refers to the memory in the graphics processing device, also known as video memory.

[0026] The process includes the following stages: Input Assembly Stage 101 receives input vertex / index data and assembles it into primitives such as points, lines, and triangles. Vertex Shader Stage 102 performs calculations on each input vertex using the vertex shader and can perform various transformations and operations, such as model transformation, view transformation, and projection transformation. It can also calculate vertex lighting and texture coordinates. Shell Shader Stage 103 is a preprocessing stage for surface tessellation, used to set the tessellation factor and control points. Tessellation Stage 104 automatically generates a large number of new vertices and topologies on the surface based on the tessellation factor output by Shell Shader Stage 103. Domain Shader Stage 105 calculates the final positions of the new vertices after tessellation using the domain shader. Geometry Shader Stage 106 manipulates and generates geometric primitives using the geometry shader, allowing for the creation of new primitives, modification of primitive geometry, and the performance of projection or clipping operations. Stream Output Stage 107 outputs the vertex or primitive data processed by the geometry shader to the graphics processing device's memory 100 (i.e., video memory).

[0027] The rasterization stage 108 converts geometric primitives into pixels on the screen and determines the position, color, and other attributes of each pixel. The pixel shader stage 109 performs calculations on each rasterized pixel using a pixel shader (also known as a fragment shader), which can perform pixel-level lighting calculations, texture sampling, depth testing, and other operations. The output merging stage 110, as the final stage of the rendering pipeline, performs a series of filtering and blending processes on the fragments output by the pixel shader, ultimately writing the valid pixels into the frame buffer and rendering them on the screen.

[0028] Depend on Figure 1 As can be seen, the streaming output stage 107 is located after the geometry shader stage 106 and before the rasterization stage 108. In the streaming output stage 107, the processing core of the graphics processing device can output the vertex or graph data processed in the rendering pipeline to the memory 100 (i.e., video memory) of the graphics processing device. This process can be called streaming output. Streaming output can be enabled or disabled.

[0029] To improve processing efficiency, graphics processing units (GPUs) typically include multiple processing cores and can operate in single-core or multi-core mode. In single-core mode, disabling the GPU's streaming output does not affect downstream rasterization. In multi-core mode, after each processing core completes its own streaming output (meaning it determines the end position of the output data in memory, not necessarily writing all the output data into memory), it needs to pass the address offset to the next processing core so that the next core can stream based on that address offset.

[0030] For example, Figure 2 This is a schematic diagram of a stream output during the rendering process. (Refer to...) Figure 2 The graphics processing device includes four processing cores: Processing Core 0, Processing Core 1, Processing Core 2, and Processing Core 3. Assume these four processing cores communicate in the order of Processing Core 0, Processing Core 1, Processing Core 2, and Processing Core 3. When Stream Output (SO) is enabled, Processing Core 0 executes the stream output first, outputting data to memory based on the base address of the stream output. During the data output process, Processing Core 0 determines the address offset for the next processing core (i.e., Processing Core 1) to write data to memory based on the end position of its output data in memory, and then sends this address offset to Processing Core 1. Upon receiving the address offset, Processing Core 1 determines the starting address for writing data to memory based on the base address of the stream output and the received address offset, and begins outputting data to memory. During the data output process, Processing Core 1 determines the address offset for the next processing core (i.e., Processing Core 2) to write data to memory based on the end position of its output data in memory, and then sends this address offset to Processing Core 2. This process continues until Processing Core 2 determines the address offset and sends it to Processing Core 3, so that Processing Core 3 can perform stream output based on this address offset. After determining the address offset, processing core 3 sends it to processing core 0 so that processing core 0 can perform stream output based on the address offset.

[0031] As mentioned above, each processing core in a graphics processing device relies on the address offset sent by the previous processing core when performing streaming output. When streaming output is disabled, the processing cores still need to perform address offset routing operations through the on-chip network. This is because when streaming output is re-enabled, since the data has been split and processed in parallel on multiple processing cores, the processing core that needs to be started cannot determine on its own whether it is the one that should be started. This is highly dependent on the routing information passed by the previous processing core.

[0032] Please continue to refer to Figure 2 After processing core 3 sends the address offset to processing core 0, stream output SO is disabled. In this case, upon receiving the address offset, processing core 0 does not perform stream output (i.e., does not output data) and sends the address offset to processing core 1. Upon receiving the address offset, processing core 1 does not perform stream output (i.e., does not output data) and sends the address offset to processing core 2. Upon receiving the address offset, processing core 2 does not perform stream output (i.e., does not output data) and sends the address offset to processing core 3. Upon receiving the address offset, processing core 3 does not perform stream output (i.e., does not output data) and sends the address offset to processing core 0. And so on. During the period when stream output is disabled, these four processing cores still perform address offset routing operations sequentially.

[0033] Please continue to refer to Figure 2After processing core 2 receives the address offset, stream output SO is enabled. Processing core 2 can determine the starting address for writing to memory based on the base address of the stream output and the received address offset, and begin outputting data to memory. During the data output process, processing core 2 determines the address offset for the next processing core (i.e., processing core 3) to write to memory based on the end position of its output data in memory, and then sends this address offset to processing core 3 so that processing core 3 can perform stream output based on this address offset, thereby entering the normal processing procedure after stream output is enabled.

[0034] As shown above, in multi-core mode (i.e., multi-core parallel architecture), even if streaming output is disabled, the processing cores of the graphics processing device still need to perform address offset routing operations through the on-chip network. This routing operation not only consumes the bandwidth of the on-chip network and increases the communication burden between processing cores, but also causes significant time waste, which may interfere with the rasterization path and affect rendering efficiency.

[0035] The specific impact on rasterization processing depends on the relative magnitude of the rasterization processing time of the processing core and the routing time of the stream output between processing cores. If the rasterization processing time of a processing core is much longer than the routing time of the stream output between processing cores, the routing operation can be masked by the rasterization process and will not have a significant impact on rasterization performance. However, if the processing core is processing small-granularity rasterized data, its processing time may be less than the routing time of the stream output between processing cores. In this case, the routing operation will become a performance bottleneck, significantly affecting the normal rasterization path and reducing overall processing efficiency. Therefore, in scenarios where graphics processing devices use multiple cores to process small-granularity rasterized data in parallel, the routing overhead that still exists after stream output is disabled is one of the key issues affecting system performance.

[0036] To address the aforementioned technical problems, embodiments of this disclosure provide a rendering processing method applied to any one of a plurality of processing cores in a graphics processing device. The method includes: in response to receiving a streaming output enable instruction from the graphics processing device, and when the current processing core is the executing processing core during the period when streaming output is disabled, determining first information of a data end marker received by the executing processing core during the period when streaming output is disabled; wherein the executing processing core is the processing core that is performing streaming output when streaming output is disabled and has not sent first address information to the next processing core; and sending first routing information including the first information and the first address information to the next processing core of the current processing core; wherein the next processing core is used to determine whether to perform streaming output based on the first routing information.

[0037] According to the rendering processing method of this disclosure, when the streaming output of the graphics processing device is enabled, the first information of the data end marker received during the period when the streaming output is disabled can be determined by the execution processing core when the streaming output is disabled. Then, the execution processing core sends first routing information, including the first information and first address information, to the next processing core. The next processing core can determine whether to perform streaming output based on the first routing information. In this way, when the streaming output of the graphics processing device is enabled, the execution processing core when the streaming output is disabled can initiate an abnormal routing round by sending the first routing information. Other non-execution processing cores determine whether to perform streaming output based on the first routing information, without relying on the routing of memory address offsets during the period when the streaming output is disabled, thus eliminating the need to perform routing operations for memory address offsets during the period when the streaming output is disabled. Therefore, the rendering processing method of this disclosure can avoid routing operations between processing cores during the period when the streaming output of the graphics processing device is disabled, reducing the occupation of on-chip network bandwidth, reducing time waste, thereby reducing the number of interactions between processing cores during the period when the streaming output is disabled, and reducing the interference of the streaming output disabling time on the rasterization path, improving rendering processing efficiency, and thus improving graphics processing efficiency.

[0038] The rendering processing method according to embodiments of this disclosure can be applied to image processing devices (such as GPUs, GPGPUs, etc.). These graphics processing devices can be standalone devices or located in electronic devices such as terminal devices or servers. The terminal device can be an in-vehicle device, user equipment (UE), mobile device, user terminal, personal digital assistant (PDA), handheld device, computing device, wearable device, etc. This method can be implemented by a processor calling computer-readable program instructions stored in memory. Alternatively, the method can be executed by a server.

[0039] Figure 3 A flowchart illustrating a rendering process method provided in an embodiment of this disclosure. (Refer to...) Figure 3 The method includes steps S31 and S32, which are described in detail below.

[0040] In step S31, in response to receiving a streaming output enable command from the graphics processing device, if the current processing core is the execution processing core when streaming output is disabled, first information regarding the data end marker received by the execution processing core during the period when streaming output is disabled is determined. Here, the execution processing core is the processing core that is performing streaming output when streaming output is disabled and has not sent the first address information to the next processing core.

[0041] In step S32, first routing information, including first information and first address information, is sent to the next processing core after the current processing core. The next processing core determines whether to perform stream output based on the first routing information.

[0042] In some possible implementations, the rendering processing method can be applied to any one of the multiple processing cores of a graphics processing device. The multiple processing cores of the graphics processing device communicate in a preset order, thereby enabling pipelined streaming output. For example, a graphics processing device may include four processing cores: core 0, core 1, core 2, and core 3. When these four processing cores perform pipelined streaming output, they can communicate in the order of core 0, core 1, core 2, and core 3. It should be noted that this disclosure does not limit the specific hardware connection method between the multiple processing cores of the graphics processing device.

[0043] It should be noted that when a graphics processing device includes multiple processing cores, its streaming output can be partially executed in parallel. For example, while processing core 0 is executing streaming output, it can determine the address offset for the next processing core (i.e., processing core 1) to write data into memory based on the end position of its output data in memory, and then send this address offset to processing core 1. When processing core 1 receives this address offset, it begins executing streaming output, but at this time, processing core 0 is still outputting data; that is, processing cores 0 and 1 execute streaming output in parallel.

[0044] In some possible implementations, the streaming output of the graphics processing device (GPU) can be enabled or disabled. When the GPU receives a streaming enable instruction from the central processing unit (CPU), it executes the instruction, and streaming output is enabled. With streaming enabled, the GPU can output vertex / graphics data from the geometry shader stage of the rendering pipeline to memory. Conversely, when the GPU receives a streaming disable instruction from the CPU, it executes the instruction, and streaming output is disabled. With streaming disabled, the GPU does not perform streaming output; that is, it no longer outputs vertex / graphics data from the geometry shader stage of the rendering pipeline to memory.

[0045] In some possible implementations, when the streaming output of the graphics processing device is disabled, in step S31, in response to receiving a streaming output enable instruction from the graphics processing device (i.e., streaming output is enabled), it can be determined whether the current processing core is the executing processing core when streaming output was disabled (disabled before this enable). An executing processing core refers to a processing core that is performing streaming output when the streaming output of the graphics processing device is disabled and has not sent the first address information to the next processing core. The first address information can be the memory address offset when the next processing core performs streaming output, or it can be the memory starting address when the next processing core performs streaming output; this disclosure does not limit this. When the streaming output of the graphics processing device is enabled, one of the multiple processing cores of the graphics processing device is an executing processing core, while the other processing cores are non-executing processing cores. Based on this, when the streaming output of the graphics processing device is disabled, one of the multiple processing cores of the graphics processing device is an executing processing core, while the other processing cores are non-executing processing cores.

[0046] When the current processing core is the execution processing core when stream output is disabled, the first information of the data end flag received by the execution processing core during the period when the output of the graphics processing device is disabled can be determined. The data end flag (last flag) is a flag bit; when its value is 1 (i.e., last flag = 1), it indicates that the data end flag is valid and can be used to indicate that the processing core has completed all computational tasks in the current stage and will no longer generate new service data packets. In the embodiments of this disclosure, the data end flag is the end flag for data output in the stream output stage. A data end flag is present whether stream output is enabled or disabled. When stream output is enabled, the data received by the processing core is "data to be output + data end flag". When stream output is disabled, the processing core does not perform stream output and therefore will not receive the data to be output, but it will receive the data end flag.

[0047] When streaming output of the graphics processing device is enabled, and the current processing core is the execution processing core when streaming output is disabled, the execution processing core can determine first information about the data end-of-processor markers it received during the period when streaming output was disabled. This first information can be used to characterize the quantity of data end-of-processor markers. The first information can be a first quantity, which can be used to characterize the number of data end-of-processor markers received by the execution processing core during the period when streaming output was disabled. The first information can also be a first flag bit, which can be used to characterize the parity of the number of data end-of-processor markers received by the execution processing core during the period when streaming output was disabled. For example, a first flag bit of 1 indicates that the number of data end-of-processor markers received by the execution processing core during the period when streaming output was disabled is odd; a first flag bit of 0 indicates that the number of data end-of-processor markers received by the execution processing core during the period when streaming output was disabled is even.

[0048] After obtaining the first information, in step S32, the first routing information is determined based on the first information and the first address information, and then sent to the next processing core according to a preset order. The first routing information may include the first information of the data end marker received by the executing processing core during the period when stream output is disabled, and the first address information. The first address information is the memory address information last received by the executing processing core before stream output is disabled. The operation of the executing processing core sending the first routing information can be regarded as an abnormal routing operation after stream output is enabled. The first routing information can be considered abnormal routing information, as it includes the first information compared to normal routing information. This abnormal routing operation is used to determine the first processing core to execute stream output after stream output is enabled. After the executing processing core sends the first routing information to its next processing core, the next processing core can determine whether it should execute stream output based on the first routing information.

[0049] For example, a graphics processing device has four processing cores: processing core 0, processing core 1, processing core 2, and processing core 3, which execute in parallel. Assume these four processing cores communicate in the order of processing core 0, processing core 1, processing core 2, and processing core 3. Processing core 1 is the executing processing core when streaming output is disabled, while processing cores 0, 2, and 3 are non-executing processing cores when streaming output is disabled. If the current processing core is processing core 1, in response to receiving a streaming output enable command, processing core 1 can determine the first information (e.g., a first quantity of 4, or a first flag bit of 0) and the first address information received during the period when streaming output was disabled, which are the memory address information last received by processing core 1 before streaming output was disabled. Then, based on the first information and the first address information, it generates first routing information and sends the first routing information to its next processing core, processing core 2. Processing core 2 can determine whether it should execute streaming output based on the received first routing information.

[0050] It should be noted that the first address information is included in the first routing information so that after the processing core for executing the stream output is determined, the first address information can be directly used for stream output, thereby improving processing efficiency.

[0051] According to the rendering processing method of this disclosure, when the streaming output of the graphics processing device is enabled, the first information of the data end marker received during the period when the streaming output is disabled can be determined by the execution processing core when the streaming output is disabled. Then, the execution processing core sends first routing information, including the first information and first address information, to the next processing core. The next processing core can determine whether to perform streaming output based on the first routing information. In this way, when the streaming output of the graphics processing device is enabled, the execution processing core when the streaming output is disabled can initiate an abnormal routing round by sending the first routing information. Other non-execution processing cores determine whether to perform streaming output based on the first routing information, without relying on the routing of memory address offsets during the period when the streaming output is disabled, thus eliminating the need to perform routing operations for memory address offsets during the period when the streaming output is disabled. Therefore, the rendering processing method of this disclosure can avoid routing operations between processing cores during the period when the streaming output of the graphics processing device is disabled, reducing the occupation of on-chip network bandwidth, reducing time waste, thereby reducing the number of interactions between processing cores during the period when the streaming output is disabled, and reducing the interference of the streaming output disabling time on the rasterization path, improving rendering processing efficiency, and thus improving graphics processing efficiency.

[0052] The rendering processing method according to the embodiments of this disclosure will now be described in detail.

[0053] As previously stated, when stream output is disabled, the executing processing core may, in step S32, send first routing information, including first information and first address information, to the next processing core of the current processing core. In some possible implementations, the rendering processing method of this disclosure embodiment further includes: in response to receiving a stream output enable instruction from a graphics processing device, when the current processing core is a non-executing processing core when stream output is disabled, determining second information of the data end marker received by the current processing core during the period when stream output is disabled; and in response to receiving first routing information sent by the previous processing core, determining whether the current processing core should perform stream output based on the second information and the first information in the first routing information.

[0054] When the streaming output of the graphics processing device is disabled, in response to receiving a streaming output enable command from the graphics processing device (i.e., streaming output is enabled), and if the current processing core is a non-executing processing core when streaming output is disabled, it can determine second information about the data end markers it received during the period when streaming output is disabled. This second information is used to characterize the number of data end markers received by the non-executing processing core during the period when streaming output is disabled. The second information can be a second quantity, which can be used to characterize the number of data end markers received by the non-executing processing core during the period when streaming output is disabled. The second information can also be a second flag bit, which can be used to characterize the parity of the number of data end markers received by the non-executing processing core during the period when streaming output is disabled. For example, a second flag bit of 1 indicates that the number of data end markers received by the non-executing processing core during the period when streaming output is disabled is odd; a second flag bit of 0 indicates that the number of data end markers received by the non-executing processing core during the period when streaming output is disabled is even.

[0055] After the current processing core determines the second information, upon receiving the first routing information sent by the previous processing core, it can determine whether to perform stream output based on the received first routing information and its own determined second information. The first information in the first routing information can be compared with the second information. If they are the same, the current processing core does not perform stream output. If they are different, the current processing core performs stream output. For example, a graphics processing device has four processing cores: processing core 0, processing core 1, processing core 2, and processing core 3. These four processing cores can perform stream output in parallel. Assuming processing core 0 is the executing processing core when stream output is disabled, and the current processing core is processing core 1, which is a non-executing processing core, it can receive the first routing information sent by the previous processing core (i.e., processing core 0) and determine whether to perform stream output based on whether its own determined second information is the same as the first information in the first routing information.

[0056] In the embodiments of this disclosure, when the streaming output of the graphics processing device is disabled and then enabled, the non-executing processing core during the period when the streaming output was disabled only needs to compare the second information of the data end marker received by itself during the period when the streaming output was disabled with the first information in the first routing information sent by the previous processing core to determine whether it should perform streaming output, without relying on the routing of memory address information during the period when the streaming output was disabled. Therefore, the rendering processing method of the embodiments of this disclosure not only avoids the routing information between processing cores during the period when the streaming output of the graphics processing device is disabled, reducing the occupation of on-chip network bandwidth and reducing time waste, but also can quickly and accurately determine whether it should perform streaming output based on the information of the data end marker received by itself and the executing processing core during the period when the streaming output was disabled, thereby improving the rendering processing efficiency and thus improving the graphics processing efficiency.

[0057] In some possible implementations, determining whether the current processing core should perform stream output based on the second information and the first information in the first routing information includes: if the second information and the first information in the first routing information are the same, determining that the current processing core should not perform stream output; or, if the second information and the first information in the first routing information are different, determining that the current processing core should perform stream output.

[0058] When determining whether the current processing core should perform stream output, it can be checked whether the second information of the data end marker received by the current processing core during the period when stream output was disabled is the same as the first information in the first routing information received by the current processing core from the previous processing core. If the first and second information are the same, the data flow of the current processing core is considered continuous, and no special processing is required; therefore, it can be determined that the current processing core does not perform stream output. If the first and second information are different, it can be determined that the current processing core is the processing core that should be activated after stream output is enabled, that is, the processing core that performs stream output after stream output is enabled.

[0059] In the embodiments of this disclosure, it is possible to determine whether the current processing core should perform stream output based on whether the first information and the second information are the same. This is simple and fast, and can improve the processing efficiency of stream output.

[0060] In some possible implementations, when it is determined that the current processing core is performing stream output, the current processing core can determine the starting address for writing to memory based on the base address of the stream output (which can be set by the application) and the first address information in the first routing information, and then output the data to memory. During the data output process, the current processing core can determine the second address information for the next processing core to write to memory based on the end position of its output data in memory, and send this second address information as the second routing information to the next processing core, thereby entering the normal processing flow of the graphics processing device's stream output. Here, the second routing information only includes the second address information, and the second routing information can be regarded as normal routing information for stream output.

[0061] In some possible implementations, the method also includes sending the first routing information to the next processing core if the current processing core does not perform stream output.

[0062] When streaming output is not performed, the current processing core can send the first routing information to the next processing core, which then determines whether to perform streaming output. For example, a graphics processing device may have four processing cores: core 0, core 1, core 2, and core 3. These four cores execute in parallel. Assume they communicate in the order of core 0, core 1, core 2, and core 3. Core 0 is the executing core when streaming output is disabled, while cores 1, 2, and 3 are the non-executing cores when streaming output is disabled. In response to receiving a streaming output enable command, core 0 (the executing core) determines the first information of the data end marker it received during the period when streaming output was disabled (e.g., the first information is a first quantity, which is 4). It then generates first routing information, which includes first information and first address information (the memory address information last received by core 0 before being disabled). This first routing information is then sent to core 1 (the next processing core after core 0). The first routing information is abnormal routing information, containing the additional first information compared to normal routing information.

[0063] If the current processing core is processing core 1 (non-executing processing core): In response to receiving a stream output enable instruction, processing core 1 determines the second information of the data end marker it received during the period when stream output was disabled (for example, the second information is the second quantity, and the second quantity of processing core 1 is 4). Then, if it receives the first routing information sent by the previous processing core (i.e., processing core 0), it determines whether the second information is the same as the first information in the first routing information received from processing core 0. Both are 4, which is the same. Then, it can be determined that processing core 1 does not execute stream output, and then the first routing information is sent to the next processing core (i.e., processing core 2).

[0064] If the current processing core is processing core 2 (not the execution processing core): In response to receiving a stream output enable command, processing core 2 determines the second information of the data end marker it received during the period when stream output was disabled (for example, the second information is the second quantity, and the second quantity of processing core 2 is 3). Then, upon receiving the first routing information sent by the previous processing core (i.e., processing core 1), it determines whether the second information is the same as the first information in the first routing information received from processing core 1. If the first information is the first quantity 3 and the second information is the second quantity 4, and they are different, then it can be determined that processing core 2 will execute stream output. Processing core 2 can output the data of the current processing core to memory according to the first address information in the first routing information. After processing core 2 determines the second address information after it has completed stream output, it can generate second routing information according to the second address information and send it to the next processing core (i.e., processing core 3). The second routing information is normal routing information, which only includes the second address information.

[0065] If the current processing core is processing core 3 (not the execution processing core): In response to receiving the stream output enable command, processing core 3 determines the second information of the data end marker it received during the period when stream output was disabled (for example, the second information is the second quantity, and the second quantity of processing core 3 is 3). Then, upon receiving the second routing information sent by the previous processing core (i.e., processing core 2), since the second routing information is normal routing information, processing core 3 executes stream output normally. Afterwards, these four processing cores execute the stream output processing flow normally in the order of processing core 4, processing core 1, processing core 2, processing core 3, processing core 4...

[0066] In the embodiments of this disclosure, in response to receiving a stream output enable command, if the current processing core does not perform stream output, the first routing information is sent to the next processing core of the current processing core. The next processing core then determines whether it performs stream output. By making sequential judgments, the processing core that performs stream output can be determined. This enables the activation core (i.e. the processing core that performs stream output) to be determined through at most one round of abnormal routing after stream output is enabled, thereby improving the processing efficiency of stream output and thus improving the graphics processing efficiency.

[0067] In some possible implementations, the rendering processing method of this disclosure embodiment further includes: when the current processing core is the execution processing core and the current processing core receives the first routing information sent by the previous processing core, performing stream output according to the first address information in the first routing information.

[0068] If the current processing core is the executing processing core and has received the first routing information sent by the previous processing core, the current processing core may consider the data streams of other processing cores to be continuous and will not perform stream output processing. The current processing core may determine that it will perform stream output (i.e., determine itself as the starting core) and output the data to memory according to the first address information in the first routing information.

[0069] For example, a graphics processing device has four processing cores: processing core 0, processing core 1, processing core 2, and processing core 3. These four processing cores execute in parallel. Assume that these four processing cores communicate in the order of processing core 0, processing core 1, processing core 2, and processing core 3. Processing core 0 is the executing processing core when streaming output is disabled, while processing cores 1, 2, and 3 are the non-executing processing cores when streaming output is disabled. If the current processing core is processing core 0, in response to receiving a streaming output enable command, processing core 0 can determine a first quantity 4 of data end markers received during the period when its streaming output is disabled (i.e., the first information is the first quantity) and a first address information. Then, based on the first quantity 4 and the first address information, it generates first routing information and sends the first routing information to its next processing core, i.e., processing core 1.

[0070] After receiving the first routing information, processing core 1 determines that it will not perform flow output based on the second number 4 of data end markers received by processing core 1 during the period when flow output is disabled (i.e., the second information is the second number) and the first number 4 in the first routing information, and then sends the first routing information to processing core 2. After receiving the first routing information, processing core 2 determines that it will not perform flow output based on the second number 4 of data end markers received by processing core 2 during the period when flow output is disabled and the first number 4 in the first routing information, and then sends the first routing information to processing core 3. After receiving the first routing information, processing core 3 determines that it will not perform flow output based on the second number 4 of data end markers received by processing core 3 during the period when flow output is disabled and the first number 4 in the first routing information, and then sends the first routing information to processing core 0.

[0071] After receiving the first routing information, processing core 0 determines its own execution flow output and outputs its own data to memory according to the first address information in the first routing information.

[0072] In the embodiments of this disclosure, when the current processing core is the execution processing core and the current processing core receives the first routing information sent by the previous processing core, it can determine that it is executing the stream output. Thus, when the data streams of all non-execution processing cores are continuous when the stream output is disabled, the execution processing core when the stream output is disabled can be determined as the starting core. This enables the starting core (i.e. the processing core executing the stream output) to be determined through at most one round of abnormal routing after the stream output is enabled, thereby improving the processing efficiency of the stream output and thus improving the graphics processing efficiency.

[0073] In some possible implementations, the method further includes: when the streaming output of the graphics processing device is enabled, in response to receiving a streaming output disable command, recording the number of received data end markers.

[0074] When the streaming output of the graphics processing device is enabled, in response to receiving a streaming output disable command, the current processing core can immediately initiate the recording operation of the quantity information of the data end marker. That is, when the streaming output of the graphics processing device is enabled and a streaming output disable command is received, the current processing core can immediately begin recording the quantity information of the received data end marker. The quantity information can be a specific quantity, such as 2, 3, 4, etc. The quantity information can also be the parity of the quantity. This disclosure does not limit the specific implementation of the quantity information.

[0075] In this way, it is possible to simply, quickly, and accurately record the data reception status of each processing core while the streaming output of the graphics processing device is disabled.

[0076] Figure 4This is a schematic diagram illustrating a rendering processing method provided in an embodiment of this disclosure. (Refer to...) Figure 4 This rendering method is applied to a graphics processing device that includes four processing cores: processing core 0, processing core 1, processing core 2, and processing core 3. These four processing cores execute in parallel and communicate in the order of processing core 0, processing core 1, processing core 2, and processing core 3. Figure 4 The order from left to right is chronological. In the icon corresponding to each processing core, the horizontal line represents the received stream output data, and the circle represents the end of the data.

[0077] With streaming output (SO) enabled on the graphics processing device, processing core 0 begins streaming output. After determining the memory address offset of processing core 1, it routes the memory address offset of processing core 1 to processing core 1. Upon receiving the memory address offset from processing core 0, processing core 1 begins streaming output. After determining the memory address offset of processing core 2, it routes the memory address offset of processing core 2 to processing core 2. Upon receiving the memory address offset from processing core 1, processing core 2 begins streaming output. After determining the memory address offset of processing core 3, it routes the memory address offset of processing core 3 to processing core 3. Upon receiving the memory address offset from processing core 2, processing core 3 begins streaming output. After determining the memory address offset of processing core 0, it routes the memory address offset of processing core 0 to processing core 0.

[0078] After receiving the memory address offset, the processing core 0 has not yet executed the stream output, that is, it receives the stream output SO disable instruction and starts to execute the rendering processing method of this embodiment of the present disclosure, as follows.

[0079] The first step is the statistics phase during the period when stream output is disabled.

[0080] When stream output (SO) is disabled, routing operations between processing cores are no longer initiated. Instead, each processing core independently counts the number of last flags in empty data packets received during this period. In other words, in response to the stream output disable command, processing core 0, processing core 1, processing core 2, and processing core 3 begin recording the number of last flags they received during the period when stream output was disabled. Figure 4 As shown, processing core 0 recorded 4 data end markers, processing core 1 recorded 4 data end markers, processing core 2 recorded 3 data end markers, and processing core 3 recorded 3 data end markers. These statistics reflect the data reception status of each processing core during the period when stream output SO was disabled.

[0081] The second step is the abnormal route phase during re-enabling.

[0082] When streaming output SO is enabled, it is not necessary to traverse all processing cores; instead, the execution processing core (i.e., the last processing core that executed the route in the previous iteration, such as...) is responsible for the execution. Figure 4 The processing core 0 initiates an abnormal routing operation. The difference between abnormal routing operations and regular routing operations is that the routing information for abnormal routing operations includes not only address information, but also the number of data end markers received by the processing core during the period when stream output was disabled.

[0083] Specifically, in response to receiving a stream output enable instruction, processing core 0 determines itself to be the execution processing core when stream output is disabled. Based on the number of data end markers it received during the period when stream output was disabled (4) and the memory address offset of the last received data before stream output was disabled, it generates abnormal routing information (i.e., first routing information) and sends the abnormal routing information to processing core 1.

[0084] The third step is to activate the determination mechanism for the processing core.

[0085] Upon receiving abnormal routing information, each processing core compares the number of data end markers carried in the abnormal routing information with the number of data end markers it counted during the period when stream output was disabled. If the two are the same, it indicates that the data stream of that processing core is continuous and no special processing is required; if the two are inconsistent (i.e., the number of data end markers carried in the abnormal routing information is different from the number of data end markers counted locally), then that processing core is determined to be the processing core that should be activated when stream output is started.

[0086] Specifically, in response to receiving a stream output enable command, processing core 1 determines that it is a non-executing processing core when stream output is disabled, and the number of data end markers it receives during the period when stream output is disabled is 4. Upon receiving abnormal routing information sent by processing core 0, processing core 1 compares its own count of 4 with the count of 4 in the abnormal routing information; if they are the same, it determines that it will not perform stream output processing, and then sends the abnormal routing information to processing core 2.

[0087] In response to receiving a stream output enable command, processing core 2 determines that it is a non-executing processing core when stream output is disabled, and determines that the number of data end markers it received during the period when stream output was disabled is 3. Upon receiving abnormal routing information from processing core 1, processing core 2 compares its own count of 3 with the count of 4 in the abnormal routing information; if they are different, it determines that it will perform stream output processing, and then sends the stream output data to memory according to the memory address offset in the abnormal routing information. After determining the memory address offset of processing core 3, processing core 2 sends normal routing information to processing core 3.

[0088] In response to receiving a stream output enable command, processing core 3 determines that it is a non-executing processor when stream output is disabled, and that the number of data end markers it received during the period when stream output was disabled was 3. After receiving routing information sent by processing core 2, processing core 3 determines that the routing information is normal routing information, and no longer performs the start-up judgment. Instead, it sends the stream output data to memory according to the memory address offset in the normal routing information. After determining the memory address offset of processing core 0, processing core 3 sends normal routing information to processing core 0, thereby entering the normal stream output processing flow.

[0089] Through the above methods, this disclosure achieves the following technical effects:

[0090] Eliminate invalid routes: During the flow output disabling period, the processing of inter-core routing operations is completely avoided, thus completely eliminating time waste;

[0091] Precise startup determination: When re-enabling, only one abnormal route is needed to determine the startup processing core, without polling all processing cores;

[0092] Reduced communication overhead: Significantly reduces the number of data interactions between processing cores, improving the overall processing efficiency of image processing devices, especially suitable for scenarios involving small-granularity raster data processing.

[0093] According to the rendering processing method of this disclosure, when multi-core parallel processing is performed, the performance interference caused by the routing operations between processing cores after streamout is turned off on the normal rasterization path can be eliminated or reduced, thereby improving graphics processing efficiency. Specifically, this disclosure optimizes the communication mechanism between processing cores or adjusts the data flow control method to avoid processing bottlenecks caused by relatively long stream output routing time in small-granularity rasterization data processing scenarios, ensuring that the on / off state of the stream output function (i.e., whether it is enabled or disabled) does not negatively affect the execution efficiency of the rasterization path.

[0094] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0095] In addition, this disclosure also provides graphics processing devices and electronic devices, all of which can be used to implement any of the rendering processing methods provided in this disclosure. The corresponding technical solutions and descriptions are described in the relevant section on methods and will not be repeated here.

[0096] Figure 5 This is a block diagram of a graphics processing device provided in an embodiment of the present disclosure.

[0097] Reference Figure 5 This disclosure provides a graphics processing device, which includes a plurality of processing cores 510 and an on-chip network 520, the on-chip network 520 being configured to interact with data between the plurality of processing cores 510 and external data.

[0098] Any processing core 510 is configured to: in response to receiving a streaming output enable command from a graphics processing device, and when the current processing core is the execution processing core during which streaming output is disabled, determine first information of a data end marker received by the execution processing core during the period when streaming output is disabled; wherein the execution processing core is the processing core that is performing streaming output when streaming output is disabled and has not sent the first address information to the next processing core; and send first routing information, including the first information and the first address information, to the next processing core of the current processing core; wherein the next processing core is configured to determine whether to perform streaming output based on the first routing information.

[0099] In some possible implementations, any processing core 510 is further configured to: perform stream output based on the first address information in the first routing information when the current processing core is the execution processing core and the execution processing core receives the first routing information sent by the previous processing core.

[0100] In some possible implementations, any processing core 510 is further configured to: in response to receiving a streaming output enable instruction from a graphics processing device, in the case that the current processing core is a non-executing processing core when streaming output is disabled, determine second information of the data end marker received by the current processing core during the period when streaming output is disabled; in response to receiving first routing information sent by the previous processing core, determine whether the current processing core performs streaming output based on the second information and the first information in the first routing information.

[0101] In some possible implementations, any processing core 510 is specifically configured to: determine that the current processing core does not perform flow output if the second information is the same as the first information in the first routing information; or determine that the current processing core performs flow output if the second information is different from the first information in the first routing information.

[0102] In some possible implementations, any processing core 510 is also configured to: send first routing information to the next processing core in a preset order when the current processing core does not perform stream output.

[0103] In some possible implementations, the first information is a first quantity, which is used to characterize the number of data end markers received by the processing core during the period when the stream output is disabled; or, the first information is a first flag bit, which is used to characterize the parity of the number of data end markers received by the processing core during the period when the stream output is disabled.

[0104] In some possible implementations, any processing core 510 is also configured to: record the number of received data end markers in response to receiving a stream output disable instruction, provided that the stream output of the graphics processing device has been enabled.

[0105] This disclosure provides an electronic device that includes the graphics processing device described in any of the above embodiments.

[0106] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as integrated circuits, such as application-specific integrated circuits (ASICs).

[0107] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0108] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A rendering processing method characterized by, The method includes: applying to any one of a plurality of processing cores in a graphics processing device; In response to receiving a streaming output enable command from the graphics processing device, if the current processing core is the execution processing core when the streaming output is disabled, first information of a data end marker received by the execution processing core during the period when the streaming output is disabled is determined; wherein, the execution processing core is the processing core that is executing streaming output when the streaming output is disabled and has not sent the first address information to the next processing core; The first routing information, including the first information and the first address information, is sent to the next processing core of the current processing core; The next processing core is used to determine whether to execute the stream output based on the first routing information.

2. The method according to claim 1, characterized in that, The method further includes: When the current processing core is the execution processing core, and the execution processing core receives the first routing information sent by the previous processing core, the stream output is performed according to the first address information in the first routing information.

3. The method according to claim 1, characterized in that, The method further includes: In response to receiving a streaming output enable command from the graphics processing device, if the current processing core is a non-executing processing core when the streaming output is disabled, determine second information about the data end marker received by the current processing core during the period when the streaming output is disabled; In response to receiving the first routing information sent by the previous processing core, the current processing core determines whether to execute the stream output based on the second information and the first information in the first routing information.

4. The method according to claim 3, characterized in that, The step of determining whether the current processing core should execute the stream output based on the second information and the first information in the first routing information includes: If the second information is the same as the first information in the first routing information, it is determined that the current processing core does not execute the stream output; or, If the second information differs from the first information in the first routing information, it is determined that the current processing core will execute the stream output.

5. The method according to claim 3, characterized in that, The method further includes: If the current processing core does not execute the stream output, the first routing information is sent to the next processing core of the current processing core.

6. The method according to any one of claims 1 to 5, characterized in that, The first information is a first quantity, which characterizes the number of data end markers received by the execution processing core during the period when the stream output is disabled; or, The first information is a first flag bit, which is used to characterize the parity of the number of data end markers received by the execution processing core during the period when the stream output is disabled.

7. The method according to any one of claims 1 to 5, characterized in that, The method further includes: When the streaming output of the graphics processing device is enabled, in response to receiving a streaming output disable command, the number of received data end markers is recorded.

8. A graphics processing device, characterized in that, The graphics processing device includes multiple processing cores and an on-chip network, the on-chip network being configured to interact with data between the multiple processing cores and external data; Any of the processing cores is configured to: in response to receiving a streaming output enable command from the graphics processing device, and when the current processing core is the execution processing core when the streaming output is disabled, determine first information of a data end marker received by the execution processing core during the period when the streaming output is disabled; wherein the execution processing core is the processing core that is executing streaming output when the streaming output is disabled and has not sent the first address information to the next processing core; The first routing information, including the first information and the first address information, is sent to the next processing core of the current processing core; The next processing core is used to determine whether to execute the stream output based on the first routing information.

9. The graphics processing device according to claim 8, characterized in that, Any processing core is also used for: In response to receiving a streaming output enable command from the graphics processing device, if the current processing core is a non-executing processing core when the streaming output is disabled, determine second information about the data end marker received by the current processing core during the period when the streaming output is disabled; In response to receiving the first routing information sent by the previous processing core, the current processing core determines whether to execute the stream output based on the second information and the first information in the first routing information.

10. An electronic device, characterized in that, include: The graphics processing device according to claim 8 or 9.

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