Data processing circuit, method, electronic device and chip

Abstract

This application discloses a data processing circuit, method, electronic device, and chip. The apparatus includes: a shared memory module and at least two logic processing modules; the shared memory module is connected to the logic processing modules; the shared memory module stores data to be processed; the logic processing modules perform image processing based on the data to be processed in the shared memory module to obtain processing results, wherein the data to be processed is image-related data. By storing shared data for different image processing operations in the shared memory component, and reading data from the shared memory component for different logic processing, the utilization rate of storage space is effectively improved, further enhancing the efficiency of data processing.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a data processing circuit, method, electronic device, and chip. Background Technology

[0002] In today's digital age, the demand for image data processing is increasing daily. From security monitoring and medical imaging to autonomous driving, efficient and accurate image processing hardware is crucial. In related technologies, image processing architectures often employ a single processing unit paired with independent memory. However, when faced with massive amounts of image data, this approach often reveals several drawbacks. Firstly, data transmission efficiency is low. Each time the processing unit processes image data, it needs to repeatedly read from the corresponding external memory, resulting in limited data transmission bandwidth and low image processing efficiency. Secondly, even if different image processing tasks require the same images, they still need to read image data from their respective independent memory locations. This leads to duplicate image data occupying multiple independent memory locations, reducing storage space utilization. Summary of the Invention

[0003] This application aims to solve the problems of low storage space utilization and low image processing efficiency in related technologies by storing the data to be processed shared by different image processing into a shared memory component and reading the data from the shared memory component for different logical processing.

[0004] Therefore, this application proposes a data processing circuit, method, electronic device, and chip.

[0005] One embodiment of this application proposes a data processing apparatus, comprising: a circuit, characterized in that it includes: a shared memory component and at least two logic processing components, wherein the shared memory component is connected to the logic processing components;

[0006] The shared memory component is used to store data to be processed;

[0007] The logic processing component is used to perform image processing based on the data to be processed in the shared memory component to obtain the processing result, wherein the data to be processed is image-related data.

[0008] Optionally, the shared memory component includes:

[0009] The data reading component is used to read the data to be processed according to the image processing type of the logic processing component, and input the read data into the corresponding logic processing component.

[0010] Optionally, the data reading component includes:

[0011] A sliding window control component is used to control the data window to slide on the data rows in the data to be processed, read the data in the data window and transmit it to the logic processing component; the size of the data window is related to the image processing type.

[0012] Optionally, the sliding window control component is used to read the data in the data window and transmit it to the corresponding logic processing component after the data window has finished scanning a data row of the data to be processed.

[0013] Optionally, the logic processing component is used to perform image processing based on the data read from the data window within a preset time slot.

[0014] Optionally, the data reading component is used to control the data window to jump on the data column according to the number of rows to jump in the window after the logic processing component performs image processing based on the data read from the data window; the number of rows to jump in the window is related to the image processing.

[0015] Another embodiment of this application proposes a data processing method, including:

[0016] The data to be processed is stored in a shared memory component, and the data to be processed is image-related data;

[0017] Read the data to be processed from the shared memory component, input the data to be processed into the logic processing component to perform at least two different image processing operations, and obtain the processing result.

[0018] Optionally, the step of inputting the data to be processed into the logic processing component for at least two different image processing steps includes:

[0019] The data to be processed is read according to the image processing type of the logic processing component, and the corresponding image processing is performed based on the read data.

[0020] Optionally, reading the data to be processed according to the image processing type of the logical processing component includes:

[0021] The control data window slides over data rows in the data to be processed; the size of the data window is related to the image processing type.

[0022] Read the data from the data window and input it into the logic processing component to perform image processing.

[0023] Optionally, reading the data in the data window and performing the corresponding image processing includes:

[0024] In response to the completion of reading one data row of the data to be processed, the corresponding image processing is performed based on the data read from the data window.

[0025] Optionally, performing corresponding image processing based on the data read from the data window includes:

[0026] Image processing is performed based on the data read from the data window within a preset time slot.

[0027] Optionally, after performing the corresponding image processing based on the data read from the data window, the process further includes:

[0028] The number of rows the window jumps through controls the data window to jump on the data columns; the number of rows the window jumps through is related to the image processing.

[0029] Another embodiment of this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method described in the foregoing aspect.

[0030] Another embodiment of this application proposes a chip including processing circuitry configured to perform the method described in one aspect above.

[0031] Another embodiment of this application proposes a chip including the circuitry described in the foregoing aspect.

[0032] Another embodiment of this application provides an electronic device including the circuitry described in the foregoing aspect.

[0033] The data processing circuit, method, electronic device, and chip proposed in this application effectively improve the utilization of storage space and further enhance the efficiency of data processing by storing the data to be processed, which is shared by different image processing, in a shared memory component and reading the data from the shared memory component for different logical processing.

[0034] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0035] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0036] Figure 1 This is a schematic diagram of the structure of a data processing circuit provided in an embodiment of this application;

[0037] Figure 2 A flowchart illustrating the data sliding window processing method provided in this application embodiment;

[0038] Figure 3This is a schematic flowchart illustrating a data processing method provided in an embodiment of this application.

[0039] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0040] Figure 5 This is a schematic diagram of the structure of a chip proposed in an embodiment of this application. Detailed Implementation

[0041] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0042] Image processing and computer vision technologies have reached a relatively mature stage, and are widely used in products across various market sectors such as mobile phones, automobiles, security, and aerial photography for image acquisition, image processing, and visual computing. When combined with hardware implementations such as chips and FPGAs, they can accelerate algorithm processing performance, better and more real-time serve various related product applications, and improve user experience, such as mobile phone video preview and photography, and rapid response control in automotive driver assistance systems.

[0043] The data processing circuits, methods, electronic devices, and chips of embodiments of this application are described below with reference to the accompanying drawings.

[0044] Figure 1 This is a schematic diagram of the structure of a data processing circuit provided in an embodiment of this application.

[0045] It should be noted that all data collection operations related to users in this application are conducted with the user's authorization and in strict compliance with relevant laws and regulations such as privacy and security.

[0046] like Figure 1 As shown, the circuit may include:

[0047] A shared memory component 10 and at least two logical processing components 20, wherein the shared memory component is connected to the logical processing components;

[0048] The shared memory component is used to store data to be processed;

[0049] The logic processing component is used to perform image processing based on the data to be processed in the shared memory component to obtain the processing result, wherein the data to be processed is image-related data.

[0050] In this embodiment, the circuit mainly includes a shared memory component and at least two logic processing components, and a stable connection path is established between the shared memory component and each logic processing component. The shared memory component plays a key data storage center role in the circuit, specifically used to store various types of data to be processed. This data mainly focuses on image-related information and can provide raw data support for subsequent image processing operations.

[0051] The logic processing components are the key execution units in the circuit that perform image processing operations. Each logic processing component has independent processing capabilities and logical judgment functions. They can actively obtain image-related data to be processed from the shared memory components and, based on their configured image processing algorithms and rules, perform a series of complex calculations and processing operations on this data, such as image filtering and denoising, edge detection, and feature extraction. Ultimately, they obtain processing results with practical application value. These results can be used in various scenarios such as image optimization and display, and image recognition and analysis, effectively improving the utilization value and processing efficiency of image data. Through the collaborative cooperation of the shared memory components and logic processing components, the overall circuit achieves efficient processing and utilization of image data, providing strong technical support for various image-related applications.

[0052] These logical processing components use the same or partially the same data to process images. During image processing, these logical processing components can read the data to be processed from the shared memory component and perform the corresponding image processing, without having to read the same data to be processed from multiple memory locations, thus making effective use of storage space.

[0053] In one possible embodiment, the data to be processed is provided to the logic processing component for binocular parallax calculation. Parallax is defined as the difference in the position of the object's image on the retinal plane of the two cameras when two cameras (or human eyes) simultaneously observe the same object, due to the distance between the two cameras (baseline distance). The magnitude of parallax is related to factors such as the object distance, the camera baseline length, and the camera's focal length. The closer the object is to the camera, the greater the parallax; conversely, the farther the object is from the camera, the smaller the parallax. Therefore, binocular parallax calculation requires two images of the same area from different perspectives as the data to be processed. Based on the camera's intrinsic parameters (focal length, principal point, etc.) and extrinsic parameters (position and attitude), as well as the parallax, the depth information of the object can be calculated using the principle of triangulation. That is, using the camera's optical center as the vertex, and the triangle formed by the lines connecting the projection points of the object point on the left and right images to the optical center, the three-dimensional coordinates of the object point are calculated using geometric relationships.

[0054] The process of binocular disparity calculation is as follows: Two images are simultaneously acquired using a binocular camera. Preprocessing of the images, such as grayscale conversion and noise removal, is performed to improve the efficiency and accuracy of subsequent processing. The camera's intrinsic parameters (focal length, principal point, etc.) and extrinsic parameters (position and pose), as well as lens distortion parameters, are determined to convert image coordinates to world coordinates. Stereo correction is performed on the images to ensure corresponding points in the left and right images lie on the same scan line. This simplifies disparity calculation, requiring only a one-dimensional search for corresponding points, significantly reducing computational load. Feature points, such as corners and edges, are extracted from the images. Feature matching is then performed between the left and right images to find corresponding feature point pairs. Alternatively, pixel blocks in the images can be directly matched to calculate the optimal matching point for each pixel in the left and right images, establishing a correspondence between them. Based on the matched point pairs, the disparity value for each point is calculated. Then, triangulation formulas are used to convert the disparity value into depth information, obtaining the three-dimensional coordinates of objects in the scene.

[0055] In one possible embodiment, the data to be processed is provided to the logic processing component for superpixel segmentation calculation. Superpixel segmentation is a clustering-based image segmentation technique that divides an image into multiple regions with similar features, called superpixels. Pixels within a superpixel have similar colors, textures, and other features. Superpixel segmentation can reduce the amount of data in image processing, improve processing efficiency, and preserve important structural information of the image, facilitating subsequent image analysis tasks. A commonly used superpixel segmentation algorithm is SLIC (Simple Linear Iterative Clustering), whose core idea is to convert the image from the RGB color space to the CIELAB color space, and then perform k-means clustering in this color space by combining color and spatial information. First, cluster centers are initialized, and then a region search is performed around each cluster center, assigning pixels to the nearest cluster center. The cluster center positions are iteratively updated until a stopping condition is met. The SLIC algorithm can generate relatively regular and compact superpixels with high computational efficiency.

[0056] The specific steps of the SLIC algorithm are as follows: The image is converted from the RGB color space to the CIELAB color space to better capture color information and the characteristics of human visual perception. Based on the set number of superpixels k, the image is divided into k grids, with the center of each grid serving as the initial cluster center. To prevent the initial cluster centers from falling on edge areas or noise points, the point with the lowest gradient in the nearest 3x3 region is selected as the final initial cluster center. Within a 2S×2S region around each cluster center (S is the grid width), pixels are assigned to the nearest cluster center. The distance metric uses a distance function that combines color and spatial information, such as D = (dc / dt). 2 / 25)+(ds 2 / S 2 ), where dc is the Euclidean distance in the color space and ds is the spatial distance. Based on the clustering results, the average value of pixels in the same category is taken as the new cluster center, and the mean squared error between the new cluster center and the previous cluster center is calculated to determine if it is less than a set threshold. If the change in cluster centers is less than the set threshold, the iteration stops; otherwise, the steps of cluster assignment and updating cluster centers are repeated until the stopping condition is met.

[0057] Optionally, the shared memory component includes:

[0058] The data reading component 11 is used to read the data to be processed according to the image processing type of the logic processing component, and input the read data into the corresponding logic processing component.

[0059] In this embodiment, the shared memory component integrates a data reading component as a sub-component. This data reading component possesses intelligent sensing and precise reading capabilities. Its core responsibility is to accurately filter and read matching data content from the large amount of data to be processed stored in the shared memory component, based on the image processing type to be performed by different logic processing components.

[0060] After reading the corresponding data, the data reading component can accurately input the data into the corresponding logic processing component according to the established data transmission rules and format. This ensures that the logic processing component can receive the required processing data in a timely and efficient manner, thus laying a solid foundation for its smooth subsequent image processing work. It further improves the operating efficiency and data processing accuracy of the entire data processing circuit, enabling the circuit to better adapt to different types of image processing needs and enhancing the circuit's flexibility and practicality.

[0061] Optionally, the data reading component includes:

[0062] The sliding window control component 111 is used to control the data window to slide on the data rows in the data to be processed, read the data in the data window and transmit it to the logic processing component; the size of the data window is related to the image processing type.

[0063] In this embodiment, a sliding window control component is introduced as a core component. This component utilizes sliding window technology to flexibly control the sliding operation of the data window on the data rows to be processed. Its working principle is to pre-set a data window size appropriate for the image processing type being performed by the current logic processing component. Different image processing processes handle data differently and read different numbers of pixels from the image, necessitating adjustments to the data window size to accommodate these different image processing methods.

[0064] For example, when performing local feature analysis of an image, if it is necessary to focus on pixel feature changes within a small area of ​​the image, a smaller data window is set; while for processing tasks that require analyzing features of a larger area of ​​the image, such as overall grayscale distribution analysis, a larger data window is configured accordingly. In actual operation, the sliding window control component drives the data window to slide sequentially along the data rows. Each time it slides to a new position, it can quickly read the data content within the area covered by the data window and transmit this data to the corresponding logic processing component in real time. This achieves efficient and orderly reading and transmission of the data to be processed, providing more timely and accurate data support for the logic processing component to perform precise image processing operations. This further improves the circuit's data processing performance and image processing effect, enabling the entire circuit to more intelligently and flexibly cope with diverse image processing task scenarios.

[0065] Optionally, the sliding window control component is used to read the data in the data window and transmit it to the corresponding logic processing component after the data window has finished scanning a data row of the data to be processed.

[0066] In this embodiment, after the data window completes scanning of a complete data row in the data to be processed, the sliding window control component immediately triggers a data reading action to completely read the data contained in the data window at this time, and transmits this data to the corresponding logic processing component in a high-speed and stable data transmission mode. A row of data is treated as an atomic, indivisible unit; a complete row of data must be cached before computation can be performed. The logic processing component processes one row at a time before controlling the data window to read other rows. During the processing of one row, it is unaffected by input data bubbles or fluctuations, thus eliminating unnecessary data state flipping power consumption during processing.

[0067] This design ensures that the logic processing component can obtain the relevant data immediately after the data window completes the scanning of each row of data, avoiding data reading delays and waiting time, greatly improving the timeliness and efficiency of data transmission, ensuring the continuity and smoothness of the image processing process, and enabling the entire data processing circuit to operate more efficiently and stably when processing large-scale image data, effectively improving the overall performance of the circuit and better meeting the high requirements for image processing speed and efficiency in practical applications.

[0068] Optionally, the logic processing component is used to perform image processing based on the data read from the data window within a preset time slot.

[0069] In this embodiment, the logic processing component is designed to execute corresponding image processing tasks based on the data read from the data window within a preset time slot. This preset time slot is carefully calculated and optimized, taking into full account factors such as the complexity of the image processing algorithm, data transmission rate, and overall circuit performance. Each line of data has a fixed time slot for processing, centrally managed by a gated clock. This allows for decoupling of processing from control logic, reducing unnecessary clocking and power consumption switching. Furthermore, increasing the clock frequency within the time slot can further improve processing performance and power efficiency.

[0070] In actual operation, after the logic processing component receives data from the data window transmitted by the data reading component, it will efficiently and orderly start and complete the image processing operations within a pre-set time slot. This design ensures that the logic processing component processes data with good timeliness and regularity, avoiding disorderly fluctuations in processing time and waste of resources. It also effectively improves the overall operating efficiency of the entire circuit, enabling each logic processing component to fully utilize data resources for image processing within the specified time. This better achieves the circuit's goal of high-speed and accurate image data processing, providing more stable and efficient data processing services for various image processing applications and meeting users' stringent requirements for image processing quality and speed.

[0071] Optionally, the data reading component is used to control the data window to jump on the data column according to the number of rows to jump in the window after the logic processing component performs image processing based on the data read from the data window; the number of rows to jump in the window is related to the image processing.

[0072] In this embodiment, after the logic processing component completes the corresponding image processing task based on the data read from the data window, the data reading component will drive the data window to perform precise jump operations in the data column direction according to the preset window jump row number control rules.

[0073] The number of rows to jump in the window is a parameter carefully determined after in-depth research into image processing requirements and data distribution characteristics. It is closely related to the image processing task being performed. For example, when processing image blocks, if it is necessary to process the next specific region of the image, the data reading component will control the data window to jump to the corresponding target position on the data column according to the corresponding number of rows to jump, so as to start a new round of data reading and image processing. Through this orderly data window jumping mechanism, a comprehensive and systematic scan and processing of the entire image data to be processed can be achieved, avoiding omissions and duplications in the data processing process. This further improves the completeness, accuracy, and efficiency of the circuit in processing image data, enhances the adaptability and reliability of the circuit when processing complex image data tasks, and provides a strong guarantee for obtaining high-quality image processing results. This makes the entire data processing circuit more competitive and practical in the field of image processing.

[0074] Figure 2 This is a flowchart illustrating the data sliding window processing method provided in the embodiments of this application, as shown below. Figure 2 As shown, in one possible embodiment, depth parallax calculation involves a row-by-row sliding window operation on the image. The vertical window's sliding span is one row at a time, and after each row is slid through, the center row of the window jumps down one row. This allows for the acquisition of image data within a certain window range in the vertical direction. In the horizontal window direction, the operation is performed continuously, atomically, to complete an entire row of data. The vertical windowing of SLIC shares a data row cache with the parallax calculation. Since SLIC performs multiple iterative calculations on image segments of fixed size, it requires repeated iterations in the vertical windowing direction. The illustration shows an example of four iterations, where the vertical window of the image acquired in the four iterations is the same data row. After each four iterations, the image jumps down four rows, with the segmentation block height being four rows. The shared cache controller needs to control two sets of data shuffling logic: one set supplies data for parallax calculation, and the other supplies data for SLIC iterative calculation. This implements a dedicated data sliding window control logic, coupled with a shared cache control design for two hardened acceleration operators.

[0075] Based on the above embodiments, Figure 3 This is a flowchart illustrating the data processing method provided in an embodiment of this application. As one implementation, the data processing method of this embodiment can be configured in a data processing circuit, which can be applied to any electronic device so that the electronic device can perform data processing functions.

[0076] Among them, electronic devices can be any device with computing capabilities, such as mobile terminals, which can be hardware devices with various operating systems, touch screens and / or displays, such as mobile phones, tablets, personal digital assistants, wearable devices, etc.

[0077] As another implementation, the data processing method of this application embodiment can also be executed by a chip with processing capabilities. The chip includes an image signal processing chip (ISP), a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), a field-programmable gate array (FPGA), a system on a chip (SOC), a reduced instruction set computer (RISC), etc., which will not be listed here.

[0078] like Figure 3 As shown, the method includes the following steps:

[0079] Step 301: Store the data to be processed in the shared memory component, wherein the data to be processed is image-related data;

[0080] Step 302: Read the data to be processed from the shared memory component, input the data to be processed into the logic processing component for at least two different image processing operations, and obtain the processing result.

[0081] In this embodiment, the image data to be processed is stored in a shared memory component, and at least two logical processing components are used to perform various image processing operations on this data. Specifically, the data to be processed is first stored in the shared memory component, which can quickly and temporarily store the data so that subsequent processing components can easily access it. Then, the logical processing components read the data to be processed from the shared memory component; these components have sufficient computing power to perform complex processing tasks.

[0082] During processing, the logic processing component performs at least two different image processing operations on the image data. These operations may include image filtering and denoising, edge detection, feature extraction, and image enhancement. Each processing operation has its unique algorithm and purpose. For example, filtering and denoising can remove random noise from an image, making it clearer; edge detection can identify the boundaries of different regions in an image, providing crucial information for subsequent image segmentation and object recognition. By combining multiple processing methods, the image quality can be comprehensively improved, meeting the diverse image processing needs of different application scenarios.

[0083] The advantage of this approach lies in its efficiency and flexibility. The collaborative work of the shared memory component and the logic processing component not only improves the speed of data reading and processing but also enables the parallel execution of multiple processing tasks, thereby significantly reducing the total image processing time and improving the overall system performance. This method is particularly suitable for scenarios requiring rapid processing of large amounts of image data, such as real-time monitoring systems, medical image analysis, and visual processing in autonomous driving.

[0084] Optionally, the step of inputting the data to be processed into the logic processing component for at least two different image processing steps includes:

[0085] The data to be processed is read according to the image processing type of the logic processing component, and the corresponding image processing is performed based on the read data.

[0086] In this embodiment, it is necessary to specify the type of image processing to be performed by each logical processing component. For example, one component may be responsible for image sharpening, while another component focuses on image color correction.

[0087] The shared memory components selectively read the data to be processed based on these processing types. This selective reading ensures that each logical processing component only processes data that matches its function, thereby improving the accuracy and efficiency of the processing. For example, for image sharpening, the system reads pixel intensity and edge information from the image, while for color correction, it reads data from the color channels.

[0088] After reading the data, the logic processing component performs corresponding image processing operations based on the data. Each component has its own processing algorithm, which is designed with full consideration of its processing objectives and the characteristics of the input data to ensure high-quality processing results. For example, an image sharpening algorithm may enhance the edge contrast in an image, while a color correction algorithm adjusts the color distribution to make the image colors more accurate and natural.

[0089] This embodiment not only enhances the flexibility of the method, enabling it to adapt to various image processing needs, but also reduces unnecessary computation and improves the overall performance of the system through selective data reading and processing. This method is particularly suitable for complex scenarios that require simultaneous processing of multiple image features, such as image classification and object detection.

[0090] Optionally, reading the data to be processed according to the image processing type of the logical processing component includes:

[0091] The control data window slides over data rows in the data to be processed; the size of the data window is related to the image processing type.

[0092] Read the data from the data window and input it into the logic processing component to perform image processing.

[0093] In this embodiment, the concept of a data window can move across data rows depending on the image processing type. The size of the data window is related to the image processing type, meaning that the window size can be adjusted to best suit the needs of different types of tasks. For example, for image processing tasks requiring fine analysis, such as object recognition, the data window may be set smaller to more accurately capture object features; while for tasks such as image enhancement, a larger window may be needed to obtain more contextual information.

[0094] The system controls this data window to slide across the rows of data to be processed. This sliding operation can be horizontal or vertical, depending on the image layout and processing requirements. During the sliding process, the system reads the data within the data window and inputs this data into the logical processing component for corresponding image processing.

[0095] This embodiment can more effectively acquire and utilize spatial information in image data because the data window can flexibly slide across data rows, covering different regions of the image. Furthermore, by adjusting the size of the data window, it can better adapt to different types of image processing needs, thereby improving processing accuracy and efficiency. This method is particularly effective for tasks that require processing local features in images, such as image segmentation and texture analysis.

[0096] Optionally, reading the data in the data window and performing the corresponding image processing includes:

[0097] In response to the completion of reading one data row of the data to be processed, the corresponding image processing is performed based on the data read from the data window.

[0098] In this embodiment, during the sliding of the data window, when a complete data row is read, the system triggers a response mechanism. This response mechanism notifies the logic processing component that a complete data row has been successfully read and that data available for processing has been acquired from the data window. This step ensures the synchronicity and timeliness of the processing, avoiding delays or premature start-up in data processing.

[0099] Based on the data read from the data window, the system performs corresponding image processing operations. These operations are based on the data contained in the data window, utilizing the local image information provided by the data window. For example, if the data in the data window covers the edge portion of an object in the image, the processing operations might involve edge detection and enhancement.

[0100] After image processing is performed, the data window is controlled to jump through data columns based on the number of rows to jump. This number of rows to jump is related to the image processing task, meaning that the number of rows to jump can be adjusted to best suit the current processing needs. For example, if the goal is to perform image smoothing, the data window may need to jump through fewer rows in the data columns; while if it is to perform object recognition, it may need to jump through more rows to cover different regions in the image.

[0101] The advantage of this method lies in its ability to manage and utilize image data more efficiently. Through response mechanisms and window transition strategies, it ensures the continuity of image processing and the effective use of system resources. It is particularly suitable for scenarios requiring line-by-line or region-by-region image processing, such as image encoding and image compression.

[0102] Optionally, performing corresponding image processing based on the data read from the data window includes:

[0103] Image processing is performed based on the data read from the data window within a preset time slot.

[0104] In this embodiment, during actual data processing, each frame of image data may contain a large number of pixels and information. The challenge of real-time processing of this data lies in ensuring both processing speed and accuracy. A preset time slot refers to a fixed time period allocated for image processing operations. The length of this time period can be preset according to the complexity of the processing task and system performance.

[0105] The system divides image data into multiple parts and assigns a time slot to each part. Then, within each time slot, the system performs corresponding image processing operations based on the data read from the data window. The advantage of this time management mechanism is that it ensures that each processing operation is completed within a specified time, thereby improving processing efficiency and real-time performance. For example, in a real-time monitoring system, each frame of image needs to be processed within a short time to promptly detect anomalies and respond accordingly.

[0106] Pre-defined time slots can also help the system avoid excessive resource consumption when processing large amounts of data. By allocating time slots appropriately, the system can concentrate resources on processing a portion of the data in each time period, rather than attempting to process all the data simultaneously. This approach not only reduces processing latency but also lowers system power consumption and resource usage.

[0107] Performing image processing operations within preset time slots also ensures the continuity and consistency of the processing. For example, in processing video streams, the processing time slot for each frame can be uniformly set, making the entire video processing process stable and smooth. At the same time, this method also contributes to the scalability and maintainability of the system, because the execution of processing tasks is based on time slots, allowing for easy addition or modification of processing tasks without affecting the overall system structure.

[0108] Optionally, after performing the corresponding image processing based on the data read from the data window, the process further includes:

[0109] The number of rows the window jumps through controls the data window to jump on the data columns; the number of rows the window jumps through is related to the image processing.

[0110] In this embodiment, the introduction of the window jump row number is an important parameter in the image processing workflow. During image processing, the data window typically slides row by row along the data column direction to process different parts of the image. However, after processing the data in the current data window, the system needs to decide on the next operation, i.e., how to adjust the position of the data window to obtain new data for the next round of processing. The setting of the window jump row number determines the movement step size of the data window in the data column direction, which directly affects the efficiency and quality of image processing.

[0111] For example, in some image processing tasks, such as image smoothing, a smaller number of window jumps may be needed because smoothing typically requires processing adjacent regions consecutively to ensure the continuity of the smoothing effect. However, tasks like object recognition or feature extraction, which need to cover different regions of the image, may require a larger number of window jumps to quickly cover key areas of the image and avoid repeatedly processing the same areas.

[0112] The number of rows to jump in a window is closely related to the complexity and objectives of the image processing task. For high-precision image analysis tasks, such as cell detection in medical imaging, the number of rows to jump in a window may be set smaller to ensure that no critical details are missed. However, in scenarios with high speed requirements, such as real-time monitoring or video streaming, the number of rows to jump in a window can be set larger to improve processing speed. This flexibility allows the present invention to adapt to a variety of different image processing needs, providing broader applicability.

[0113] This embodiment not only enhances the flexibility and adaptability of the entire data processing method, but also significantly improves the efficiency and accuracy of image processing. In practical applications, this method can effectively reduce the total data processing time while ensuring the quality of the processing results, bringing an innovative and practical solution to the field of image processing.

[0114] To implement the above embodiments, this application also proposes a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the method described in the foregoing method embodiments.

[0115] To implement the above embodiments, this application also proposes a computer program product having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method described in the foregoing method embodiments.

[0116] To implement the above embodiments, this application also proposes an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method described in the foregoing method embodiments.

[0117] To implement the above embodiments, this application also proposes an electronic device, which includes the data processing circuit as described in the foregoing embodiments.

[0118] To implement the above embodiments, this application also proposes a chip that includes the data processing circuitry as described in the foregoing embodiments.

[0119] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. For example, the electronic device 800 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0120] Reference Figure 4 The electronic device 800 may include one or more of the following components: processing component 802, memory 804, power component 806, multimedia component 808, audio component 810, input / output (I / O) interface 812, sensor component 814, and communication component 816.

[0121] Processing component 802 typically controls the overall operation of electronic device 800, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 802 may include one or more processors 820 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 802 may include one or more modules to facilitate interaction between processing component 802 and other components. For example, processing component 802 may include a multimedia module to facilitate interaction between multimedia component 808 and processing component 802.

[0122] Memory 804 is configured to store various types of data to support the operation of electronic device 800. Examples of this data include instructions for any application or method operating on electronic device 800, contact data, phonebook data, messages, pictures, videos, etc. Memory 804 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0123] Power component 806 provides power to various components of electronic device 800. Power component 806 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 800.

[0124] Multimedia component 808 includes a screen that provides an output interface between the electronic device 800 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 808 includes a front-facing camera and / or a rear-facing camera. When the electronic device 800 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0125] Audio component 810 is configured to output and / or input audio signals. For example, audio component 810 includes a microphone (MIC) configured to receive external audio signals when electronic device 800 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 804 or transmitted via communication component 816. In some embodiments, audio component 810 also includes a speaker for outputting audio signals.

[0126] I / O interface 812 provides an interface between processing component 802 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0127] Sensor assembly 814 includes one or more sensors for providing state assessments of various aspects of electronic device 800. For example, sensor assembly 814 can detect the on / off state of electronic device 800, the relative positioning of components such as the display and keypad of electronic device 800, changes in position of electronic device 800 or a component of electronic device 800, the presence or absence of user contact with electronic device 800, orientation or acceleration / deceleration of electronic device 800, and temperature changes of electronic device 800. Sensor assembly 814 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 814 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 814 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0128] Communication component 816 is configured to facilitate wired or wireless communication between electronic device 800 and other devices. Electronic device 800 can access wireless networks based on communication standards, such as WiFi, 4G, or 5G, or combinations thereof. In one exemplary embodiment, communication component 816 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 816 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0129] In an exemplary embodiment, the electronic device 800 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the methods described above.

[0130] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 804 including instructions, which can be executed by a processor 820 of an electronic device 800 to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0131] To implement the above embodiments, this application also proposes a chip, including: the chip includes a processing circuit configured to perform the methods provided in the foregoing embodiments.

[0132] Figure 5 This is a schematic diagram of the structure of a chip according to an embodiment of this application. See also... Figure 5 The diagram shown is a schematic representation of the structure of chip 1100, but it is not limited to this.

[0133] Chip 1100 includes processing circuitry 1101, which is configured to perform any of the above methods.

[0134] In some embodiments, chip 1100 further includes one or more interface circuits 1102. Optionally, the interface circuit 1102 is connected to memory 1103, and the interface circuit 1102 can be used to receive signals from memory 1103 or other devices, and the interface circuit 1102 can be used to send signals to memory 1103 or other devices. For example, the interface circuit 1102 can read instructions stored in memory 1103 and send the instructions to processing circuit 1101.

[0135] In some embodiments, the interface circuit 1102 performs at least one of the communication steps such as sending and / or receiving in the above method, while the processing circuit 1101 performs other steps.

[0136] In some embodiments, the terms interface circuit, interface, transceiver pin, transceiver, etc., can be used interchangeably.

[0137] In some embodiments, chip 1100 further includes one or more memories 1103 for storing instructions. Optionally, all or part of the memories 1103 may be located outside of chip 1100.

[0138] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0139] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0140] Any process or method description in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0141] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0142] It should be understood that various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0143] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0144] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0145] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A data processing circuit, characterized in that, include: A shared memory component, and at least two logical processing components, wherein the shared memory component is connected to the logical processing components; The shared memory component is used to store data to be processed; The logic processing component is used to perform image processing based on the data to be processed in the shared memory component to obtain the processing result, wherein the data to be processed is image-related data.

2. The circuit according to claim 1, characterized in that, The shared memory component includes: The data reading component is used to read the data to be processed according to the image processing type of the logic processing component, and input the read data into the corresponding logic processing component.

3. The circuit according to claim 2, characterized in that, The data reading component includes: A sliding window control component is used to control the data window to slide on the data rows in the data to be processed, read the data in the data window and transmit it to the logic processing component; the size of the data window is related to the image processing type.

4. The circuit according to claim 3, characterized in that, The sliding window control component is used to read the data in the data window and transmit it to the corresponding logic processing component after the data window has finished scanning a data row of the data to be processed.

5. The circuit according to claim 4, characterized in that, The logic processing component is used to perform image processing based on the data read from the data window within a preset time slot.

6. The circuit according to claim 4, characterized in that, The data reading component is used to control the data window to jump on the data column according to the number of rows to jump in the window after the logic processing component performs image processing based on the data read from the data window; the number of rows to jump in the window is related to the image processing.

7. A data processing method, characterized in that, include: The data to be processed is stored in a shared memory component, and the data to be processed is image-related data; Read the data to be processed from the shared memory component, input the data to be processed into the logic processing component to perform at least two different image processing operations, and obtain the processing result.

8. The method according to claim 7, characterized in that, The step of inputting the data to be processed into the logic processing component for at least two different image processing operations includes: The data to be processed is read according to the image processing type of the logic processing component, and the corresponding image processing is performed based on the read data.

9. The method according to claim 8, characterized in that, The step of reading the data to be processed according to the image processing type of the logic processing component includes: The control data window slides over data rows in the data to be processed; the size of the data window is related to the image processing type. Read the data from the data window and input it into the logic processing component to perform image processing.

10. The method according to claim 9, characterized in that, The step of reading data from the data window and performing corresponding image processing includes: In response to the completion of reading one data row of the data to be processed, the corresponding image processing is performed based on the data read from the data window.

11. The method according to claim 10, characterized in that, The step of performing corresponding image processing based on the data read from the data window includes: Image processing is performed based on the data read from the data window within a preset time slot.

12. The method according to claim 10, characterized in that, After performing the corresponding image processing based on the data read from the data window, the process further includes: The number of rows the window jumps through controls the data window to jump on the data columns; the number of rows the window jumps through is related to the image processing.

13. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, it implements the method as described in any one of claims 7-12.

14. A chip, characterized in that, The chip includes processing circuitry configured to perform the method described in any one of claims 7-12.

15. A chip, characterized in that, Includes the circuit as described in any one of claims 1-6.

16. An electronic device, characterized in that, Includes the circuit as described in any one of claims 1-6.

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