Goa repair circuit, array substrate and display panel

Abstract

This application discloses a GOA repair circuit, an array substrate, and a display panel, belonging to the field of display technology. The GOA repair circuit is applied to an array substrate, which includes a display area and a non-display area. The non-display area surrounds the display area, and the GOA repair circuit is disposed within the non-display area. The GOA repair circuit is electrically connected to an input repair line, an output repair line, a power line, and a clock line. The GOA repair circuit is configured to: when a specified scan line electrically connected to an abnormal GOA unit needs to be driven, receive a drive signal output from a normal GOA unit through the input repair line, adjust the drive signal based on signals from the power line and the clock line to obtain a repair signal, and output the repair signal to the specified scan line through the output repair line; wherein, the abnormal GOA unit is electrically connected to the nth scan line on the first side of the display area, and the normal GOA unit is electrically connected to the nth scan line on the second side of the display area.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to GOA repair circuits, array substrates, and display panels. Background Technology

[0002] The gate driving circuit of the array substrate contains multiple cascaded GOA (Gate on Array) units. The output signal generated by each GOA unit not only provides the turn-on voltage for the pixel unit in the current row, but also serves as the pull-up and pull-down signals for the GOA units in front and behind. Therefore, an abnormality in a single GOA unit not only affects the display output of the current stage, but also affects the output of the cascaded signals, causing abnormalities in the output of other GOA units, resulting in display abnormalities in the entire screen.

[0003] Due to the large number of components and high integration of GOA units, repairing faulty components is quite difficult. Currently, a common solution is to output the normal in-plane signal to the outside of the panel, and then amplify and regulate the signal through an external PCB (Printed Circuit Board) before sending it back into the in-plane. This method has a large operating space on the outside, so the repair effect is good. However, this method requires the addition of related logic processing functions on the external PCB, resulting in higher design and electronic component costs. Summary of the Invention

[0004] The main objective of this application is to provide a GOA repair circuit, an array substrate, and a display panel, aiming to solve the technical problem of how to repair abnormal GOA cells in the array substrate without the aid of an external PCB.

[0005] To achieve the above objectives, this application provides a GOA repair circuit, which is applied to an array substrate. The array substrate includes a display area and a non-display area. The non-display area surrounds the periphery of the display area. The GOA repair circuit is disposed in the non-display area and is electrically connected to an input repair line, an output repair line, a power line, and a clock line. The GOA repair circuit is configured to: when a designated scan line electrically connected to an abnormal GOA unit needs to be driven, a drive signal output by a normal GOA unit is received through the input repair line; the drive signal is adjusted based on signals from the power line and the clock line to obtain a repair signal; and the repair signal is output to the designated scan line through the output repair line; wherein, the abnormal GOA unit is electrically connected to the nth scan line on the first side of the display area, and the normal GOA unit is electrically connected to the nth scan line on the second side of the display area.

[0006] In one embodiment, the GOA repair circuit includes: The first thin-film transistor has a common gate and drain, and its source serves as a first signal node. The second thin-film transistor has a gate for accessing the drive signal through the input repair line, a drain for being electrically connected to the first signal node, and a source for being connected to a source reference voltage. The third thin-film transistor has its gate and drain connected together and is electrically connected to the gate and drain of the first thin-film transistor. The source of the third thin-film transistor serves as the second signal node. A fourth thin-film transistor, wherein the gate of the fourth thin-film transistor is electrically connected to the first signal node, the drain of the fourth thin-film transistor is electrically connected to the second signal node, and the source of the fourth thin-film transistor is connected to the source reference voltage; The fifth thin-film transistor has its gate electrically connected to the second signal node, its drain used to receive a first clock signal from the input side of the abnormal GOA unit via the clock line, and its source used as the third signal node. A sixth thin-film transistor, the drain of which is electrically connected to the third signal node, and the source of which is used to output the repair signal to the output repair line.

[0007] In one embodiment, when a scan line electrically connected to an abnormal GOA cell needs to be driven, the gate and drain of the first thin-film transistor, the gate and drain of the third thin-film transistor are connected to a first driving voltage from the power supply line, the gate of the second thin-film transistor is connected to the driving signal, the drain of the fifth thin-film transistor is connected to the first clock signal, and the gate of the sixth thin-film transistor is connected to a second driving voltage from the power supply line, such that the first and third thin-film transistors are turned on, the second thin-film transistor is turned on, the fourth thin-film transistor is turned off, the fifth thin-film transistor is turned on, and the sixth thin-film transistor is turned on; wherein, the first driving voltage is greater than the source reference voltage and the peak voltage of the first clock signal, and the second driving voltage is greater than the source reference voltage.

[0008] In one embodiment, a first ratio obtained by dividing the channel width-to-length ratio of the first thin-film transistor by the channel width-to-length ratio of the second thin-film transistor is less than a second ratio obtained by dividing the channel width-to-length ratio of the third thin-film transistor by the channel width-to-length ratio of the fourth thin-film transistor. The channel width-to-length ratio of the fifth thin-film transistor and the channel width-to-length ratio of the sixth thin-film transistor are greater than the channel width-to-length ratio of the driving thin-film transistor in the normal GOA unit.

[0009] In one embodiment, the GOA repair circuit further includes: A seventh thin-film transistor, wherein the gate and drain of the seventh thin-film transistor are connected together and are used to access the driving signal through the input repair line; the source of the seventh thin-film transistor is electrically connected to the gate of the second thin-film transistor, serving as the fourth signal node. The eighth thin-film transistor has its drain electrically connected to the fourth signal node, its gate used to receive a second clock signal, and its source connected to the source reference voltage; wherein the waveform of the second clock signal does not overlap with the waveform of the first clock signal at all.

[0010] In one embodiment, the start time of the rising edge of the second clock signal is later than the end time of the falling edge of the first clock signal, so that the falling edge of the signal of the fourth signal node, the rising edge of the signal of the first signal node, and the falling edge of the signal of the second signal node are delayed.

[0011] In one embodiment, the GOA repair circuit further includes: A ninth thin-film transistor, wherein the gate of the ninth thin-film transistor is electrically connected to the first signal node, the drain of the ninth thin-film transistor is electrically connected to the third signal node, and the source of the ninth thin-film transistor is connected to the source reference voltage.

[0012] In one embodiment, when the gate and drain of the first thin-film transistor and the gate and drain of the third thin-film transistor are connected to a first driving voltage from the power line, and the gate of the seventh thin-film transistor is not connected to the driving signal, the ninth thin-film transistor is turned on to suppress noise at the third signal node.

[0013] In addition, to achieve the above objectives, this application embodiment also provides an array substrate, the array substrate including a display area and a non-display area, the non-display area surrounding the periphery of the display area, and the non-display area being provided with the GOA repair circuit as described above.

[0014] In addition, to achieve the above objectives, this application embodiment also provides a display panel, which includes the array substrate described above.

[0015] This application provides a GOA repair circuit, an array substrate, and a display panel. The GOA repair circuit can be disposed in the non-display area of ​​the array substrate. When a specified scan line that is electrically connected to an abnormal GOA unit needs to be driven, the circuit can input the drive signal output by the normal GOA unit through the repair line, and adjust the drive signal based on the signals from the power line and the clock line to obtain the repair signal. The repair signal is then output to the specified scan line through the output repair line, thereby driving the corresponding pixel normally. Therefore, in the case of an abnormal GOA unit in the array substrate, this application can directly repair it through the in-plane GOA repair circuit without adding an external PCB and its related logic processing functions. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only a part of the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the layout structure of a GOA repair circuit in an array substrate provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a GOA repair circuit provided in an embodiment of this application; Figure 3 A timing waveform diagram related to a GOA repair circuit provided in an embodiment of this application; Figure 4 This is a schematic diagram of another GOA repair circuit provided in an embodiment of this application; Figure 5 A timing waveform diagram of another GOA repair circuit provided in this application embodiment; Figure 6 In order to be in Figure 3 Based on this, a time-series waveform diagram illustrating the noise is presented; Figure 7 This is a schematic diagram of another GOA repair circuit provided in an embodiment of this application.

[0018] Explanation of icon numbers: AA, Display area; IN_L & IN_R, Input repair lines; OUT_L & OUT_R, Output repair lines; CK_L & CK_R, Clock lines; T1, First thin-film transistor; P1, First signal node; Vin, Drive signal; T2, Second thin-film transistor; VSS, Source reference voltage; T3, Third thin-film transistor; P2, Second signal node; T4, Fourth thin-film transistor; T5, Fifth thin-film transistor; CK, First clock signal; P3, Third signal node; T6, Sixth thin-film transistor; Vout, Repair signal; Vgh1, First drive voltage; Vgh2, Second drive voltage; T7, Seventh thin-film transistor; P4, Fourth signal node; T8, Eighth thin-film transistor; CK_b, Second clock signal; T9, Ninth thin-film transistor. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that the embodiments of this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the embodiments of this application with unnecessary detail.

[0020] The gate driving circuit of the array substrate contains multiple cascaded GOA (Gate on Array) units. The output signal generated by each GOA unit not only provides the turn-on voltage for the pixel unit in the current row, but also serves as the pull-up and pull-down signals for the GOA units in front and behind. Therefore, an abnormality in a single GOA unit not only affects the display output of the current stage, but also affects the output of the cascaded signals, causing abnormalities in the output of other GOA units, resulting in display abnormalities in the entire screen.

[0021] Due to the large number of components and high integration of GOA units, repairing faulty components is quite difficult. Currently, a common solution is to output the normal in-plane signal to the outside of the panel, and then amplify and regulate the signal through an external PCB (Printed Circuit Board) before sending it back into the in-plane. This method has a large operating space on the outside, so the repair effect is good. However, this method requires the addition of related logic processing functions on the external PCB, resulting in higher design and electronic component costs.

[0022] Based on this, this application provides a GOA repair circuit, an array substrate, and a display panel. The GOA repair circuit can be disposed in the non-display area of ​​the array substrate. When a specified scan line that is electrically connected to an abnormal GOA unit needs to be driven, the circuit can input the drive signal output by the normal GOA unit through the repair line, and adjust the drive signal based on the signals from the power line and the clock line to obtain the repair signal. Then, the repair signal is output to the specified scan line through the output repair line, thereby driving the corresponding pixel normally. Therefore, when an abnormal GOA unit appears in the array substrate, this application can directly repair it through the in-plane GOA repair circuit, and has strong control capability and good repair effect, without the need to add an external PCB and its related logic processing functions.

[0023] The GOA repair circuit, array substrate, and display panel provided in this application are specifically described through the following embodiments. First, the GOA repair circuit in this application embodiment is described.

[0024] This application provides a GOA repair circuit, referring to... Figure 1 , Figure 1 This is a schematic diagram of a GOA repair circuit provided in an embodiment of this application. In this embodiment, the GOA repair circuit is applied to an array substrate. The array substrate includes a display area AA (Active Area) and a non-display area. The non-display area surrounds the periphery of the display area AA. The GOA repair circuit is disposed in the non-display area and is electrically connected to the input repair line, the output repair line, the power line, and the clock line. The GOA repair circuit is configured as follows: when a specified scan line that needs to be driven and electrically connected to the abnormal GOA unit needs to be driven, the drive signal output by the normal GOA unit is connected through the input repair line, the drive signal is adjusted based on the signals from the power line and the clock line to obtain the repair signal, and the repair signal is output to the specified scan line through the output repair line; wherein, the abnormal GOA unit is electrically connected to the nth scan line on the first side of the display area, and the normal GOA unit is electrically connected to the nth scan line on the second side of the display area.

[0025] In this embodiment, a multi-level GOA unit is disposed on both sides of the display area AA in the non-display area of ​​the array substrate. Each GOA unit is connected to the display area AA through a corresponding scan line. When it is necessary to activate the nth row of pixels, the driving signal can be provided to the display area AA through the nth scan line connected to the nth level GOA unit on both sides to activate the nth row of pixels. Figure 1As shown, when the GOA units are located close to the first side and the second side of the display area AA, respectively, the GOA repair circuit can be added to the third side of the display area AA without changing the original layout of the GOA units relative to the display area AA.

[0026] It should be noted that since both GOA units may malfunction, in order to facilitate repair on both sides, the input repair line and the output repair line in this embodiment can also be arranged on the first and second sides of the display area AA respectively, and cross the scan line at different layers. When it is necessary to connect the drive signal or output repair signal, the input repair line and the output repair line can be connected to the corresponding scan line by using the reserved laser points.

[0027] As an example, with Figure 1 Taking the left side as the first side of the display area AA and the right side as the second side of the display area AA as an example, the input repair lines include IN_L on the left and IN_R on the right, and the output repair lines include OUT_L on the left and OUT_R on the right. In this way, if the abnormal GOA unit is the nth level GOA unit on the right, the drive signal output by the nth level GOA unit on the left can be connected to the left input repair line IN_L, and provided to the GOA repair circuit for adjustment to obtain a repair signal. Then, the right output repair line OUT_R provides the repair signal to the nth level scan line connected to the nth level GOA unit on the right, thereby normally opening the nth row of pixels. Similarly, if the abnormal GOA unit is the nth level GOA unit on the left, the drive signal output by the nth level GOA unit on the right can be connected to the right input repair line IN_R, and provided to the GOA repair circuit for adjustment to obtain a repair signal. Then, the left output repair line OUT_L provides the repair signal to the nth level scan line connected to the nth level GOA unit on the left, thereby normally opening the nth row of pixels.

[0028] It should be noted that when using the GOA repair circuit provided in this embodiment for repair, the output signal of the abnormal GOA unit needs to be isolated from the display area AA. The specific isolation method can be flexibly adjusted according to the actual situation, and this embodiment does not impose any restrictions on it.

[0029] In this embodiment, as Figure 1 The array substrate shown omits the buslines on both sides. The buslines are used to import pole drive signals from the bonding area to each GOA unit. The power lines can be two additional traces added to the buslines, which can provide Vgh1 and Vgh2 to the GOA repair circuit respectively.

[0030] Understandably, the clock lines CK_L & CK_R can also be laid out on the left and right sides, and when repair is needed, the reserved laser points are used to connect with the clock signal line on the input side of the abnormal GOA unit, so that the GOA repair circuit can access the clock signal synchronized with the abnormal GOA unit.

[0031] Reference Figure 2 In some feasible embodiments, the above-described GOA repair circuit may include: The first thin-film transistor T1 has its gate and drain connected together, and its source is used as the first signal node P1. The second thin-film transistor T2 has its gate connected to the drive signal Vin via the input repair line, its drain connected to the first signal node P1, and its source connected to the source reference voltage VSS. The third thin-film transistor T3 has its gate and drain connected together and is electrically connected to the gate and drain of the first thin-film transistor T1. The source of the third thin-film transistor T3 serves as the second signal node P2. The fourth thin-film transistor T4 has its gate electrically connected to the first signal node P1, its drain electrically connected to the second signal node P2, and its source connected to the source reference voltage VSS. The fifth thin-film transistor T5 has its gate electrically connected to the second signal node P2. The drain of the fifth thin-film transistor T5 is used to receive the first clock signal CK from the input side of the abnormal GOA unit through the clock line. The source of the fifth thin-film transistor T5 serves as the third signal node P3. The sixth thin-film transistor T6 has its drain electrically connected to the third signal node P3, and its source is used to output the repair signal Vout to the output repair line.

[0032] In this embodiment, when repair is required, the gate and drain of the first thin-film transistor T1 and the gate and drain of the third thin-film transistor T3 can be connected to Vgh1 from the power supply line, and the gate opening of the sixth thin-film transistor T6 should be connected to Vgh2 from the power supply line. When no repair is required, the gate and drain of the first thin-film transistor T1, the gate and drain of the third thin-film transistor T3, and the gate of the sixth thin-film transistor T6 can all be connected to the source reference voltage VSS or ground. Such signal switching can be achieved by setting a switch between each terminal and the power supply line and the reference ground, or by additional component bonding or wire bonding. This embodiment does not limit this.

[0033] In this embodiment, the GOA repair circuit can be based on, for example... Figure 3 Repair each signal in the timing waveform diagram shown. Figure 3 In this context, the Gout signal is the output signal of the normal GOA unit, which is at the same level as the abnormal GOA unit. Its ideal waveform is as follows: Figure 3 The standard square wave is represented by the blue dashed line. However, due to the loading effect of the clock signal line and the display area AA, the actual output waveform of the Gout signal will have slight waveform distortion. Therefore, its actual output waveform is as follows: Figure 3 As shown by the green dashed line, this is a normal waveform change. However, because the Gout signal needs to travel a long distance through the input repair line to reach the GOA repair circuit, its waveform may experience further delay. Therefore, the waveform of the drive signal Vin actually received by the GOA repair circuit is as follows: Figure 3 As shown by the red dashed line in the middle. It can be understood that the first clock signal CK is synchronized with the clock signal connected to the abnormal GOA unit.

[0034] In some feasible embodiments, when it is necessary to drive the scan line electrically connected to the abnormal GOA unit, the gate and drain of the first thin-film transistor T1 and the gate and drain of the third thin-film transistor T3 are connected to the first driving voltage Vgh1 from the power supply line, the gate of the second thin-film transistor T2 is connected to the driving signal Vin, the drain of the fifth thin-film transistor T5 is connected to the first clock signal CK, and the gate of the sixth thin-film transistor T6 is connected to the second driving voltage Vgh2 from the power supply line, so that the first thin-film transistor T1 and the third thin-film transistor T3 are turned on, the second thin-film transistor T2 is turned on, the fourth thin-film transistor T4 is turned off, the fifth thin-film transistor T5 is turned on, and the sixth thin-film transistor T6 is turned on; wherein, the first driving voltage Vgh1 is greater than the source reference voltage VSS and the peak voltage of the first clock signal CK, and the second driving voltage Vgh2 is greater than the source reference voltage VSS.

[0035] In this embodiment, combined with Figure 2 and Figure 3It can be seen that when the gate and drain of the first thin-film transistor T1 and the gate and drain of the third thin-film transistor T3 are connected to a high-level first driving voltage Vgh1, the first thin-film transistor T1 and the third thin-film transistor T3 are turned on, and the first signal node P1 is at a high level. When the gate of the second thin-film transistor T2 is connected to the driving signal Vin, as the driving signal Vin voltage gradually increases, the second thin-film transistor T2 is turned on, thereby pulling the potential of the first signal node P1 down to the source reference voltage VSS. The fourth thin-film transistor T4 is turned off, and the potential of the second signal node P2 is pulled up to a high level by the first driving voltage Vgh1. The fifth thin-film transistor T5 is turned on, and the first clock signal CK is output to the third signal node P3. The sixth thin-film transistor T6 is turned on because its gate is connected to a high-level second driving voltage Vgh2, so that the signal at the third signal node is formed into a repair signal Vout through the sixth thin-film transistor T6. As the voltage of the driving signal Vin gradually decreases to the source reference voltage VSS, the second thin-film transistor T2 will turn off again, causing the potential of the first signal node P1 to be pulled up by the unidirectional circuit formed by the first thin-film transistor T1. Since the driving signal Vin has a large Tr (rising edge) and Tf (falling edge), the first signal node P1 has similar delay characteristics.

[0036] In this embodiment, the first ratio obtained by dividing the channel width-to-length ratio (W / L) of the first thin-film transistor T1 by the channel width-to-length ratio of the second thin-film transistor T2 is less than the second ratio obtained by dividing the channel width-to-length ratio of the third thin-film transistor T3 by the channel width-to-length ratio of the fourth thin-film transistor T4; the channel width-to-length ratios of the fifth thin-film transistor T5 and the sixth thin-film transistor T6 are greater than the channel width-to-length ratios of the driving thin-film transistors in a normal GOA cell.

[0037] As an example, the first ratio is smaller than that of a conventional inverter, and the channel width-to-length ratio of the first thin-film transistor T1 needs to be smaller. The purpose is to reduce the charge release rate within the second signal node P2 during the falling edge Tf of the drive signal Vin, thereby increasing the output delay and thus increasing the rising edge Tr of the first signal node P1. Conversely, during the rising edge Tr of the drive signal Vin, the charge accumulation rate within the first signal node P1 is faster, resulting in a shorter falling edge Tf for the first signal node P1. Similarly, the third thin-film transistor T3 and the fourth thin-film transistor T4 form the same structure as the first thin-film transistor T1 and the second thin-film transistor T2. When the first signal node P1 is high, the second signal node P2 is low; when the first signal node P1 is low, the second signal node P2 is high (Vgh1). Therefore, the second signal node P2 has the same delay characteristics as the first signal node P1. The second ratio does not need to be larger than that of a conventional inverter to increase the falling edge Tf of the second signal node P2 and avoid a surge in power consumption. In addition, the channel width-to-length ratio of the fifth thin-film transistor T5 and the sixth thin-film transistor T6 should be set to be much larger than the channel width-to-length ratio of the driving TFT (ThinFilm Transistor) responsible for outputting the driving signal in the normal GOA cell, so as to improve the driving capability of the GOA repair circuit and avoid the degradation of waveform quality due to insufficient channel width-to-length ratio of the thin-film transistor.

[0038] Furthermore, when the third signal node P3 is at the rising edge Tr, the output of the first clock signal CK is limited by the rising edge Tr waveform of the gate signal P2. The rising edge Tr result of the third signal node P3 is basically the same as the rising edge Tr of P2. However, when the third signal node P3 is at the falling edge Tf, the second signal node P2 has a large falling edge Tf due to the delay characteristics of the drive signal Vin and the adjustment of the TFT channel width-to-length ratio. Therefore, when the first clock signal CK is at the falling edge Tf, the fifth thin film transistor T5 is still in the on state, the third signal node P3 can be pulled down normally, and it has a good falling edge Tf performance, just like the first clock signal CK.

[0039] In this embodiment, the first driving voltage Vgh1 is greater than the highest voltage Vgh corresponding to the first clock signal CK, so that when the fifth thin-film transistor T5 is turned on based on Vgh1 at the second signal node P2, it has a better on state (Vgs of the fifth thin-film transistor T5 = Vgh1 - Vgh), avoiding severe distortion of the signal waveform at the third signal node P3 due to insufficient on state of the fifth thin-film transistor T5. The voltage value of the first driving voltage Vgh1 can be adjusted appropriately. When the first driving voltage Vgh1 is reduced, the highest voltage of the first signal node P1 and the second signal node P2 decreases, and the waveform delay is aggravated. Therefore, controlling the on state of the fifth thin-film transistor T5 can control the falling edge Tf of the third signal node P3.

[0040] In this embodiment, the highest voltage of the repair signal Vout is limited by the highest voltage of the gate signal of the sixth thin film transistor T6. Therefore, the signal waveform of the repair signal Vout is basically the same as the signal waveform of the third signal node P3. However, its highest voltage is the second driving voltage Vgh2 connected to the gate of the sixth thin film transistor T6. Therefore, the highest voltage of the repair signal Vout can be controlled by adjusting the voltage of the second driving voltage Vgh2.

[0041] The GOA repair circuit provided in this embodiment ensures the driving strength of the repair signal Vout. The falling edge of the repair signal Vout can be adjusted by changing the first driving voltage Vgh1, and the peak voltage of the repair signal Vout can be adjusted by changing the second driving voltage Vgh2. Therefore, during the actual repair process, the waveform quality of the repair signal Vout can be adjusted according to the actual display effect, thereby controlling its charging rate and degree of incorrect charging, so that the display effect after repair on the side where the abnormal GOA unit is located is consistent with that on the side where the normal GOA unit is located. In practical applications, repair conditions can also be set using the above adjustment method for abnormal GOA units located in different positions, so that the repair effect can be optimal at any position.

[0042] The GOA repair circuit provided in this embodiment only needs to adjust the first driving voltage Vgh1 and the second driving voltage Vgh2 provided by the outside to complete the effect control after repair. Therefore, there is no need to design an external logic unit to process and transmit the output signal, which greatly reduces the design cost required for repair. Moreover, the additional signal is a DC signal, which hardly increases the design difficulty and cost of external control. It has a wide range of applications, and this function can be reserved for mass production materials in the actual production process.

[0043] Considering that the falling edge Tf period of the third signal node P3 in the above embodiment mainly relies on the delay waveform of the falling edge Tf of the second signal node P2, and that Vgs=VP2-VSS of the fifth thin film transistor T5 will decrease as the voltage of the second signal node P2 decreases during this process, the pull-down of the signal of the third signal node P3 is greatly affected by the falling edge Tf of the second signal node P2, and the falling edge Tf of the second signal node P2 is greatly affected by the Tf condition of the input drive signal Vin, the TFT ratio, and the degree of TFT aging.

[0044] To avoid such situations, this embodiment provides the following: Figure 4 Another GOA repair circuit is shown, refer to Figure 4 In this embodiment, as Figure 2 The GOA repair circuit shown may also include: The seventh thin-film transistor T7 has a common gate and drain, and is used to connect the drive signal Vin through the input repair line. The source of the seventh thin-film transistor T7 is electrically connected to the gate of the second thin-film transistor T2, serving as the fourth signal node P4. The eighth thin-film transistor T8 has its drain electrically connected to the fourth signal node P4, its gate used to receive the second clock signal CK_b, and its source connected to the source reference voltage VSS. The waveform of the second clock signal CK_b is completely different from the waveform of the first clock signal CK.

[0045] The GOA repair circuit provided in this embodiment adds a seventh thin-film transistor T7 and an eighth thin-film transistor T8 compared to the previous embodiment, and can be based on... Figure 5 The signals in the timing waveform diagram shown are repaired. The waveform of the newly added second clock signal CK_b is completely different from that of the first clock signal CK. It can be regarded as a complementary clock signal of the first clock signal CK. The selective input method of the second clock signal CK_b can be the same as that of the first clock signal CK, that is, based on the clock line and the reserved solder point for conduction input. Other feasible methods can also be used. This embodiment does not limit this.

[0046] In this embodiment, the starting time of the rising edge of the second clock signal CK_b is later than the ending time of the falling edge of the first clock signal CK, causing the falling edge of the signal at the fourth signal node P4, the rising edge of the signal at the first signal node P1, and the falling edge of the signal at the second signal node P2 to be delayed. Specifically, in conjunction with Figure 4 and Figure 5It can be seen that after the drive signal Vin is applied to the gate of the seventh thin-film transistor T7, the seventh thin-film transistor T7 is turned on, and the drive signal Vin charges the fourth signal node P4, so that the high potential of the fourth signal node P4 can continue to be maintained for a certain period of time after the drive signal Vin drops to VSS, that is, the falling edge of the signal at the fourth signal node P4 is delayed; it can be understood that the eighth thin-film transistor T8 can only be turned on when the second clock signal CK_b is high, and pulls the potential of the fourth signal node P4 down to VSS. Therefore, the falling edge of the gate signal acting on the second thin-film transistor T2 is relatively delayed compared to the aforementioned Figure 2 and Figure 3 In the corresponding embodiment, there is a controlled delay. Under the control of the signal waveform of the fourth signal node P4, the rising edge of the first signal node P1 and the falling edge of the second signal node P2 are both controlled to be delayed. Therefore, when the first clock signal CK is at the falling edge, the second signal node P2 is still at a high level, which makes the third signal node P3 have a better falling edge and is not affected by the Tf condition of the driving signal Vin, the TFT ratio and the degree of TFT aging, thus improving the upper limit of waveform quality.

[0047] In the above embodiments, when the second signal node P2 is at a low potential, due to the voltage division effect of the third thin-film transistor T3 and the fourth thin-film transistor T4, the voltage of the second signal node P2 will be slightly higher than VSS. Therefore, even when the fifth thin-film transistor T5 does not require conduction, a micro-conduction phenomenon may occur, resulting in the third signal node P3 generating a voltage similar to VSS. Figure 6 The noise shown leads to noise in the repair signal Vout as well, affecting the display effect after repair.

[0048] Based on this, this embodiment provides the following: Figure 7 Another GOA repair circuit is shown, refer to Figure 7 In this embodiment, as Figure 4 The GOA repair circuit shown may also include: The ninth thin-film transistor T9 has its gate electrically connected to the first signal node P1, its drain electrically connected to the third signal node P3, and its source connected to the source reference voltage VSS.

[0049] In this embodiment, when the gate and drain of the first thin-film transistor T1 and the gate and drain of the third thin-film transistor T3 are connected to the first driving voltage Vgh1 from the power supply line, and the gate of the seventh thin-film transistor T7 is not connected to the driving signal Vin, the ninth thin-film transistor T9 is turned on to suppress the noise of the third signal node P3. That is, when the GOA repair circuit is powered on but does not need to drive the scan line corresponding to the abnormal GOA unit, the high potential at the first signal node P1 keeps the ninth thin-film transistor T9 in a continuously conducting state, thereby pulling down the third signal node P3 to reduce noise and effectively suppressing the influence of the noise generated by the fifth thin-film transistor T5 on the repair signal Vout. At the same time, the noise reduction effect of the ninth thin-film transistor T9 can also suppress various coupling noises caused by newly reserved lines such as input repair lines, output repair lines, power supply lines, and clock lines.

[0050] Furthermore, this application embodiment also provides an array substrate, which includes a display area and a non-display area, with the non-display area surrounding the periphery of the display area, and the aforementioned GOA repair circuit disposed in the non-display area.

[0051] The specific structure of the GOA repair circuit in this embodiment refers to the above embodiments. Since the array substrate provided in this embodiment adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here.

[0052] Furthermore, embodiments of this application also provide a display panel, which includes the array substrate described above.

[0053] As an example, the display panel in this embodiment can be a TN (Twisted Nematic) display panel, an IPS (In-Plane Switching) display panel, a VA (Vertical Alignment) display panel, or an MVA (Multi-Domain Vertical Alignment) display panel. Of course, it can also be other types of display panels, such as an OLED (Organic Light-Emitting Diode) display panel.

[0054] As an example, the display panel can be applied to display devices, such as mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, and any other products or components with display functions.

[0055] The specific structure of the array substrate in this embodiment refers to the above embodiments. Since the display panel proposed in this embodiment adopts all the technical solutions of all the above embodiments and belongs to the same technical concept, this embodiment has at least all the beneficial effects brought by the technical solutions of the above embodiments, and will not be described in detail here.

[0056] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0057] Furthermore, in the embodiments of this application, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B.

[0058] In the embodiments of this application, unless otherwise expressly specified and limited, the terms "connection" and "fixed" should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0059] It should also be understood that references to "one embodiment" or "some embodiments" in the specification of embodiments of this application mean that one or more embodiments of this application include the specific features, structures, or characteristics described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0060] It should be noted that the technical solutions of the various embodiments of this application can be combined with each other, but only if they are implemented by those skilled in the art. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the embodiments of this application.

[0061] The above are merely optional embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A GOA repair circuit, characterized in that, The method is applied to an array substrate, which includes a display area and a non-display area. The non-display area surrounds the periphery of the display area. The GOA repair circuit is disposed in the non-display area and is electrically connected to an input repair line, an output repair line, a power line, and a clock line. The GOA repair circuit is configured to: when a designated scan line electrically connected to an abnormal GOA unit needs to be driven, a drive signal output by a normal GOA unit is received through the input repair line; the drive signal is adjusted based on signals from the power line and the clock line to obtain a repair signal; and the repair signal is output to the designated scan line through the output repair line; wherein, the abnormal GOA unit is electrically connected to the nth scan line on the first side of the display area, and the normal GOA unit is electrically connected to the nth scan line on the second side of the display area.

2. The GOA repair circuit as described in claim 1, characterized in that, The GOA repair circuit includes: The first thin-film transistor has a common gate and drain, and its source serves as a first signal node. The second thin-film transistor has a gate for accessing the drive signal through the input repair line, a drain for being electrically connected to the first signal node, and a source for being connected to a source reference voltage. The third thin-film transistor has its gate and drain connected together and is electrically connected to the gate and drain of the first thin-film transistor. The source of the third thin-film transistor serves as the second signal node. A fourth thin-film transistor, wherein the gate of the fourth thin-film transistor is electrically connected to the first signal node, the drain of the fourth thin-film transistor is electrically connected to the second signal node, and the source of the fourth thin-film transistor is connected to the source reference voltage; The fifth thin-film transistor has its gate electrically connected to the second signal node, its drain used to receive a first clock signal from the input side of the abnormal GOA unit via the clock line, and its source used as the third signal node. A sixth thin-film transistor, the drain of which is electrically connected to the third signal node, and the source of which is used to output the repair signal to the output repair line.

3. The GOA repair circuit as described in claim 2, characterized in that, When a scan line electrically connected to an abnormal GOA cell needs to be driven, the gate and drain of the first thin-film transistor, the gate and drain of the third thin-film transistor are connected to a first driving voltage from the power supply line, the gate of the second thin-film transistor is connected to the driving signal, the drain of the fifth thin-film transistor is connected to the first clock signal, and the gate of the sixth thin-film transistor is connected to a second driving voltage from the power supply line, so that the first and third thin-film transistors are turned on, the second thin-film transistor is turned on, the fourth thin-film transistor is turned off, the fifth thin-film transistor is turned on, and the sixth thin-film transistor is turned on; wherein, the first driving voltage is greater than the source reference voltage and the peak voltage of the first clock signal, and the second driving voltage is greater than the source reference voltage.

4. The GOA repair circuit as described in claim 2, characterized in that, The first ratio obtained by dividing the channel width-to-length ratio of the first thin-film transistor by the channel width-to-length ratio of the second thin-film transistor is less than the second ratio obtained by dividing the channel width-to-length ratio of the third thin-film transistor by the channel width-to-length ratio of the fourth thin-film transistor. The channel width-to-length ratio of the fifth thin-film transistor and the channel width-to-length ratio of the sixth thin-film transistor are greater than the channel width-to-length ratio of the driving thin-film transistor in the normal GOA unit.

5. The GOA repair circuit as described in claim 2, characterized in that, The GOA repair circuit also includes: A seventh thin-film transistor, wherein the gate and drain of the seventh thin-film transistor are connected together and are used to access the driving signal through the input repair line; the source of the seventh thin-film transistor is electrically connected to the gate of the second thin-film transistor, serving as the fourth signal node. The eighth thin-film transistor has its drain electrically connected to the fourth signal node, its gate used to receive a second clock signal, and its source connected to the source reference voltage; wherein the waveform of the second clock signal does not overlap with the waveform of the first clock signal at all.

6. The GOA repair circuit as described in claim 5, characterized in that, The starting time of the rising edge of the second clock signal is later than the ending time of the falling edge of the first clock signal, which causes the falling edge of the fourth signal node, the rising edge of the first signal node, and the falling edge of the second signal node to be delayed.

7. The GOA repair circuit as described in claim 5, characterized in that, The GOA repair circuit also includes: A ninth thin-film transistor, wherein the gate of the ninth thin-film transistor is electrically connected to the first signal node, the drain of the ninth thin-film transistor is electrically connected to the third signal node, and the source of the ninth thin-film transistor is connected to the source reference voltage.

8. The GOA repair circuit as described in claim 7, characterized in that, When the gate and drain of the first thin-film transistor and the gate and drain of the third thin-film transistor are connected to the first driving voltage from the power line, and the gate of the seventh thin-film transistor is not connected to the driving signal, the ninth thin-film transistor is turned on to suppress the noise of the third signal node.

9. An array substrate, the array substrate comprising a display area and a non-display area, the non-display area surrounding the periphery of the display area, characterized in that, The non-display area is provided with a GOA repair circuit as described in any one of claims 1 to 8.

10. A display panel, characterized in that, The display panel includes the array substrate as described in claim 9.

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