Display control method and display device

Abstract

This invention provides a display control method and a display device. The display control method includes: generating a pseudo-random number sequence and generating a triangular wave signal based on the pseudo-random number sequence; wherein the pseudo-random number sequence includes multiple pseudo-random numbers, and the triangular wave signal includes multiple signal segments, the slope of each signal segment being determined by a pseudo-random number; generating a spread spectrum control signal based on the triangular wave signal to frequency modulate a reference clock signal, thereby obtaining a clock signal; determining the offset of the current frequency of the clock signal relative to the reference frequency; and charging the pixels corresponding to each row based on the current frequency and offset of the clock signal. The display control method provided by this invention, where the current frequency and offset of the clock signal are used to charge the pixels corresponding to each row, helps improve pixel brightness uniformity and effectively suppresses the water ripple phenomenon.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display control method and a display device. Background Technology

[0002] With the increasing data transmission rates of display devices, EMI (Electromagnetic Interference) problems are becoming increasingly prominent. SSCG (Spread Spectrum Clock Generator) technology, by periodically modulating the frequency of the clock signal CLK, disperses narrowband EMI energy to a wider bandwidth, making it an effective means of suppressing EMI. Traditional SSCG uses a fixed modulation function (usually a triangular wave) to globally synchronize CLK. Since the timing of the data signal DATA remains unchanged, while the pixel charging time is determined by the time from the rising edge of the data signal DATA to the falling edge of the clock signal CLK, the periodic frequency offset of CLK causes the charging time to exhibit regular, frame-synchronized periodic changes. The difference in charging time directly maps to the difference in pixel brightness, forming visible alternating bright and dark stripes in the vertical scanning direction, i.e., the "water ripple" phenomenon. Summary of the Invention

[0003] This invention mainly provides a display control method and a display device that can effectively suppress water ripple phenomenon.

[0004] To solve the above-mentioned technical problems, the first technical solution adopted by the present invention is: to provide a display control method for a display device, the display device including a timing control circuit, a gate driving circuit, a source driving circuit, and a pixel array composed of multiple pixels; the gate driving circuit and the source driving circuit are electrically connected to the pixel array respectively; and the gate driving circuit and the source driving circuit are respectively used to connect to the timing control circuit, the timing control circuit is used to generate a clock signal, and control the gate driving circuit and the source driving circuit to charge the pixels corresponding to each row according to the clock signal; the display control method includes: A pseudo-random number sequence is generated, and a triangular wave signal is generated based on the pseudo-random number sequence; wherein, the pseudo-random number sequence includes multiple pseudo-random numbers, the triangular wave signal includes multiple signal segments, and the slope of each signal segment is determined by one of the pseudo-random numbers; A spread spectrum control signal is generated based on the triangular wave signal to modulate the frequency of the reference clock signal, thereby obtaining the clock signal; Determine the offset of the current frequency of the clock signal relative to the reference frequency; The corresponding pixels in each row are charged based on the current frequency and offset of the clock signal.

[0005] In one embodiment, charging the pixels corresponding to each row based on the current frequency and offset of the clock signal includes: The charging time of pixels is adjusted based on the current frequency and offset of the clock signal, thereby charging the pixels corresponding to each row; and / or The slew rate of the data signal is adjusted based on the current frequency and offset of the clock signal, thereby charging the corresponding pixel in each row.

[0006] In one embodiment, adjusting the charging time of a pixel based on the current frequency and offset of the clock signal includes: In response to an offset greater than a preset value and a current frequency greater than a reference frequency, the charging time is extended; the extended charging time includes: advancing the rising edge of the data signal; and / or delaying the falling edge of the clock signal; In response to an offset less than a preset value and a current frequency less than a reference frequency, the charging time is shortened; shortening the charging time includes: delaying the rising edge of the data signal; and / or, advancing the falling edge of the clock signal.

[0007] In one embodiment, adjusting the slew rate of the data signal based on the current frequency and offset of the clock signal includes: In response to an offset greater than a preset value and a current frequency greater than a reference frequency, the slew rate of the rising edge of the data signal is increased. In response to an offset less than a preset value and a current frequency less than a reference frequency, the slew rate of the rising edge of the data signal is reduced.

[0008] In one embodiment, adjusting the charging time of a pixel includes: The current time compensation parameters are determined based on the offset and the nominal charging time; the nominal charging time is determined based on the reference frequency and the number of clock cycles per row of pixels. The charging time can be extended or shortened based on the current time compensation parameters.

[0009] In one embodiment, adjusting the charging time of a pixel includes: The first time compensation parameter is determined based on the offset and the nominal charging time, and the second time compensation parameter is determined based on the parasitic capacitance and parasitic resistance of the data line. The current time compensation parameter is determined based on the first time compensation parameter and the second time compensation parameter. The charging time can be extended or shortened based on the current time compensation parameters.

[0010] In one embodiment, in response to the row synchronization signal of each row of pixels, the current phase of the triangular wave signal is adjusted to the initial phase.

[0011] In one embodiment, in response to the field synchronization signal of each frame, the current phase of the triangular wave signal is adjusted to the target phase; wherein the phase difference between the target phase and the current phase is 0~180°.

[0012] To solve the above-mentioned technical problems, the second technical solution adopted by the present invention is: to provide a display device, including: a timing control circuit, a gate driving circuit, a source driving circuit, and a pixel array composed of multiple pixels; The timing control circuit is used to generate a clock signal and determine the offset of the current frequency of the clock signal relative to the reference frequency; a charging control signal is generated based on the current frequency and offset of the clock signal. The gate driving circuit and the source driving circuit are electrically connected to the pixel array and the timing control circuit, respectively. The gate driving circuit and the source driving circuit are used to receive the clock signal and the charging control signal, respectively, and charge the corresponding pixel of each row according to the clock signal and the charging control signal.

[0013] The beneficial effects of this invention are as follows: Unlike existing technologies, the display control method provided by this invention includes: generating a pseudo-random number sequence and generating a triangular wave signal based on the pseudo-random number sequence; wherein the pseudo-random number sequence includes multiple pseudo-random numbers, and the triangular wave signal includes multiple signal segments, the slope of each signal segment being determined by a pseudo-random number; generating a spread spectrum control signal based on the triangular wave signal to frequency modulate a reference clock signal, thereby obtaining a clock signal; determining the offset of the current frequency of the clock signal relative to the reference frequency; and charging the corresponding pixels for each row based on the current frequency and offset of the clock signal. The display control method provided by this invention utilizes a pseudo-random number sequence to generate a triangular wave, thereby hiding water ripples, and further charges the corresponding pixels for each row based on the current frequency and offset of the clock signal, which helps improve pixel brightness uniformity and effectively suppresses the water ripple phenomenon. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 A flowchart illustrating the first embodiment of the display control method provided in this application; Figure 2 This is a timing diagram of the clock signal and data signal; Figure 3 A timing diagram of an embodiment of the clock signal and data signal in the display control method provided in this application; Figure 4 A timing diagram of another embodiment of the clock signal and data signal in the display control method provided in this application; Figure 5 A timing diagram of another embodiment of the clock signal and data signal in the display control method provided in this application; Figure 6 for Figure 1 A flowchart illustrating an embodiment of step S12; Figure 7 for Figure 1 A flowchart illustrating another embodiment of step S12; Figure 8 A flowchart illustrating a second embodiment of the display control method provided in this application; Figure 9 This is a schematic diagram of the frequency distribution of the clock signal; Figure 10 This is a schematic diagram of an embodiment of the display device provided in this application.

[0016] Explanation of reference numerals in the attached drawings: display device 90, timing control circuit 91, gate drive circuit 92, source drive circuit 93, pixel 940, pixel array 94. Detailed Implementation

[0017] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0018] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0019] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0021] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0022] To enable those skilled in the art to better understand the technical solution of the present invention, the display device provided by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] See Figure 1 , Figure 1 This is a flowchart illustrating a first embodiment of the display control method provided in this application. The display control method is used in a display device, which includes a timing control circuit, a gate driving circuit, a source driving circuit, and a pixel array composed of multiple pixels. The gate driving circuit and the source driving circuit are electrically connected to the pixel array. The gate driving circuit and the source driving circuit are respectively connected to the timing control circuit, which generates a clock signal and controls the gate driving circuit and the source driving circuit to charge the pixels corresponding to each row according to the clock signal. The display control method specifically includes: Step S11: Determine the offset of the current frequency of the clock signal relative to the reference frequency.

[0024] In one embodiment, the offset is calculated using the following formula: Formula (1); in, This represents the offset at time t. This represents the current frequency at time t. Indicates the reference frequency. This represents the frequency offset at time t.

[0025] Step S12: Charge the corresponding pixels for each row based on the current frequency and offset of the clock signal.

[0026] In one embodiment, the charging time of the pixels is adjusted based on the current frequency and offset of the clock signal, thereby charging the pixels corresponding to each row.

[0027] Specifically, the pixel charging time is determined based on the rising edge of the data signal and the falling edge of the clock signal. See details. Figure 2 Let t be the charging time, which begins at the rising edge of the data signal DATA and ends at the falling edge of the clock signal CLK. It's important to note that the rising edge of the data signal transitioning from low to high marks the beginning of the target grayscale voltage establishment for the current pixel, and the pixel capacitor officially enters the charging preparation stage. After the data signal voltage gradually stabilizes, the falling edge of the clock signal triggers the source drive circuit to latch the currently stable grayscale data and officially initiates the charging process for the corresponding pixel capacitor. Therefore, the time interval from the rising edge of the data signal to the falling edge of the clock signal determines the grayscale voltage establishment time, and the complete duration defined by these two timing nodes is the effective charging time of the pixel capacitor.

[0028] In one specific embodiment, in response to the offset being greater than a preset value and the current frequency being greater than the reference frequency, the charging time t is extended. Specifically, the preset value is denoted as A. In one specific embodiment, A is 0. In other embodiments, A can also be other values, such as positive numbers like 0.5, 1, 2, etc., or negative numbers like -0.5, 1, 2, etc. This application uses A being 0 as an example for explanation.

[0029] Specifically, if the offset ,and This indicates that the clock speed has increased, the clock cycle has shortened, and the charging time is insufficient, which may lead to lower pixel brightness. To maintain pixel brightness, the charging time t of the pixel needs to be extended.

[0030] In one specific embodiment, extending the charging time t includes: advancing the rising edge of the data signal; and / or delaying the falling edge of the clock signal. Combined with Figure 3 In one embodiment, the rising edge of the data signal DATA can be advanced from position 0 to position 'a'. In this case, the charging time t becomes t1, and t1... t. Combination Figure 4 In another embodiment, the falling edge of the clock signal CLK can be delayed from position m to position y. In this case, the charging time t becomes t1, and t1 It is understood that in other embodiments, the rising edge of the data signal DATA can be brought forward while the falling edge of the clock signal CLK is delayed, thereby extending the charging time.

[0031] In response to an offset less than a preset value and a current frequency less than a reference frequency, the charging time is shortened. Specifically, if the offset... ,and This indicates that the clock has slowed down, the clock cycle has lengthened, and the charging time is excessive, which may lead to excessively high pixel brightness. To ensure pixel brightness, the charging time t of the pixel needs to be shortened.

[0032] In one specific embodiment, shortening the charging time t includes: delaying the rising edge of the data signal DATA; and / or, advancing the falling edge of the clock signal CLK. Combined with Figure 3 In one embodiment, the rising edge of the data signal DATA can be delayed from position 0 to position b. In this case, the charging time t becomes t2, and t2... t. Combination Figure 4 In another embodiment, the falling edge of the clock signal CLK can be advanced from position m to position x. In this case, the charging time t becomes t2, and t2 It is understood that in other embodiments, the rising edge of the data signal DATA can be delayed while the falling edge of the clock signal can be advanced, thereby shortening the charging time.

[0033] In another embodiment, the slew rate of the data signal is adjusted based on the current frequency and offset of the clock signal, thereby charging the corresponding pixel for each row.

[0034] Furthermore, for some large-size display panels, the data lines have long extension distances and limited trace widths. The data lines themselves have distributed resistance, and parasitic capacitances exist between the data lines and surrounding gate lines, substrates, etc., forming an overall RC distributed load. Ideally, the data signal would be a step square wave. However, due to the influence of the RC distributed load, the voltage cannot change instantaneously, and the actual waveform is no longer a square wave, but rather a curve with a gradual rise and fall edge, specifically as shown below. Figure 5 As shown. In this embodiment, the slew rate of the data signal can be adjusted based on the current frequency and offset of the clock signal, thereby charging the corresponding pixel of each row.

[0035] In response to an offset greater than a preset value and a current frequency greater than a reference frequency, the slew rate of the rising edge of the data signal is increased. This is understandable; if the offset... ,and This indicates that the clock speed has increased, the clock cycle has shortened, and the charging time is insufficient, which may lead to lower pixel brightness. To ensure pixel brightness, the slew rate of the data signal DATA can be increased, for example, by increasing the slew rate of the rising edge of the data signal DATA from P to P1. It should be noted that the slew rate of the data signal DATA represents the maximum rate of change of the level of the data signal DATA output by the source drive circuit, corresponding to the steepness of the rising and falling edges of the data signal DATA. When the charging time is insufficient, increasing the slew rate of the rising edge of the data signal DATA can make the rising edge of the DATA signal steeper, thus shortening the grayscale voltage settling time. This ensures that the grayscale voltage has stabilized to the target value when the falling edge of the clock signal CLK triggers charging, preventing insufficient charging of the pixel capacitor.

[0036] In response to an offset less than a preset value and a current frequency less than a reference frequency, the slew rate of the data signal rising edge is reduced. Understandably, if the offset... This indicates that the clock has slowed down, the clock cycle has lengthened, and the charging time is excessive, which may lead to excessively high pixel brightness. To ensure pixel brightness, the slew rate of the data signal DATA can be reduced, for example, by reducing the slew rate of the rising edge of the data signal DATA from P to P2. It should be noted that when the charging time is long, reducing the slew rate of the rising edge of the data signal DATA can make the rising edge of the DATA signal slower, thus extending the grayscale voltage settling time.

[0037] It should be noted that when reducing the slew rate of the rising edge of the data signal, it is necessary to ensure that the grayscale voltage has stabilized to the target value when the falling edge of the clock signal CLK triggers charging. For example, the high-level stabilization point of the data signal DATA, such as P3, is earlier than the falling edge of the clock signal CLK, so as to ensure that the pixel capacitor is fully charged.

[0038] Combination Figure 6 In one embodiment of this application, step S12 further includes: Step S21: Determine the current time compensation parameters based on the offset and nominal charging time; the nominal charging time is determined based on the reference frequency and the number of clock cycles per row of pixels.

[0039] It should be noted that for TFT-LCD (Thin Film Transistor Liquid Crystal Display), the charging time is related to the clock cycle of the clock signal. They are directly proportional. The specific calculation formula is: Formula (2); in, This represents the charging time corresponding to row t. This represents the clock cycle corresponding to the t-th row, and N represents the number of clock cycles corresponding to a single row, which is determined by the timing controller.

[0040] because Therefore, we can obtain: Formula (3); in, This represents the frequency corresponding to the t-th row.

[0041] Based on the above formula (3), without performing spread spectrum technology, i.e. When =fcenter, the nominal charging time is: ; Specifically, the nominal midpoint time is the charging time corresponding to the reference frequency.

[0042] When performing spread spectrum technology, i.e. =fcenter+ At that time, the instantaneous charging time is: .

[0043] Simplify formula (5): Formula (6); Substituting formulas (1) and (4) into formula (6), we get: Formula (7).

[0044] Because the modulation depth (i.e., maximum frequency offset, representing the maximum deviation of the instantaneous frequency relative to the reference frequency) of SSCG technology is relatively small, it is generally... This can be understood as Using a first-order Taylor expansion, we can approximate the result as: 1 / (1+P(t))≈1 Substituting P(t) into the above formula (7), we can obtain: Formula (8).

[0045] Theoretically, charging time deviation The calculation formula is: Formula (9).

[0046] Substituting formula (8) into formula (9), we get: Formula (10).

[0047] It should be noted that, in order to ensure the actual effective charging time Able to achieve the nominal charging time Therefore, it is necessary to use the current time compensation parameter to compensate for the rising edge timing of the data signal, so that: Formula (11).

[0048] Simplifying formula (11), we get: Formula (12).

[0049] Combining formulas (9) and (10) above, we can obtain: Formula (13); in, This represents the current time compensation parameter. Based on formula (13), the current time compensation parameter... Based on offset and nominal charging time The calculation is as follows. Furthermore, combining this with formula (4), it can be seen that the nominal charging time is based on the reference frequency. It is determined by the number of clock cycles N for a row of pixels.

[0050] Step S22: Extend or shorten the charging time based on the current time compensation parameters.

[0051] Specifically, if the offset Then, the result calculated using the above formula (13) is... And in To ensure pixel brightness, the rising edge of the data signal DATA is advanced or the falling edge of the clock signal CLK is delayed based on the current time compensation parameter. For example, the current time compensation parameter is subtracted from the current rising edge of the data signal DATA, thus advancing the rising edge of the data signal DATA; or the current time compensation parameter is added to the current falling edge of the clock signal CLK, thus delaying the falling edge of the clock signal CLK, thereby extending the pixel charging time.

[0052] If offset Then, the result calculated using the above formula (13) is... And in To ensure pixel brightness, the rising edge of the data signal DATA is delayed based on the current time compensation parameter; or the falling edge of the clock signal CLK is advanced. For example, the absolute value of the current time compensation parameter is added to the time of the current rising edge of the data signal DATA, thus delaying the rising edge of the data signal DATA. Alternatively, the absolute value of the current time compensation parameter is subtracted from the time of the current falling edge of the clock signal CLK, thus advancing the falling edge of the clock signal CLK, thereby shortening the pixel charging time.

[0053] In one embodiment, the relationship between the time interval t (i.e., the charging time t) and the current time compensation parameter can be determined. If the charging time t... In this case, only the rising edge of the data signal DATA needs to be delayed, thereby shortening the charging time. If the charging time t If it is necessary to shorten the charging time, the rising edge ta of the data signal DATA can be delayed (ta... t) time, and simultaneously advance the falling edge of the clock signal CLK by tb (tb t) time, and ta + tb = This ensures that the rising edge of the data signal DATA always precedes the falling edge of the clock signal CLK, and that the pixels in that row have a corresponding charging time.

[0054] Furthermore, the time interval between the rising edge of the data signal DATA and the falling edge of the previous cycle's DATA signal can also be determined. Figure 4 The given tx. If tx If it is necessary to extend the charging time, the rising edge tc of the data signal DATA can be brought forward. tx), and simultaneously delay the falling edge td of the clock signal CLK by time td, and tc + td = .

[0055] The control method described in this application can effectively improve pixel brightness differences, enhance brightness uniformity, and reduce water ripple effects.

[0056] Combination Figure 7 In one embodiment of this application, step S12 further includes: Step S31: Determine the first time compensation parameter based on the offset and nominal charging time, and determine the second time compensation parameter based on the parasitic capacitance and parasitic resistance of the data line.

[0057] Specifically, in this embodiment, the first-time compensation parameter is equivalent to the above. Figure 6 The current time compensation parameter in the illustrated embodiment is used as an example. Therefore, the calculation method of the first time compensation parameter in this embodiment is described above. Figure 6 The embodiments shown will not be described in detail here.

[0058] Furthermore, due to the presence of RC loading (parasitic load) on the panel, the actual charging rate is usually lower than the theoretical charging rate. The larger the RC loading, the lower the charging rate. Different panels have different RC values. The larger the RC loading, the worse the charging rate, the greater the difference in brightness during jitter, and the more severe the water ripple phenomenon. Based on this, this embodiment determines the second time compensation parameter based on the parasitic capacitance and resistance of the data line. Specifically, an RC model is constructed for the parasitic capacitance C and parasitic resistance R. This RC model can be equivalent to a first-order RC low-pass filter, expressed as: Where 's' represents a coefficient, and the RC models of parasitic capacitance C and parasitic resistance R are determined during panel design. The actual voltage at the pixel end is... Under the influence of the RC model, the time to reach the TFT (TFT connected to the data line) threshold voltage Vth is: )= ,Right now = ), where v represents the voltage difference between the target pixel voltage and the actual pixel voltage.

[0059] Step S32: Determine the current time compensation parameter based on the first time compensation parameter and the second time compensation parameter.

[0060] Specifically, the current time compensation parameter is the sum of the first time compensation parameter and the second time compensation parameter.

[0061] Step S33: Extend or shorten the charging time based on the current time compensation parameters.

[0062] In this embodiment, the influence of parasitic resistance and parasitic capacitance of the data line on charging time is taken into account. Using the method of this embodiment, pixel brightness difference can be further improved, brightness uniformity can be enhanced, and water ripple phenomenon can be reduced.

[0063] In one embodiment, see Figure 8 , Figure 8 This is a flowchart illustrating a second embodiment of the display control method provided in this application. This embodiment is similar to the one described above. Figure 1 Compared to the first embodiment shown, the difference in this embodiment is that, before step S11, it further includes: Step S13: Generate a pseudo-random number sequence and generate a triangular wave signal based on the pseudo-random number sequence; wherein, the pseudo-random number sequence includes multiple pseudo-random numbers, the triangular wave signal includes multiple signal segments, and the slope of each signal segment is determined by a pseudo-random number.

[0064] Step S14: Generate a spread spectrum control signal based on the triangular wave signal to frequency modulate the reference clock signal, thereby obtaining the clock signal.

[0065] It should be noted that traditional triangular waves are linear, which can cause a ripple effect. In the method of this application, a pseudo-random number sequence is generated, and a triangular wave signal is generated based on this sequence. The pseudo-random number sequence includes multiple pseudo-random numbers. Understandably, the clock signal obtained by generating a triangular wave signal based on the pseudo-random number sequence will have a charging time offset. Figure 1 The method shown can compensate for the offset in charging time.

[0066] Specifically, the triangular wave signal comprises multiple signal segments, and the slope of each segment is no longer a constant but a variable determined by pseudo-random numbers. For example, the slope KM of the Mth signal segment is: KM = K + ΔK, where K represents the original slope and ΔK represents the pseudo-random number. After pseudo-random number processing, although the triangular wave signal still appears as a triangular wave overall, ensuring EMI spectrum broadening, the frequency variation becomes "jittery" at the microscopic level. This causes the charging time variation to no longer follow a smooth sine / triangular pattern but rather a fluctuation with random noise. The human eye is not sensitive to high-frequency random noise, thus concealing the ripples.

[0067] It should be noted that when introducing pseudo-random numbers to cause frequency jitter, the jitter range must be kept within a preset range to avoid excessive offset and timing errors. Therefore, a frequency modulation range needs to be defined. For example, if the reference frequency is 110MHz and the spread spectrum amplitude is ±2%, the frequency will randomly vary between 100MHz and 120MHz. Figure 9 The horizontal axis represents the number of rows, and the vertical axis represents the frequency. Each row corresponds to a frequency, which randomly falls between 100MHz and 120MHz.

[0068] Specifically, after a long period of random number processing, phase shift may occur. Therefore, in one embodiment, the spread spectrum modulation period is reset at the beginning of each frame to avoid the cumulative phase error affecting the display timing.

[0069] In one embodiment, the frequency of the clock signal required for each row can be generated according to the frequency modulation range limitation, and then the clock signals are passed through a phase-locked loop in sequence to filter out high-frequency jitter.

[0070] In one embodiment, in response to the line synchronization signal of each row of pixels, the current phase of the triangular wave signal is adjusted to the initial phase. Specifically, when the line synchronization signal HSYNC is detected, the current phase of the triangular wave signal is adjusted to the initial phase. This ensures that the phase of the triangular wave signal corresponding to each row of pixels starts from the initial phase. Although there may still be changes within each row, there is no continuous phase accumulation between rows, and the water ripples no longer roll, thus suppressing the water ripple rolling problem.

[0071] In another embodiment, in response to the field synchronization signal of each frame, the current phase of the triangular wave signal is adjusted to the target phase; wherein the phase difference between the target phase and the current phase is 0~180°. Specifically, when the field synchronization signal VSYNC is detected, the current phase of the triangular wave signal is adjusted to the target phase. This creates a phase difference between the target phase and the current phase, which can break the continuity between frames and prevent the water ripples from forming fixed interference fringes in the vertical direction. Specifically, the phase difference is 0~180°, for example, 0, 45, 90, 180, etc. In a specific embodiment, the phase difference between the target phase and the current phase is 180°.

[0072] It should be noted that for images with a large grayscale, such as a white image, the water ripple effect is not obvious when displayed. Therefore, in one embodiment of this application, it is further determined whether the current display image is a white image, such as a document display. If it is a white image, the display control method of this application is not enabled. If it is not a white image, the display control method of this application is enabled for display, thereby suppressing the water ripple problem.

[0073] See Figure 10 , Figure 10 This is a schematic diagram of the structure of an embodiment of the display device provided in this application. The display device 90 provided in this application includes: a timing control circuit 91, a gate driving circuit 92, a source driving circuit 93, and a pixel array 94 composed of a plurality of pixel points 940.

[0074] The timing control circuit 91 is used to generate a clock signal CLK and determine the offset of the current frequency of the clock signal CLK relative to the reference frequency; and to generate a charging control signal based on the current frequency and offset of the clock signal CLK.

[0075] The gate driving circuit 92 and the source driving circuit 93 are electrically connected to the pixel array 94 and the timing control circuit 91, respectively. The gate driving circuit 92 and the source driving circuit 93 are used to receive the clock signal CLK and the charging control signal, respectively, and charge the corresponding pixel of each row according to the clock signal and the charging control signal.

[0076] In one embodiment, the timing control circuit 91 adjusts the charging time of the pixel based on the current frequency and offset of the clock signal. Specifically, in response to the offset being greater than a preset value and the current frequency being greater than a reference frequency, the charging time is extended; extending the charging time includes: the timing control circuit 91 outputting a charging control signal to the source drive circuit 93 to advance the rising edge of the data signal DATA; and / or, the timing control circuit 91 delaying the falling edge of the clock signal based on the charging control signal. In response to the offset being less than a preset value and the current frequency being less than a reference frequency, the charging time is shortened; shortening the charging time includes: the timing control circuit 91 outputting a charging control signal to the source drive circuit 93 to delay the falling edge of the data signal DATA; and / or, the timing control circuit 91 advancing the falling edge of the clock signal based on the charging control signal.

[0077] In response to the offset being greater than a preset value and the current frequency being greater than the reference frequency, the timing control circuit 91 outputs a charging control signal to the source drive circuit 93 to increase the slew rate of the rising edge of the data signal. In response to the offset being less than a preset value and the current frequency being less than the reference frequency, the timing control circuit 91 outputs a charging control signal to the source drive circuit 93 to reduce the slew rate of the rising edge of the data signal.

[0078] In one embodiment, the timing control circuit 91 is further configured to determine the current time compensation parameter based on the offset and the nominal charging time; the nominal charging time is determined based on the reference frequency and the number of clock cycles per row of pixels; and the charging time is extended or shortened based on the current time compensation parameter.

[0079] In one embodiment, the timing control circuit 91 is further configured to generate a pseudo-random number sequence and generate a triangular wave signal based on the pseudo-random number sequence; wherein the pseudo-random number sequence includes multiple pseudo-random numbers, the triangular wave signal includes multiple signal segments, and the slope of each signal segment is determined by a pseudo-random number; a spread spectrum control signal is generated based on the triangular wave signal to frequency modulate the reference clock signal, thereby obtaining a clock signal.

[0080] In one embodiment, the timing control circuit 91 is further configured to adjust the current phase of the triangular wave signal to the initial phase in response to the line synchronization signal of each row of pixels.

[0081] In one embodiment, the timing control circuit 91 is further configured to adjust the current phase of the triangular wave signal to a target phase in response to the field synchronization signal of each frame; wherein the phase difference between the target phase and the current phase is 0~180°.

[0082] In one embodiment, the phase difference between the target phase and the current phase is 180°.

[0083] The above are merely embodiments of the present invention and do not limit the scope of patent protection of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A display control method, characterized in that, For a display device, the display device includes a timing control circuit, a gate driving circuit, a source driving circuit, and a pixel array composed of multiple pixels; The gate driving circuit and the source driving circuit are respectively electrically connected to the pixel array; Furthermore, the gate driving circuit and the source driving circuit are respectively used to connect to the timing control circuit. The timing control circuit is used to generate a clock signal and control the gate driving circuit and the source driving circuit to charge the corresponding pixel of each row according to the clock signal. The display control method includes: A pseudo-random number sequence is generated, and a triangular wave signal is generated based on the pseudo-random number sequence; wherein, the pseudo-random number sequence includes multiple pseudo-random numbers, the triangular wave signal includes multiple signal segments, and the slope of each signal segment is determined by one of the pseudo-random numbers; A spread spectrum control signal is generated based on the triangular wave signal to modulate the frequency of the reference clock signal, thereby obtaining the clock signal; Determine the offset of the current frequency of the clock signal relative to the reference frequency; The pixels corresponding to each row are charged based on the current frequency of the clock signal and the offset.

2. The display control method according to claim 1, characterized in that, Based on the current frequency of the clock signal and the offset, the pixels corresponding to each row are charged, including: The charging time of the pixels is adjusted based on the current frequency of the clock signal and the offset, thereby charging the pixels corresponding to each row; and / or The slew rate of the data signal is adjusted based on the current frequency of the clock signal and the offset, thereby charging the corresponding pixel in each row.

3. The display control method according to claim 2, characterized in that, Adjusting the charging time of the pixel based on the current frequency of the clock signal and the offset includes: In response to the offset being greater than a preset value and the current frequency being greater than the reference frequency, the charging time is extended; extending the charging time includes: advancing the rising edge of the data signal; and / or delaying the falling edge of the clock signal; In response to the offset being less than the preset value and the current frequency being less than the reference frequency, the charging time is shortened; shortening the charging time includes: delaying the rising edge of the data signal; and / or, advancing the falling edge of the clock signal.

4. The display control method according to claim 2, characterized in that, Adjusting the slew rate of the data signal based on the current frequency of the clock signal and the offset includes: In response to the offset being greater than a preset value and the current frequency being greater than the reference frequency, the slew rate of the rising edge of the data signal is increased; In response to the offset being less than the preset value and the current frequency being less than the reference frequency, the slew rate of the rising edge of the data signal is reduced.

5. The display control method according to claim 3, characterized in that, Adjusting the charging time of the pixel includes: The current time compensation parameter is determined based on the offset and the nominal charging time; the nominal charging time is determined based on the reference frequency and the number of clock cycles per row of the pixels. The charging time can be extended or shortened based on the current time compensation parameter.

6. The display control method according to claim 3, characterized in that, Adjusting the charging time of the pixel includes: The first time compensation parameter is determined based on the offset and the nominal charging time, and the second time compensation parameter is determined based on the parasitic capacitance and parasitic resistance of the data line. The current time compensation parameter is determined based on the first time compensation parameter and the second time compensation parameter; The charging time can be extended or shortened based on the current time compensation parameter.

7. The display control method according to claim 1, characterized in that, In response to the line synchronization signal of each row of pixels, the current phase of the triangular wave signal is adjusted to the initial phase.

8. The display control method according to claim 1, characterized in that, In response to the field synchronization signal of each frame, the current phase of the triangular wave signal is adjusted to the target phase; wherein the phase difference between the target phase and the current phase is 0~180°.

9. A display device, characterized in that, include: Timing control circuit, gate drive circuit, source drive circuit, and pixel array composed of multiple pixels; The timing control circuit is used to generate a pseudo-random number sequence, generate a triangular wave signal based on the pseudo-random number sequence, generate a spread spectrum control signal based on the triangular wave signal to frequency modulate the reference clock signal, thereby generating a clock signal, and determining the offset of the current frequency of the clock signal relative to the reference frequency. A charging control signal is generated based on the current frequency of the clock signal and the offset. The gate driving circuit and the source driving circuit are electrically connected to the pixel array and the timing control circuit, respectively. The gate driving circuit and the source driving circuit are respectively used to receive the clock signal and the charging control signal, and charge the corresponding pixel of each row according to the clock signal and the charging control signal.

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