Refresh controller, memory controller, chip, device, and priority adjustment method

Abstract

This application discloses a refresh controller, a memory controller, a chip, a device, and a priority adjustment method, belonging to the field of chip technology. The refresh controller includes a priority control module; the priority control module is used to receive the number of pending arbitration instructions and the number of already arbitration instructions in the first block of memory; the priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration instructions and the number of already arbitration instructions in the first block satisfying a priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block. This application improves the flexibility of refreshing by determining whether to adjust the refresh command priority of the first block based on the numerical relationship between the number of pending arbitration instructions and the number of already arbitration instructions in the first block.

Description

Technical Field

[0001] This application relates to the field of chips, and in particular to a refresh controller, a memory controller, a chip, a device, and a priority adjustment method. Background Technology

[0002] Refreshing refers to recharging the capacitors in the memory to solve the problem of data loss in memory due to capacitor leakage.

[0003] The relevant technology refreshes memory periodically, but this method is not flexible enough and cannot differentiate memory blocks. Summary of the Invention

[0004] This application provides a refresh controller, a memory controller, a chip, a device, and a priority adjustment method. This application determines whether to adjust the refresh command priority of the first block by using the numerical relationship between the number of pending arbitration instructions and the number of arbitrated instructions in the first block, thereby improving the flexibility of refreshing.

[0005] According to one aspect of this application, a refresh controller is provided, the refresh controller including a priority control module; The priority control module is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0006] According to one aspect of this application, a memory controller is provided, the memory controller including a refresh controller, the refresh controller including a priority control module; The priority control module is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0007] According to one aspect of this application, a chip is provided, the chip including a refresh controller, the refresh controller including a priority control module; The priority control module is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0008] According to one aspect of this application, a computing device is provided, the computing device including a refresh controller, the refresh controller including a priority control module; The priority control module is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0009] According to one aspect of this application, a priority adjustment method is provided, the method being executed by a refresh controller, the refresh controller including a priority control module, the method comprising: The priority control module receives the number of pending arbitration instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module adjusts the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0010] The beneficial effects of the technical solutions provided in this application include at least the following:

[0011] In this embodiment, the priority of the refresh command of the first block is determined by the numerical relationship between the number of pending arbitration instructions and the number of arbitrated instructions in the first block, i.e. the change in the traffic of memory access instructions in the first block. This improves the flexibility of the refresh and avoids refreshing a large number of blocks at the same time.

[0012] Furthermore, by determining whether to adjust the refresh command priority based on traffic changes, it is possible to avoid refreshing the first block during periods of high traffic, and to fully utilize the idle or relatively idle bandwidth time of the first block to perform block refresh, thereby improving the performance of the first block. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of a refresh controller provided in one embodiment of this application.

[0015] Figure 2 This is a schematic diagram of a memory controller provided in one embodiment of this application.

[0016] Figure 3 This is a schematic diagram illustrating the adjustment of refresh command priority in the basic mode provided by one embodiment of this application.

[0017] Figure 4 This is a schematic diagram illustrating the adjustment of refresh command priority in enhanced mode according to an embodiment of this application.

[0018] Figure 5 This is a schematic diagram of a memory controller provided in another embodiment of this application.

[0019] Figure 6 This is a schematic diagram of a chip provided in one embodiment of this application.

[0020] Figure 7 This is a flowchart of a priority adjustment method provided in one embodiment of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0022] First, some terms used in the embodiments of this application will be introduced: Memory: The system's main memory, used to store the operating system, applications, and runtime data. Optionally, memory can be Double Data Rate Dynamic Random Access Memory (DDR). The memory organization includes bank groups, which consist of multiple banks. Banks are arrays of rows and columns. Memory access instructions can only access data after a row has been loaded into the bank's buffer.

[0023] The memory controller is a hardware module responsible for data transfer, scheduling, and management between the central processing unit (CPU) and memory. The CPU cannot directly access memory; its memory access instructions are first executed by the memory controller, which handles addressing, timing control, data transmission and reception, channel management, and error correction.

[0024] Refresh: This refers to the operation of charging the capacitors in memory. During a refresh, the system traverses line by line. When a line is refreshed, the data in that line cannot be accessed by the Central Processing Unit (CPU).

[0025] Figure 1 A structural block diagram of a refresh controller provided in an exemplary embodiment of this application is shown. The refresh controller 100 includes a priority control module 110.

[0026] The priority control module 110 is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block; If the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfies the priority adjustment condition, the priority of refresh commands for the first block is adjusted; the refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0027] For example, the refresh controller 100 is a hardware structure provided in this application, used to control the priority of refresh commands for each block in memory. Optionally, the refresh controller 100 is located in the memory controller.

[0028] For example, the priority control module 110 is a hardware module in the refresh controller 100 that specifically executes the refresh command priority of each block in the memory. Optionally, there may be other modules in the refresh controller 100 to assist the priority control module 110 in performing priority control.

[0029] The refresh command is used to refresh a block. Optionally, the refresh command is the RefSb refresh command, which refreshes only a few lines in a block, rather than the entire block.

[0030] Pending arbitration instructions refer to memory access instructions waiting to be arbitrated before being sent to memory, while arbitrated instructions are memory access instructions that have already been arbitrated and sent to memory. In other words, pending arbitration instructions are current memory access instructions, and arbitrated instructions are historical memory access instructions. The numerical relationship between the number of pending arbitration instructions and the number of arbitrated instructions represents the numerical relationship between current and historical memory access instructions, i.e., the change in the flow of memory access instructions.

[0031] When the numerical relationship between the number of pending arbitration instructions and the number of arbitrated instructions in the first block meets the priority adjustment condition, that is, when the change in the memory access instruction flow of the first block meets the priority adjustment condition, the priority of the refresh command of the first block will be adjusted.

[0032] Optionally, when the numerical relationship between the number of pending arbitration instructions and the number of arbitrated instructions in the first block meets the priority adjustment condition, and the number of pending arbitration instructions in the first block is less than the number of arbitrated instructions, the priority of the refresh command for the first block is increased. At this time, the memory access instruction traffic of the first block is reduced, and the refresh command can be issued during the low traffic bandwidth period of the first block to reduce the performance impact of the first block being inaccessible during refresh.

[0033] Optionally, when the numerical relationship between the number of pending arbitration instructions and the number of arbitrated instructions in the first block meets the priority adjustment condition, and the number of pending arbitration instructions in the first block is greater than the number of arbitrated instructions, the priority of the refresh command in the first block is reduced. At this time, the memory access instruction traffic of the first block increases, which can avoid issuing refresh commands during the high traffic bandwidth period of the first block.

[0034] Optionally, the priority control module 110 adjusts the priority of the refresh command for the first block by sending a request to the arbitrator to adjust the priority of the refresh command for the first block. The arbitrator is used to arbitrate instructions destined for memory from the instructions to be arbitrated, forming arbitrated instructions.

[0035] In this embodiment, the numerical relationship between the number of pending arbitration instructions and the number of arbitrated instructions in the first block is utilized, i.e., the traffic changes of memory access instructions in the first block are used to determine whether to adjust the refresh command priority of the first block. This application improves the flexibility of refreshing and avoids refreshing a large number of blocks simultaneously. Furthermore, determining whether to adjust the refresh command priority based on traffic changes can avoid refreshing the first block during periods of high traffic, making full use of the idle bandwidth time or relatively idle bandwidth time of the first block to perform block refresh, thereby improving the performance of the first block.

[0036] It should be noted that the priority control module receives the number of pending and arbitrated instructions for each block in memory. In response to the numerical relationship between the number of pending and arbitrated instructions for each block satisfying the priority adjustment condition, the priority of the refresh commands for each block is adjusted. In this application, the refresh command priority control mechanism for the first block is reused for all blocks in memory. For ease of explanation, this application will only discuss one block in memory, namely the first block.

[0037] In one possible implementation, the priority of refresh commands for the first block is adjusted in response to the difference between the number of pending arbitration commands and the number of arbitrated commands in the first block reaching a difference threshold.

[0038] Optionally, in response to the difference between the number of pending arbitration instructions and the number of arbitrated instructions in the first block reaching a difference threshold, if the number of pending arbitration instructions in the first block is less than the number of arbitrated instructions, the priority of the refresh command for the first block is increased; if the number of pending arbitration instructions in the first block is greater than the number of arbitrated instructions, the priority of the refresh command for the first block is decreased.

[0039] In another possible implementation, the instruction size change level of the first block is adjusted in response to the difference between the number of pending and arbitrated instructions in the first block reaching a difference threshold. When the instruction size change level of the first block reaches the pre-configured level, adjust the priority of the refresh command of the first block.

[0040] Optionally, in response to the difference between the number of pending arbitration instructions and the number of arbitrated instructions in the first block reaching a difference threshold, if the number of pending arbitration instructions in the first block is less than the number of arbitrated instructions, the instruction size change level of the first block is adjusted so that the size change level of the first block changes toward the instruction collapse level. When the instruction size change level of the first block reaches the instruction collapse level, the priority of the refresh command of the first block is increased.

[0041] Optionally, in response to the difference between the number of pending arbitration instructions and the number of arbitrated instructions in the first block reaching a difference threshold, if the number of pending arbitration instructions in the first block is greater than the number of arbitrated instructions, the instruction size change level of the first block is adjusted so that the size change level of the first block changes toward the instruction expansion level. When the instruction size change level of the first block reaches the instruction expansion level, the priority of the refresh command of the first block is reduced.

[0042] Figure 2 A structural block diagram of a memory controller provided in an exemplary embodiment of this application is shown.

[0043] Figure 2 In this configuration, the memory controller includes a refresh controller 100 and a command queue 200; the refresh controller 100 and the command queue 200 are electrically connected; the command queue 200 is used to store memory access instructions awaiting arbitration, and to send the number of instructions awaiting arbitration for the first block to the refresh controller 100. The command queue 200 stores memory access instructions sent by the central processing unit, waiting for arbitration by the arbitrator.

[0044] Optionally, the refresh controller 100 also includes a traffic monitoring module 120; the traffic monitoring module 120 is used to receive the number of pending arbitration instructions for the first block sent by the command queue 200, and transmit the number of pending arbitration instructions for the first block to the priority control module 110. The traffic monitoring module 120 is a hardware module that monitors the real-time traffic of the first block and provides adjustment strategy support for the priority control module 110.

[0045] Optionally, the traffic monitoring module 120 may also have an alarm function. For example, if the number of pending arbitration instructions in the first block is abnormally high or low, the traffic monitoring module 120 will trigger an interrupt, and the central processing unit will detect whether a fault has occurred and the cause of the fault.

[0046] Reference Figure 2 The memory controller includes a refresh controller 100 and an arbitrator 300; the refresh controller 100 and the arbitrator 300 are electrically connected; the arbitrator 300 is used to arbitrate memory access instructions sent to memory; Optionally, the refresh controller 100 also includes an instruction recording module 130; the instruction recording module 130 is used to receive memory access instructions arbitrated by the arbitrator 300, count the number of instructions arbitrated in the first block within a preset time window, and obtain the number of arbitrated instructions in the first block.

[0047] Within a preset time window, the number of memory access instructions arbitrated by the arbitrator 300 is approximately equal to the depth of the command queue 200. Optionally, the window length of the preset time window is configurable, such as 500 cycles. Optionally, the sending time of the command queue 200 (referring to the time from the number of pending arbitration instructions in the first block to the time of refresh controller 100) falls within the preset time window, such as the first frame, middle frame, or last frame of the preset time window; optional, the sending time of the command queue 200 is configurable.

[0048] In the memory controller, the pipeline position of the command queue 200 is naturally located before the pipeline position of the arbitrator 300. At this time, the number of instructions sent by the command queue 200 naturally represents the current number of instructions, and the number of instructions obtained by counting the instructions sent by the arbitrator 300 naturally represents the historical number of instructions. Therefore, this embodiment can make full use of the existing hardware structure of the memory controller (command queue 200 and arbitrator 300) to obtain the current number of instructions and the historical number of instructions of the first block, thereby measuring the traffic change of the first block and determining whether to adjust the refresh command priority of the first block.

[0049] It should be noted that the command queue 200 will send the number of pending arbitration instructions for each block in memory to the refresh controller 100, the instruction recording module 130 will count the number of instructions arbitrated for each block in memory within a preset time window, and the priority control module 110 will adjust the refresh command priority for each block in memory. For ease of explanation, this embodiment will only focus on the first block in memory.

[0050] based on Figure 1 In the optional embodiment shown, the priority control module 110 is used to calculate the difference between the number of pending arbitration instructions and the number of already arbitrated instructions in the first block; optionally, the difference is an absolute value. If the difference reaches a threshold, the instruction size change level corresponding to the first block is adjusted; the instruction size change level is used to indicate the stability of the memory access instruction size in the first block. Optionally, a larger or smaller instruction size change level indicates that the memory access instruction size in the first block is less stable, that is, it is easier to increase or decrease.

[0051] If the instruction size change level reaches the pre-configuration level and the number of pending arbitration instructions in the first block meets the instruction quantity condition, adjust the priority of the refresh command in the first block.

[0052] In this embodiment, relative information (instruction size change level) and absolute information (number of pending arbitration instructions in the first block) of the traffic will be used to comprehensively determine whether to adjust the refresh command priority. The refresh command priority will only be adjusted if both relative and absolute information are satisfied, which can improve the accuracy of the judgment result.

[0053] The following will introduce two possible methods for adjusting priorities.

[0054] (a) If the number of pending arbitration instructions in the first block is less than the number of already arbitrated instructions; The priority control module 110 is used to adjust the instruction size change level corresponding to the first block when the difference reaches the difference threshold, so that the instruction size change level corresponding to the first block changes towards the instruction collapse level. If the instruction size change level of the first block reaches the instruction collapse level, and the number of pending arbitration instructions in the first block is less than the first instruction number threshold, the priority of the refresh command of the first block is increased.

[0055] Optionally, the instruction collapse level is configurable.

[0056] Optionally, the first instruction quantity threshold is a configurable threshold.

[0057] At this time, if the number of pending arbitration instructions in the first block is less than the number of already arbitrated instructions and the difference reaches the difference threshold, it means that the current number of instructions in the first block is less than the number of historical instructions and the difference is large. That is, the traffic reduction of the first block is large. The priority control module 110 will change the instruction scale change level of the first block in the direction of instruction collapse level to increase the possibility of prioritizing the refresh of the first block.

[0058] (ii) If the number of pending arbitration instructions in the first block is greater than the number of already arbitrated instructions; The priority control module 110 is used to adjust the instruction size change level corresponding to the first block when the difference reaches the difference threshold, so that the instruction size change level corresponding to the first block changes towards the instruction inflation level. If the instruction size change level of the first block reaches the instruction inflation level, and the number of pending arbitration instructions in the first block is greater than the second instruction number threshold, the priority of the refresh command of the first block shall be reduced.

[0059] Optionally, the instruction inflation level is configurable.

[0060] Optionally, the second instruction quantity threshold is a configurable threshold.

[0061] At this time, if the number of pending arbitration instructions in the first block is greater than the number of already arbitrated instructions and the difference reaches the difference threshold, it means that the current number of instructions in the first block is greater than the number of historical instructions and the difference is large. That is, the traffic of the first block has increased significantly. The priority control module 110 will change the instruction scale change level of the first block in the direction of instruction expansion level to reduce the possibility of prioritizing the refresh of the first block.

[0062] For example, such as Figure 3 As shown, assuming the current instruction size change level of the first block is zero, if it is determined that the number of pending instructions in the first block is less than the number of already arbitrated instructions and the difference between the two is greater than the difference threshold, the instruction size change level will be adjusted to positive level one. Assuming the current instruction size change level of the first block is positive level 1, if it is determined that the number of pending instructions in the first block is less than the number of already arbitrated instructions and the difference between the two is greater than the difference threshold, the instruction size change level will be adjusted to positive level 2. Level 2 refers to the instruction collapse level. Therefore, if the number of pending arbitration instructions in the first block is less than the first instruction quantity threshold, the priority control module 110 will increase the priority of the refresh command for the first block. Optionally, the priority control module 110 can increase the priority of the refresh command for the first block by sending a request to the arbitrator 300 to increase the priority of the refresh command for the first block.

[0063] Assuming the current instruction size change level of the first block is zero, if it is determined that the number of pending instructions in the first block is greater than the number of already arbitrated instructions and the difference between the two is greater than the difference threshold, the instruction size change level will be adjusted to negative level one. Assuming the current instruction size change level of the first block is negative level one, if it is determined that the number of pending instructions in the first block is greater than the number of already arbitrated instructions and the difference between the two is greater than the difference threshold, the instruction size change level will be adjusted to negative level two. The negative level is the instruction inflation level. Therefore, if the number of pending arbitration instructions in the first block exceeds the second instruction quantity threshold, the priority control module 110 will reduce the priority of the refresh command for the first block. Optionally, the priority control module 110 can reduce the priority of the refresh command for the first block by sending a request to the arbitrator 300 to reduce the priority of the refresh command for the first block.

[0064] like Figure 2 As shown, the refresh controller 100 also includes a traffic monitoring module 120, which is used to record the instruction scale change level corresponding to the first block in real time.

[0065] In one embodiment, the value of the difference threshold is associated with the instruction size change level before the first block adjustment; for example, the instruction size change level before the first block adjustment is the first instruction size change level, the difference threshold is the first difference threshold, the instruction size change level before the first block adjustment is the second instruction size change level, and the difference threshold is the second difference threshold. Optionally, the mapping relationship between the instruction size change level and the difference threshold is configurable.

[0066] Optionally, the closer the instruction size change level before the first block adjustment is to the pre-configured level, the larger the difference threshold is, meaning that the closer the instruction size change level is to the pre-configured level, the more difficult it is to be adjusted.

[0067] And / or, The value of the difference threshold is related to the size relationship type, which includes either the number of pending instructions in the first block being less than the number of already arbitrated instructions, or the number of pending instructions in the first block being greater than the number of already arbitrated instructions.

[0068] For example, if the number of pending arbitration instructions in the first block is less than the number of already arbitrated instructions, the difference threshold is set to a first value; optionally, if the number of pending arbitration instructions in the first block is greater than the number of already arbitrated instructions, the difference threshold is set to a second value; the first value and the second value are different, and optionally, the first value and the second value are configurable values.

[0069] Understandably, the difference threshold can be related only to the instruction size change level before the first block adjustment, or only to the size relationship type. That is, the difference threshold used when instruction collapses is different from the difference threshold used when instruction expands. Optionally, the difference threshold can also be related to both. For example, if the instruction size change level before the first block adjustment is positive level 1, and the number of instructions to be arbitrated in the first block is greater than the number of instructions already arbitrated, the corresponding difference threshold is A; if the instruction size change level before the first block adjustment is positive level 1, and the number of instructions to be arbitrated in the first block is less than the number of instructions already arbitrated, the corresponding difference threshold is B.

[0070] In one embodiment, in the basic mode, the priority control module 110 is further configured to adjust the instruction size change level of the first block to the initial level after adjusting the refresh command priority of the first block; thereafter, the first block will enter the next polling window. (Refer to the reference...) Figure 3 The initial level is level zero.

[0071] And / or, The priority control module 110 is also used to adjust the instruction size change level of the first block to the target level after adjusting the refresh command priority of the first block; then, the first block will enter the next polling window. Compared to the initial level, the target level is closer to the pre-configured level.

[0072] For example, without distinguishing between modes, after adjusting the refresh command priority of the first block, the priority control module 110 can adjust the instruction size change level of the first block to the initial level or the instruction size change level of the first block to the target level. When distinguishing between basic mode and enhanced mode, in basic mode, after adjusting the refresh command priority of the first block, the priority control module 110 adjusts the instruction size change level of the first block to the initial level, and in enhanced mode, after adjusting the refresh command priority of the first block, the priority control module 110 adjusts the instruction size change level of the first block to the target level.

[0073] Optionally, in enhanced mode, the priority control module 110 is also used to adjust the instruction size change level of the first block to the first target level after increasing the priority of the refresh command of the first block; the first target level is closer to the instruction collapse level than the initial level. or, The priority control module 110 is also used to adjust the instruction size change level of the first block to the second target level after reducing the priority of the refresh command of the first block; the second target level is closer to the instruction expansion level than the initial level.

[0074] like Figure 4As shown, assuming the instruction size change level of the first block reaches positive level 2, after increasing the priority of the refresh command of the first block, the instruction size change level of the first block will be adjusted to positive level 1; similarly, assuming the instruction size change level of the first block reaches negative level 2, after decreasing the priority of the refresh command of the first block, the instruction size change level of the first block will be adjusted to negative level 1; compared with the initial level (level 0), positive level 1 is closer to the instruction collapse level (positive level 2), and negative level 1 is closer to the instruction expansion level (negative level 2).

[0075] At this point, after adjusting the refresh command priority, only adjusting it to the target level (rather than the initial level) will make the refresh command priority of that block easier to adjust. In this case, the same block with low traffic will be refreshed continuously to cope with possible sudden traffic storms in the future.

[0076] In one embodiment, in the basic mode, the priority control module 110 is used to adjust the refresh command priority of the first block by a first magnitude; for example, the priority control module 110 sends a request to the arbitrator to adjust the refresh command priority of the first block.

[0077] And / or, In enhanced mode, priority control module 110 is used to adjust the refresh command priority of the first block by a first magnitude if the number of pending arbitration instructions in the first block is not the extreme value of the number of pending arbitration instructions in each block in memory; for example, priority control module 110 sends a request to the arbitrator to adjust the refresh command priority of the first block by a first level. The priority control module 110 is used to adjust the refresh command priority of the first block by a second magnitude when the number of pending arbitration instructions in the first block is the extreme value of the number of pending arbitration instructions in each block in memory; for example, the priority control module 110 sends a request to the arbitrator to adjust the refresh command priority of the first block by two levels; wherein the first magnitude is smaller than the second magnitude.

[0078] For example, if the number of pending instructions in the first block is the minimum number of pending instructions in all blocks in memory, and the first block has reached the instruction collapse level, the priority control module 110 will increase the refresh command priority of the first block by two levels; or, for example, if the number of pending instructions in the first block is the maximum number of pending instructions in all blocks in memory, and the first block has reached the instruction bloat level, the priority control module 110 will decrease the refresh command priority of the first block by two levels. At this point, by controlling the number of pending arbitration commands, the priority of refresh commands can be adjusted. This allows the block with the highest traffic to have its refresh command priority reduced by more, while the block with the lowest traffic to have its refresh command priority increased by more. This prioritizes refreshing blocks with less traffic and delays refreshing blocks with higher traffic.

[0079] In one embodiment, the priority control module 110 is further configured to refresh the target row when the duration of a single refresh on the target row spacing has reached the maximum refresh interval.

[0080] A block consists of multiple rows. When a target row has not been refreshed for a long time, the priority control module 110 will force a refresh of the target row to avoid data loss within the target row.

[0081] Optionally, the maximum refresh interval is 8. 3.9us. For DDR5 memory, the RefSb refresh command is typically used for efficiency. The RefSb refresh command is used to refresh certain rows of a block. The JEDEC Solid State Technology Association stipulates that a RefSb refresh command must be sent at least once every tREFISb time period; otherwise, data will be lost. If a refresh delay is implemented, it must be sent within 8... At least one Refsb refresh command must be sent within the tREFISb time period; otherwise, a memory error, blue screen, or system crash will occur.

[0082] Optional, such as Figure 2 As shown, the refresh controller also includes a refresh timing module 140; the refresh timing module 140 is used to receive refresh commands arbitrated by the arbitrator 300 and to time the time since the last refresh for each row in memory. The refresh timing module sends the identifier of the target row whose time since the last refresh has reached the maximum refresh interval to the priority control module 110, which then forces the refresh of the target row. For example, the priority control module may send a request to the arbitrator 300 to refresh the target row.

[0083] In one embodiment, in enhanced mode, if the instruction size change level corresponding to the second block in memory also reaches the instruction collapse level, and the number of instructions to be arbitrated in the second block is also less than the first instruction number threshold. The priority control module 110 is used to increase the priority of the refresh command of the first block when the instruction size change level of the first block reaches the instruction collapse level, the number of pending instructions in the first block is less than the first instruction number threshold, and the page hit status of the first block is worse than the page hit status of the second block.

[0084] Optionally, the page hit status of the first block is better than the page hit status of the second block, including at least one of the following: 1. During the measurement period, the number of page hit instructions in the first block is less than the number of page hit instructions in the second block; 2. During the measurement period, the number of page hit instructions in the first block is the same as the number of page hit instructions in the second block, and the number of page miss instructions in the first block is less than the number of page miss instructions in the second block. 3. During the measurement period, the number of page hit instructions in the first block is the same as the number of page hit instructions in the second block, the number of page miss instructions in the first block is the same as the number of page miss instructions in the second block, and the number of page conflict instructions in the first block is less than the number of page conflict instructions in the second block.

[0085] Page hit instruction: A page hit instruction indicates that the accessed data page has been loaded into the block. A block can load different data pages at different times.

[0086] Page miss: A page miss instruction is an instruction that the accessed block does not contain any data pages, or in other words, an instruction that the accessed block does not contain any rows.

[0087] Page conflict instruction: A page conflict instruction is an instruction to access a block that contains other data pages, which are different from the data pages accessed by the page conflict instruction.

[0088] For example, the priority control module 110 will increase the priority of the refresh command for the first block if the number of page hit instructions in the first block is less than the number of page hit instructions in the second block. If the number of page hit instructions in the first block is the same as the number of page hit instructions in the second block, page miss instructions will be further compared, and the priority of the refresh command for the first block will be increased if the number of page miss instructions in the first block is less than the number of page miss instructions in the second block. If the number of page miss instructions in the first block is the same as the number of page miss instructions in the second block, page conflict instructions will be further compared, and the priority of the refresh command for the first block will be increased if the number of page conflict instructions in the first block is less than the number of page conflict instructions in the second block.

[0089] At this point, the memory access instructions for the blocks will be further subdivided, and the priority of the refresh command will be managed through the page hit status. The blocks that are relatively idle (i.e., those with poor page hit status) will be refreshed first, which can improve the overall memory performance.

[0090] Optional, refer to the reference Figure 2The memory controller also includes an address decoding module 400, which is used to map the operating system address of the memory access instruction to the memory particle address. For example, the address decoding module 400 decodes the operating system address of the memory access instruction according to the address mapping configuration to obtain the RANK / BANKGROUP / BANK / ROW / COL address information of the memory particle.

[0091] Optionally, the memory controller also includes a front-side interface (FSI). Figure 2 (Not shown), the front-end interface is used to receive memory access instructions sent by the upstream central processing unit and send the memory access instructions to the address decoding module 400.

[0092] The address decoding module 400 is electrically connected to the refresh controller 100.

[0093] Figure 2 In addition, the refresh controller 100 also includes a page status recording module 150; Page status recording module 150 is used to receive the memory granule address of the memory access instruction issued by address decoding module 400 during the measurement period. The system calculates the number of page hit instructions, page miss instructions, and page conflict instructions in the first block and transmits this information to the priority control module 110; it also calculates the number of page hit instructions, page miss instructions, and page conflict instructions in the second block and transmits this information to the priority control module 110.

[0094] Optionally, the memory controller also includes a back-end interface ( Figure 2 (Not shown), the backend interface is used to receive the memory access command arbitrated by the arbitrator 300 and send the memory access command to the memory.

[0095] In one embodiment, in conjunction with reference Figure 2 The refresh controller 100 also includes an instruction recording module 130; The instruction recording module 130 is used to store the markers of memory access instructions that are blocked during the refresh process of the first block; and to determine that the number of blocked memory access instructions reaches a pre-configured blocking number threshold. The priority control module 110 is used to increase the sending priority of blocked memory access instructions.

[0096] For example, instruction flags that cannot be arbitrated by the arbitrator 300 because the first block is in the refresh process will be stored in the instruction recording module 130. After the first block is refreshed, the instruction recording module 130 will count the number of these blocked memory access instructions. If the number of blocked memory access instructions reaches the pre-configured blocking threshold, the priority control module 110 will send a request to the arbitrator 300 to increase the arbitration priority of these blocked memory access instructions, and the arbitrator 300 will prioritize excluding these instructions.

[0097] In this embodiment, the refresh controller 100 also provides a scheduling mechanism for instructions blocked during the refresh process, increasing the priority of instructions blocked by the refresh and reducing the performance impact caused by refresh blocks. The refresh controller 100 provided in this embodiment offers a more comprehensive refresh control mechanism.

[0098] In this application embodiment, a basic mode and an enhanced mode are provided. Both apply the following mechanism.

[0099] The priority control module 110 is used to calculate the difference between the number of pending arbitration instructions and the number of already arbitrated instructions in the first block; If the difference reaches the difference threshold, adjust the instruction size change level corresponding to the first block; If the instruction size change level reaches the pre-configuration level and the number of pending arbitration instructions in the first block meets the instruction quantity condition, adjust the priority of the refresh command in the first block.

[0100] The differences between the two are as follows: (1) In the basic mode, after adjusting the refresh command priority of the first block, the priority control module 110 adjusts the instruction scale change level of the first block to the initial level; In enhanced mode, after adjusting the refresh command priority of the first block, the priority control module 110 adjusts the instruction size change level of the first block to the target level. Compared to the initial level, the target level is closer to the pre-configured level.

[0101] (2) In the basic mode, the priority control module 110 always adjusts the refresh command priority of the first block with the first amplitude; In enhanced mode, if the number of pending arbitration instructions in the first block is the extreme value of the number of pending arbitration instructions in all blocks in memory, the priority control module 110 will adjust the priority of the refresh command of the first block by a second magnitude; the second magnitude is greater than the first magnitude.

[0102] (3) In enhanced mode, if the instruction size change level of two blocks reaches the instruction collapse level at the same time, the priority control module 110 will compare the page hit status of the two blocks and increase the refresh command priority of the block with the better page hit status.

[0103] This application provides a basic mode and an enhanced mode, which can be applied to memory refresh under different scenario requirements. The basic mode can be used for general scenarios with high requirements for memory latency stability and block load balancing; the enhanced mode can be used for high-concurrency and high-performance server scenarios with drastic block load fluctuations.

[0104] like Figure 5 As shown, this application embodiment provides a memory controller 500, which includes a refresh controller 100 and a priority control module 110. The priority control module 110 is used to determine the number of pending instructions in the first block of memory and the number of already arbitrated instructions in the first block. The priority control module 110 is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0105] For further information regarding the memory controller 500, please refer to the section on "Refresh Controller" above. Those skilled in the art will understand that... Figure 5 The structure shown does not constitute a limitation on the memory controller 500. The memory controller 500 may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0106] like Figure 6 As shown, this application embodiment provides a chip 600, which includes a refresh controller 100 and a priority control module 110. The priority control module 110 is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block; The priority control module 110 is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0107] For further information regarding chip 600, please refer to the above description of the "refresh controller." Those skilled in the art will understand that... Figure 6The structure shown does not constitute a limitation on chip 600. Chip 600 may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0108] This application provides a computing device, which includes a refresh controller and a priority control module. The priority control module is used to receive the number of pending instructions in the first block of memory, as well as the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0109] For more information on computing devices, please refer to the section above on the "Refresh Controller".

[0110] Optionally, the computing device can be a portable mobile terminal, such as a smartphone, tablet, MP3 player (Moving Picture Experts Group Audio Layer III), MP4 player (Moving Picture Experts Group Audio Layer IV), laptop, or desktop computer. The computing device may also be referred to as a user device, portable terminal, laptop terminal, desktop terminal, or other names. Optionally, the computing device can also be a server.

[0111] Figure 7 A flowchart of a priority adjustment method provided in an exemplary embodiment of this application is shown, illustrated by an example of the method being executed by a refresh controller, which includes a priority control module. The method includes: Step 720: The priority control module receives the number of pending instructions in the first block of memory, and the number of arbitrated instructions in the first block. In an optional embodiment, the refresh controller is located within the memory controller; the memory controller also includes a command queue for storing memory-pending arbitration instructions.

[0112] The refresh controller also includes a traffic monitoring module; The traffic monitoring module receives the number of pending arbitration instructions for the first block sent by the command queue and passes the number of pending arbitration instructions for the first block to the priority control module.

[0113] In an optional embodiment, the refresh controller is located in the memory controller; the memory controller also includes an arbitrator; the arbitrator is used to arbitrate memory access instructions sent to memory.

[0114] The refresh controller also includes an instruction recording module; The instruction recording module receives the memory access instructions arbitrated by the arbitrator, counts the number of instructions arbitrated in the first block within a preset time window, and obtains the number of arbitrated instructions in the first block.

[0115] Step 740: The priority control module responds to the fact that the numerical relationship between the number of pending arbitration instructions and the number of arbitrated instructions in the first block meets the priority adjustment condition, and adjusts the refresh command priority of the first block. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

[0116] In an optional embodiment, the priority control module calculates the difference between the number of pending arbitration instructions and the number of already arbitrated instructions in the first block; If the difference reaches the difference threshold, adjust the instruction size change level corresponding to the first block; If the instruction size change level reaches the pre-configuration level and the number of pending arbitration instructions in the first block meets the instruction quantity condition, adjust the priority of the refresh command in the first block.

[0117] Optionally, the refresh controller also includes a traffic monitoring module; the traffic monitoring module records the change level of the instruction scale corresponding to the first block in real time.

[0118] Optionally, if the number of pending arbitration instructions in the first block is less than the number of already arbitrated instructions; When the difference reaches the difference threshold, the priority control module adjusts the instruction size change level corresponding to the first block, so that the instruction size change level corresponding to the first block changes toward the instruction collapse level. If the instruction size change level corresponding to the first block reaches the instruction collapse level, and the number of pending arbitration instructions in the first block is less than the first instruction number threshold, the priority of the refresh command for the first block is increased.

[0119] Optionally, if the number of pending arbitration instructions in the first block is greater than the number of already arbitrated instructions; When the difference reaches the difference threshold, the priority control module adjusts the instruction size change level corresponding to the first block, so that the instruction size change level corresponding to the first block changes towards the instruction inflation level. If the instruction size change level of the first block reaches the instruction inflation level, and the number of pending arbitration instructions in the first block is greater than the second instruction number threshold, the priority of the refresh command of the first block shall be reduced.

[0120] Optionally, the value of the difference threshold is related to the level of instruction size change before the first block adjustment; And / or, The value of the difference threshold is related to the size relationship type, which includes either the number of pending instructions in the first block being less than the number of already arbitrated instructions, or the number of pending instructions in the first block being greater than the number of already arbitrated instructions.

[0121] Optionally, after adjusting the priority of the refresh command in the first block, the priority control module adjusts the instruction size change level of the first block to the initial level. And / or, After adjusting the priority of the refresh command for the first block, the instruction size change level for the first block is adjusted to the target level. Among them, the target level is closer to the pre-configured level than the initial level.

[0122] Optionally, after increasing the priority of the refresh command for the first block, the priority control module adjusts the instruction size change level of the first block to the first target level. or, After reducing the priority of the refresh command for the first block, the instruction size change level for the first block is adjusted to the second target level. Among them, compared to the initial level, the first target level is closer to the instruction collapse level, and the second target level is closer to the instruction expansion level.

[0123] Optionally, if the number of pending arbitration instructions in the first block is not the extreme value of the number of pending arbitration instructions in each block in memory, the priority control module adjusts the priority of the refresh command of the first block by a first magnitude. If the number of pending arbitration instructions in the first block is the extreme value of the number of pending arbitration instructions in all blocks in memory, the priority of the refresh command in the first block is adjusted by the second magnitude. The first amplitude is smaller than the second amplitude.

[0124] In an optional embodiment, the priority control module refreshes the target row if the duration of a single refresh on the target row spacing has reached the maximum refresh interval.

[0125] In an optional embodiment, the refresh controller further includes a refresh timing module; The refresh timing module receives the refresh command arbitrated by the arbitrator and times the time elapsed since the last refresh for each row in memory.

[0126] Optionally, if the instruction size change level corresponding to the second block in memory also reaches the instruction collapse level and the number of instructions to be arbitrated in the second block is less than the first instruction number threshold. If the priority control module increases the priority of the refresh command in the first block when the instruction size change level of the first block reaches the instruction collapse level, the number of pending instructions in the first block is less than the first instruction number threshold, and the page hit status of the first block is worse than the page hit status of the second block.

[0127] Optionally, the page hit status of the first block is worse than that of the second block, including at least one of the following: During the measurement period, the number of page hit instructions in the first block is less than the number of page hit instructions in the second block; During the measurement period, the number of page hit instructions in the first block is the same as the number of page hit instructions in the second block, and the number of page miss instructions in the first block is less than the number of page miss instructions in the second block. During the measurement period, the number of page hit instructions in the first block is the same as the number of page hit instructions in the second block, the number of page miss instructions in the first block is the same as the number of page miss instructions in the second block, and the number of page conflict instructions in the first block is less than the number of page conflict instructions in the second block.

[0128] Optionally, the refresh controller is located in the memory controller, which also includes an address decoding module. The address decoding module is used to map the operating system address of the memory access instruction to the memory particle address; the refresh controller also includes a page status recording module. During the measurement period, the page status recording module receives the memory granular address of the memory access instruction issued by the address decoding module. The system calculates the number of page hit instructions, page miss instructions, and page conflict instructions in the first block and passes this information to the priority control module; it also calculates the number of page hit instructions, page miss instructions, and page conflict instructions in the second block and passes this information to the priority control module.

[0129] In an optional embodiment, the refresh controller further includes an instruction recording module; The instruction recording module stores the markers of memory access instructions that are blocked during the refresh process of the first block; it determines that the number of blocked memory access instructions has reached a pre-configured blocking threshold. The priority control module increases the sending priority of blocked memory access commands.

[0130] For more information on priority adjustment methods, please refer to the above introduction to the "Refresh Controller".

[0131] It should be understood that "multiple" as used in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0132] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0133] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent switching, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A refresh controller, characterized by The refresh controller includes a priority control module; The priority control module is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

2. The refresh controller of claim 1, wherein, The refresh controller is located within the memory controller; the memory controller also includes a command queue; The command queue is used to store the instructions to be arbitrated in the memory.

3. The refresh controller of claim 2, wherein, The refresh controller also includes a traffic monitoring module; The traffic monitoring module is used to receive the number of pending arbitration instructions for the first block sent by the command queue, and to transmit the number of pending arbitration instructions for the first block to the priority control module.

4. The refresh controller according to any one of claims 1 to 3, characterized in that, The refresh controller is located within the memory controller; the memory controller also includes an arbitrator. The arbitrator is used to arbitrate memory access instructions that are sent to memory.

5. The refresh controller according to claim 4, characterized in that, The refresh controller also includes an instruction recording module; The instruction recording module is used to receive memory access instructions arbitrated by the arbitrator, count the number of instructions arbitrated for the first block within a preset time window, and obtain the number of arbitrated instructions for the first block.

6. The refresh controller according to any one of claims 1 to 3, characterized in that, The priority control module is used to calculate the difference between the number of pending arbitration instructions and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the instruction size change level corresponding to the first block when the difference reaches the difference threshold. The priority control module is used to adjust the priority of the refresh command of the first block when the instruction size change level reaches the pre-configured level and the number of instructions to be arbitrated in the first block meets the instruction quantity condition.

7. The refresh controller according to claim 6, characterized in that, The refresh controller also includes a traffic monitoring module; The traffic monitoring module is used to record the change level of the instruction scale corresponding to the first block in real time.

8. The refresh controller according to claim 6, characterized in that, If the number of pending arbitration instructions in the first block is less than the number of already arbitrated instructions; The priority control module is used to adjust the instruction size change level corresponding to the first block when the difference reaches the difference threshold, so that the instruction size change level corresponding to the first block changes towards the instruction collapse level. The priority control module is used to increase the priority of the refresh command of the first block when the instruction size change level corresponding to the first block reaches the instruction collapse level and the number of instructions to be arbitrated in the first block is less than the first instruction number threshold.

9. The refresh controller according to claim 6, characterized in that, If the number of pending arbitration instructions in the first block is greater than the number of already arbitrated instructions; The priority control module is used to adjust the instruction size change level corresponding to the first block when the difference reaches the difference threshold, so that the instruction size change level corresponding to the first block changes towards the instruction inflation level. The priority control module is used to reduce the priority of the refresh command of the first block when the instruction size change level corresponding to the first block reaches the instruction inflation level and the number of pending arbitration instructions in the first block is greater than the second instruction number threshold.

10. The refresh controller according to claim 6, characterized in that, The value of the difference threshold is related to the level of change in the instruction size before the adjustment of the first block; And / or, The value of the difference threshold is associated with the size relationship type, which includes either the number of pending arbitration instructions in the first block being less than the number of already arbitrated instructions, or the number of pending arbitration instructions in the first block being greater than the number of already arbitrated instructions.

11. The refresh controller according to claim 6, characterized in that, The priority control module is also used to adjust the instruction scale change level of the first block to the initial level after adjusting the refresh command priority of the first block. And / or, The priority control module is also used to adjust the instruction scale change level of the first block to the target level after adjusting the refresh command priority of the first block. The target level is closer to the pre-configured level than the initial level.

12. The refresh controller according to claim 11, characterized in that, The priority control module is further configured to adjust the instruction scale change level of the first block to the first target level after increasing the priority of the refresh command of the first block. or, The priority control module is further configured to adjust the instruction size change level of the first block to the second target level after reducing the priority of the refresh command of the first block. Among them, compared with the initial level, the first target level is closer to the instruction collapse level, and the second target level is closer to the instruction expansion level.

13. The refresh controller according to claim 6, characterized in that, The priority control module is used to adjust the refresh command priority of the first block by a first magnitude when the number of pending arbitration instructions in the first block is not the extreme value of the number of pending arbitration instructions in each block in the memory. The priority control module is used to adjust the refresh command priority of the first block by a second magnitude when the number of pending arbitration instructions in the first block is the extreme value of the number of pending arbitration instructions in each block in the memory. Wherein, the first amplitude is smaller than the second amplitude.

14. The refresh controller according to any one of claims 1 to 3, characterized in that, The priority control module is also used to refresh the target row when the duration of a single refresh on the target row spacing has reached the maximum refresh interval.

15. The refresh controller according to claim 14, characterized in that, The refresh controller also includes a refresh timing module; The refresh timing module is used to receive the refresh command arbitrated by the arbitrator and to time the time since the last refresh for each row in the memory.

16. The refresh controller according to claim 8, characterized in that, If the instruction size change level corresponding to the second block in the memory also reaches the instruction collapse level and the number of instructions to be arbitrated in the second block is less than the first instruction number threshold; The priority control module is used to increase the priority of the refresh command of the first block when the instruction size change level corresponding to the first block reaches the instruction collapse level, the number of pending arbitration instructions in the first block is less than the first instruction number threshold, and the page hit status of the first block is worse than the page hit status of the second block.

17. The refresh controller according to claim 16, characterized in that, The page hit status of the first block is worse than that of the second block, including at least one of the following: During the measurement period, the number of page hit instructions in the first block is less than the number of page hit instructions in the second block; During the measurement period, the number of page hit instructions in the first block is the same as the number of page hit instructions in the second block, and the number of page miss instructions in the first block is less than the number of page miss instructions in the second block. During the measurement period, the number of page hit instructions in the first block is the same as the number of page hit instructions in the second block, the number of page miss instructions in the first block is the same as the number of page miss instructions in the second block, and the number of page conflict instructions in the first block is less than the number of page conflict instructions in the second block.

18. The refresh controller according to claim 17, characterized in that, The refresh controller is located in the memory controller, which also includes an address decoding module. The address decoding module is used to map the operating system address of the memory access instruction to the memory granular address. The refresh controller also includes a page status recording module. The page state recording module is used to receive the storage granular address of the memory access instruction issued by the address decoding module during the measurement period. The page status recording module is also used to count the number of page hit instructions, the number of page miss instructions, and the number of page conflict instructions in the first block, and transmit them to the priority control module. The system also calculates the number of page hit instructions, page miss instructions, and page conflict instructions in the second block and transmits this information to the priority control module.

19. The refresh controller according to any one of claims 1 to 3, characterized in that, The refresh controller also includes an instruction recording module; The instruction recording module is used to store the markers of memory access instructions that are blocked during the refresh process of the first block; and to determine that the number of blocked memory access instructions reaches a pre-configured blocking number threshold. The priority control module is used to increase the sending priority of the blocked memory access instruction.

20. A memory controller, characterized in that, The memory controller includes a refresh controller, and the refresh controller includes a priority control module; The priority control module is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

21. A chip, characterized in that, The chip includes a refresh controller, and the refresh controller includes a priority control module; The priority control module is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

22. A computing device, characterized in that, The computing device includes a refresh controller, and the refresh controller includes a priority control module; The priority control module is used to receive the number of pending instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module is used to adjust the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

23. A priority adjustment method, characterized in that, The method is executed by a refresh controller, which includes a priority control module, and the method includes: The priority control module receives the number of pending arbitration instructions in the first block of memory, and the number of already arbitrated instructions in the first block. The priority control module adjusts the refresh command priority of the first block in response to the numerical relationship between the number of pending arbitration commands and the number of arbitrated commands in the first block satisfying the priority adjustment condition. The refresh command priority is used to indicate the priority of issuing refresh commands to the first block.

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