Refresh control method and device for dynamic random access memory and dynamic random access memory

Abstract

This application provides a refresh control method, apparatus, and dynamic random access memory (DRAM). The method includes: in response to satisfying a refresh pre-control condition, when any memory cell reaches its refresh judgment time, acquiring the identifier of the refresh flag bit of the current memory cell; if the acquired identifier is a first identifier, skipping the refresh of the current memory cell and modifying the identifier of the refresh flag bit of the current memory cell to a second identifier; if the acquired identifier is the second identifier, refreshing the current memory cell and modifying the identifier of the refresh flag bit of the current memory cell to the first identifier; wherein, between two adjacent refresh judgment times of any memory cell, if any memory cell is hit by a read operation or a write operation, the identifier of the refresh flag bit of any memory cell is modified to the first identifier. This improves the processor's memory access response speed and the overall energy efficiency of the memory system.

Description

Technical Field

[0001] This application relates to the field of computer storage technology, and in particular to a refresh control method for dynamic random access memory (DRAM), a refresh control device for DRAM, DRAM, a computer-readable storage medium, and a computer program product. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a widely used type of main memory in computer systems. A basic DRAM storage cell consists of a transistor and a capacitor, with the presence or absence of charge stored in the capacitor representing binary data "1" or "0". Because capacitors are prone to leakage, the stored charge gradually dissipates over time; without intervention, the stored data will be lost within milliseconds. Therefore, DRAM must maintain data validity through periodic refresh operations.

[0003] Currently, DRAM commonly employs a centralized periodic refresh strategy. Specifically, first, the DRAM controller internally sets up a refresh timer that generates a refresh trigger signal at fixed intervals. Second, when the refresh trigger signal arrives, the controller suspends all read / write access requests from the processor or external devices. Then, starting from address 0, the controller sends refresh commands to the DRAM row by row, incrementing the address pointer after each row is refreshed, until all memory rows have been refreshed. Finally, after the refresh is complete, the controller resumes responding to normal read / write access requests and restarts the refresh timer, awaiting the next refresh cycle.

[0004] However, during each global refresh, all read and write access requests are blocked. Furthermore, the duration of a single refresh operation is proportional to the total number of DRAM rows. As DRAM capacity continues to increase and the number of storage rows continues to climb, the time window occupied by the refresh also expands linearly. The processor needs to wait for all storage rows to be refreshed before it can complete a memory access operation, which directly leads to a linear increase in the processor's memory access latency. It is impossible to guarantee that a single memory access operation will be completed within the expected time, thereby reducing the real-time response of the entire computing system when facing time-sensitive tasks. Summary of the Invention

[0005] The purpose of this application is to provide a refresh control method for dynamic random access memory (DRAM), a refresh control device for DRAM, DRAM, a computer-readable storage medium, and a computer program product, so as to improve memory access efficiency and shorten the longest blocking time of a single memory access.

[0006] To address the aforementioned technical problems, the embodiments of this application provide the following technical solutions: The first aspect of this application provides a refresh control method for a dynamic random access memory (DRAM). The method is applied to DRAM, which includes multiple memory cells. Each memory cell is configured with a refresh flag bit. When the refresh flag bit has a first identifier, it indicates that the corresponding memory cell will not be refreshed. When the refresh flag bit has a second identifier, it indicates that the corresponding memory cell will be refreshed. The multiple memory cells correspond to multiple refresh judgment times within a global refresh cycle. Each memory cell reaches a refresh judgment time once every target cycle, where the target cycle is less than the global refresh cycle. The method includes: in response to satisfying a refresh pre-control condition, when any memory cell reaches its own refresh judgment time, obtaining the identifier of the refresh flag bit of the current memory cell; if the obtained identifier is the first identifier, skipping the refresh of the current memory cell and modifying the identifier of the refresh flag bit of the current memory cell to the second identifier; if the obtained identifier is the second identifier, refreshing the current memory cell and modifying the identifier of the refresh flag bit of the current memory cell to the first identifier; wherein, between two adjacent refresh judgment times of any memory cell, if any memory cell is hit by a read operation or a write operation, the identifier of the refresh flag bit of any memory cell is modified to the first identifier.

[0007] Compared to existing technologies, the refresh control method for dynamic random access memory (DRAM) provided in the first aspect of this application, by independently configuring a refresh flag bit for each memory cell and dispersing its refresh judgment time, allows each memory cell to reach its judgment time at different times. Then, based on the first or second identifier of the flag bit, it determines whether to skip the refresh or perform a refresh. This reduces the longest blocking time caused by locking all memory rows at once in traditional centralized refresh to the refresh time of a single memory cell, effectively solving the defect that memory access latency increases linearly with capacity. Simultaneously, by modifying the flag bit to the first identifier (i.e., no refresh) if a memory cell is hit by a read / write operation between two adjacent refresh judgment times, the charge compensation effect of the read / write operation itself on the storage capacitor replaces the additional refresh command, allowing frequently accessed data rows to be dynamically skipped from refresh, further reducing the number of invalid refreshes and lowering the average memory access latency. Ultimately, the coordinated efforts of distributed judgment timing, on-demand refresh based on flag bits, and read / write hit replacement refresh reduce the time that would otherwise be blocked by a single memory access request due to the unified refresh operation of all memory units to the refresh time of a single memory unit. The average memory access latency decreases significantly as access frequency increases, the memory bandwidth occupied by invalid refreshes is effectively released, dynamic power consumption is greatly reduced due to the elimination of redundant refreshes, and the uncertainty of memory access timing is eliminated. Ultimately, this improves the effective bandwidth utilization, memory access real-time performance, and overall energy efficiency of the memory system.

[0008] In other embodiments provided in this application, each storage unit is further configured with a refresh enable switch. When the refresh enable switch is in a first state, it indicates that the corresponding storage unit stores data. When the refresh enable switch is in a second state, it indicates that the corresponding storage unit does not store data. Meeting the refresh pre-control conditions includes the refresh enable switch being in the first state. The method further includes: in response to not meeting the refresh pre-control conditions, skipping the refresh of the corresponding storage unit, wherein not meeting the refresh pre-control conditions includes the refresh enable switch being in the second state.

[0009] By configuring a refresh enable switch independently for each storage cell and performing refresh judgment only when the switch is in the first state, storage cells without stored data are completely isolated from the refresh control process, thereby reducing the refresh power consumption of storage cells without stored data to zero and avoiding unnecessary judgment and processing overhead.

[0010] In other embodiments provided in this application, satisfying the refresh pre-control conditions includes the access frequency of the storage unit within a preset historical period being higher than a preset threshold; the method further includes: in response to not satisfying the refresh pre-control conditions, skipping the refresh of the corresponding storage unit, wherein not satisfying the refresh pre-control conditions includes the access frequency of the storage unit within a preset historical period being lower than or equal to a preset threshold.

[0011] By using the access frequency within a preset historical period as the pre-control condition for refresh, the refresh operation is only performed on the actively accessed storage units, thereby freeing up refresh resources from inactive storage units that have not been accessed for a long time and focusing on storage units that actually store valid data and need to maintain charge, thus improving the utilization accuracy of refresh resources and the overall energy efficiency ratio.

[0012] In other embodiments provided in this application, obtaining the identifier of the refresh flag bit of the current storage unit includes: in response to the current storage unit not having any pending read / write requests, obtaining the identifier of the refresh flag bit of the current storage unit; the method further includes: in response to the current storage unit currently storing pending read / write requests, processing the read / write requests, and after the read / write requests are processed, modifying the identifier of the refresh flag bit of the current storage unit to a first identifier, in preparation for the next refresh judgment time of the current storage unit.

[0013] By prioritizing the processing of read / write requests pending in the current memory unit during the refresh decision and setting the completed flag to a non-refresh state, the refresh operation no longer blocks waiting memory access requests. Furthermore, the charge compensation effect of this access is used to replace this refresh, thereby shortening the additional memory access latency caused by the read / write request waiting for the refresh to complete and improving the processor's memory access response speed.

[0014] In other embodiments provided in this application, the target period is half of the global refresh period; before any storage cell reaches its own refresh judgment time, the method further includes: dividing the global refresh period into a first half period and a second half period; in the first half period, setting a refresh judgment time for each storage cell; and in the second half period, setting a refresh judgment time for each storage cell.

[0015] By dividing the global refresh cycle in half and setting refresh judgment times for all storage rows in each half-cycle, it ensures that each row gets at least one refresh opportunity within each refresh cycle T to maintain data reliability, reduces the risk of data loss due to sparse judgment times in storage units, and reserves more flexible timing adjustment space for subsequent dynamic scheduling based on access patterns.

[0016] In other embodiments provided in this application, the refresh judgment times of each storage unit are evenly distributed in the first half of the cycle, and the refresh judgment times of each storage unit are evenly distributed in the second half of the cycle; or, in the first half of the cycle, each storage unit is set with its own refresh judgment time, including: obtaining historical access information of each storage unit within a preset historical duration, the historical access information including access frequency and / or the most recent access time; determining the data activity level of each storage unit based on the historical access information; configuring the refresh judgment time of each storage unit in the first half of the cycle based on the data activity level, wherein the higher the data activity level, the closer the refresh judgment time of the corresponding storage unit in the first half of the cycle is to the end of the first half of the cycle, and the smaller the time interval between the refresh judgment times of adjacent storage units.

[0017] By delaying the refresh judgment time of highly active storage cells and increasing the interval between them and adjacent rows, frequently accessed storage cells can use read and write operations to replace refresh for most of the first half of the cycle to maintain data and trigger judgment as late as possible. At the same time, it avoids contention caused by multiple highly active storage cells reaching the judgment time at the same time. Thus, without increasing the peak load of the refresh circuit, the substitution effect of read and write operations on refresh is maximized, effectively reducing the number of invalid refreshes and power consumption of highly active storage cells.

[0018] In other embodiments provided in this application, after modifying the refresh flag bit of the current storage unit to the first flag, the method further includes: detecting the power supply voltage corresponding to the current storage unit; if the power supply voltage is higher than or equal to a first preset voltage threshold, then keeping the refresh flag bit of the current storage unit to the first flag; if the power supply voltage is lower than the first preset voltage threshold but higher than a second preset voltage threshold, then re-refreshing the current storage unit, and after the re-refresh is completed, keeping the refresh flag bit of the current storage unit to the first flag, wherein the first preset voltage threshold is greater than the second preset voltage threshold; if the power supply voltage is lower than or equal to the second preset voltage threshold, then modifying the refresh flag bit of the current storage unit to the second flag, and issuing a refresh failure prompt message.

[0019] By introducing graded monitoring and differentiated response of power supply voltage after refresh, the system can adaptively compensate for the attenuation of data retention capability under low voltage according to real-time voltage conditions, and issue failure prompts in a timely manner when the voltage is severely insufficient, thereby effectively reducing the risk of data loss due to voltage fluctuations while ensuring data reliability.

[0020] A second aspect of this application provides a refresh control device for a dynamic random access memory (DRAM). The device is applied to DRAM, which includes multiple memory cells. Each memory cell is configured with a refresh flag bit. When the refresh flag bit has a first identifier, it indicates that the corresponding memory cell should not be refreshed. When the refresh flag bit has a second identifier, it indicates that the corresponding memory cell should be refreshed. The multiple memory cells correspond to multiple refresh judgment times within a global refresh cycle. Each memory cell reaches a refresh judgment time once every target cycle, where the target cycle is less than the global refresh cycle. The device includes: an acquisition module, configured to acquire the identifier of the refresh flag bit of the current memory cell when any memory cell reaches its own refresh judgment time in response to satisfying a refresh pre-control condition; a modification module, configured to skip refreshing the current memory cell and modify the identifier of the refresh flag bit of the current memory cell to the second identifier if the acquired identifier is the first identifier; and a refresh module, configured to refresh the current memory cell and modify the identifier of the refresh flag bit of the current memory cell to the first identifier if the acquired identifier is the second identifier. Specifically, if any memory cell is hit by a read operation or a write operation between two adjacent refresh judgment times of any memory cell, the identifier of the refresh flag bit of any memory cell is modified to the first identifier.

[0021] A third aspect of this application provides a dynamic random access memory (DRAM) including a memory body and a refresh control circuit. The memory body includes multiple memory cells, each memory cell being configured with a refresh flag bit. When the refresh flag bit has a first identifier, it indicates that the corresponding memory cell should not be refreshed; when the refresh flag bit has a second identifier, it indicates that the corresponding memory cell should be refreshed. The multiple memory cells correspond to multiple refresh judgment times within a global refresh cycle. Each memory cell reaches a refresh judgment time every target cycle, where the target cycle is less than the global refresh cycle. The refresh control circuit is used to execute the steps of the method in the first aspect.

[0022] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed, implements the steps of the method in the first aspect.

[0023] The fifth aspect of this application provides a computer program product, including a computer program that, when executed, implements the steps of the method in the first aspect.

[0024] The refresh control device for dynamic random access memory provided in the second aspect of this application, the dynamic random access memory provided in the third aspect, the computer-readable storage medium provided in the fourth aspect, and the computer program product provided in the fifth aspect have the same or similar beneficial effects as the refresh control method for dynamic random access memory provided in the first aspect. Attached Figure Description

[0025] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily understood by reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this application are illustrated by way of example and not limitation, with the same or corresponding reference numerals denoteing the same or corresponding parts, wherein: Figure 1 This is a schematic diagram of the structure of the dynamic random access memory in the embodiments of this application. Figure 1 ; Figure 2 This is a flowchart illustrating the refresh control method for dynamic random access memory in the embodiments of this application. Figure 1 ; Figure 3 This is a timing diagram illustrating the storage unit refresh control process in an embodiment of this application; Figure 4 This is a schematic diagram of the structure of the dynamic random access memory in the embodiments of this application. Figure 2 ; Figure 5 This is a flowchart illustrating the refresh control method for dynamic random access memory in the embodiments of this application. Figure 2 ; Figure 6 This is a schematic diagram illustrating the continuous rolling of the global refresh cycle between the first and second halves of the cycle in an embodiment of this application. Figure 7 This is a schematic diagram of the structure of the refresh control device for the dynamic random access memory in the embodiments of this application. Figure 1 ; Figure 8 This is a schematic diagram of the structure of the refresh control device for the dynamic random access memory in the embodiments of this application. Figure 2 ; Figure 9 This is a schematic diagram of the structure of the dynamic random access memory in the embodiments of this application. Figure 3 . Detailed Implementation

[0026] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0027] It should be noted that, unless otherwise stated, the technical or scientific terms used in this application shall have the ordinary meaning as understood by one of ordinary skill in the art to which this application pertains.

[0028] It should be noted that the user data, data acquisition, and / or use involved in the embodiments of this application strictly comply with the laws, regulations, and industry standards of relevant countries and regions. The collection and acquisition of data involved in the embodiments of this application are all done in advance by actively prompting or prominently displaying information to inform users and obtaining authorization, or by obtaining full authorization from all parties. The processing, manipulation, forwarding, and use of data involved in the embodiments of this application are all carried out on the premise that the user or relevant party is fully informed and authorized. In implementing the various embodiments of this application, the types of data or information, scope of use, and usage scenarios that may be involved are informed to users or relevant parties and authorization is obtained through appropriate means. The specific methods of notification and authorization may vary according to the actual situation, and this application is not limited in this regard. The processing of personal information involved in the embodiments of this application is carried out under the premise of having a legal basis (such as obtaining the consent of the personal information subject or being necessary for the performance of a contract), and is only processed within the prescribed or agreed scope. Sensitive personal information such as biometric information, medical and health information, financial account information, and precise location information involved in the embodiments of this application are all processed under the premise of having a specific purpose and sufficient necessity, and with the separate authorization and consent of the user or relevant party. In some embodiments of this application, if the user or related party refuses to process personal information other than the information necessary for the basic functions, it will not affect the use of the basic functions of the embodiments of this application.

[0029] In computing scenarios where DRAM capacity continues to increase, setting a fixed-period timer to trigger a refresh and then pausing all read and write requests, and refreshing from address 0 to the last line, results in a linear increase in processor memory access latency due to the linear increase in the blocking time of a single refresh with the total number of lines, and cannot guarantee the real-time response of time-sensitive tasks.

[0030] In view of this, embodiments of this application provide a refresh control method, a refresh control device, a dynamic random access memory (DRAM), a computer-readable storage medium, and a computer program product for DRAM. This breaks the refresh paradigm of global synchronization and periodic locking. By refining the granularity of refresh control from global batches to individual rows, and reconstructing the refresh trigger time base from a single fixed global moment to independent distributed time nodes for each row, the rigid blocking of all-or-nothing in centralized refresh is transformed into flexible scheduling of individual rows on demand in distributed refresh. On top of this distributed timing framework, a dynamic flag self-correction mechanism based on read / write hits is further introduced, so that each normal memory access operation simultaneously acts as an implicit refresh command, deeply integrating data retention behavior with business access behavior, thereby forming a closed-loop link of time-series decoupling, on-demand triggering, and access substitution. The distributed judgment moment provides an independent refresh decision window for each row, fundamentally eliminating the long-term occupation of the global bus by refresh operations. Conditional refresh triggered by flag bits ensures that the real refresh command is executed only when no access occurs, avoiding invalid operations. The dynamic rewriting of the flag bit during read / write hits allows frequently accessed rows to be naturally refreshed between two judgment windows, enabling real-time linkage between refresh decisions and actual access patterns. The synergy of these three factors ultimately achieves a systemic leap of "1+1+1>3," not only compressing the worst-case memory access latency from being linearly related to capacity to a constant-level single-row refresh time, but also making the average latency adaptively decrease with access frequency. At the same time, it releases memory bandwidth occupied by invalid refreshes and reduces dynamic power consumption, providing deterministic low-latency access capabilities for DRAM in high-capacity, high-bandwidth scenarios, completely changing the negative scaling rule of traditional refresh strategies where "the larger the capacity, the worse the performance."

[0031] First, the refresh control method for dynamic random access memory provided in the embodiments of this application will be described in detail.

[0032] This method is applied to DRAM. Figure 1 This is a schematic diagram of the structure of the dynamic random access memory in the embodiments of this application. Figure 1 See Figure 1 As shown, DRAM includes multiple memory cells.

[0033] A storage unit is the basic operational unit for refresh control in DRAM. Its granularity can be flexibly defined according to the actual application scenario and is not limited to a traditional single continuous physical row. In one embodiment, a storage unit can refer to a complete physical row in a DRAM array, such as using row 0 as a storage unit. In another embodiment, a storage unit can refer to a group of multiple physical rows, such as using every four adjacent rows as a storage unit, suitable for scenarios with a large number of rows and a need to reduce control logic overhead. In yet another embodiment, a storage unit can refer to a combination of multiple non-contiguous physical rows, such as using row 1 and row 3 as a storage unit, suitable for scenarios that require merging and managing dispersed address spaces. In yet another embodiment, a storage unit can refer to a combination of a portion of a single physical row with other rows, such as merging the first half of row 1 with the entire second row as a storage unit, while the second half of row 1 belongs to another storage unit, thereby achieving fine-grained refresh control across rows and address segments based on the physical distribution or logical grouping of data. The storage units in the embodiments of this application cover a variety of implementation methods, from single row, partial area in a row, arbitrary combination of multiple rows to combination of cross-row segments. Those skilled in the art can flexibly choose according to data layout and control requirements.

[0034] Each storage unit is configured with a refresh flag.

[0035] The refresh flag is a binary status identifier used to indicate whether a refresh operation needs to be performed on the corresponding storage unit at the current refresh judgment time. This identifier only has two states: refresh required and refresh not required. When the storage unit reaches its respective refresh judgment time, it serves as the basis for decision-making to control whether a refresh command is issued. At the same time, it is dynamically rewritten by read / write hit events between two judgment times, thereby quantifying the contribution of access behavior to data preservation as a change in the status of the flag, realizing adaptive control of access replacing refresh.

[0036] There are several ways to implement the refresh flag setting. In one embodiment, the refresh flag can be centrally located within the DRAM refresh control device, maintained uniformly in the form of a register array or Content Addressable Memory (CAM) indexed by row addresses. This allows the refresh control device to access all flags locally at high speed, without needing to read or write via the external bus of the memory array, thus significantly reducing decision latency and interference with normal read / write operations of the memory array. In another embodiment, the refresh flag can be distributed around each memory bank of the DRAM memory array. For example, a flag storage circuit can be attached next to the row address decoder of each memory bank, and the refresh control device accesses the corresponding memory bank's flags via chip select and row address signals. This decentralizes the refresh decision logic to each memory bank, facilitating parallel execution of refresh decisions and operations by multiple memory banks, preventing the centralized flag array from becoming a global access bottleneck, and reducing the overhead of long-distance signal transmission between the refresh control device and distant memory banks. In another embodiment, the refresh flag can also be directly integrated as an extension bit into the metadata storage area corresponding to the row address of each storage unit, sharing the same physical storage array's read channel with the row data. In this way, when a read / write hit occurs, the refresh control device can update the flag simultaneously with the read / write access, eliminating the need for additional addressing and independent write-back operations. This atomically merges the flag update with the normal memory access operation, further reducing the additional timing overhead of refresh control.

[0037] When the refresh flag contains the first identifier, it indicates that the corresponding storage cell should not be refreshed. When the refresh flag contains the second identifier, it indicates that the corresponding storage cell should be refreshed.

[0038] The first and second flags represent two mutually exclusive states of the refresh flag, and their specific implementation can be flexibly chosen according to the circuit design. In one embodiment, the first flag is a logic low level "0" and the second flag is a logic high level "1". At this time, the refresh control device reads the flag level at the judgment moment. If it is "0", the refresh is skipped and the flag is set to "1"; if it is "1", the refresh is performed and the flag is set to "0". In another embodiment, the first flag is a logic high level "1" and the second flag is a logic low level "0". Their physical meanings are interchanged with the previous embodiment, i.e., no refresh when high level, refresh when low level. In yet another embodiment, the flag may not use a level form, but rather a pulse trigger edge as the identifier. For example, the first flag is a rising edge and the second flag is a falling edge. The refresh control device determines the state through an edge detection circuit, suitable for high-speed refresh scenarios that are sensitive to timing. Regardless of the specific form used, as long as the two states of no refresh and refresh can be clearly distinguished logically, and the state can be controllably switched at the judgment moment and when a read / write hit event occurs, it is acceptable.

[0039] Multiple storage units correspond to multiple refresh judgment moments within the global refresh cycle. Each storage unit reaches a refresh judgment moment once every target cycle, and the target cycle is shorter than the global refresh cycle.

[0040] In other words, within a complete global refresh cycle, the refresh decision time for each storage unit is not exactly the same. Some storage units may have the same refresh decision time. Alternatively, different storage units may be assigned different time points as their refresh decision trigger times, and these times are staggered and do not overlap. The refresh decision time for each storage unit recurs periodically at a target period interval, and this target period is shorter than the global refresh cycle, meaning that each storage unit will reach its refresh decision time at least twice within each global refresh cycle.

[0041] For example, if the global refresh cycle T = 64ms and the target cycle can be set to 48ms (i.e., 3T / 4), then each storage unit will reach the refresh judgment time in sequence at 0ms, 48ms, 96ms (i.e., 32ms in the next global refresh cycle), 144ms (i.e., 16ms in the next global refresh cycle)... The interval between two adjacent judgments is always 48ms and less than T, ensuring that each row has at least one judgment opportunity within any 64ms window.

[0042] In this way, the refresh judgment time of all storage units is evenly or adaptively distributed on the time axis, which avoids contention caused by multiple rows triggering judgment at the same time, and ensures that each row has at least enough judgment opportunities in any global refresh cycle to maintain data reliability.

[0043] Figure 2 This is a flowchart illustrating the refresh control method for dynamic random access memory in the embodiments of this application. Figure 1 See Figure 2 As shown, the method may include: S21: In response to the fulfillment of the refresh pre-control conditions, when any storage cell reaches its own refresh judgment time, the refresh flag bit of the current storage cell is obtained.

[0044] The reason why the subsequent refresh judgment process is only executed after the refresh pre-control conditions are met is to avoid performing flag bit reading and status judgment operations on all memory cells, which would lead to unnecessary power consumption waste and control logic overhead.

[0045] Refresh pre-control conditions refer to the prerequisites used to determine whether a storage unit is eligible to be included in the refresh control process. Only after the determination is passed can the corresponding storage unit be allowed to enter the subsequent refresh judgment and operation process.

[0046] Meeting the pre-refresh control conditions can include factors such as the data retention time of the current storage unit being less than a preset duration threshold, or the temperature of the storage area where the current storage unit is located being higher than a preset temperature threshold. By including storage units with excessively short data retention times or excessively high operating temperatures in the refresh control process, differentiated refresh management can be implemented for storage units with weaker reliability, thereby effectively improving the reliability of data retention while keeping the overall refresh overhead essentially unchanged.

[0047] The refresh control device maintains a global timer or an independent timer for each storage unit. When the timer value matches the preset judgment time of a certain storage unit (e.g., the timer overflows or the count reaches the refresh judgment time of the storage unit), the refresh decision process of that storage unit is triggered.

[0048] At this time, the refresh control device accesses the refresh flag storage area through the address index of the storage unit, reads the identifier of the flag corresponding to the storage unit, and uses it as the basis for subsequent judgment.

[0049] S22: If the obtained identifier is the first identifier, skip refreshing the current storage unit and change the identifier of the refresh flag bit of the current storage unit to the second identifier.

[0050] The acquired identifier is the first identifier, meaning that the current memory cell has been hit by a read / write operation before this judgment time. The charge in its capacitor has been effectively compensated through bit line pre-charging or write drive during the read / write access process, and the data is still in a valid state, requiring no additional refresh operation. At this time, the refresh control device does not issue any refresh command to the memory cell (i.e., it does not activate the word line of this row for read-and-write refresh cycle), nor does it pause the normal read / write channel of this row, but simply ignores the trigger signal of this judgment time.

[0051] Then, the refresh control device modifies the flag bit's identifier to the second identifier via the flag bit writing circuit, switching the state of the memory cell from not needing a refresh to needing a refresh. This can be achieved by writing the corresponding bit in the register array from logic "0" to logic "1", or by using a write enable signal in the distributed flag bit storage circuit to complete the state flip. This prepares the device for the next judgment. If the memory cell remains unaccessed within the next target cycle, the flag bit will be the second identifier at the next judgment, triggering the actual refresh operation. This ensures that data is not lost due to exceeding one global refresh cycle even if the cell remains unaccessed for an extended period.

[0052] S23: If the obtained identifier is the second identifier, then refresh the current storage unit and modify the identifier of the refresh flag bit of the current storage unit to the first identifier.

[0053] The acquired identifier is the second identifier, meaning that the current memory cell was not hit by any read or write operation in the previous target cycle, and the charge stored in its capacitor has not been accessed and is approaching or has reached the critical state that requires refreshing to maintain data validity. At this time, the refresh control device issues a standard refresh command to the memory cell, first activating the memory cell (i.e., pulling the word line high to connect the memory cell to the bit line), then reading the data through the sensitive amplifier and rewriting the original data back into the capacitor of the memory cell, completing a complete read-write refresh cycle, thereby restoring the partially lost charge to a full level, ensuring that the data is not lost during the subsequent retention time.

[0054] After the refresh is completed, the refresh control device modifies the flag bit of the memory cell to the first identifier through the flag bit writing circuit, so that its state changes from needing refresh to not needing refresh. This prevents the memory cell from being refreshed again in the adjacent target period after the refresh is completed. At the same time, it also enables subsequent read / write hit events to maintain the state on the side that does not need refresh, thus achieving the adaptive control effect of access replacing refresh.

[0055] In addition to the refresh control process based on the refresh judgment time mentioned above, a dynamic update mechanism for the flag bit triggered by read and write access events is further introduced: between two adjacent refresh judgment times of any storage cell, if any storage cell is hit by a read operation or a write operation, the refresh flag bit of any storage cell is modified to the first flag.

[0056] Specifically, within the time window between two consecutive refresh determination moments for each memory cell, the refresh control device continuously monitors whether the memory cell receives read or write access requests from the processor or external devices. Once a read / write hit event is detected for the memory cell, it indicates that the memory cell has been actually accessed within the current time period, and its capacitors have received effective charge replenishment through bit line pre-charging in read operations or drive writing in write operations, thus naturally refreshing the data retention state. At this time, the refresh control device immediately modifies the refresh flag bit of the memory cell to the first flag (i.e., no refresh state required) without waiting for the next refresh determination moment.

[0057] The essence of this operation is to transform a normal read / write access into an implicit refresh signal. The access behavior itself indicates that the data has been reactivated and compensated, so there is no need to execute an additional refresh command for this storage unit at subsequent refresh determination times.

[0058] It is worth noting that this modification operation is immediate and prioritized. Regardless of the current state of the flag, once a read / write hit occurs, the flag is unconditionally set to the first flag to ensure that the charge compensation effect brought about by the access is recorded in a timely manner. Furthermore, this operation is triggered independently of the main process at the refresh judgment time; it is asynchronously driven by read / write access events, and its update timing depends entirely on the actual memory access activity.

[0059] This mechanism allows frequently accessed storage units to be continuously reset to a refresh-free state with each read / write hit, thus skipping refreshes repeatedly between adjacent judgment times. This achieves an adaptive energy-saving effect where more frequent access results in fewer refreshes. Storage units that have not been accessed for a long time will retain their second flag after a target cycle, without being rewritten to the first flag. A true refresh will be triggered at the next judgment time, achieving a dynamic balance between data reliability and refresh overhead.

[0060] Figure 3 This is a timing diagram illustrating the memory cell refresh control process in an embodiment of this application. See [link / reference] Figure 3As shown, assuming a global refresh cycle T = 64ms, a DRAM chip has N = 16384 rows, and the target cycle is set to T / 2 = 32ms. Taking row 0 as an example, its refresh judgment time occurs at 0ms, 32ms, 64ms, 96ms... with each adjacent judgment time interval being 32ms, and the initial judgment times of each row are evenly staggered (the first judgment time of row i is t = (i / N) × 64ms). At 0ms, row 0 reaches its first refresh judgment time. The refresh control device reads the refresh flag bit of this row, which is initially preset to 0 (refresh required). Therefore, the controller performs a standard refresh operation on this row and sets the flag bit to 1 after the refresh is completed (refresh not required). Subsequently, within the time window from 0ms to 32ms, this row is not hit by any read or write operation, and the flag bit remains unchanged at 1. Then, at 32ms, this row reaches its second refresh judgment time. The controller reads the flag bit as 1, therefore skips the refresh, and flips the flag bit to 0 (refresh required), preparing for the next 32ms window. Within the 32ms to 64ms time window, if the processor initiates a write request for that row, the refresh control immediately changes the row's flag from 0 to 1 upon successful write operation (no refresh is required). This write operation replenishes the row's capacitor with sufficient charge through drive writing, effectively replacing a refresh with a write operation. Therefore, no refresh is needed at subsequent checkpoints within this window. At the 64ms checkpoint, during the third refresh check, the controller reads the flag as 1, skips the refresh again, flips the flag to 0, and enters the next target cycle. Within the 64ms to 96ms time window, if the row is not hit by any read or write operation, the flag remains at 0. At the 96ms checkpoint, the flag is 0, a refresh is performed, and the flag is changed to 1. This cycle repeats, and the row will only keep its flag bit at 0 and trigger a real refresh operation if it has not been hit by any read or write operation for 32 consecutive ms. Any write or read operation can immediately set the flag bit to 1, delaying the refresh timing by at least one target cycle. This ensures both data reliability (the interval between any two refresh executions never exceeds the global refresh cycle T=64ms) and fully utilizes the proactive refresh effect of write operations on data, reducing the number of actual refresh command executions to the lowest level that dynamically matches memory access activity.

[0061] As can be seen from the above, the refresh control method for dynamic random access memory provided in this application, by independently configuring a refresh flag bit for each memory cell and dispersing its refresh judgment time, allows each memory cell to reach its judgment time at different times. Then, based on the first or second identifier of the flag bit, it determines whether to skip the refresh or perform a refresh. This shortens the longest blocking time caused by locking all memory rows at once in traditional centralized refresh to the refresh time of a single memory cell, effectively solving the defect that memory access latency increases linearly with capacity. Simultaneously, by modifying the flag bit to the first identifier (i.e., no refresh) if a memory cell is hit by a read / write operation between two adjacent refresh judgment times, the charge compensation effect of the read / write operation itself on the storage capacitor replaces the additional refresh command, allowing frequently accessed data rows to be dynamically skipped from refresh, further reducing the number of invalid refreshes and lowering the average memory access latency. Ultimately, the coordinated efforts of distributed judgment timing, on-demand refresh based on flag bits, and read / write hit replacement refresh reduce the time that would otherwise be blocked by a single memory access request due to the unified refresh operation of all memory units to the refresh time of a single memory unit. The average memory access latency decreases significantly as access frequency increases, the memory bandwidth occupied by invalid refreshes is effectively released, dynamic power consumption is greatly reduced due to the elimination of redundant refreshes, and the uncertainty of memory access timing is eliminated. Ultimately, this improves the effective bandwidth utilization, memory access real-time performance, and overall energy efficiency of the memory system.

[0062] Furthermore, as a response to Figure 2 In a refinement and extension of the method shown, this application embodiment also provides a refresh control method for dynamic random access memory.

[0063] Figure 4 This is a schematic diagram of the structure of the dynamic random access memory in the embodiments of this application. Figure 2 See Figure 4 As shown, each storage unit is also equipped with a refresh enable switch.

[0064] The refresh enable switch is used to independently control whether each memory cell participates in the refresh control process. When the switch is on, the cell performs refresh judgment and operation normally. When the switch is off, the cell is completely skipped from the refresh process, without consuming refresh power or occupying the judgment resources of the refresh control device.

[0065] When the refresh enable switch is in the first state, it indicates that the corresponding storage cell contains data. When the refresh enable switch is in the second state, it indicates that the corresponding storage cell does not contain data.

[0066] The first and second states of the refresh enable switch can take different forms depending on the circuit implementation. In one embodiment, the first state is a logic high level "1", indicating that the corresponding memory cell stores data, and the second state is a logic low level "0", indicating that the corresponding memory cell does not store data. In another embodiment, the first state is a logic low level "0", and the second state is a logic high level "1", with their physical meanings interchanged with the previous embodiment. Of course, the first and second states can also be distinguished by pulse width, for example, the first state is a wide pulse (indicating that data is stored) and the second state is a narrow pulse (indicating that no data is stored), or by analog signal forms such as duty cycle or frequency encoding. The specific manifestation of the first and second states is not limited here.

[0067] In short, "data stored" means that the storage unit is currently actually allocated and written with valid data by the operating system or application. The charge state of its capacitor represents meaningful binary information and needs to be refreshed and maintained. "No data stored" means that the storage unit is currently not allocated or used. The charge state of its capacitor does not need to be maintained (it may be a random value or all zeros), and even if the charge is lost, no valid data will be lost. The refresh enable switch can completely shut down the refresh activity of a storage unit when the system knows that some storage units are idle (e.g., physical memory is not fully used, a storage block is reserved, or a segment of address space is released) by configuring the enable switch of the corresponding storage unit to the second state. This allows the refresh control device to completely skip the storage unit in the global timing and judgment process, thereby reducing the refresh power consumption of the storage unit to zero and reducing the processing overhead of the refresh control device for invalid reading and judgment of idle storage units, thus achieving fine-grained power management at the system level.

[0068] Figure 5 This is a flowchart illustrating the refresh control method for dynamic random access memory in the embodiments of this application. Figure 2 See Figure 5 As shown, the method may include: S51: Divide the global refresh cycle into a first half cycle and a second half cycle.

[0069] The global refresh cycle refers to the maximum allowable refresh interval time set by DRAM to ensure that data in all memory cells is not lost. If the refresh is not performed within this cycle, the storage charge will decay to the point that the data cannot be correctly identified.

[0070] The target period is the time interval between two consecutive refresh judgment moments for the same storage unit. It is set to half of the global refresh period to ensure that each row reaches at least two judgment moments within each global refresh period, so that if it is not accessed in the first half of the period, there is still a chance to refresh in the second half of the period. If the target period is longer than half of the global refresh period, the interval between the two judgments may exceed half of the global refresh period, resulting in a row having only one judgment opportunity within the global refresh period and failing to use access to replace refresh. If the target period is shorter than half of the global refresh period, it will lead to excessively frequent judgments, increasing control overhead.

[0071] Therefore, setting the target period to half of the global refresh period essentially means dividing the global refresh period into a first half and a second half, so that each storage unit reaches a refresh judgment time exactly in each half-cycle, thus obtaining a decision opportunity in each of the two half-cycles.

[0072] S52: In the first half of the cycle, each storage unit is set with its own refresh judgment time; in the second half of the cycle, each storage unit is set with its own refresh judgment time.

[0073] The global refresh cycle T is divided into a first half and a second half. Each storage unit reaches a refresh decision time once within each half-cycle, meaning the interval between two adjacent decision times is fixed at T / 2. This division method repeats continuously along the entire time axis, and the second half of the previous global refresh cycle completely overlaps with the first half of the next global refresh cycle on the time axis. In other words, the second half of the previous global refresh cycle is also the first half of the next global refresh cycle, sharing the same physical time. This allows the decision times of each storage unit to continuously roll forward at equal intervals of T / 2 along the entire time axis. The interval between two adjacent decision times will never exceed T / 2, thus ensuring that the time interval between any two refresh executions (or access-alternative refreshes) does not exceed the complete refresh cycle T. This guarantees data reliability while creating sufficient decision frequency for access-alternative refreshes.

[0074] Figure 6 This is a schematic diagram illustrating the continuous rolling of the global refresh cycle between the first and second halves of the cycle in an embodiment of this application. See [link / reference]. Figure 6As shown, taking a global refresh cycle T=64ms as an example, the k-th global refresh cycle consists of the first half of the cycle (0~32ms) and the second half of the cycle (32~64ms). Simultaneously, the period from 32 to 64ms also constitutes the first half of the (k+1)-th global refresh cycle. That is, the second half of the k-th global refresh cycle and the first half of the (k+1)-th global refresh cycle completely overlap on the time axis, representing the same physical time. When time progresses to 64ms, the first half of the (k+1)-th global refresh cycle (i.e., the second half of the k-th cycle) ends, and the second half of the (k+1)-th global refresh cycle (64~96ms) begins. Similarly, 64~96ms is also the first half of the (k+2)-th global refresh cycle. Thus, the second half of each global refresh cycle shares the same physical time with the first half of the next global refresh cycle. The entire time axis is thus continuously covered by alternating first and second half cycles without any gaps or breaks, and each storage unit gets one refresh opportunity within each half-cycle.

[0075] In the first and second halves of the cycle, the refresh decision time for each storage unit can be flexibly configured according to system requirements. It can be evenly distributed in each half cycle to ensure that the refresh request time is evenly distributed, or it can be non-uniformly distributed in each half cycle to meet the comprehensive trade-off requirements of different systems for latency, power consumption and implementation complexity.

[0076] In the case of uniform distribution, the refresh judgment time of each storage cell is evenly distributed in the first half of the cycle, and the refresh judgment time of each storage cell is evenly distributed in the second half of the cycle.

[0077] In specific settings, the first half of the cycle (T / 2) can be divided into N time slots according to the total number of DRAM rows N. The width of each time slot is Δt=(T / 2) / N, and the refresh judgment time of the i-th memory cell in the first half of the cycle is set to t. half1i =i×Δt (i=0,1,…,N-1). Similarly, the refresh judgment time in the second half of the cycle is set to t. half2i =T / 2+i×Δt, thus ensuring that the judgment time of all storage units in the entire global refresh cycle T is 0,Δt,2Δt,…,(N-1)Δt,T / 2,T / 2+Δt,…,T / 2+(N-1)Δt, that is, the judgment time interval between two adjacent storage units is always Δt.

[0078] For example, assuming a global refresh cycle T = 64ms and a total number of DRAM rows N = 16384, the first half-cycle length is 32ms, and the width of each time slot Δt = 32ms / 16384 ≈ 1.953μs. Therefore, the judgment time for the first half-cycle of row 0 is 0ms, for row 1 it's 1.953μs, for row 2 it's 3.906μs, and so on, until row 16383 is 31.998ms. The second half-cycle starts at 32ms, with the judgment time for row 0 being 32ms, for row 1 it's 32ms + 1.953μs, and so on, until row 16383 is 63.998ms. Through this uniform distribution setting, the refresh judgment time interval between any two adjacent rows (in row address order) is fixed at 1.953μs. The refresh request is evenly distributed throughout the entire T, avoiding bus contention and sudden blocking caused by multiple rows triggering judgments simultaneously.

[0079] For non-uniform distribution scenarios, each storage cell is configured with a basic refresh judgment time in the first half of the cycle and a basic refresh judgment time in the second half of the cycle. For storage cells physically located near the array edge or far from the power supply, and with a leakage rate higher than a preset threshold, an additional first supplementary refresh judgment time is configured in the first half of the cycle, and an additional second supplementary refresh judgment time is configured in the second half of the cycle. Storage cells physically located near the array center or near the power supply, and with a leakage rate lower than or equal to the preset threshold, are not configured with supplementary refresh judgment times in either the first or second half of the cycle. The first supplementary refresh judgment time in the first half of the cycle is configured once per first half of the cycle or once every few first half of the cycle. The second supplementary refresh judgment time in the second half of the cycle is configured once per second half of the cycle or once every few second half of the cycle. The basic refresh judgment time and the supplementary refresh judgment time are matched with the inherent physical retention characteristics of each storage cell, allowing storage cells with higher leakage rates to obtain more refresh judgment opportunities in a single cycle, thereby improving data reliability without significantly increasing the overall number of refreshes.

[0080] Alternatively, the refresh judgment time for each storage unit in the first and second halves of the cycle can be set based on the access frequency and / or the data activity level determined by the most recent access time within a preset historical period.

[0081] Specifically, step S52 above may include: S52a: Obtain historical access information for each storage unit within a preset historical time period. The historical access information includes access frequency and / or the most recent access time.

[0082] The preset history duration is the length of the time window used to statistically analyze storage unit access behavior. Its value can be greater than or equal to the target period and less than the global refresh period to fully reflect recent access patterns. For example, it can be set to the global refresh period or dynamically adjusted according to the application scenario.

[0083] Historical access information refers to the statistical data and timing data of each storage unit being hit by read / write operations within a preset historical period, which are recorded by the refresh control device. It can be obtained by monitoring the matching of read / write request addresses and storage unit addresses on the memory bus.

[0084] The access frequency is the total number of read and write operations that hit the storage unit within a preset historical period, and the most recent access time is the timestamp of the last hit of the storage unit within a preset historical period.

[0085] S52b: Determine the data activity level of each storage unit based on historical access information.

[0086] Specifically, any of the following methods can be used to determine this: Method 1: Determined by access frequency. The access frequency within a preset historical period is compared with multiple preset frequency thresholds. The higher the access frequency, the higher the corresponding data activity level. For example: an access frequency greater than the first threshold indicates a high activity level, between the first and second thresholds indicates a medium activity level, and less than the second threshold indicates a low activity level.

[0087] Method 2: Determined based on the most recent access time. The time difference between the most recent access time and the current time is compared with several preset time difference thresholds. The smaller the time difference, the higher the data activity level. For example: a time difference less than the first threshold indicates a high activity level, a time difference between the first and second thresholds indicates a medium activity level, and a time difference greater than the second threshold indicates a low activity level.

[0088] Method 3: Determined based on a weighted combination of access frequency and most recent access time. Access frequency and most recent access time are each assigned a preset weight, and then summed. The weighted sum is compared with multiple preset combination thresholds to determine the data activity level.

[0089] S52c: Based on the data activity level, configure the refresh judgment time for each storage unit in the first half of the cycle. The higher the data activity level, the closer the refresh judgment time of the corresponding storage unit is to the end of the first half of the cycle, and the smaller the time interval between the refresh judgment time of the adjacent storage units.

[0090] On the timeline of the first half of the cycle (from time 0 to time T / 2), storage cells with higher data activity levels have their refresh judgment time shifted further back (i.e., closer to time T / 2), while the judgment interval between high-activity rows is compressed to a smaller extent. This way, high-activity storage cells are judged near the end of the half-cycle, maximizing the use of the large number of read and write operations in the first half of the cycle to replace refreshes and reducing unnecessary refresh commands. Compressing the intervals between high-activity storage cells further ensures that the judgments of these most important rows are processed centrally within the time window near the end, preventing high-activity rows from missing a judgment opportunity in the first half of the cycle due to excessively large intervals.

[0091] For example, assuming the first half-cycle is 32ms long and the DRAM has four rows (rows 0 to 3), based on historical access information, rows 0 and 1 are determined to be high-activity, row 2 to be medium-activity, and row 3 to be low-activity. The configuration would be as follows: the judgment time for low-activity row 3 would be set at t=8ms (close to the start), for medium-activity row 2 at t=16ms, and for high-activity rows 0 and 1 at t=28ms and t=30ms respectively, with an interval of only 2ms, both close to the end of the first half-cycle at 32ms. In this way, within the 0-28ms window, when rows 0 and 1 are frequently accessed, their flag bits will be continuously reset to the first flag (no refresh required). Therefore, when the judgment times are reached at t=28ms and t=30ms, a refresh is highly likely to be skipped, maximizing the effect of "access replacing refresh".

[0092] The refresh timing configuration method for the second half of the cycle is the same as that for the first half of the cycle, and will not be repeated here.

[0093] S53: If the refresh enable switch is in the first state, determine whether the corresponding memory cell has reached its own refresh judgment time.

[0094] When the refresh enable switch of the current storage cell is in the first state, it means that the storage cell stores valid data, and the refresh control device incorporates it into the refresh control process. That is, when the global timing and judgment time arrives, the flag bit reading, judgment, and refresh operations are performed normally, allowing it to participate in the complete refresh decision and execution process.

[0095] S54: If the refresh enable switch is in the second state, skip refreshing the corresponding memory cell.

[0096] When the refresh enable switch of the current storage cell is in the second state, it means that the storage cell does not store valid data, and the refresh control device skips the storage cell in the global timing and judgment process. That is, it does not read its refresh flag bit, does not perform any refresh judgment or refresh operation, and completely removes it from the refresh control process.

[0097] Here, the refresh enable switch of the storage unit can be manually set by the user or system software through the configuration register according to the current actual memory usage, or it can be automatically and dynamically configured by the refresh control device according to the historical access information of each storage unit.

[0098] Specifically, prior to steps S53 and S54 above, the method may further include: S5301: Obtain the access frequency of each storage unit within a preset historical period.

[0099] The preset history duration can be set to be greater than or equal to the target period but less than the global refresh period, such as a global refresh period T. This ensures that the activity level determination is based on the latest memory access behavior without introducing outdated historical information due to an excessively long window, guaranteeing that the configuration at the refresh determination time can quickly respond to the migration of memory access hotspots. Alternatively, the preset history duration can also be set to an integer multiple of the global refresh period T (e.g., 2T, 3T, etc.). This can smooth out frequency fluctuations caused by short-term bursts of access, thereby avoiding the control overhead and instability caused by frequent jittering of the configuration at the refresh determination time.

[0100] Alternatively, the preset history duration can be dynamically determined based on the information entropy of the access patterns of each storage unit. Specifically, the access frequency distribution of all storage units within the current statistical window is obtained, the information entropy value of this distribution is calculated, and the preset history duration is dynamically adjusted based on the information entropy value. A higher information entropy value indicates a more dispersed access distribution, thus increasing the preset history duration to capture more comprehensive access patterns. Conversely, a lower information entropy value indicates a more concentrated access distribution, thus decreasing the preset history duration to improve the response sensitivity to local access hotspots.

[0101] By dynamically adjusting the preset historical duration based on the access distribution information entropy, the statistical window can adaptively match the concentration or dispersion of the current access pattern. When the access distribution is uniform, the window is extended to stabilize the activity level determination and avoid misjudgment. When the access is concentrated, the window is shortened to quickly track hotspot migration, thereby improving the accuracy and adaptability of activity level determination, and ultimately improving the adaptive accuracy of refresh control and system energy efficiency.

[0102] Access frequency refers to the cumulative number of times a storage unit is hit by read or write operations within a preset historical time period. For example, if a row is hit by read or write operations 120 times within 64ms, then its access frequency is 120.

[0103] S5302: If the access frequency is lower than or equal to the preset frequency threshold, it is determined that the current storage unit does not store data, and the refresh enable switch of the current storage unit is configured to the second state.

[0104] If the access frequency is lower than the preset frequency threshold, it means that the storage unit has been accessed very little or not at all within the preset historical period. Since valid data is usually read and written regularly by the program, the long-term sporadic access pattern strongly indicates that the storage unit is not currently being used. Therefore, the refresh control device switches the refresh enable switch of the storage unit from the first state to the second state. For example, by writing to the configuration register, the enable bit corresponding to the row is changed from logic "1" to logic "0", so that the subsequent refresh process is completely skipped.

[0105] S5303: If the access frequency is higher than the preset frequency threshold, it is determined that the current storage unit stores data, and the refresh enable switch of the current storage unit is configured to the first state.

[0106] If the access frequency is not lower than the preset frequency threshold, it means that the storage unit is accessed regularly and frequently within the preset historical time period. Since valid data can only be used by the program through read and write operations, the continuous and stable access activity fully indicates that the storage unit currently contains valid data. Therefore, the refresh control device switches the refresh enable switch of the row from the second state to the first state. For example, by writing to the configuration register, the enable bit of the row corresponding to the row is changed from logic "0" to logic "1", so that it can resume participating in the complete refresh control process.

[0107] It should be noted that both the refresh enable switch and the access frequency-based judgment can be used independently to determine whether a storage unit participates in refresh control. Specifically, when the refresh control device obtains the access frequency of the current storage unit within a preset historical time period, if the access frequency is lower than or equal to a preset frequency threshold, it can directly determine that the storage unit will not participate in the refresh judgment time, completely skipping the refresh judgment process; if it is higher than the preset frequency threshold, it is determined that it participates in the refresh judgment, and at its own refresh judgment time, it normally performs the acquisition, judgment, and refresh operation of the refresh flag bit. This method can automatically determine the refresh eligibility of storage units without relying on the preset state of the refresh enable switch, further simplifying hardware configuration requirements, improving the automation level of refresh control, and reducing power consumption and control overhead of invalid refreshes.

[0108] S55: When any storage unit reaches its own refresh judgment time, check whether there are any pending read / write requests in the current storage unit.

[0109] At the refresh decision point, there may be pending read or write requests for that memory cell, meaning these requests are waiting to be executed. If a refresh operation is performed directly, read requests will be blocked, increasing access latency. Therefore, prioritizing the detection of pending read / write requests before making a refresh decision allows memory access operations that would otherwise have to wait for the refresh to complete to be processed in advance. The charge compensation effect of these operations replaces the current refresh, eliminating the additional waiting latency for read / write requests and avoiding the timing and power consumption overhead of subsequent redundant refreshes.

[0110] When detecting the existence of read / write requests, the address matching signal on the memory bus can be listened to. When the target address of the request falls within the address range corresponding to the memory unit, it is determined that there is a request to be processed. The type of read / write request can be determined by parsing the command type signal on the memory bus. Read Command indicates a read request, and WriteCommand indicates a write request.

[0111] S56: If a read / write request exists, process the read / write request, and after the read / write request is processed, change the refresh flag of the current storage unit to the first flag, in preparation for the next refresh judgment time of the current storage unit.

[0112] When a pending read / write request is detected in the current memory cell, it means that the memory cell is currently being accessed by the processor at the moment of this refresh decision. Its storage capacitor will receive charge compensation due to bit line pre-charging during read operations or drive writing during write operations, thus naturally maintaining data validity. At this time, the refresh control device can determine the request type by parsing the command type signal on the memory bus, pause the refresh decision process, and prioritize allocating the memory channel to the read / write request for execution. After the access operation is completed, the charge of the memory cell has been effectively replenished, and the refresh control device directly modifies the refresh flag to the first identifier, thereby recording that the memory cell has been accessed and compensated, and no further refresh is needed, before continuing the subsequent refresh scheduling process.

[0113] If the read / write request is a read request, the flag bit is set immediately after the read operation is completed and the read data is returned to the processor. If it is a write request, the flag bit must be set only after the write operation is completed to ensure that the state of the newly written data is correctly recorded.

[0114] S57: If there is no read / write request, obtain the identifier of the refresh flag bit of the current storage unit.

[0115] If there are no read / write requests, it means that the storage unit is currently idle and there are no access operations that need to be responded to first. Therefore, it can directly enter the refresh judgment process and decide whether to perform refresh according to the refresh flag bit according to normal logic, so as to ensure that the data can still be refreshed and maintained within the specified period without access compensation.

[0116] The refresh judgment process and the execution order of pending read and write requests are not limited to the above scheme, and can also be flexibly configured to other orders according to actual application needs.

[0117] Specifically, it can be configured so that regardless of whether the pending request is a read or write request, read and write requests are executed first, and the refresh judgment process is executed only after the read and write requests are processed. This places the memory access operation with the highest priority, which can minimize memory access latency and is suitable for real-time computing scenarios with extremely high response speed requirements. Alternatively, it can be configured so that regardless of whether the pending request is a read or write request, the refresh judgment process is executed first, and read and write requests are executed only after the refresh judgment and refresh operation are completed. This places the refresh operation with the highest priority, which can ensure that the refresh cycle is strictly controlled and data reliability is guaranteed to the greatest extent, and is suitable for mission-critical scenarios with extremely stringent data retention requirements. Either of the above execution orders can be flexibly selected according to the system's different priorities regarding latency sensitivity and data reliability.

[0118] S58: If the obtained identifier is the first identifier, skip refreshing the current storage unit and change the identifier of the refresh flag bit of the current storage unit to the second identifier.

[0119] S59: If the obtained identifier is the second identifier, then refresh the current storage unit and modify the identifier of the refresh flag bit of the current storage unit to the first identifier.

[0120] Steps S58-S59 here are implemented in the same way as S22-S23 in the aforementioned embodiments, and can be found in the relevant descriptions in the aforementioned embodiments, which will not be repeated here.

[0121] Before the refresh flag of the current storage cell is modified to the first flag, i.e. when the refresh operation is performed, the refresh operation may fail to restore the charge of the storage capacitor to the full level due to the low power supply voltage, resulting in substandard refresh quality. Therefore, after the refresh is completed, the power supply voltage is further detected to determine whether additional refresh or error reporting is needed based on the actual voltage level.

[0122] S510: Detects the power supply voltage corresponding to the current storage unit.

[0123] Specifically, the voltage value of the memory cell or the global power supply network can be sampled in real time by a voltage monitoring circuit set inside the DRAM chip, and the sampled value is compared with a preset voltage threshold to detect the power supply voltage corresponding to the current memory cell.

[0124] S511: If the power supply voltage is higher than or equal to the first preset voltage threshold, then the refresh flag of the current storage cell is kept as the first flag.

[0125] If the power supply voltage is higher than or equal to the first preset voltage threshold, it means that the current power supply is sufficient and the storage unit is working in the normal voltage range. The refresh operation can reliably restore the storage capacitor to a fully charged state, and the validity of data retention is fully guaranteed. Therefore, no additional processing is required. The refresh flag of the current storage unit is directly kept as the first flag to maintain the state that does not need to be refreshed.

[0126] S512: If the power supply voltage is lower than the first preset voltage threshold and higher than the second preset voltage threshold, the current storage cell is refreshed again, and the refresh flag of the current storage cell is kept as the first flag after the refresh is completed.

[0127] If the supply voltage is lower than the first preset voltage threshold but higher than the second preset voltage threshold, it means that the current supply voltage is in a critical range of undervoltage but still capable of completing a basic refresh operation. At this voltage, the charge recovery capability of the storage capacitor decreases, and the already performed refresh operation may not be able to restore the charge to the standard full level. Although the data has not been lost, the retention margin is insufficient. If the first flag is maintained without intervention, the storage cell may experience charge decay below the critical value due to voltage instability before the next refresh judgment time, resulting in data loss. Therefore, after detecting this voltage range, a refresh operation needs to be performed on the current storage cell immediately to replenish the charge to the maximum level achievable under undervoltage conditions. After the refresh is completed, the flag bit should be maintained at the first flag. This secondary refresh enhances the data retention margin and improves data reliability in harsh power supply environments, even when the supply voltage is low but still operable.

[0128] S513: If the power supply voltage is lower than or equal to the second preset voltage threshold, the refresh flag of the current storage cell is modified to the second flag, and a refresh failure message is issued.

[0129] If the power supply voltage is lower than or equal to the second preset voltage threshold, it means that the power supply voltage is seriously insufficient, the refresh operation cannot be reliably completed and the data may be lost at any time. Therefore, the refresh flag of the current storage unit is modified to the second flag, and a refresh failure prompt message containing the address of the storage unit and the voltage abnormality type is sent to the processor or system management unit. The system management unit can then initiate emergency handling measures such as frequency reduction, voltage reduction recovery or data migration based on the prompt message to prevent system crash or calculation errors due to data loss.

[0130] Here, the first preset voltage threshold is greater than the second preset voltage threshold.

[0131] In practical applications, the first preset voltage threshold and the second preset voltage threshold can be set according to the data retention voltage characteristic curve in the DRAM's electrical datasheet. The first preset voltage threshold is set to 90% of the nominal operating voltage (e.g., 1.62V for a nominal voltage of 1.8V), and the second preset voltage threshold is set to the minimum critical voltage for reliable data retention (e.g., 1.35V).

[0132] Thus, this embodiment of the application completes a comprehensive adaptive refresh control process through the coordinated operation of multiple stages, including refresh flag management, refresh enable switch control, distributed judgment timing configuration, dynamic update of read / write hits, priority processing of read / write requests, and graded feedback compensation of power supply voltage. The above steps can be flexibly combined or selectively executed according to the actual application scenario. For example, in a system with stable power supply, the voltage detection and compensation steps can be omitted to simplify the control logic, while in scenarios with high energy efficiency requirements, the access frequency monitoring and automatic enable switch configuration functions can be emphasized. Those skilled in the art, based on an understanding of the core ideas of this application, can delete, combine, or adjust the order of some steps in the above embodiments according to the specific characteristics of the DRAM chip, system power consumption budget, and performance requirements; all such modifications and adjustments fall within the protection scope of this application.

[0133] Based on the same inventive concept, embodiments of this application also provide a refresh control device for a dynamic random access memory.

[0134] This device is applied to DRAM, which includes multiple memory cells. Each memory cell is configured with a refresh flag bit. When the refresh flag bit has a first identifier, it indicates that the corresponding memory cell should not be refreshed. When the refresh flag bit has a second identifier, it indicates that the corresponding memory cell should be refreshed. Multiple memory cells correspond to multiple refresh judgment times within the global refresh cycle. Each memory cell reaches a refresh judgment time once every target cycle. The target cycle is less than the global refresh cycle.

[0135] Figure 7 This is a schematic diagram of the structure of the refresh control device for the dynamic random access memory in the embodiments of this application. Figure 1 See Figure 7 As shown, the device may include: The acquisition module 71 is used to acquire the refresh flag of the current storage unit when any storage unit reaches its own refresh judgment time in response to the fulfillment of the refresh pre-control conditions.

[0136] Modify module 72 to skip refreshing the current storage unit if the obtained identifier is the first identifier, and modify the refresh flag of the current storage unit to the second identifier.

[0137] The refresh module 73 is used to refresh the current storage unit if the obtained identifier is the second identifier, and modify the identifier of the refresh flag bit of the current storage unit to the first identifier.

[0138] Specifically, if a read operation or write operation hits any storage cell between two adjacent refresh judgment times, the refresh flag of any storage cell is modified to the first flag.

[0139] Furthermore, as a response to Figure 7 In a refinement and extension of the illustrated device, this application embodiment also provides a refresh control device for a dynamic random access memory.

[0140] Each storage unit is also equipped with a refresh enable switch. When the refresh enable switch is in the first state, it indicates that the corresponding storage unit stores data; when the refresh enable switch is in the second state, it indicates that the corresponding storage unit does not store data. Meeting the refresh pre-control conditions includes the refresh enable switch being in the first state and the storage unit's access frequency exceeding a preset threshold within a preset historical period. The target period is half of the global refresh period.

[0141] Figure 8 This is a schematic diagram of the structure of the refresh control device for the dynamic random access memory in the embodiments of this application. Figure 2 See Figure 8 As shown, the device may include: Configuration module 81 is used to divide the global refresh cycle into a first half cycle and a second half cycle; in the first half cycle, a refresh judgment time is set for each storage unit; in the second half cycle, a refresh judgment time is set for each storage unit.

[0142] Each storage unit's refresh judgment time is evenly distributed in the first half of the cycle, and also evenly distributed in the second half of the cycle. Alternatively, configuration module 81 is specifically used to obtain historical access information for each storage unit within a preset historical duration, including access frequency and / or the most recent access time; determine the data activity level of each storage unit based on the historical access information; and configure the refresh judgment time for each storage unit in the first half of the cycle based on the data activity level, wherein the higher the data activity level, the closer the refresh judgment time of the corresponding storage unit is to the end of the first half of the cycle, and the smaller the time interval between the refresh judgment times of adjacent storage units.

[0143] The preprocessing module 82 is used to skip refreshing the corresponding storage unit in response to the failure to meet the refresh pre-control conditions, wherein the failure to meet the refresh pre-control conditions includes the refresh enable switch being in the second state.

[0144] The preprocessing module 82 is also used to skip refreshing the corresponding storage unit in response to the failure to meet the refresh pre-control conditions, wherein the failure to meet the refresh pre-control conditions includes the storage unit having an access frequency of less than or equal to a preset threshold within a preset historical period.

[0145] The preprocessing module 82 is also used to process read / write requests that are currently stored in the current storage unit when any storage unit reaches its own refresh judgment time, and after the read / write request is processed, modify the refresh flag of the current storage unit to the first flag, so as to wait for the next refresh judgment time of the current storage unit, and then enter the acquisition module 83.

[0146] The acquisition module 83 is used to acquire the refresh flag of the current storage unit in response to the absence of a pending read / write request in the current storage unit.

[0147] Modify module 84 to skip refreshing the current storage unit if the obtained identifier is the first identifier, and modify the refresh flag of the current storage unit to the second identifier.

[0148] The refresh module 85 is used to refresh the current storage unit if the obtained identifier is the second identifier, and modify the identifier of the refresh flag bit of the current storage unit to the first identifier.

[0149] The compensation module 86 is used to detect the power supply voltage corresponding to the current storage unit; if the power supply voltage is higher than or equal to the first preset voltage threshold, the refresh flag of the current storage unit is kept as the first flag; if the power supply voltage is lower than the first preset voltage threshold but higher than the second preset voltage threshold, the current storage unit is refreshed again, and the refresh flag of the current storage unit is kept as the first flag after the refresh is completed, wherein the first preset voltage threshold is greater than the second preset voltage threshold; if the power supply voltage is lower than or equal to the second preset voltage threshold, the refresh flag of the current storage unit is modified to the second flag, and a refresh failure prompt message is issued.

[0150] It should be noted that the description of the above device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0151] Based on the same inventive concept, embodiments of this application also provide a dynamic random access memory.

[0152] Figure 9 This is a schematic diagram of the structure of the dynamic random access memory in the embodiments of this application. Figure 3 See Figure 9 As shown, the dynamic random access memory may include a memory body 91 and a refresh control circuit 92. The memory body 91 includes multiple memory cells, each memory cell being configured with a refresh flag bit. When the refresh flag bit has a first identifier, it indicates that the corresponding memory cell should not be refreshed. When the refresh flag bit has a second identifier, it indicates that the corresponding memory cell should be refreshed. The multiple memory cells correspond to multiple refresh judgment times within the global refresh cycle. Each memory cell reaches a refresh judgment time every target cycle. The target cycle is less than the global refresh cycle. The refresh control circuit 92 is used to execute the method in the aforementioned embodiment.

[0153] It should be noted that the description of the above dynamic random access memory embodiments is similar to the description of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the dynamic random access memory embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0154] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed, implements the methods described in the foregoing embodiments.

[0155] It should be noted that the description of the above computer-readable storage medium embodiments is similar to the description of the above method embodiments, and has similar beneficial effects. For technical details not disclosed in the computer-readable storage medium embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0156] Based on the same inventive concept, this application also provides a computer program product. The computer program product includes a computer program, which, when executed, implements the methods described in the foregoing embodiments.

[0157] It should be noted that the descriptions of the above computer program product embodiments are similar to those of the above method embodiments, and have similar beneficial effects. For technical details not disclosed in the computer program product embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0158] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A refresh control method of a dynamic random access memory, characterized by, The method is applied to a dynamic random access memory (DRAM), which includes multiple memory cells. Each memory cell is configured with a refresh flag. When the refresh flag has a first identifier, it indicates that the corresponding memory cell should not be refreshed. When the refresh flag has a second identifier, it indicates that the corresponding memory cell should be refreshed. Multiple memory cells correspond to multiple refresh judgment times within a global refresh cycle. Each memory cell reaches a refresh judgment time every target cycle, where the target cycle is less than the global refresh cycle. The method includes: In response to the fulfillment of the refresh pre-control conditions, when any storage cell reaches its own refresh judgment time, the refresh flag bit of the current storage cell is obtained; If the obtained identifier is the first identifier, then skip refreshing the current storage unit and change the identifier of the refresh flag bit of the current storage unit to the second identifier; If the obtained identifier is the second identifier, then refresh the current storage unit and change the identifier of the refresh flag bit of the current storage unit to the first identifier; Specifically, if a read operation or write operation hits any storage cell between two adjacent refresh judgment times, the refresh flag of any storage cell is modified to the first flag.

2. The method of claim 1, wherein, Each storage cell is also configured with a refresh enable switch. When the refresh enable switch is in a first state, it indicates that the corresponding storage cell stores data. When the refresh enable switch is in a second state, it indicates that the corresponding storage cell does not store data. The condition for satisfying the refresh pre-control includes the refresh enable switch being in the first state. The method further includes: In response to the failure to meet the refresh pre-control conditions, the corresponding memory cell is skipped from being refreshed, wherein the failure to meet the refresh pre-control conditions includes the refresh enable switch being in the second state.

3. The method of claim 1, wherein, The conditions for satisfying the refresh pre-control criteria include that the access frequency of the storage unit within a preset historical period is higher than a preset threshold; the method further includes: In response to the failure to meet the refresh pre-control conditions, the corresponding storage unit is skipped from being refreshed. The failure to meet the refresh pre-control conditions includes the storage unit having an access frequency of less than or equal to a preset threshold within a preset historical period.

4. The method of claim 1, wherein, The method of obtaining the identifier of the refresh flag bit of the current storage unit includes: In response to the fact that there are no pending read / write requests in the current storage cell, obtain the refresh flag of the current storage cell; The method further includes: In response to the pending read / write request stored in the current storage unit, the read / write request is processed, and after the read / write request is processed, the refresh flag of the current storage unit is modified to the first flag to await the next refresh judgment time of the current storage unit.

5. The method of claim 1, wherein, The target period is half of the global refresh period; before any storage unit reaches its own refresh determination time, the method further includes: The global refresh cycle is divided into a first half cycle and a second half cycle; During the first half of the cycle, a separate refresh judgment time is set for each storage unit; During the latter half of the cycle, a separate refresh judgment time is set for each storage unit.

6. The method of claim 5, wherein, The refresh judgment time of each storage unit is evenly distributed in the first half of the cycle, and the refresh judgment time of each storage unit is evenly distributed in the second half of the cycle. or, During the first half of the cycle, each storage unit is assigned its own refresh judgment time, including: Obtain historical access information for each storage unit within a preset historical time period, wherein the historical access information includes access frequency and / or the most recent access time; Based on the historical access information, determine the data activity level of each storage unit; Based on the data activity level, each storage unit is configured with a refresh judgment time in the first half of the cycle. The higher the data activity level, the closer the refresh judgment time of the corresponding storage unit is to the end of the first half of the cycle, and the smaller the time interval between the refresh judgment time of the storage unit and the adjacent storage unit.

7. The method according to any one of claims 1 to 6, characterized in that, After modifying the refresh flag of the current storage unit to the first flag, the method further includes: Detect the power supply voltage corresponding to the current storage unit; If the power supply voltage is higher than or equal to the first preset voltage threshold, the refresh flag of the current storage cell will be kept as the first flag. If the power supply voltage is lower than the first preset voltage threshold and higher than the second preset voltage threshold, the current storage unit is refreshed again, and the refresh flag of the current storage unit is kept as the first flag after the refresh is completed, wherein the first preset voltage threshold is greater than the second preset voltage threshold. If the power supply voltage is lower than or equal to the second preset voltage threshold, the refresh flag of the current storage cell will be changed to the second flag, and a refresh failure message will be issued.

8. A refresh control apparatus of a dynamic random access memory, characterized by comprising: The device is applied to a dynamic random access memory (DRAM), which includes multiple memory cells. Each memory cell is configured with a refresh flag bit. When the refresh flag bit has a first identifier, it indicates that the corresponding memory cell is not refreshed. When the refresh flag bit has a second identifier, it indicates that the corresponding memory cell is refreshed. The multiple memory cells correspond to multiple refresh judgment times within a global refresh cycle. Each memory cell reaches a refresh judgment time every target cycle, where the target cycle is less than the global refresh cycle. The device includes: The acquisition module is used to acquire the refresh flag of the current storage unit when the refresh pre-control conditions are met. The modification module is used to skip refreshing the current storage unit and modify the refresh flag of the current storage unit to the second flag if the obtained identifier is the first identifier. The refresh module is used to refresh the current storage unit and change the refresh flag of the current storage unit to the first flag if the obtained identifier is the second identifier. Specifically, if a read operation or write operation hits any storage cell between two adjacent refresh judgment times, the refresh flag of any storage cell is modified to the first flag.

9. A dynamic random access memory, characterized by The method includes a memory body and a refresh control circuit. The memory body includes multiple memory cells, each memory cell being configured with a refresh flag bit. When the refresh flag bit has a first identifier, it indicates that the corresponding memory cell should not be refreshed. When the refresh flag bit has a second identifier, it indicates that the corresponding memory cell should be refreshed. The multiple memory cells correspond to multiple refresh judgment times within a global refresh cycle. Each memory cell reaches a refresh judgment time every target cycle, where the target cycle is less than the global refresh cycle. The refresh control circuit is used to execute the steps of the method as described in any one of claims 1 to 7.

10. A computer readable storage medium storing a computer program, characterized in that, When the computer program is executed, it implements the steps of the method as described in any one of claims 1 to 7.

11. A computer program product comprising a computer program, characterized in that, When the computer program is executed, it performs the steps of the method according to any one of claims 1 to 7.

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