Memory device and programming operations thereof

Abstract

In certain aspects, a memory device includes a memory cell and a peripheral circuit coupled to the memory cell. The peripheral circuit is configured to initiate a program operation on a selected memory cell of the memory cell, obtain a number of occurrences of one or more pauses during the program operation, and determine a program pulse limit for the program operation based on the number of occurrences of pauses.

Description

[0001] This application is a divisional application of Chinese patent application filed on August 27, 2021, with application number 202180002843.3 and entitled "Storage Device and Programming Operation Thereof". Technical Field

[0002] This disclosure relates to storage devices and methods of operation thereof. Background Technology

[0003] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash and NAND flash. Flash memory can perform various operations, such as reading, programming (writing), and erasing, to change the threshold voltage of each storage cell to a desired level. For NAND flash memory, erasing operations can be performed at the block level, and programming or reading operations can be performed at the page level. Summary of the Invention

[0004] In one aspect, a storage device includes: a storage cell; and peripheral circuitry coupled to the storage cell. The peripheral circuitry is configured to: initiate a programming operation on a selected storage cell from the storage cells; obtain the number of times one or more pauses occur during the programming operation; and determine a programming pulse limit for the programming operation based on the number of pauses.

[0005] In another aspect, a system includes: a storage device configured to store data; and a storage controller coupled to the memory. The storage device includes: storage cells; and peripheral circuitry coupled to the storage cells. The peripheral circuitry is configured to: initiate a programming operation on a selected storage cell from the storage cells; obtain a number of occurrences of one or more pauses during the programming operation; and determine a programming pulse limit for the programming operation based on the number of pauses. The storage controller is configured to: transmit a programming command to the peripheral circuitry to initiate the programming operation; and, after the programming command, transmit one or more pause commands to the peripheral circuitry to induce one or more pauses during the programming operation.

[0006] In another aspect, a method for operating a storage device is provided. The storage device includes storage cells. A programming operation is initiated on a selected storage cell within the storage cells. During the programming operation, one or more pauses are recorded. A programming pulse limit for the programming operation is determined based on the number of pauses. Attached Figure Description

[0007] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of this disclosure and, together with the description, serve to explain the principles of this disclosure and enable those skilled in the art to implement and use it.

[0008] Figure 1 A block diagram of a system having a storage device according to some aspects of this disclosure is shown.

[0009] Figure 2A A diagram of a memory card having a storage device according to some aspects of this disclosure is shown.

[0010] Figure 2B A diagram of a solid-state drive (SSD) having a storage device is shown according to some aspects of this disclosure.

[0011] Figure 3 A schematic diagram of a storage device including peripheral circuitry according to some aspects of this disclosure is shown.

[0012] Figure 4A and 4B Side and plan views of a cross-section of a memory cell array including NAND memory strings, according to some aspects of this disclosure, are shown respectively.

[0013] Figure 5 A block diagram of a memory device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0014] Figure 6 Schemes for pausing and resuming programming operations according to some aspects of this disclosure are shown.

[0015] Figure 7 A scheme for incremental step pulse programming (ISPP) in response to the pause and resumption of programming operations, according to some aspects of this disclosure, is shown.

[0016] Figure 8 A comparison is shown between normal ISPP programming operations and ISPP programming operations with programming pause and resume, according to some aspects of this disclosure.

[0017] Figure 9 Some aspects of this disclosure are shown. Figure 1 Detailed block diagram of the control logic unit and registers of the storage devices in the diagram.

[0018] Figure 10 A flowchart illustrating a scheme for obtaining the number of pauses during programming operations according to some aspects of this disclosure.

[0019] Figure 11 Some aspects of this disclosure are shown. Figure 1Another detailed block diagram of the control logic unit and registers of the memory devices in the diagram.

[0020] Figure 12 A flowchart of a method for operating a storage device according to some aspects of this disclosure is shown.

[0021] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0022] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Therefore, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other and in ways not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0023] Generally, terms can be understood at least in part based on their usage in the context. For example, the term "one or more" as used herein depends at least in part on the context and can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a," "an," or "described" can still be understood, at least in part on the context, to express either a singular or plural usage. Furthermore, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but may allow for the presence of additional factors that are not necessarily explicitly described, which still depends at least in part on the context.

[0024] NAND flash memory devices can perform programming (write) operations at the page / word line level, meaning that all memory cells coupled to the same select word line can be programmed simultaneously. Because each programming operation takes a relatively long time (e.g., hundreds of microseconds (μS)), and because it may involve multiple passes, each with multiple cycles of applying programming pulses and verifying pulses, NAND flash memory devices typically support interruptions during a programming operation on one page to pause the ongoing programming operation and switch to another operation (e.g., a read operation on another page). Once the other operation completes, the paused programming operation can be resumed to program the original page.

[0025] During pause periods (e.g., between the pause and resumption of programming operations), the channel of each select memory string (e.g., a NAND memory string) is floating. The release of the programming voltage applied to the select word line during programming of the select page, combined with the coupling capacitance between the select word line and the channel, can induce a negative coupling potential in the channel. As a result, holes may be attracted to the negative potential and accumulate in the channel and charge trapping layer of the select memory cell. The additional holes accumulated during the programming pause period can increase the threshold voltage of the select memory cell, making it easier for the select memory cell to pass verification when programming operations resume, even if the select memory cell may not have been programmed to the desired threshold voltage level. Furthermore, once programming operations resume, the negative potential in the channel of the select memory string disappears, and the accumulated holes can also be released, thereby lowering the threshold voltage. As a result, due to the aforementioned "overprogramming" problem associated with pause / resumption in programming operations, more faulty bits may occur during subsequent read operations of the programmed page.

[0026] To address the overprogramming problem, for programming operations using the ISPP scheme (which gradually increases the voltage of the programming pulse from the starting voltage to the target voltage based on step voltage (i.e., incremental voltage), the incremental voltage of the programming pulse immediately following each recovery of the programming operation (i.e., the first recovered programming pulse) needs to be reduced from the default incremental voltage of the normal programming pulse.

[0027] On the other hand, programming interference can occur to verified (i.e., programmed-disabled) memory cells (e.g., in NAND flash memory strings) while other memory cells sharing the same word line are still being programmed. In particular, if leakage or other faults exist on a particular word line, the number of programming pulses applied to that word line will increase, exacerbating programming interference to verified memory cells and causing their threshold voltage distribution to drift. Therefore, an upper limit (maximum value) needs to be set to limit the total number of programming pulses that can be applied to the word line in each programming operation to avoid threshold voltage drift due to programming interference.

[0028] However, for programming operations using the ISPP scheme, the reduced incremental voltage due to programming pauses / resumptions increases the number of programming pulses required to reach the target programming voltage. As a result, programming operations may be forced to terminate when the programming pulse limit is reached prematurely due to frequent programming pauses / resumptions. Conversely, blindly relaxing the programming pulse limit due to possible programming pauses / resumptions is also undesirable, as it increases the risk of threshold voltage drift due to programming interference.

[0029] To address one or more of the aforementioned problems, this disclosure proposes a scheme that dynamically adjusts the programming pulse limit based on the number of programming pauses / resumes in each programming operation. This balances the risk of threshold voltage drift due to programming interference with the need to fully complete the programming operation. By applying the dynamic programming pulse limit adjustment scheme disclosed herein, for normal programming operations not interrupted by pauses / resumes, the default programming pulse limit remains unchanged to prevent threshold voltage drift due to programming interference; and for programming operations interrupted by pauses / resumes, the default programming pulse limit can be relaxed to ensure correct completion of the programming operation. The default programming pulse limit can be preset based on various factors, such as being independent of pauses / resumes. In some embodiments, the default programming pulse limit is preset based on different programming operations, different pages, etc. Furthermore, in some embodiments, the number of programming pauses / resumes is also considered to dynamically and finely adjust the degree of relaxation of the programming pulse limit in each programming operation.

[0030] Figure 1 A block diagram of an exemplary system 100 having storage devices according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a storage system 102 having a storage controller 106 and one or more storage devices 104. The host 108 may be a processor of an electronic device such as a central processing unit (CPU) or a system-on-a-chip (SoC) such as an application processor (AP). The host 108 may be configured to send or receive data to or from the storage device 104. In addition to data, the host 108 may also send instructions to the storage system 102 in order to send or receive data to or from the storage device 104.

[0031] Storage device 104 can be any storage device disclosed herein. As detailed below, storage device 104, such as a NAND flash memory device, can support interrupt-triggered programming operation pauses. Storage device 104 may include, for example, memory cells in a NAND memory string. Consistent with the scope of this disclosure, storage device 104 can obtain the number of times one or more pauses occur during a programming operation and determine a programming pulse limit for the programming operation based on the number of pauses, thereby adjusting the maximum number of programming pulses allowed in an ongoing programming operation. As a result, the risk of threshold voltage drift due to programming interference can be balanced with the need to adequately complete the programming operation, and the performance of storage device 104 can be improved.

[0032] According to some embodiments, a storage controller 106 is coupled to a storage device 104 and a host 108 and is configured to control the storage device 104. The storage controller 106 can manage data stored in the storage device 104 and communicate with the host 108. In some embodiments, the storage controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media for electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the storage controller 106 is designed for high duty cycle environments, such as SSDs, or as embedded multimedia cards (eMMC) used as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for operation in enterprise storage arrays. The storage controller 106 can be configured to control the operation of the storage device 104, such as read, erase, and program operations. For example, based on instructions received from the host 108, the storage controller 106 can transmit various commands to the storage device 104, such as programming commands, read commands, erase commands, etc., to control the operation of the storage device 104. Consistent with the scope of this disclosure, in some embodiments, the storage controller 106 transmits programming commands to the storage device 104 to initiate a programming operation performed by the storage device 104. During the ongoing programming operation, an interrupt / pause may occur, for example, from the host 108, and the storage controller 106 may be configured to transmit one or more pause commands to the storage device 104 to cause one or more pauses during the programming operation. In some embodiments, once other operations (e.g., read operations) triggered by each pause have completed, the storage controller 106 may be further configured to transmit a resume command to the storage device 104 to resume the paused programming operation. In some embodiments, the storage controller 106 records the number of pauses that occur during the programming operation for each storage device 104 and transmits the occurrence count to the corresponding storage device 104.

[0033] Storage controller 106 can also be configured to manage various functions relating to data stored or to be stored in storage device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear-leveling, etc. In some embodiments, storage controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to storage device 104. Any other suitable functions may also be performed by storage controller 106, such as formatting storage device 104. Storage controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, storage controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0034] The storage controller 106 and one or more storage devices 104 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 102 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the storage controller 106 and a single storage device 104 can be integrated into the memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include components configured to connect the memory card 202 to a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, storage controller 106 and multiple storage devices 104 can be integrated into SSD 206. SSD 206 may also include components configured to connect SSD 206 to a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0035] Figure 3A schematic circuit diagram of an exemplary storage device 300, including peripheral circuitry 302, is shown according to some aspects of this disclosure. The storage device 300 may be... Figure 1 An example of memory device 104 is shown. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND flash memory cell array, wherein memory cells 306 are arranged in an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell (including a floating-gate transistor) or a charge-trapping type memory cell (including a charge-trapping transistor).

[0036] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, while a second storage state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in four or more storage states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed from an erase state to present one of three possible programming levels by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used in the erase state.

[0037] like Figure 3As shown, each NAND memory string 308 may further include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and DSG transistor 312 can be configured to activate and select the NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the drain of each NAND memory string 308 is coupled to a corresponding bit line 316 from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a DSG select voltage or DSG deselect voltage to the gate of the corresponding DSG transistor 312 via one or more DSG lines 313 and / or by applying an SSG select voltage or SSG deselect voltage to the gate of the corresponding SSG transistor 310 via one or more SSG lines 315.

[0038] like Figure 3 As shown, NAND memory strings 308 can be organized into multiple blocks 304, each block may have a common source (ACS) line 314, for example, coupled to the ACS. In some embodiments, each block 304 is the basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in the selected block 304, the source line 314 coupled to the selected block 304 and the unselected blocks 304 in the same plane as the selected block 304 can be biased with an erase voltage (Vers), such as a high positive voltage (e.g., 20V or higher). Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is the basic data unit for program and read operations. The size of a page 320, measured in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) and gate lines coupled to the control gates at each memory cell 306 on the corresponding page 320.

[0039] Figure 4A and 4BSide and plan views of a cross-section of an exemplary memory cell array 301 including NAND memory strings 308, according to some aspects of this disclosure, are shown respectively. Figure 4A As shown, the NAND memory string 308 may extend vertically through the memory stack 404 above the substrate 402. The substrate 402 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. Note that x , y and z The shaft includes Figure 4A The following further illustrates the spatial relationships of the components in the memory device. Substrate 402 includes... x - y Two transverse surfaces extending laterally in a plane: a top surface on the front side of the wafer on which a memory device can be formed; and a bottom surface on the back side opposite the front side of the wafer. z Axis perpendicular to x and y Axis. As used herein, whether a component (e.g., a layer or device) is "on another component (e.g., a layer or device) of the memory device", "above another component (e.g., a layer or device) of the memory device", or "below another component (e.g., a layer or device) of the memory device" is determined when substrate 402 is on z When positioned in the lowest plane of the storage device, in z Direction (orthogonal to) x - y The plane is defined relative to the substrate 402 of the storage device in the direction perpendicular to the plane. The same concepts used to describe spatial relationships apply throughout this disclosure.

[0040] The memory stack 404 may include staggered gate conductive layers 406 and gate-to-gate dielectric layers 408. The number of logarithms of the gate conductive layers 406 and gate-to-gate dielectric layers 408 in the memory stack 404 determines the number of memory cells 306 in the memory cell array 301. The gate conductive layers 406 may include conductive materials, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate conductive layer 406 includes a metal layer, such as a tungsten layer. In some embodiments, each gate conductive layer 406 includes a doped polysilicon layer. Each gate conductive layer 406 may include a control gate of a memory cell 306, a gate of a DSG transistor 312, or a gate of an SSG transistor 310, and may extend laterally as a DSG line 313 in the upper portion of the memory stack 404, an SSG line 315 in the lower portion of the memory stack 404, or a word line 318 between DSG lines 313 and SSG lines 315. It should be understood that, although Figure 4A The diagram shows one SSG line 315 and one DSG line 313, but the number of SSG lines 315 and DSG lines 313 (as well as the number of SSG transistors 310 and DSG transistors 312 coupled to SSG lines 315 and DSG lines 313 respectively) may vary in other examples.

[0041] like Figure 4A As shown, the NAND flash memory string 308 includes a channel structure 412 extending vertically through the memory stack 404. In some embodiments, the channel structure 412 includes channel openings filled with one or more semiconductor materials (e.g., as a semiconductor channel 420) and one or more dielectric materials (e.g., as a memory film 418). In some embodiments, the semiconductor channel 420 includes silicon, such as polycrystalline silicon. In some implementations, the memory film 418 is a composite dielectric layer including a tunneling layer 426, a storage layer 424 (also referred to as a "charge trapping layer"), and a barrier layer 422. The channel structure 412 may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel 420, tunneling layer 426, storage layer 424, and barrier layer 422 are arranged radially from the center of the pillar toward the outer surface in this order. The tunneling layer 426 may include silicon oxide, silicon oxynitride, or any combination thereof. Storage layer 424 may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. Barrier layer 422 may comprise silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, storage film 418 may comprise a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0042] like Figure 4AAs shown, according to some embodiments, a well 414 (e.g., a P-well and / or an N-well) is formed in substrate 402, and the source of the NAND memory string 308 is in contact with the well 414. For example, during an erase operation, the source line 314 may be coupled to the well 414 to apply an erase voltage to the well 414, i.e., the source of the NAND memory string 308. As described above, during and after the release of the programming voltage in response to an interruption during a programming operation, holes may be attracted from the well 414 (e.g., a P-well) and accumulate in the semiconductor channel 420 and the storage layer 424 due to the negative potential coupled in the semiconductor channel 420. In some embodiments, the NAND memory string 308 also includes a channel plug 416 at the drain end of the NAND memory string 308, for example, as part of the drain of the NAND memory string 308.

[0043] like Figure 4B As shown in the plan view, the NAND memory strings 308 of the memory cell array 301 can be arranged into blocks 304 via slot structures 430 (e.g., gate line slots (GLS)). The slot structures 430 electrically separate word lines 318 between adjacent blocks 304, allowing each block 304 to be individually controlled during read, program, and erase operations. In one example, each slot structure 430 can be arranged along... x Extending in a direction (e.g., word line direction), and multiple blocks 304 can extend along... y Orientation (e.g., bit line orientation). In some embodiments, each block 304 may be further divided into smaller regions (e.g., fingers 434) by a DSG cutout 432, which electrically separates the DSG lines 313 between adjacent fingers 434, so that the DSG lines 313 in different fingers 434 can be individually controlled during read and program operations.

[0044] like Figure 4A As shown in the side view, due to deep-hole etching processes, such as Deep-to-Ion Etching (DRIE), the channel structure 412 of the NAND memory string 308 may include a non-uniform lateral dimension (e.g., diameter) along the vertical direction. Because of this non-uniform lateral dimension distribution along the vertical direction of the channel structure 412, memory cells 306 coupled to word lines 318 (some of the gate conductive layers 406) at different locations (depths) can be associated with different channel lateral dimensions (e.g., diameters). Consequently, according to some embodiments, the programming speed of memory cells 306 coupled to word lines 318 at different locations also varies.

[0045] Return to reference Figure 3Peripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying and sensing voltage and / or current signals to and from each target (selected) memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may also be included. Figure 5 Additional peripheral circuitry not shown.

[0046] Page buffer / sensor amplifier 504 can be configured to read and program (write) data to and from memory cell array 301 based on control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into the selected memory cell 306 coupled to select word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 and amplify a small voltage swing to a recognizable logic level during a read operation, the low-power signal representing a data bit stored in memory cell 306. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0047] The line decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 according to control signals, and to select / deselect block 304 of the memory cell array 301, and to select / deselect word line 318 of block 304. The line decoder / word line driver 508 can be further configured to drive word line 318 using word line voltages generated from the voltage generator 510. In some embodiments, the line decoder / word line driver 508 can also select / deselect and drive SSG lines 315 and DSG lines 313, again using SSG and DSG voltages generated from the voltage generator 510.

[0048] Voltage generator 510 can be configured to be controlled by control logic unit 512 and generate various word line voltages (e.g., read voltage, programming voltage, pass voltage, verification voltage), SSG voltages (e.g., select / deselect voltage), DSG voltages (e.g., select / deselect voltage), bit line voltages (e.g., ground voltage) and source line voltages (e.g., ground voltage) to be supplied to memory cell array 301.

[0049] Control logic unit 512 can be coupled to each of the aforementioned peripheral circuits and configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit.

[0050] In some implementations, the control logic unit 512 may receive data from the memory controller (e.g., Figure 1 The control logic unit 512 issues programming commands from the memory controller 106 and sends control signals to various peripheral circuits, such as row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510, to initiate programming operations on the selected memory cell 306 coupled to the selected word line 318. In response to receiving a pause command from the memory controller during an ongoing programming operation, the control logic unit 512 can send control signals to various peripheral circuits, such as row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510, to pause the programming operation and initiate another operation (e.g., a read operation) triggered by the pause command. In some embodiments, register 514 is configured to store information about the paused programming operation, such as programming page, programming pass, programming / verification cycle used to pause the programming operation, etc., which is necessary to resume the paused programming operation. In some embodiments, the control logic unit 512 is configured to check the status of other operations from the status register of register 514. According to some implementations, in response to the completion of other operations (e.g., a read operation), the control logic unit 512 is also configured to retrieve information about a paused programming operation stored in register 514 and send control signals to various peripheral circuits such as row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510 to resume the paused read operation based on the information retrieved from register 514.

[0051] Consistent with the scope of this disclosure, during an ongoing programming operation, control logic unit 512 can obtain the number of occurrences of one or more pauses during the programming operation, and can then determine programming pulse limits for the programming operation based on the number of pause occurrences. In some embodiments, control logic unit 512 is configured to track the number of pause occurrences during the programming operation, and register 514 is configured to store the tracked number of pause occurrences. In some embodiments, control logic unit 512 is configured to obtain data from a storage controller (e.g., Figure 1 The memory controller 106 receives the number of pauses that occur during the programming operation. In response to the number of programming pulses in the programming operation reaching the programming pulse limit, the control logic unit 512 may send control signals to various peripheral circuits such as the row decoder / word line driver 508, the column decoder / bit line driver 506, and the voltage generator 510 to terminate the programming operation. Otherwise, according to some embodiments, the programming operation is complete when all selected memory cells 306 coupled to the selected word line 318 are verified (successfully programmed).

[0052] Interface 516 may be coupled to control logic unit 512 and act as a control buffer to retrieve data from the memory controller (e.g., Figure 1 The control commands (e.g., programming commands and pause commands) received by the storage controller 106 are buffered and relayed to the control logic unit 512, and status information (e.g., the number of pauses) received from the control logic unit 512 are buffered and relayed to the storage controller. Interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and acts as a data input / output (I / O) interface and data buffer to buffer and relay data to and from the storage cell array 301.

[0053] Figure 6 Schemes for pausing and resuming programming operations according to some aspects of this disclosure are shown. For example... Figure 6 As shown, in order to program the selection memory cell coupled to the selection word line, the programming operation sequentially includes one or more programming / verification cycles. N -1、 N , N+1, ...). During the programming operation, in any programming / verification cycle, a programming voltage (e.g., Vpgm_n-1, Vpgm_n, or Vpgm_n+1) is applied to the select word line to program the selected memory cell coupled to the select word line. Then, a verification voltage (e.g., Vvf_n-1, Vvf_n, or Vvf_n+1) is applied to check if the threshold voltage of each programmed memory cell reaches the verification voltage (i.e., verification / successful programming). If one or more memory cells (verification-failed cells) fail verification, i.e., their threshold voltage is below the verification voltage, a subsequent programming / verification cycle is applied to the verification-failed memory cells with an increased programming voltage.

[0054] When an interruption occurs during programming operations, such as when an instruction to perform a read operation is received from the host, a pause command is issued to suspend the programming operation. For example... Figure 6 As shown, when a pause command is issued simultaneously with the application of the programming voltage (Vpgm_n), the programming operation is paused once the programming voltage is completely released, and no verification voltage (Vvf_n) is applied during the same programming / verification cycle. The programming operation then enters a paused state (indicated by dashed lines) until another interrupt-triggered operation completes. Once the programming operation resumes, the corresponding verification voltage for the same programming / verification cycle is applied to complete this extended programming / verification cycle. Depending on some implementations, the duration of the paused state depends on the duration of the other interrupt-triggered operation.

[0055] In some implementations, programming voltages (e.g., Vpgm_n-1, Vpgm_n, and Vpgm_n+1) are applied according to an ISPP scheme (ISPP schemes are typically used in the (single or multiple) operation of memory devices such as NAND flash memory devices) to achieve fast programming performance under process and environmental variations while maintaining a tight programming cell threshold voltage profile. The ISPP scheme can program selected memory cells multiple times by progressively increasing the word line bias voltage (programming voltage) based on a step voltage. The magnitude of this "step" (e.g., the increase in the amplitude of each programming pulse relative to the immediately preceding programming pulse) is referred to herein as the increment voltage (also known as the pulse step height).

[0056] As described above, during the pause period, each selected storage string (e.g., Figure 4A The channel of the NAND flash memory string 308 is floating. The release of the programming voltage applied to the select word line during select page programming, combined with the coupling capacitance between the select word line and the channel, can induce a negative coupling potential in the channel. As a result, holes can be attracted by this negative potential, for example, from the P-well (e.g., Figure 4AThe holes accumulate in the channel and charge trapping layer of the selected memory cell (well 414). The additional holes accumulated during the programming pause period can increase the threshold voltage of the selected memory cell, making it easier for the selected memory cell to pass verification when programming resumes, even if the selected memory cell may not have been programmed to the desired threshold voltage level. Furthermore, once programming resumes, the negative potential in the channel of the selected memory string disappears, and the accumulated holes can be released, thereby lowering the threshold voltage. As a result, due to the aforementioned "overprogramming" problem associated with pause / resumption in programming operations, more faulty bits may occur during subsequent read operations of the programmed page.

[0057] Figure 7 An ISPP scheme for responding to the pause and resumption of programming operations according to some aspects of this disclosure is illustrated. This is to overcome the over-programming problem associated with pause / resumption in programming operations using the ISPP scheme, such as... Figure 7 As shown, according to some implementations, the default increment voltage (ISPP) is reduced for the corresponding programming pulse (e.g., Vpgm_n+1) immediately following each recovery of the programming operation. That is, the programming pulse can be divided into two types: a recovery programming (single or multiple) pulse (e.g., Vpgm_n+1) immediately following each recovery of the programming operation; and other programming (single or multiple) pulses not immediately following each recovery of the programming operation (e.g., Vpgm_n-1, Vpgm_n, and Vpgm_n+2). Similarly, the increment voltage used in the ISPP scheme can also be divided into two types: the recovery increment voltage for the recovery programming (single or multiple) pulses (e.g., the voltage difference between Vpgm_n and Vpgm_n+1); and the default increment voltage (ISPP) for other programming (single or multiple) pulses. In some implementations, the recovery increment voltage (ISPP-ΔISPP) is smaller than the default increment voltage (ISPP) by, for example, ΔISPP. Figure 7 As shown, by reducing the incremental voltage between the programming voltage before and after each pause, the undesirable increase in threshold voltage caused by pauses in the programming operation can be compensated.

[0058] Figure 8 A comparison is shown between normal ISPP programming operation and ISPP programming operation with programming pause and resume, according to some aspects of this disclosure. According to some embodiments, in normal ISPP programming operation without any programming pause (e.g., ...), ... Figure 8As shown on the left), the voltage of the programming pulse gradually increases from the starting programming voltage (Vpgm_start) to the target programming voltage (Vpgm_target) with a default increment voltage (ISPP) between two adjacent programming pulses. According to some implementations, after reaching the target voltage, if at least one selected memory cell remains unverified (i.e., fails verification), programming (single or multiple) pulses are continuously applied at the target voltage. On the other hand, a preset programming pulse limit (Max Prog Pulse) can limit the total number of programming pulses in an ongoing programming operation to manage the risk of threshold voltage drift due to programming interference, as described in detail above. For example, for an ISPP scheme with a starting voltage of 10V, a target voltage of 20V, and a default increment voltage of 1V, a normal programming operation might require 11 programming pulses (including both 10V and 20V programming pulses) to reach the target voltage. If the default programming pulse limit is set to 20, the normal programming operation in this example might still have up to 9 20V programming voltages before termination.

[0059] Conversely, the recovery increment voltage used by an ISPP programming operation with programming pauses and resumes may result in more programming pulses being used to achieve the same target programming voltage because the recovery increment voltage is smaller than the default increment voltage. According to some implementations, the number of additional programming pulses is related to the number of pauses that occur during the programming operation. For example, the more programming pauses and resumes occur during the programming operation, the more programming pulses may be required to achieve the same target programming voltage. The increased number of programming pulses required to reach the programming target voltage makes it easier to reach the same default programming pulse limit, thereby reducing the number of programming pulses allowed at the target programming voltage under that limit. As a result, the chance of the programming operation terminating prematurely (with insufficient opportunity to attempt programming all selected cells) may increase under the same default programming pulse limit.

[0060] Taking an extreme case in programming operations as an example, where the programming operation pauses and resumes (S / R) after each programming pulse (e.g.) Figure 8(As shown on the right), the recovery increment voltage (ISPP – ΔISPP) essentially replaces the default increment voltage used for each programming pulse. For example, for the same ISPP scheme with a starting voltage of 10V, a target voltage of 20V, and a recovery increment voltage of 0.5V per programming pulse, it might require 21 programming pulses (including the 10V and 20V programming pulses) to reach the same target voltage. If the default programming pulse limit is still set to 20, the programming operation in this example could even terminate before reaching the target programming voltage. On the other hand, if the default programming pulse limit is relaxed (e.g., increased to 25) to accommodate programming operations with programming pauses and resumes, the relaxed programming pulse limit may not be suitable for normal programming operations, and the risk of threshold voltage drift due to programming interference in normal programming operations may increase.

[0061] Consistent with the scope of this disclosure, instead of using the same default programming pulse limit for all programming operations, the programming pulse limit can be dynamically adjusted for different programming operations based on the number of pauses, thereby balancing the risk of threshold voltage drift due to programming interference with the need to fully complete the programming operation. Various schemes for dynamic programming pulse limit adjustment adapted to programming pauses and resumptions are described in detail below. These schemes can be derived from the above... Figure 3 , 4A The storage device 300 described in 4B and 5 is implemented.

[0062] like Figure 3 , 4A As shown in Figure 5, the control logic unit 512 of the peripheral circuitry 302 can be configured to initiate a programming operation on the selected memory cell 306 of the NAND flash memory string 308. In some embodiments, the control logic unit 512 receives a programming command from a memory controller (e.g., memory controller 106) via interface 516 and, in response, sends control signals to at least the row decoder / word line driver 508, the column decoder / bit line driver 506, and the voltage generator 510 to initiate a programming operation on the selected memory cell 306 coupled to the select word line 318. Depending on the number of states to be programmed (i.e., the number of bits in each memory cell 306, such as SLC, MLC, TLC, QLC, etc.), one or more programming passes can be performed. Figure 7As shown, in each programming pass, one or more programming / verification cycles (e.g., N-1, N, N+1, N+2, ...) can be sequentially included in the programming operation. During the programming operation, in any programming / verification cycle, a programming voltage (i.e., a voltage pulse signal including one or more programming pulses, e.g., Vpgm_n-1, Vpgm_n, Vpgm_n+1, and Vpgm_n+2) is applied to the select word line 318 via the word line driver 508 to program the select memory cell 306 coupled to the select word line 318.

[0063] Back Figure 3 , 4A And 5, the control logic unit 512 of the peripheral circuit 302 can also be configured to, during some programming operations (not in all programming operations, such as normal programming operations without pauses), from, for example, a memory controller (e.g., Figure 1 The storage controller 106 receives one or more pause commands. According to some implementations, the pause command is issued by the storage controller when an interrupt occurs. The interrupt can be from the host (e.g., ...). Figure 1 The host (108) in the memory module 300 needs to interrupt the ongoing programming operation being performed by the memory device 300 in order to be able to process any requests for events in a timely manner. For example, it may be necessary to perform a read operation on page 320 of the memory cell array 301 just before the currently executing programming operation completes. It should be understood that any suitable interrupt event can trigger the memory controller to transmit a pause command to the control logic unit 512 of the peripheral circuitry 302 to pause the ongoing programming operation so that another operation, such as a read operation, can be performed first. In some embodiments, the interrupt occurs when a programming pulse is applied to the select word line 318. It should also be understood that the interrupt (and the reception of the pause command) can occur in any programming / verification cycle (including the first cycle, the last cycle, or any intermediate cycle) or in a single programming / verification cycle. It should also be understood that the number of interrupt events and the number of pause commands generated can vary during different programming operations, for example from 0 (i.e., normal programming operation) to the same number as the number of programming pulses (e.g., in the case of a normal programming operation). Figure 8 middle).

[0064] In response to receiving a pause command, peripheral circuitry 302 can be configured to pause the ongoing programming operation. In some embodiments, control logic unit 512 is configured to store information about the paused programming operation in register 514. This information includes, for example, the programming page, programming success, and the programming / verification cycle used to pause the programming operation; such information is necessary to resume the paused programming operation. Control logic unit 512 can then send control signals to other peripheral circuitry 302 to perform other operations triggered by the received interrupt command, such as to row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510 to perform a read operation on another page 320 of memory cell array 301. The corresponding programming page of memory device 300 can then enter a programming pause state. In response to the completion of other operations triggered by the interrupt, peripheral circuitry 302 can be configured to resume the paused programming operation. In some implementations, the control logic unit 512 is also configured to retrieve information about a suspended programming operation stored in register 514, and based on the information retrieved from register 514, send control signals to at least the row decoder / word line driver 508, the column decoder / bit line driver 506, and the voltage generator 510 to resume the suspended programming operation.

[0065] In some implementations, the ISPP scheme is applied to the programming operation, causing the line decoder / word line driver 508 to apply one or more programming pulses with incremental voltages to the select word line 318. Depending on whether a programming pause occurs during the programming operation, the incremental voltage between adjacent programming pulses may include: a default incremental voltage only (ISPP) (not shown); or a default incremental voltage (e.g., Figure 7 Between Vpgm_n and Vpgm_n-1 and between Vpgm_n+2 and Vpgm_n+1) and the recovery increment voltage (ISPP-ΔISPP, e.g., less than the default increment voltage) Figure 7 (between Vpgm_n+1 and Vpgm_n).

[0066] like Figure 3 , 4A As shown in Figure 5, the control logic unit 512 of the peripheral circuit 302 can be further configured to obtain the number of times one or more pauses occur during the programming operation (also referred to herein as the number of pauses or pause occurrences). According to some aspects of this disclosure, such as Figure 9 As shown, the control logic unit 512, in conjunction with register 514 within the storage device 300, tracks the number of pauses that occur during each programming operation. For example... Figure 9As shown, the control logic unit 512 may include a pause / resume control unit 900, a maximum pulse counting unit 902, and a programming control unit. Each unit of the control logic unit 512 described herein may be: a software module and / or firmware module running on a processor, such as a microcontroller unit (MCU) as part of the control logic unit 512; or a hardware module of a finite state machine (FSM), such as an integrated circuit (IC, e.g., an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), etc.); or a combination of software modules, firmware modules, and hardware modules. Register 514 may include two status registers—a programmable pause track (PST) register 906 and a maximum pulse register 908.

[0067] In some implementations, the pause / resume control unit 900 is configured to receive one or more pause commands (CMDs) from the storage controller 106 during some programming operations. Since each pause command can cause a corresponding programming pause and resume, the pause / resume control unit 900 of the control logic unit 512 can track the number of pauses that occur and store that number in the PST register 906. Figure 10 As shown, after the programming operation begins in operation 1002, the pause / resume control unit 900 can first check in operation 1004 whether the programming operation will complete (e.g., when all selected memory units 306 have passed verification). If the answer is "no" (the programming operation will not complete now), the pause / resume control unit 900 can proceed to operation 1006 to check whether a programming pause has occurred (e.g., when a pause command is received). If the answer is "yes" (a programming pause has occurred), in operation 1008, the pause / resume control unit 900 can update the number of pauses recorded in the PST register 906 (e.g., by incrementing PST by 1). If the answer is "no" (no programming pause has occurred) or after updating the number of pauses, the pause / resume control unit 900 can return to operation 1004 to check whether the programming operation will now complete. If the answer is "yes" (the programming operation will now complete), the programming operation ends in operation 1010, and the number of pauses recorded in the PST register 906 can be returned to 0 for the next programming operation. It should be understood that during a normal programming operation without any pauses, the number of pauses stored in the PST register 906 can remain at 0. If the answer is still "no" (the programming operation will not be completed yet), the pause / resume control unit 900 can repeat operation 1006 as described above. That is, as long as the current programming operation has not been completed, the pause / resume control unit 900 can continuously track the number of pauses and update the number in the PST register 906.

[0068] According to some aspects of this disclosure, such as Figure 11 As shown, the control logic unit 512 does not use register 514 within the storage device 300 to track the number of pauses during each programming operation; instead, it receives the number of pauses from the storage controller 106. Figure 11 As shown, similar to Figure 9 The control logic unit 512 may also include a pause / resume control unit 900, a maximum pulse counting unit 902, and a programming control unit 904. Register 514 may still include a maximum pulse register 908, but not the PST register 906 (e.g., Figure 9 (As shown).

[0069] In some implementations, in addition to one or more pause commands (CMDs), the pause / resume control unit 900 also receives the number of pause occurrences (PST) from the storage controller 106 during some programming operations. That is, the storage controller 106 may record the number of pause occurrences (e.g., based on the number of pause commands sent to the control logic units 512 of each storage device 300 during the current programming operation) and transmit the number of pause occurrences to the pause / resume control unit 900. In some implementations, the number of pause occurrences is transmitted along with the transmission of each pause command. That is, whenever a new pause command is received, the number of pause occurrences received by the pause / resume control unit 900 from the storage controller 106 is updated. It should be understood that whether the number of pause occurrences is tracked internally (e.g., within the storage device 300) or externally (e.g., via the storage controller 106), the number of pause occurrences can be dynamically updated during each programming operation as the number of programming pauses increases.

[0070] like Figure 3 , 4A As shown in Figure 5, the control logic unit 512 of the peripheral circuit 302 can be further configured to determine the programming pulse limit of the ongoing programming operation based on the number of pauses. In some embodiments, the control logic unit 512 is configured to calculate the programming pulse limit based on a default programming pulse limit, a weight, and the number of pauses. The maximum pulse counting unit 902 of the control logic unit 512 can be configured to count pulses from... Figure 9 The PST register 906 shown retrieves the number of pauses (PST), or directly through, as shown in the example... Figure 10 The pause / resume control unit 900 shown receives the number of pause occurrences (PST) from the storage controller 106. Nevertheless, the maximum pulse counting unit 902 can be configured to, based on the received number of pause occurrences (PST), a weight ( wThe programmable pulse limit (program_max_pulse_count) is calculated using the default programmable pulse limit (program_max_pulse_count_def), also known as the factor.

[0071] In some implementations, the maximum pulse counting unit 902 relaxes (e.g., increases) the programming pulse limit of a programming operation to a degree related to the number of pauses occurring in the same programming operation. For example, the more pauses occur, the greater the relaxation that the maximum pulse counting unit 902 can calculate. In one example, the relaxation of the programming pulse limit is proportional to the number of pauses. In some implementations, weights can be pre-set (i.e., preset) to define a linear proportional relationship between the number of pauses and the relaxation. For example, the maximum pulse counting unit 902 can calculate a weighted number of pauses, representing the relaxation, based on the weights and the number of pauses. The maximum pulse counting unit 902 can then adjust the default programming pulse limit based on the weighted number of pauses, for example, according to the following Equation 1: program_max_pulse_count=program_max_pulse_count_def+ w ×PST (1).

[0072] Weights can be set based on various factors or any combination thereof. w In some implementations, the difference between the recovery increment voltage and the default increment voltage is used (e.g., Figure 7 and 8 The weights are set using ΔISPP (as mentioned above). Figure 7 and 8 As described, the larger the difference between the recovery and default increment voltages, the more programming pulses may be required to achieve the same target programming voltage. Therefore, a larger difference between the recovery and default increment voltages allows for greater weighting of the programming pulse limits. In some implementations, weighting is set based on the position of the selected word line 318 within word line 318. (As described above regarding...) Figure 4AAs described, the location of the select word line 318 can affect the programming speed of the memory cells 306 coupled to the select word line 318 due to the non-uniform lateral dimensions (e.g., diameter) of the channel structure 412 of the NAND memory string 308 along the vertical direction. In one example, since the select word line 318 coupled to the memory cells 306 with slower programming speeds can more easily reach the programming pulse limit, the corresponding weight can be set larger to further relax the programming pulse limit. In some implementations, the weight is set based on the default programming pulse limit. In some cases, a relatively large margin may have been reserved when setting the default programming pulse limit, allowing the corresponding weight to be set relatively small because the programming pulse limit has already been relaxed by the default programming pulse limit.

[0073] It should be understood that, in some examples, weights can be set based on any other suitable factor or combination thereof. It should also be understood that, in some examples, a non-linear relationship between the relaxation level and the number of pauses can be applied to calculate the relaxation level and adjust the default programming pulse limit. It should also be understood that, in some examples, for adjustment, the relaxation level may not be directly added to the default programming pulse limit, but can be used as a weight for linearly adjusting the default programming pulse limit or as a factor for adjusting the default programming pulse limit in a non-linear manner. However, the obtained number of pauses can be used to adjust the default programming pulse limit to dynamically determine the programming pulse limit for each programming operation in any suitable manner. It should be understood that, since the number of pauses can be dynamically updated during each programming operation as the number of programming pauses increases, the programming pulse limit can also be dynamically updated during a programming operation as the number of programming pauses increases. On the other hand, for normal programming operations without any programming pauses, the programming pulse limit can remain at the default programming pulse limit, so that the risk of threshold voltage drift due to programming interference is not increased for normal operation.

[0074] like Figure 9 and 11 As shown, the maximum pulse counting unit 902 can be configured to store the calculated programming pulse limit in the maximum pulse register 908 and dynamically update the programming pulse limit when the number of programming pauses changes.

[0075] like Figure 3 , 4A As shown in Figure 5, the control logic unit 512 of the peripheral circuit 302 can also be configured to terminate the programming operation in response to the number of programming pulses in the programming operation reaching the programming pulse limit. Figure 9 and 11As shown, in some embodiments, the programming control unit 904 of the control logic unit 512 is configured to monitor the number of programming pulses applied to the select word line 318 by the line decoder / word line driver 508 during the current programming operation, and compare this number with a programming pulse limit stored in the maximum pulse register 908. According to some embodiments, in response to the number of programming pulses reaching the most recently updated programming pulse limit, the programming control unit 904 is configured to instruct peripheral circuitry 302, such as the line decoder / word line driver 508, to terminate the ongoing programming operation, even if the programming operation has not yet been completed (e.g., not all select memory units 306 have been successfully programmed). Conversely, in response to the number of programming pulses not yet reaching the most recently updated programming pulse limit, the programming control unit 904 may not instruct peripheral circuitry 302 to terminate the ongoing programming operation. Since the programming pulse limit is dynamically updated based on the number of programming pauses in the current programming operation, the termination of the ongoing programming operation attributable to the programming pulse limit can also be dynamically adjusted to accommodate the frequency of programming pauses occurring in the ongoing programming operation.

[0076] Figure 12 A flowchart of a method 1200 for operating a memory device according to some aspects of this disclosure is shown. The memory device can be any suitable memory device disclosed herein, such as memory device 300. Method 1200 can be implemented by peripheral circuitry 302, such as control logic unit 512, register 514, and line decoder / word line driver 508. It should be understood that the operations shown in method 1200 may not be exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 12 The different execution sequences are shown.

[0077] refer to Figure 12 Method 1200 begins with operation 1202, in which a programming command is received. For example, control logic unit 512 may receive a programming operation on a selected memory cell 306 (e.g., in NAND memory string 308) in the selection page 320 of memory cell array 301 from memory controller 106 via interface 516.

[0078] Method 1200 proceeds to operation 1204, such as... Figure 12As shown, a programming operation is initiated in response to receiving a programming command. For example, control logic unit 512 may send control signals to at least row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510 to initiate a programming operation on the selected memory cell 306 coupled to the selected word line 318. In some embodiments, word line driver 508 applies a series of programming pulses with incremental voltages (e.g., according to the ISPP scheme) to selected word line 318 to program the selected memory cell 306.

[0079] In some implementations, one or more pauses occur during the programming operation to temporarily suspend the programming operation. According to some implementations, a corresponding pause command is received during the programming operation to cause each pause. In some implementations, the pause command is received when a programming pulse is applied to the select word line. For example, during an ongoing programming operation, the control logic unit 512 may receive a pause command from the memory controller 106. The pause command may be issued by the memory controller 106 upon the occurrence of an interrupt. The interrupt may be any request from the host 108 requiring the ongoing programming operation to be paused in order to process events in a timely manner.

[0080] In some implementations, the programming operation is resumed in response to the completion of another operation triggered by the pause command. For example, in response to the completion of another operation, control logic unit 512 may retrieve information about the paused programming operation stored in register 514 and send control signals to row decoder / word line driver 508, column decoder / bit line driver 506, and voltage generator 510 to resume the paused programming operation based on the information retrieved from register 514. In one example, row decoder / word line driver 508 may apply a programming pulse immediately after resuming the programming operation with a recovery increment voltage. In some implementations, the recovery increment voltage of the programming pulse may be less than the default increment voltage of the programming pulse to address overprogramming issues caused by programming pauses and resumes.

[0081] Method 1200 proceeds to operation 1206, such as... Figure 12As shown, the number of pauses occurring during the programming operation is obtained. For example, control logic unit 512 may obtain the number of pauses occurring during the programming operation. In some embodiments, the number of pauses occurring during the programming operation is tracked and stored. For example, control logic unit 512 may track the number of pauses occurring during the programming operation, and register 514 (e.g., PST register 906) may store the tracked number of pauses occurring. In some embodiments, the number of pauses occurring during the programming operation is received. For example, storage controller 106 may record the number of pauses occurring during the programming operation (e.g., the same number as the number of pause commands sent by storage controller 106) and transmit the number of pauses occurring to control logic unit 512.

[0082] Method 1200 proceeds to operation 1208, such as... Figure 12 As shown, a programming pulse limit for programming operations is determined based on the number of pauses. For example, control logic unit 512 may determine a programming pulse limit (e.g., an upper limit / maximum value). In some implementations, the programming pulse limit is calculated based on a default programming pulse limit, weights, and the number of pauses. In some implementations, a weighted number of pauses is calculated based on weights and the number of pauses, and the default programming pulse limit is adjusted based on the weighted number of pauses. For example, control logic unit 512 may calculate the programming pulse limit based on a default programming pulse limit, weights, and the number of pauses. In one example, control logic unit 512 may calculate a weighted number of pauses based on weights and the number of pauses, and may adjust the default programming pulse limit based on the weighted number of pauses. Weights may be set based on various factors, such as the difference between the recovery increment voltage and the default increment voltage, the position of the selected word line in the word line, and / or the default programming pulse limit.

[0083] Method 1200 proceeds to operation 1210, such as... Figure 12As shown, the programming operation is terminated in response to the number of programming pulses in the programming operation reaching the programming pulse limit. For example, in response to the number of programming pulses in the programming operation reaching the programming pulse limit, the control logic unit 512 may send control signals to the row decoder / word line driver 508, the column decoder / bit line driver 506, and the voltage generator 510 to terminate the programming operation before it is completed (i.e., all selected memory cells 306 have been successfully programmed / verified). It should be understood that in some examples, the programming operation can be completed before the number of programming pulses in the programming operation reaches the programming pulse limit even if there are one or more pauses during the programming operation. It should also be understood that in some examples, the programming operation can be completed without any pauses. It should also be understood that in some examples, even without any pauses, the programming operation can be terminated before it is completed in response to the number of programming pulses in the programming operation reaching the programming pulse limit.

[0084] According to one aspect of this disclosure, a storage device includes: a storage cell; and peripheral circuitry coupled to the storage cell. The peripheral circuitry is configured to: initiate a programming operation on a selected storage cell from the storage cells; obtain a number of times one or more pauses occur during the programming operation; and determine a programming pulse limit for the programming operation based on the number of pauses.

[0085] In some embodiments, the peripheral circuitry is further configured to terminate the programming operation in response to the number of programming pulses in the programming operation reaching the programming pulse limit.

[0086] In some implementations, in order to determine the programming pulse limit, the peripheral circuitry includes a control logic unit configured to calculate the programming pulse limit based on a default programming pulse limit, a weight, and the number of pauses that occur.

[0087] In some implementations, in order to calculate the programming pulse limit, the control logic unit is configured to: calculate a weighted number of pauses based on the weights and the number of pauses; and adjust the default programming pulse limit based on the weighted number of pauses.

[0088] In some embodiments, the storage device further includes word lines coupling the peripheral circuitry to the memory cells. In some embodiments, the peripheral circuitry includes a word line driver coupled to a select word line in the word lines that is coupled to the selected memory cell, and the word line driver is configured to apply a programming pulse with an incremental voltage to the select word line. In some embodiments, the recovery incremental voltage of the programming pulse immediately following the recovery of the programming operation is less than the default incremental voltage of the programming pulse.

[0089] In some implementations, the weights are set based on the difference between the recovery increment voltage and the default increment voltage.

[0090] In some implementations, the weight is set based on the position of the selected word line among the word lines.

[0091] In some implementations, the weights are set based on the default programming impulse limit.

[0092] In some implementations, in order to obtain the number of pauses, the peripheral circuitry includes: a control logic unit configured to track the number of pauses during the programming operation; and a register coupled to the control logic unit and configured to store the tracked number of pauses.

[0093] In some implementations, in order to obtain the number of pauses, the peripheral circuitry includes a control logic unit configured to receive from the memory controller the number of pauses during the programming operation.

[0094] In some implementations, the storage unit is in a NAND flash memory string.

[0095] According to another aspect of this disclosure, a system includes: a storage device configured to store data; and a storage controller coupled to the memory. The storage device includes: storage cells; and peripheral circuitry coupled to the storage cells. The peripheral circuitry is configured to: initiate a programming operation on a selected storage cell from the storage cells; obtain a number of occurrences of one or more pauses during the programming operation; and determine a programming pulse limit for the programming operation based on the number of pauses. The storage controller is configured to: transmit a programming command to the peripheral circuitry to initiate the programming operation; and transmit one or more pause commands to the peripheral circuitry after the programming command to induce the one or more pauses during the programming operation.

[0096] In some implementations, the system includes an SSD or a memory card.

[0097] In some implementations, the storage controller is also configured to transmit the number of times the pause occurred during the programming operation to the peripheral circuitry.

[0098] In some embodiments, the storage device includes a 3D NAND storage device, and the storage cells are in a NAND storage string.

[0099] According to another aspect of this disclosure, a method for operating a storage device is provided. The storage device includes storage cells. A programming operation is initiated on a selected storage cell in the storage cells. During the programming operation, one or more pauses are recorded. A programming pulse limit for the programming operation is determined based on the number of pauses.

[0100] In some implementations, the programming operation is terminated in response to the number of programming pulses in the programming operation reaching the programming pulse limit.

[0101] In some implementations, the programming pulse limit is calculated based on a default programming pulse limit, a weight, and the number of pauses to determine the programming pulse limit.

[0102] In some implementations, in order to calculate the programming pulse limit, a weighted number of pauses is calculated based on the weights and the number of pauses, and the default programming pulse limit is adjusted based on the weighted number of pauses.

[0103] In some embodiments, the storage device further includes a select word line coupled to the select memory cell; and a programming pulse with an incremental voltage is applied to the select word line. In some embodiments, the recovery incremental voltage of the programming pulse immediately following the recovery of the programming operation is less than the default incremental voltage of the programming pulse.

[0104] In some implementations, the weights are set based on the difference between the recovery increment voltage and the default increment voltage.

[0105] In some implementations, the weight is set based on the position of the selected word line within the word line.

[0106] In some implementations, the weights are set based on the default programming impulse limit.

[0107] In some implementations, the programming voltage on the select word line is released, and an SSG voltage is applied to the SSG line at the same time as the programming voltage on the select word line is released.

[0108] In some implementations, in order to obtain the number of pauses that occur, the number of pauses that occur during the programming operation is tracked, and the tracked number of pauses is stored.

[0109] In some implementations, in order to obtain the number of times the pauses occurred, the number of times the pauses occurred during the programming operation is received.

[0110] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, it is intended that such adaptations and modifications be within the meaning and scope of equivalents of the disclosed embodiments.

[0111] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A storage device, comprising: Storage unit; Word lines are coupled to the memory cells; as well as Peripheral circuitry, coupled to the word line and configured as follows: During programming, a programming pulse is applied to the select word line; Obtain the number of pauses that occurred during the programming operation; as well as The programming pulse limit for the programming operation is determined based on the number of pauses that occur.

2. The storage device as claimed in claim 1, wherein, The peripheral circuit is also configured to: In response to the pause occurring 0 times, the programming pulse limit is determined to be a first quantity.

3. The storage device as claimed in claim 2, wherein, The peripheral circuit is also configured to: In response to the pause occurring more than 0 times, it is determined that the programming pulse limit is a second number greater than the first number.

4. The storage device as claimed in claim 1, wherein, The peripheral circuit is also configured to terminate the programming operation in response to the number of programming pulses in the programming operation reaching the programming pulse limit.

5. The storage device as claimed in claim 1 or 2, wherein, To determine the programming pulse limit, the peripheral circuitry is configured to calculate the programming pulse limit based on weights and the number of pauses that occur.

6. The storage device as claimed in claim 5, wherein, To calculate the programming pulse limit, the peripheral circuitry is configured as follows: The weighted number of pauses is calculated based on the weights and the number of pauses. as well as The programming pulse limit is determined based on the number of weighted occurrences of the pause.

7. The storage device as claimed in claim 5, wherein, The peripheral circuitry includes a word line driver coupled to the word line; The word line driver is configured to apply programming pulses with incremental voltages to the selected word line; as well as The recovery increment voltage of the programming pulse immediately following the recovery of the programming operation is less than the default increment voltage of the programming pulse.

8. The storage device of claim 7, wherein, The weight is related to the difference between the recovery increment voltage and the default increment voltage.

9. The storage device as claimed in claim 5, wherein, The weight is set based on the position of the selected character line in the character line.

10. The storage device according to any one of claims 1-9, wherein, To obtain the number of pauses, the peripheral circuitry includes: The control logic unit is configured to acquire the number of times the pause occurs during the programming operation; and A register, coupled to the control logic unit, is configured to store the number of times the pauses have occurred.

11. The storage device according to any one of claims 1-9, wherein, In order to obtain the number of pauses, the peripheral circuitry includes a control logic unit configured to receive the number of pauses during the programming operation from the memory controller.

12. The storage device according to any one of claims 1-10, wherein, The storage unit is located in a NAND flash memory string.

13. A system comprising: The storage device as described in claims 1-12; A controller, coupled to the storage device, is configured to control the storage device.

14. The system of claim 13, wherein, The controller is also configured to transmit the number of times the pause occurred during the programming operation to the peripheral circuitry.

15. A method for operating a storage device including storage cells, the method comprising: During programming, a programming pulse is applied to the select word line; Obtain the number of pauses that occurred during the programming operation; as well as The programming pulse limit for the programming operation is determined based on the number of pauses that occur.

16. The method of claim 15, further comprising: In response to the pause occurring 0 times, the programming pulse limit is determined to be a first quantity.

17. The method of claim 16, wherein, Also includes: In response to the pause occurring more than 0 times, it is determined that the programming pulse limit is a second number greater than the first number.

18. The method of claim 15, wherein, Also includes: The programming operation is terminated when the number of programming pulses in the programming operation reaches the programming pulse limit.

19. The method of claim 15, wherein, Also includes: The programming pulse limit is calculated based on the weight and the number of pauses.

20. The method of claim 19, wherein, Also includes: The weighted number of pauses is calculated based on the weights and the number of pauses. as well as The programming pulse limit is determined based on the number of weighted occurrences of the pause.

21. The method of claim 19, wherein, Also includes: The weight is set based on the position of the selected word line in the word line.

22. The method of claim 15, wherein, The weights are set based on the default programming impulse limit.

23. The method of claim 15, wherein, The number of times a pause occurs includes: Obtain the number of times the pause occurred during the programming operation; and The number of pauses tracked by the storage.

24. The method of claim 15, wherein, The number of pauses received includes the number of pauses received during the programming operation.

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