Semiconductor device and method of operating the same

Abstract

This disclosure provides a semiconductor device and its operating method. The semiconductor device includes: a first semiconductor structure including a memory array and multiple bit lines coupled to the memory array, the memory array including a first memory cell and a second memory cell; and a second semiconductor structure including peripheral circuitry. The peripheral circuitry is coupled to the memory array and configured to: receive a first command, the first command including first data and address information of the bit lines coupled to the first memory cell; the first command instructs the storage of the first data to the first memory cell; and in response to the first command, when at least a portion of the bit line address information in the address information of the bit lines coupled to the first memory cell is the same as the address information of a failed bit line among the multiple bit lines, the storage of the first data corresponding to the at least a portion of the bit line address information is stored in the second memory cell.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device and its operating method. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] In view of the above, this disclosure provides a semiconductor device and a method of operating the same.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, comprising: a first semiconductor structure including a memory array and a plurality of bit lines coupled to the memory array, the memory array including a first memory cell and a second memory cell; and a second semiconductor structure including peripheral circuitry; the peripheral circuitry being coupled to the memory array and configured to: receive a first command, the first command including first data and address information of the bit lines coupled to the first memory cell; the first command instructing the storage of the first data to be stored in the first memory cell; and in response to the first command, storing the data corresponding to the at least some bit line address information in the address information of the bit lines coupled to the first memory cell in the second memory cell when at least a portion of the bit line address information is the same as the address information of a failed bit line among the plurality of bit lines.

[0005] In some embodiments, the peripheral circuit is further configured to: store all of the first data in the second storage unit when all the address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line; store the second data corresponding to the partial bit line address information in the first data in the second storage unit when a portion of the address information of the bit lines coupled to the failed bit line is the same as the address information of the failed bit line; and store the remaining third data in the first data in the first storage unit.

[0006] In some embodiments, the peripheral circuitry is further configured to: receive a second command, the second command indicating that the first data should be read; and, in response to the second command, provide feedback the address information of the second memory cell coupling bit line, the second data, and the third data.

[0007] In some embodiments, the peripheral circuitry further includes an addressing register; the addressing register is configured to store the address information of the failed bit line, and the address information of the bit line coupled to the second storage cell.

[0008] In some embodiments, the peripheral circuitry further includes: a data path; the data path is coupled to the addressing register and configured to: transmit the first data in response to the first command; and transmit the address information of the second memory cell coupled bit line, the second data, and the third data in response to the second command.

[0009] In some embodiments, when the number of address information entries of the second storage cell coupled bit line includes multiple entries, the peripheral circuit further includes: a read / write control circuit; the read / write control circuit is located between the address register and the data path; the read / write control circuit is configured to: generate multiple write clock signals and multiple data write signals in response to the first command; and generate multiple read clock signals and multiple data read signals in response to the second command.

[0010] In some embodiments, the peripheral circuitry further includes: a data selection circuit; the data selection circuit is located between the data path and the read / write control circuit, and the other end of the data selection circuit is coupled to the memory array; the data selection circuit is configured to: sequentially store the second data in the second memory cell and store the third data in the first memory cell based on a plurality of write clock signals and a plurality of data write signals; and multiplex the address information of the second data, the third data, and the failed bit line onto the data path based on a plurality of read clock signals and a plurality of data read signals.

[0011] In some embodiments, the peripheral circuitry further includes a redundancy control circuit; the redundancy control circuit is located between the data selection circuit and the storage array, and the redundancy control circuit is configured to select the second data sequence to the transmission interface coupled to the second storage unit.

[0012] In some embodiments, the first semiconductor structure is bonded to the second semiconductor structure; the first semiconductor structure further includes a connection structure that runs through the memory array and is connected to the peripheral circuit; the connection structure is configured to transmit the first command and the second command.

[0013] In some embodiments, the peripheral circuit is further configured to: receive and respond to a third command to test the plurality of bit lines in order to obtain the address information of the failed bit line.

[0014] In some embodiments, the number of failed bit lines is less than or equal to the number of bit lines coupled to the second memory cell.

[0015] In some embodiments, the storage array includes a plurality of NAND storage cells; the semiconductor device includes a three-dimensional NAND type memory.

[0016] In a second aspect, embodiments of this disclosure provide a semiconductor device, comprising: a first semiconductor structure including a memory array and a plurality of bit lines coupled to the memory array, the memory array including a first memory cell and a second memory cell; a second semiconductor structure including peripheral circuitry coupled to the memory array; and a third semiconductor structure including a control circuit; the control circuitry being coupled to the peripheral circuitry; the control circuitry being configured to: send a first command, the first command including first data and address information of the bit lines coupled to the first memory cell; the first command instructing the storage of the first data to the first memory cell; the peripheral circuitry being configured to: receive and respond to the first command, when at least a portion of the bit line address information in the address information of the bit lines coupled to the first memory cell is the same as the address information of a failed bit line among the plurality of bit lines, store the data corresponding to the at least a portion of the bit line address information in the first data to the second memory cell.

[0017] In some embodiments, the peripheral circuit is specifically configured to: store all of the first data in the second storage unit when all the address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line; store the second data in the first data corresponding to the partial bit line address information in the second storage unit when a portion of the address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line; and store the remaining third data in the first data in the first storage unit.

[0018] In some embodiments, the control circuit is further configured to: send a fourth command, the fourth command instructing the address information of the failed bit line to be stored in the address register of the peripheral circuit; the peripheral circuit is further configured to: receive and respond to the fourth command, and store the address information of the failed bit line in the address register.

[0019] In some embodiments, the peripheral circuit is further configured to: store the address information of the second storage cell coupling bit line into the address register during the response to the first command.

[0020] In some embodiments, the control circuit is further configured to: send a second command; the second command instructs the acquisition of the first data; the peripheral circuit is further configured to: receive and respond to the second command; and feed back the address information of the second memory cell coupling bit line, the second data, and the third data to the control circuit.

[0021] In some embodiments, the control circuit is further configured to obtain the first data based on the address information of the second memory cell coupling bit line, the second data, and the third data.

[0022] In some embodiments, the control circuit is further configured to: send a third command, the third command instructing the testing of the plurality of bit lines; the peripheral circuit is further configured to: receive and respond to the third command, test the plurality of bit lines, and obtain the address information of the failed bit line.

[0023] Thirdly, embodiments of this disclosure provide an operation method for a semiconductor device, the operation method comprising: receiving a first command, the first command including first data and address information of bit lines coupled to a first memory cell in a memory array; the first command instructing the first data to be stored in the first memory cell; in response to the first command, when at least a portion of the bit line address information in the address information of the bit lines coupled to the first memory cell is the same as the address information of a faulty bit line among a plurality of bit lines in the memory array, storing the data in the first data corresponding to the at least a portion of the bit line address information in a second memory cell in the memory array; wherein the semiconductor device comprises: a first semiconductor structure including the memory array and a plurality of bit lines coupled to the memory array; and a second semiconductor structure including peripheral circuitry; the peripheral circuitry being coupled to the memory array.

[0024] In some embodiments, the method further includes: storing all of the first data in the second storage unit when all the address information of the first storage unit coupled bit lines is the same as the address information of the failed bit line; storing the second data in the first data corresponding to the partial bit line address information in the second storage unit when a portion of the address information of the first storage unit coupled bit lines is the same as the address information of the failed bit line; and storing the remaining third data in the first data in the first storage unit.

[0025] In some embodiments, the method further includes: receiving a second command, the second command instructing the reading of the first data; and responding to the second command by feeding back address information of the second storage cell coupling bit line, the second data, and the third data.

[0026] In some embodiments, the method further includes: storing the address information of the failed bit line and the address information of the second storage cell coupled bit line into the address register of the peripheral circuit.

[0027] In some embodiments, the method further includes: transmitting the first data through a data path in the peripheral circuit during the response to the first command; and transmitting the address information of the second memory cell coupling bit line, the second data, and the third data through the data path during the response to the second command.

[0028] In some embodiments, the method further includes: generating a plurality of write clock signals and a plurality of data write signals through a read / write control circuit in the peripheral circuit in response to the first command; and generating a plurality of read clock signals and a plurality of data read signals through the read / write control circuit in response to the second command.

[0029] In some embodiments, the method further includes: storing the second data in the second storage unit and storing the third data in the first storage unit sequentially through a data selection circuit in a peripheral circuit, based on a plurality of write clock signals and a plurality of data write signals; and multiplexing the address information of the second data, the third data and the failed bit line onto the data path through the data selection circuit, based on a plurality of read clock signals and a plurality of data read signals.

[0030] In some embodiments, the method further includes: using a redundant control circuit in the peripheral circuit to select the second data segment to the transmission interface coupled to the second storage unit.

[0031] In some embodiments, the second semiconductor structure further includes a connection structure that extends through the memory array and is connected to the peripheral circuitry; the method further includes transmitting the first command and the second command through the connection structure.

[0032] In some embodiments, the method further includes: receiving and responding to a third command, testing the plurality of bit lines, and obtaining address information of the failed bit lines.

[0033] In this embodiment, a memory array and multiple bit lines are provided in a first semiconductor structure. A first memory cell and a second memory cell are provided in the memory array. A peripheral circuit is provided in the second semiconductor structure and is coupled to the memory array. In this case, when the peripheral circuit receives a first command and instructs the storage of the first data in the first memory cell, it determines whether the bit line coupled to the first memory cell is a failed bit line. If a failed bit line is found in the bit line coupled to the first memory cell, the data corresponding to the failed bit line in the first data is transferred to the second memory cell. In this way, when a failed bit line is found in the bit line coupled to the first memory cell, a redundancy replacement mechanism can be used to transfer at least part of the data stored in the first memory cell to the second memory cell, thereby continuing to use the semiconductor structure with some failed bit lines, improving the utilization rate and final yield of the semiconductor device. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present disclosure;

[0035] Figure 2 A schematic diagram of a second semiconductor structure including peripheral circuitry provided in an embodiment of this disclosure;

[0036] Figure 3 A schematic cross-sectional view of a storage array including storage strings provided for an embodiment of this disclosure;

[0037] Figure 4 An exemplary peripheral circuit diagram provided for an embodiment of this disclosure;

[0038] Figure 5 This is a schematic diagram of the structure of a semiconductor device provided in another embodiment of the present disclosure;

[0039] Figure 6 for Figure 5 A schematic diagram of the corresponding three-dimensional structure of the semiconductor device;

[0040] Figure 7 This is a schematic flowchart of an operation method for a semiconductor device provided in an embodiment of the present disclosure;

[0041] Figure 8 A block diagram of data path multiplexing logic in a semiconductor device provided in an embodiment of this disclosure;

[0042] Figure 9 This is a schematic diagram of an exemplary electronic device having semiconductor devices according to an embodiment of the present disclosure;

[0043] Figure 10 This is a schematic diagram of an exemplary memory card having semiconductor devices according to an embodiment of the present disclosure;

[0044] Figure 11 This is a schematic diagram of an exemplary solid-state driver having a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0045] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0047] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0048] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0049] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0052] The semiconductor devices involved in the embodiments of this disclosure can be at least a part of the final device structure. Here, the final device may include, but is not limited to, NAND flash memory, vertical NAND flash memory, NOR flash memory, dynamic random access memory (DRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), phase change random access memory (PCRAM), resistive random access memory (RRAM), nano random access memory (NRAM), etc. For ease of understanding, the following description uses only NAND type memory as an example. However, it should be noted that the following description of NAND type memory is only used to illustrate this disclosure and is not intended to limit the scope of this disclosure.

[0053] It should be understood that in the classic von Neumann computing architecture, memory and processor are separate, and data is transferred between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement leads to significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. To address these bottlenecks, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions within memory and directly utilize memory for logical calculations, thereby reducing the amount and distance of data transfer between memory and processor, lowering power consumption while improving computational performance. This promises to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0054] In practical applications, memory may experience bit line failure rates during manufacturing processes. Redundancy replacement mechanisms can be used to replace failed bit lines with redundant ones, ensuring memory utilization. However, in a three-dimensional in-memory computing chip architecture, how to implement a redundant bit line replacement mechanism between the memory and the processor has become an urgent problem to be solved.

[0055] The following describes in detail, with reference to the accompanying drawings, the NAND flash memory, the in-memory computing chip with NAND flash memory, and how the in-memory computing chip with NAND flash memory implements the replacement of redundant bit lines according to the embodiments of this disclosure.

[0056] In the introduction Figure 1 Before illustrating the semiconductor device, we first define the various directions that may be used in the following description. The stacking direction of the first and second semiconductor structures in the semiconductor device is defined as the first direction (i.e., the Z-axis direction). A second direction (i.e., the X-axis direction) and a third direction (i.e., the Y-axis direction) intersect in a plane perpendicular to the Z-axis direction. In some embodiments, the X-axis, Y-axis, and Z-axis directions may be mutually perpendicular.

[0057] In a first aspect, embodiments of this disclosure provide a semiconductor device comprising: a first semiconductor structure including a memory array and a plurality of bit lines coupled to the memory array, the memory array including a first memory cell and a second memory cell; and a second semiconductor structure including peripheral circuitry; the peripheral circuitry being coupled to the memory array and configured to: receive a first command, the first command including first data and address information of the bit lines coupled to the first memory cell; the first command instructing the storage of the first data to the first memory cell; and, in response to the first command, when at least a portion of the bit line address information in the address information of the bit lines coupled to the first memory cell is identical to the address information of a failed bit line among the plurality of bit lines, storing the data corresponding to the at least a portion of the bit line address information in the first data to the second memory cell. Thus, when a failed bit line exists among the bit lines coupled to the first memory cell, a redundancy replacement mechanism can be used to transfer at least a portion of the data stored in the first memory cell to the second memory cell, thereby continuing to use the semiconductor structure with partially failed bit lines, improving the utilization rate and final yield of the semiconductor device.

[0058] refer to Figure 1 , Figure 1This is a schematic diagram of a semiconductor device provided in one embodiment of the present disclosure, wherein the semiconductor device includes a first semiconductor structure 100 and a second semiconductor structure 200. The first semiconductor structure 100 and the second semiconductor structure 200 are stacked on top of each other along the Z-axis, thereby reducing the overall size of the semiconductor device and increasing the storage density. In some specific embodiments, the first semiconductor structure 100 and the second semiconductor structure 200 can be bonded together by methods such as hybrid bonding, transfer bonding, anodic bonding, fused bonding, adhesive bonding, and eutectic bonding. For example, the first semiconductor structure 100 and the second semiconductor structure 200 can be formed in parallel on different substrates, for example, the first semiconductor structure 100 can be formed on the first substrate and the second semiconductor structure 200 can be formed on the second substrate, and then they can be stacked on top of each other using various suitable bonding techniques such as hybrid bonding.

[0059] Here, the first semiconductor structure 100 includes a memory array 101 and multiple bit lines 102 coupled to the memory array 101. The memory array 101 includes first memory cells 104 and second memory cells 105, both of which can be used to store data. The second semiconductor structure 200 includes peripheral circuitry 201, which is coupled to the memory array 101. It should be understood that the peripheral circuitry 201 and the memory array 101 can be coupled in any suitable manner, such as hybrid bonding, transfer bonding, anodic bonding, fused bonding, adhesive bonding, and eutectic bonding.

[0060] In some specific embodiments, the storage array 101 may include multiple storage planes, each storage plane may include multiple storage banks, each storage bank may include multiple storage blocks, each storage block may include multiple storage strings, and each storage string may include multiple storage cells connected in series. For example, refer to... Figure 2 The memory array 101 includes a plurality of memory blocks 303, each memory block 303 including a plurality of memory strings 304, and each memory string 304 including a plurality of memory cells 305 that are series-coupled and vertically stacked. Each memory cell 305 can hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 can be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor. In embodiments of this disclosure, the plurality of memory cells 305 in the memory array 101 can be divided into first memory cells 104 and second memory cells 105. In some specific embodiments, the memory array may include a plurality of NAND memory cells; the semiconductor device may include a three-dimensional NAND type memory.

[0061] In some implementations, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0062] like Figure 2 As shown, each memory string 304 may include a bottom select gate (BSG) 307 at its source end and a top select gate (TSG) 306 at its drain end. The bottom select gate 307 and top select gate 306 can be configured to activate the selected memory string 304 during read and program operations. In some embodiments, the source ends of memory strings 304 within the same memory block 303 can be coupled via a common source line (CSL) 310. In other words, all memory strings 304 within the same memory block 303 have a common source (ACS). According to some embodiments, the top select gate 306 of each memory string 304 is coupled to a corresponding bit line 102, allowing data to be read from or written to the bit line 102 via an output bus (not shown). In some implementations, each memory string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0063] like Figure 2As shown, the memory string 304 can be organized into multiple memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase a memory cell 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 in adjacent memory strings 304 can be coupled via word lines (WL) 312, which selects which row of memory cells 305 is affected by a read or program operation.

[0064] Figure 3 This is a schematic cross-sectional view of an exemplary storage array including storage strings, provided for embodiments of this disclosure. Figure 3 As shown, the memory array 101 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a channel structure perpendicularly penetrating the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer 411 to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form a memory string 304. The gate layers 411 and the insulating layers 412 may be stacked alternately, and adjacent gate layers 411 are separated by an insulating layer 412.

[0065] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as a top select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a bottom select gate line, and the gate layer 411 extending laterally between the top select gate line and the bottom select gate line may serve as a word line layer. The top select gate line is used to form a top select transistor 306, and the bottom select gate line is used to form a bottom select transistor 307.

[0066] In some embodiments, the stacked structure 410 may be disposed on the substrate 400. The substrate 400 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device may not include a substrate.

[0067] In some embodiments, the memory string 304 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0068] In some embodiments, return to reference Figure 2 The peripheral circuitry 201 may include any suitable analog, digital, and mixed-signal circuitry for operating the memory array 101 by applying voltage and / or current signals to each target memory cell via bit line 102, word line 312, common-source line 310, bottom select line 309, and top select line 308, and sensing voltage and / or current signals from each target memory cell. The peripheral circuitry 201 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0069] refer to Figure 4 , Figure 4 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 401, a column decoder / bit line driver 402, a row decoder / word line driver 403, a voltage generator 404, control logic 405, a register 406, a flash memory interface I / F 407, and a data bus 408. It should be understood that in some examples, the peripheral circuitry may also include... Figure 4 Additional peripheral circuitry not shown.

[0070] Page buffer / sensor amplifier 401 can be configured to read data from memory array 101 and program (write) data to memory array 101 according to control signals from control logic 405. In one example, page buffer / sensor amplifier 401 can store a page of programming data (write data) to be programmed into memory array 101. In another example, page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. Column decoder / bit line driver 402 can be configured to be controlled by control logic 405 and select one or more memory cell strings by applying a bit line voltage generated from voltage generator 404.

[0071] The row decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of memory array 101 and select / deselect word lines of memory blocks. The row decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the row decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the row decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines. The voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory array 101.

[0072] Control logic 405 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Flash interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from host devices (not shown) and relay them to control logic 405, as well as to buffer status information received from control logic 405 and relay it to the memory controller. Flash interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 101.

[0073] In this embodiment of the disclosure, refer back to [link / reference]. Figure 1 The peripheral circuit 201 also includes: data path 202, data selection circuit 203, read / write control circuit 204, addressing register (CAM) 205, and redundancy control circuit 206. The data path 202 is coupled to the data selection circuit 203, and the data path 202 can be configured to be controlled by the control logic 405 to transmit data. The data selection circuit 203 can also be coupled to the control logic 405, the read / write control circuit 204, and the storage array 101, and can be configured to be controlled by the control logic 405 to select whether to read or write data from the storage array 101 or the address register 205. The read / write control circuit 204 can be coupled to the data selection circuit 203 and the address register 205, and can be configured to be controlled by the control logic 405 to perform read or write operations. The address register 205 can be configured to be controlled by the control logic 405 to store address information or other data. The redundancy control circuit 206 can be coupled to the data selection circuit 203 and the storage array 101, and can be configured to be controlled by the control logic 405 to select the appropriate transmission interface for data transmission in shifts.

[0074] In some embodiments, the peripheral circuit 201 is configured to receive and respond to a third command CMD3 before receiving the first command CMD1. The third command CMD3 instructs a failure test to be performed on multiple bit lines 102 to determine whether a failed bit line 103 exists among the multiple bit lines 102. When a failed bit line 103 exists among the multiple bit lines 102, the address information of the failed bit line 103 is obtained. The methods for performing failure tests on multiple bit lines include, but are not limited to, voltage contrast imaging, bias-assisted detection, and hotspot analysis. A failed bit line can be understood as a bit line that cannot function properly due to manufacturing defects, short circuits, leakage, or other faults, typically manifesting as abnormal voltage contrast, leakage or short circuit phenomena, or physical structural damage.

[0075] It should be understood that when there are no faulty bit lines 103 among the multiple bit lines 102, that is, when all bit lines 102 are working properly, there is no need to perform the above-mentioned redundancy replacement operation, and the first data can be stored directly in the first storage unit according to the instruction of the first command. When there are faulty bit lines 103 among the multiple bit lines 102, a redundancy replacement operation needs to be performed.

[0076] In some embodiments, when it is determined that there is a failed bit line 103 among the multiple bit lines 102, the peripheral circuit 201 is further configured to receive and respond to the fourth command CMD4 to store the address information of the failed bit line into the address register 205.

[0077] In some embodiments, the peripheral circuit 201 is further configured to: receive a first command CMD1, the first command CMD1 including first data (data1) and address information of the bit line coupled to the first storage cell 104; the first command CMD1 instructs to store the first data (data1) into the first storage cell 104. Here, the first command CMD1 is a write command.

[0078] The peripheral circuit 201 is also configured to: in response to the first command CMD1, compare the address information of the bit lines coupled to the first storage cell 104 with the address information of the failed bit lines stored in the address register 205, and determine the storage location of the first data based on the comparison result. Specifically, when all the address information of the bit lines coupled to the first storage cell 104 is the same as the address information of the failed bit lines, it indicates that all the bit lines coupled to the first storage cell 104 are failed bit lines. In this case, the first data (data1) is completely transferred to the second storage cell 105 to achieve redundant replacement of the bit lines coupled to the second storage cell 105 with all the failed bit lines. Here, after performing redundant replacement of all the failed bit lines, the address information of the bit lines coupled to the second storage cell 105 is stored in the address register 205, and a first mapping relationship is formed with the address information of the corresponding failed bit lines.

[0079] When the address information of the bit lines coupled to the first storage cell 104 is the same as the address information of the failed bit line 103, it indicates that some bit lines coupled to the first storage cell 104 are failed bit lines. In this case, the first data (data1) is divided into two parts, such as the second data (data2) and the third data (data3). The second data (data2) is the data corresponding to the failed bit lines coupled to the first storage cell 104, and the third data (data3) is the data corresponding to the normal bit lines coupled to the first storage cell 104. The second data (data2) is stored in the second storage cell 105, and the third data (data3) is stored in the first storage cell 104, to achieve redundant replacement of the bit lines coupled to the second storage cell 105 with some failed bit lines. Here, after performing redundant replacement of some failed bit lines, the address information of the bit lines coupled to the second storage cell 105 is stored in the address register 205, and a second mapping relationship is formed with the address information of the corresponding failed bit lines.

[0080] It should be understood that the number of bit lines coupled to the second storage cell 105 is different in the first mapping relationship and the second mapping relationship.

[0081] In this embodiment, the number of failed bit lines 103 is less than or equal to the number of bit lines coupled to the second storage unit 105, thus ensuring data integrity. For example, the address register 205 can store address information for 11 failed bit lines (ca<10:0>). In the address information of the bit lines coupled to the first storage unit 104, the number of entries for redundantly replaced bit line address information must be less than or equal to 11. Thus, the address register 205 can completely store its corresponding address information, ensuring data integrity.

[0082] It should be noted that when the address information of the bit line coupled to the first storage cell 104 is different from the address information of the failed bit line, it indicates that the bit lines coupled to the first storage cell 104 are all normal bit lines. At this time, all the first data is stored in the first storage cell 104, and there is no need to perform redundant replacement.

[0083] In some embodiments, during the response to the first command CMD1, the first data is transmitted to the data selection circuit 203 through the data path 202. The data selection circuit 203, based on the comparison result output by the control logic 405, selects whether to store all of the first data in the first storage unit 104, or a portion in the first storage unit 104 and another portion in the second storage unit 105, or all of the first data in the second storage unit 105. This completes the write operation of the first data.

[0084] For ease of understanding, the following embodiments will be illustrated by the example of a faulty bit line among multiple bit lines, where a portion of the first data (such as the second data) is stored in the second storage unit 105 and another portion of the data (such as the third data) is stored in the first storage unit 104. In this case, the bit lines of the second storage unit 105 are redundantly replaced with the faulty bit lines.

[0085] In some embodiments, reference Figure 1 The redundancy control circuit 206 is located between the data selection circuit 203 and the storage array 101. The redundancy control circuit 206 is configured to select the second data segment to the transmission interface coupled to the second storage unit, such as the redundant transmission interface Red-out<10:0>.

[0086] In some embodiments, reference Figure 1 When the number of address information entries on the bit lines coupled to the second storage cell 105 includes multiple entries, the read / write control circuit 204 is configured to generate multiple write clock signals and multiple data write signals in response to the first command CMD1. The data selection circuit 203 is configured to sequentially store the second data in the second storage cell and store the third data in the first storage cell based on the multiple write clock signals and the multiple data write signals.

[0087] In some embodiments, the peripheral circuit 201 is further configured to: receive a second command CMD2, the second command CMD2 being a read command, the second command CMD2 indicating the reading of first data. The peripheral circuit 201 is also configured to: in response to the second command CMD2, feed back the address information of the bit line coupled to the second memory cell 105, the second data, and the third data.

[0088] Specifically: Control logic 405 receives and responds to the second command CMD2, generating a control signal; based on this control signal, it retrieves the address information of the bit line coupled to the second memory cell 105 from the address register 205, retrieves the third data from the first memory cell, and retrieves the second data from the second memory cell. The read / write control circuit 204 generates multiple read clock signals and multiple data read signals during the response to the second command CMD2. The data selection circuit 203, based on the multiple read clock signals and multiple data read signals, multiplexes the second data, the third data, and the address information of the failed bit line onto the data path 202. Specifically, it multiplexes the second data, the third data, and the address information of the failed bit line onto the redundant transmission interface of the data path 202, for example, Red-out<10:0>. The data path 202 transmits the address information of the bit line coupled to the second memory cell, the second data, and the third data during the response to the second command CMD2.

[0089] In the above embodiments, during the response to the second command CMD2 (i.e., to perform a read operation), the address information of the coupling bit line of the second storage unit 105 can be multiplexed onto the data path 202. That is, the transmission path of the address information of the coupling bit line of the second storage unit 105 during the read operation is multiplexed with the transmission path of the data during the read and write operations. In this way, there is no need to add a transmission path for the address information, which reduces the process difficulty and manufacturing cost.

[0090] It should be noted that when the second storage cell 105 is redundantly replaced with all the first storage cells 104, all the first data is stored in the second storage cell 105. At this time, in response to the second command CMD2, the peripheral circuit is configured to feed back the address information of the second storage cell's coupling bit line and the first data. Similarly, the address information of the second storage cell's coupling bit line reuses the transmission path of the first data (data path 202), eliminating the need to add a new transmission path and reducing manufacturing costs.

[0091] In some embodiments, reference Figure 1The first semiconductor structure 100 also includes a connection structure 207 penetrating the memory array 101, one end of which is connected to the peripheral circuit 201. The connection structure 207 is configured to transmit a fourth command CMD4, which includes a first command CMD1, a second command CMD2, a third command CMD3, and so on. The connection structure 207 can be formed using through-silicon via (TSV) technology. It should be understood that the connection structure 207 penetrates the layer or location of the memory array 101 but does not penetrate the memory cells in the memory array and will not damage the memory cells.

[0092] Secondly, this disclosure provides another semiconductor device, referenced to Figure 5 and Figure 6 , Figure 5 This is a schematic diagram of the structure of another semiconductor device. Figure 6 for Figure 5 A schematic diagram of the corresponding three-dimensional structure of the semiconductor device. It should be noted that... Figure 6 The transmission paths of different signals are illustrated using solid and dashed lines, where solid lines represent the transmission paths of data corresponding to normal bit lines, and dashed lines represent the transmission paths of data corresponding to redundant replacement bit lines. However, it should be understood that the above signal transmission paths are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0093] like Figure 5 and Figure 6 As shown, the semiconductor device includes: a first semiconductor structure 100, which includes a memory array 101 and multiple bit lines 102 coupled to the memory array 101, the memory array 101 including a first memory cell 104 and a second memory cell 105; a second semiconductor structure 200, which includes peripheral circuitry 201; and a third semiconductor structure 300, which includes a control circuitry 301; the peripheral circuitry 201 is coupled to the memory array 101 and the control circuitry 301, respectively.

[0094] like Figure 5 As shown, the first semiconductor structure 100, the second semiconductor structure 200, and the third semiconductor structure 300 can be stacked on top of each other along the Z-axis, thereby reducing the overall size of the semiconductor device and increasing storage density. Here, the first semiconductor structure 100 is located between the second semiconductor structure 200 and the third semiconductor structure 300; in other embodiments, they can also be stacked in other arrangements, such as the second semiconductor structure 200 being located between the first semiconductor structure 100 and the third semiconductor structure 300, etc., which are not limited in this disclosure.

[0095] In some specific embodiments, a first semiconductor structure 100, a second semiconductor structure 200, and a third semiconductor structure 300 may be formed in parallel on different substrates. For example, the first semiconductor structure 100 may be formed on a first substrate, the second semiconductor structure 200 on a second substrate, and the third semiconductor structure 300 on a third substrate. Then, they may be stacked on top of each other using methods such as hybrid bonding, transfer bonding, anodic bonding, melt bonding, adhesive bonding, and eutectic bonding.

[0096] In some embodiments, the semiconductor device further includes a connection structure 207 that runs through the memory array 101 and is connected to the peripheral circuit 201 and the control circuit 301 respectively, to couple the peripheral circuit 201 and the control circuit 301, thereby shortening the distance between the peripheral circuit 201 and the control circuit 301 and reducing signal delay. Here, the connection structure 207 is, for example, a TSV structure. The control circuit 301 is configured to send commands, and the connection structure 207 is used to transmit commands. The control circuit 301 can also be coupled to an external device (such as a host).

[0097] In some embodiments, reference Figure 5 The control circuit 301 is also configured to send a third command CMD3, which instructs that multiple bit lines in the memory array be tested.

[0098] The peripheral circuit 201 is also configured to receive and respond to the third command CMD3, test multiple bit lines, and obtain the address information of failed bit lines. The failure testing methods include, but are not limited to, voltage contrast imaging, bias-assisted detection, and hotspot analysis. A failed bit line can be understood as a bit line that cannot function properly due to manufacturing defects, short circuits, leakage, or other faults, typically manifesting as abnormal voltage contrast, leakage or short circuit phenomena, or physical structural damage.

[0099] In some embodiments, the control circuit 301 is further configured to send a fourth command CMD4, which instructs that the address information of the failed bit line be stored in the address register 205 of the peripheral circuit.

[0100] The peripheral circuit 201 is also configured to receive and respond to the fourth command CMD4 and store the address information of the failed bit line in the address register 205.

[0101] In some embodiments, the control circuit 301 is configured to send a first command CMD1, which is a write command. The first command CMD1 includes first data and address information of the bit line coupled to the first storage cell 104; the first command CMD1 instructs to store the first data into the first storage cell 104.

[0102] The peripheral circuit 201 is configured to receive and respond to the first command CMD1, and when at least a portion of the bit line address information in the address information of the bit lines coupled to the first storage cell 104 is the same as the address information of the failed bit line 103 among the multiple bit lines, store the data corresponding to the at least portion of the bit line address information in the first data to the second storage cell 105. In this way, when a failed bit line exists among the bit lines coupled to the first storage cell, a redundancy replacement mechanism can be used to at least partially transfer the data indicating that it is stored in the first storage cell to the second storage cell, thereby continuing to use the semiconductor structure with partially failed bit lines, improving the utilization rate and final yield of the semiconductor device.

[0103] Specifically, the peripheral circuit 201 is further configured to compare the address information of the coupled bit lines of the first storage unit 104 with the address information of the failed bit lines stored in the address register 205, and determine the storage location of the first data based on the comparison result. Specifically, when all the address information of the coupled bit lines of the first storage unit 104 is identical to the address information of the failed bit lines, the first data is entirely transferred to the second storage unit 105 to achieve redundant replacement of the coupled bit lines of the second storage unit 105 with all failed bit lines. Here, after performing all redundant replacements, the address information of the coupled bit lines of the second storage unit 105 is stored in the address register 205, and a first mapping relationship is formed with the address information of the corresponding failed bit lines. When part of the address information of the coupled bit lines of the first storage unit 104 is identical to the address information of the failed bit line 103, the data corresponding to the failed bit line in the first data (such as the second data) is stored in the second storage unit 105, and the remaining data (such as the third data) is stored in the first storage unit 104 to achieve redundant replacement of the coupled bit lines of the second storage unit 105 with some failed bit lines. Here, after performing partial redundancy replacement, the address information of the bit line coupled to the second storage unit 105 is stored in the address register 205, and a second mapping relationship is formed with the address information of the corresponding failed bit line. In this way, the writing operation of the first data is completed.

[0104] In response to the first command CMD1, the data path 202 is configured to transmit the first data; the control logic 405 is configured to generate a control signal based on the first command CMD1; and the data selection circuit 203 based on the control signal is configured to select, according to the comparison result output by the control logic 405, to store all of the first data in the first storage unit 104, or to store a portion in the first storage unit 104 and another portion in the second storage unit 105, or to store all of the first data in the second storage unit 105.

[0105] Here and below, the example of storing a portion of the first data in the first storage unit 104 and another portion in the second storage unit 105 will be used for illustration.

[0106] When the second data needs to be stored in the second storage unit 105, the redundancy control circuit 206 is configured to select the second data to the transmission interface coupled to the second storage unit, such as the redundancy transmission interface (Red-out<10:0>).

[0107] During this period, the read / write control circuit 204 is configured to generate multiple write clock signals and multiple data write signals. The data selection circuit 203 is configured to sequentially store the second data in the first storage cell 104 and store the third data in the second storage cell 105 based on the multiple write clock signals and multiple data write signals.

[0108] In some embodiments, reference Figure 5 The control circuit 301 is also configured to send a second command CMD2; the second command CMD2 is a read command. The second command CMD2 is used to instruct the reading of the first data.

[0109] In some embodiments, the peripheral circuit 201 is configured to receive and respond to the second command CMD2, and send the second data stored in the second storage unit 105, the third data stored in the first storage unit, and the address information of the second storage unit coupled bit line stored in the addressing register to the control circuit 301 through the data path 202.

[0110] After receiving the address information of the second storage cell coupling bit line, the second data, and the third data, the control circuit 301 processes the second data and the third data based on the address information of the second storage cell coupling bit line to obtain the first data. For example, based on the comparison between the address information of the second storage cell 105 coupling bit line and the address information of the first storage cell 104 coupling bit line, the specific locations of the second data and the third data are determined to obtain the complete first data.

[0111] In response to the second command CMD2, control logic 405 is configured to generate a control signal based on the second command. Data selection circuit 203 is configured to retrieve third data from the first memory cell, retrieve second data from the second memory cell, and retrieve the address information of the bit line coupled to the second memory cell from the address register based on the control signal.

[0112] During this period, the read / write control circuit 204 is configured to generate multiple read clock signals and multiple data read signals. The data selection circuit 203 is configured to, based on the multiple read clock signals and multiple data read signals, sequentially multiplex the second data, the third data, and the address information of the second memory cell coupling bit lines onto the data path 202, for example, multiplexing them onto the redundant transmission interface of the data path 202, such as Red-out<10:0>. The data path 202 is used to transmit the address information of the second memory cell coupling bit lines, the second data, and the third data during the response to the second command CMD2.

[0113] In this embodiment, on the one hand, by transmitting the address information of the second memory cell coupling bit line to the control circuit, the sharing of redundant replacement information between the peripheral circuit and the control circuit is realized. This allows for a redundant replacement mechanism to be implemented among the control circuit, peripheral circuit, and memory array when they are bonded and stacked. On the other hand, by multiplexing the data path when transmitting the address information of the second memory cell coupling bit line, no additional transmission channel is required. In other words, this disclosure increases the transmission path for redundant replacement bit line information by multiplexing the data path, but does not increase manufacturing costs. Thus, a redundant replacement mechanism can be implemented without increasing manufacturing costs when three semiconductor structures are stacked, improving the utilization rate and final yield of the semiconductor device.

[0114] Thirdly, embodiments of this disclosure provide an operation method for a semiconductor device, referring to... Figure 7 , Figure 7 A schematic flowchart of an operation method for a semiconductor device is shown, wherein the operation method includes the following steps:

[0115] Step S701: Receive the first command CMD1, which includes the address information of the first data and the bit line coupled to the first memory cell in the memory array; the first command CMD1 instructs the first data to be stored in the first memory cell.

[0116] Step S702: In response to the first command CMD1, when at least a portion of the bit line address information in the address information of the first memory cell coupled bit line is the same as the address information of the failed bit line in the multiple bit lines of the memory array, the data corresponding to the at least a portion of the bit line address information in the first data is stored in the second memory cell in the memory array; wherein, the semiconductor device includes: a first semiconductor structure including the memory array and multiple bit lines coupled to the memory array; and a second semiconductor structure including peripheral circuitry coupled to the memory array.

[0117] In some embodiments, the method further includes: storing all first data in the second storage unit when all address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line; storing second data corresponding to a portion of the bit line address information in the first data in the second storage unit when a portion of the address information of the bit lines coupled to the failed bit line is the same as the address information of the failed bit line; and storing the remaining third data in the first data in the first storage unit.

[0118] In some embodiments, the method further includes: receiving a second command, the second command instructing the reading of first data; and responding to the second command by feeding back address information of the second storage cell coupling bit line, the second data, and the third data.

[0119] In some embodiments, the method further includes storing the address information of the failed bit line and the address information of the second storage cell coupled bit line into the address register of the peripheral circuit.

[0120] In some embodiments, the method further includes: transmitting first data through a data path in a peripheral circuit during the response to a first command; and transmitting address information, second data, and third data of a second memory cell coupling bit line through a data path during the response to a second command.

[0121] In some embodiments, the method further includes: generating a plurality of write clock signals and a plurality of data write signals via a read / write control circuit in a peripheral circuit in response to a first command; and generating a plurality of read clock signals and a plurality of data read signals via a read / write control circuit in response to a second command.

[0122] In some embodiments, the method further includes: storing the second data to the second memory cell and storing the third data to the first memory cell sequentially through a data selection circuit in the peripheral circuit based on a plurality of write clock signals and a plurality of data write signals; and multiplexing the address information of the second data, the third data and the failed bit line onto the data path through a data selection circuit based on a plurality of read clock signals and a plurality of data read signals.

[0123] In some embodiments, the method further includes: using a redundant control circuit in the peripheral circuit to select the second data segment to the transmission interface where the address information of the second storage cell coupled bit line is output.

[0124] In some embodiments, the second semiconductor structure further includes a connection structure that runs through the memory array and is connected to a peripheral circuit; the method further includes transmitting a first command and a second command through the connection structure.

[0125] In some embodiments, the method further includes: storing data in the first storage cell when the address information of the bit line coupled to the first storage cell is different from the address information of the faulty bit line.

[0126] In some embodiments, the method further includes: receiving and responding to a third command, testing multiple bit lines, and obtaining address information of failed bit lines.

[0127] The following example describes the interface multiplexing between circuits during the execution of a read operation.

[0128] refer to Figure 8 , Figure 8 This is a block diagram of the multiplexing logic for the data path in a semiconductor device. During a read operation, it is assumed that the data bus width of the GIO data path is 32 bits, the page size is 2KB, and the number of entries stored in the address register is ca<10:0>. After the control circuit sends a read command (such as the second command CMD2) containing redundancy repair information to the peripheral circuit, the peripheral circuit responds to the second command CMD2 and generates an enable control signal. Here, the second command CMD2 includes the address of the plane where the target memory cell is located.

[0129] Based on multiple read clock signals (clk), the address information of the second memory cell coupled bit lines corresponding to the first failed bit line (bad column address 0) to the last failed bit line (bad column address XX) is sequentially selected and sent to the redundant transmission interface of the data path, for example, Red-out <10:0>. Then, the data path can be reused to feed this information back to the control circuit. Thus, when failed bit lines exist in a semiconductor device, the above implementation method can increase the transmission channels for redundant bit line address information, thereby enabling the sharing and unification of redundancy repair mechanisms between the control circuit and peripheral circuits, and improving the reuse rate of the semiconductor device.

[0130] Based on the above-described semiconductor devices, embodiments of this disclosure provide an electronic device. Figure 9 A schematic diagram of an exemplary electronic device having semiconductor devices provided in embodiments of this disclosure, such as... Figure 9 As shown, the electronic device 900 includes a semiconductor device 902 as described in any of the above embodiments.

[0131] In some embodiments, such as Figure 9 As shown, the electronic device 900 also includes a host 901 coupled to the semiconductor device 902.

[0132] In this embodiment of the disclosure, the electronic device 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 9 As shown, electronic device 900 may include host 901 and semiconductor device 902. Semiconductor device 902 may include one or more memory devices 903 and memory controller 904. Host 901 may include a processor of electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). Host 901 may be configured to send data to or receive data from semiconductor device 902. Memory device 903 includes a memory array and peripheral circuitry coupled to the memory array. The memory controller 904 may, for example, include the control circuitry described in the above embodiments.

[0133] In some embodiments, memory controller 904 is coupled to memory device 903 and host 901 and is configured to control memory device 903. Memory controller 904 can manage data stored in memory device 903 and communicate with host 901. In some embodiments, memory controller 904 is designed to operate in low duty cycle environments, such as in secure digital cards, compact flash cards (CFC), universal serial bus (USB) flash drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, memory controller 904 is designed to operate in high duty cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0134] In some embodiments, the memory controller 904 and one or more memory devices 903 can be integrated into various types of storage devices, that is, the semiconductor device 902 can be implemented and packaged into different types of end electronic products.

[0135] In such Figure 10In one example shown, the memory controller 904 and a single memory device 903 can be integrated into a memory card 801. The memory card 801 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC) such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 801 may also include a connection between the memory card 801 and a host device (e.g., Figure 9 The host 901 in the memory card connector 802 is coupled to the host 901. In such a way... Figure 11 In another example shown, the memory controller 904 and multiple memory devices 903 can be integrated into the SSD 803. The SSD 803 may also include components for connecting the SSD 803 to host devices (e.g., ...). Figure 9 The SSD connector 804 is coupled to the host 901. In some embodiments, the storage capacity and / or operating speed of the SSD 803 is greater than the storage capacity and / or operating speed of the memory card 801.

[0136] In some embodiments, the memory controller 904 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 904 is designed to operate in high duty cycle environments, in solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which serve as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays.

[0137] The memory controller 904 can be configured to control the operation of the memory device 903, such as read, erase, and program operations. The memory controller 904 can also be configured to manage various functions relating to data stored or to be stored in the memory device 903, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 904 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 903. The memory controller 904 can also perform any other suitable functions, such as formatting the memory device 903. The memory controller 904 can communicate with external devices (e.g., host 901) according to a specific communication protocol. For example, the memory controller 904 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0138] The memory controller 904 and one or more memory devices 903 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the semiconductor device 902 can be implemented and packaged into different types of end electronic products.

[0139] It should be understood that the phrases "some embodiments" or "embodiments of this disclosure" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "embodiments of this disclosure" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments of this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0140] The above description is merely a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. Any equivalent structural transformations made using the contents of this specification and drawings under the inventive concept of this disclosure, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A first semiconductor structure includes a memory array and multiple bit lines coupled to the memory array, the memory array including a first memory cell and a second memory cell; And a second semiconductor structure, including peripheral circuitry; said peripheral circuitry is coupled to the memory array and configured to: Receive a first command, the first command including first data and address information of the first storage cell coupling bit line; the first command instructs to store the first data into the first storage cell; In response to the first command, when at least a portion of the bit line address information in the address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line among the plurality of bit lines, the data corresponding to the at least a portion of the bit line address information in the first data is stored in the second storage unit.

2. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is also configured to: When all the address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line, all the first data is stored in the second storage unit. When the address information portion of the bit line coupled to the first storage unit is the same as the address information of the failed bit line, the second data corresponding to the address information of the bit line in the first data is stored in the second storage unit, and the remaining third data in the first data is stored in the first storage unit.

3. The semiconductor device according to claim 2, characterized in that, The peripheral circuit is also configured to: Receive a second command, which instructs the reading of the first data; In response to the second command, the address information of the second storage cell coupling bit line, the second data, and the third data are fed back.

4. The semiconductor device according to claim 3, characterized in that, The peripheral circuit also includes: Addressing register; the addressing register is configured to store the address information of the failed bit line, and the address information of the bit line coupled to the second storage cell.

5. The semiconductor device according to claim 4, characterized in that, The peripheral circuit also includes: A data path; the data path is coupled to the addressing register and is configured to: transmit the first data in response to the first command; and transmit the address information of the second memory cell coupled bit line, the second data, and the third data in response to the second command.

6. The semiconductor device according to claim 5, characterized in that, When the number of address information entries on the bit lines coupled to the second storage unit includes multiple entries, the peripheral circuit further includes: A read / write control circuit is located between the address register and the data path; the read / write control circuit is configured to: generate a plurality of write clock signals and a plurality of data write signals in response to the first command; and generate a plurality of read clock signals and a plurality of data read signals in response to the second command.

7. The semiconductor device according to claim 6, characterized in that, The peripheral circuit also includes: A data selection circuit; the data selection circuit is located between the data path and the read / write control circuit, and the other end of the data selection circuit is coupled to the storage array; the data selection circuit is configured to: based on a plurality of write clock signals and a plurality of data write signals, sequentially store the second data in the second storage cell, store the third data in the first storage cell; and, Based on multiple read clock signals and multiple data read signals, the address information of the second data, the third data, and the failed bit line is multiplexed onto the data path.

8. The semiconductor device according to claim 7, characterized in that, The peripheral circuit also includes: A redundancy control circuit is located between the data selection circuit and the storage array, and the redundancy control circuit is configured to select the second data sequence to the transmission interface coupled to the second storage unit.

9. The semiconductor device according to claim 8, characterized in that, The first semiconductor structure is bonded to the second semiconductor structure; The first semiconductor structure further includes a connection structure that runs through the memory array and is connected to the peripheral circuitry; the connection structure is configured to transmit the first command and the second command.

10. The semiconductor device according to claim 1, characterized in that, The peripheral circuit is also configured to: Receive and respond to the third command to test the multiple bit lines in order to obtain the address information of the failed bit lines.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that, The number of failed bit lines is less than or equal to the number of bit lines coupled to the second memory cell.

12. The semiconductor device according to claim 1, characterized in that, The storage array includes multiple NAND storage cells; the semiconductor device includes a three-dimensional NAND type memory.

13. A semiconductor device, characterized in that, include: A first semiconductor structure includes a memory array and multiple bit lines coupled to the memory array, the memory array including a first memory cell and a second memory cell; A second semiconductor structure includes peripheral circuitry coupled to the memory array; And a third semiconductor structure, including a control circuit; the control circuit is coupled to the peripheral circuit. The control circuit is configured to: send a first command, the first command including first data and address information of the first storage cell coupling bit line; the first command instructs to store the first data into the first storage cell; The peripheral circuit is configured to receive and respond to the first command, and when at least a portion of the bit line address information in the address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line among the plurality of bit lines, store the data in the first data corresponding to the at least a portion of the bit line address information in the second storage unit.

14. The semiconductor device according to claim 13, characterized in that, The peripheral circuit is specifically configured as follows: When all the address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line, all the first data is stored in the second storage unit. When the address information portion of the bit line coupled to the first storage unit is the same as the address information of the failed bit line, the second data corresponding to the address information of the bit line in the first data is stored in the second storage unit, and the remaining third data in the first data is stored in the first storage unit.

15. The semiconductor device according to claim 14, characterized in that, The control circuit is further configured to send a fourth command, the fourth command instructing that the address information of the failed bit line be stored in the address register of the peripheral circuit; The peripheral circuit is also configured to receive and respond to the fourth command by storing the address information of the failed bit line in the address register.

16. The semiconductor device according to claim 15, characterized in that, The peripheral circuit is also configured to store the address information of the second storage cell coupling bit line into the address register during the response to the first command.

17. The semiconductor device according to claim 16, characterized in that, The control circuit is further configured to: send a second command; the second command instructs the acquisition of the first data; The peripheral circuitry is also configured to receive and respond to the second command; The address information of the second storage cell coupled bit line, the second data, and the third data are fed back to the control circuit.

18. The semiconductor device according to claim 17, characterized in that, The control circuit is further configured to obtain the first data based on the address information of the second storage cell coupled bit line, the second data, and the third data.

19. The semiconductor device according to claim 18, characterized in that, The control circuit is also configured to send a third command, the third command instructing that the plurality of bit lines be tested; The peripheral circuit is also configured to: receive and respond to the third command, test the multiple bit lines, and obtain the address information of the failed bit line.

20. A method of operating a semiconductor device, characterized in that, The operation method includes: Receive a first command, the first command including first data and address information of a bit line coupled to a first memory cell in the memory array; the first command instructs to store the first data in the first memory cell; In response to the first command, when at least a portion of the bit line address information in the address information of the first storage cell coupled bit line is the same as the address information of the failed bit line in the multiple bit lines of the storage array, the data in the first data corresponding to the at least a portion of the bit line address information is stored in the second storage cell of the storage array. The semiconductor device includes: a first semiconductor structure including the memory array and multiple bit lines coupled to the memory array; and a second semiconductor structure including peripheral circuitry; the peripheral circuitry being coupled to the memory array.

21. The operating method according to claim 20, characterized in that, The method further includes: When all the address information of the bit lines coupled to the first storage unit is the same as the address information of the failed bit line, all the first data is stored in the second storage unit. When the address information portion of the bit line coupled to the first storage unit is the same as the address information of the failed bit line, the second data corresponding to the address information of the bit line in the first data is stored in the second storage unit, and the remaining third data in the first data is stored in the first storage unit.

22. The operating method according to claim 21, characterized in that, The method further includes: Receive a second command, which instructs the reading of the first data; In response to the second command, the address information of the second storage cell coupling bit line, the second data, and the third data are fed back.

23. The operating method according to claim 22, characterized in that, The method further includes: The address information of the failed bit line and the address information of the bit line coupled to the second storage unit are stored in the address register of the peripheral circuit.

24. The operating method according to claim 23, characterized in that, The method further includes: In response to the first command, the first data is transmitted through the data path in the peripheral circuit; and in response to the second command, the address information of the second memory cell coupling bit line, the second data, and the third data are transmitted through the data path.

25. The operating method according to claim 24, characterized in that, The method further includes: In response to the first command, a plurality of write clock signals and a plurality of data write signals are generated by the read / write control circuit in the peripheral circuit; and in response to the second command, a plurality of read clock signals and a plurality of data read signals are generated by the read / write control circuit.

26. The operating method according to claim 25, characterized in that, The method further includes: Based on multiple write clock signals and multiple data write signals, the second data is sequentially stored in the second storage unit and the third data is stored in the first storage unit via a data selection circuit in the peripheral circuit; and... Based on multiple read clock signals and multiple data read signals, the address information of the second data, the third data, and the failed bit line is multiplexed onto the data path by the data selection circuit.

27. The operating method according to claim 26, characterized in that, The method further includes: The redundant control circuit in the peripheral circuit selects the second data to the transmission interface coupled to the second storage unit.

28. The operating method according to claim 27, characterized in that, The second semiconductor structure further includes a connection structure that extends through the memory array and is connected to the peripheral circuitry; the method further includes: The first command and the second command are transmitted through the connection structure.

29. The operating method according to claim 20, characterized in that, The method further includes: Receive and respond to the third command, test the multiple bit lines, and obtain the address information of the failed bit lines.

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