Memory element test circuit and memory element test method

Abstract

A memory element test circuit and a memory element test method are disclosed. The memory element test circuit is used to test a memory element, and includes a storage circuit, a comparison circuit, and a control circuit. The storage circuit is used to store a test data. The control circuit is used to perform the following steps in a single test procedure to test the memory element: (A) controlling the memory element to enter a first power mode, and then controlling the memory element to exit the first power mode; (B) writing the test data into the memory element; (C) controlling the memory element to enter a second power mode, and then controlling the memory element to exit the second power mode; and (D) comparing a stored data of the memory element with the test data.

Description

Technical Field

[0001] This invention relates to memory elements, and more particularly to memory element test circuits and memory element test methods. Background Technology

[0002] To reduce standby power and maintain stored values ​​in a System on a Chip (SoC), power modes are typically implemented for control. For example, for memory, power modes usually include light sleep (LS), deep sleep (DS), and shutdown (SD). In terms of power consumption, shutdown mode consumes relatively less power, followed by deep sleep mode, while light sleep mode consumes relatively more power. Memory can retain data in light sleep and deep sleep modes, but it cannot retain data in shutdown mode.

[0003] Conventional built-in self-test (BIST) circuits require multiple test vectors to test different power modes separately. These test vectors require independent test procedures, making the testing of memory components complex and time-consuming. Summary of the Invention

[0004] In view of the shortcomings of the prior art, one object of the present invention is to provide a memory element test circuit and a memory element test method to improve the shortcomings of the prior art.

[0005] An embodiment of the present invention provides a memory element test circuit. The memory element test circuit is used to test a memory element and includes: a storage circuit, a comparison circuit, and a control circuit. The storage circuit is used to store test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory element, and is used to perform the following steps in a single test procedure to test the memory element: (A) controlling the memory element to enter a first power mode, and then controlling the memory element to leave the first power mode; (B) writing the test data to the memory element; (C) controlling the memory element to enter a second power mode, and then controlling the memory element to leave the second power mode; (D) comparing a stored data of the memory element with the test data.

[0006] Another embodiment of the present invention provides a method for testing a storage element, comprising the following steps in a single test procedure: (A) controlling the storage element to enter a first power mode and then controlling the storage element to leave the first power mode; (B) writing test data into the storage element; (C) controlling the storage element to enter a second power mode and then controlling the storage element to leave the second power mode; and (D) comparing a stored data of the storage element with the test data.

[0007] The technical means embodied in the embodiments of the present invention can improve at least one of the disadvantages of the prior art. Therefore, the present invention can simplify the complexity of memory element testing and save testing time compared with the prior art.

[0008] The features, implementation, and effects of this invention are described in detail below with reference to the accompanying drawings as embodiments. Attached Figure Description

[0009] Figure 1 This is a functional block diagram of an embodiment of the self-test circuit built into the storage element of the present invention;

[0010] Figures 2A to 2B This is a flowchart of an embodiment of the storage element testing method of the present invention;

[0011] Figure 3 yes Figure 1 A timing diagram of an embodiment of the main signal;

[0012] Figure 4 yes Figure 1 Timing diagram of another embodiment of the main signal;

[0013] Figure 5 This is a flowchart of an embodiment of the error diagnosis method of the present invention; and

[0014] Figure 6 yes Figure 1 Timing diagram of another embodiment of the main signal. Detailed Implementation

[0015] The technical terms used in the following description are based on the customary terms in this technical field. If this specification provides an explanation or definition for certain terms, the explanation or definition in this specification shall prevail.

[0016] The present invention discloses a storage element test circuit and a storage element test method. Since some components of the storage element test circuit of the present invention may be known individually, details of known components will be omitted in the following description without affecting the full disclosure and implementability of the invention. Furthermore, part or all of the process of the storage element test method of the present invention may be in the form of software and / or firmware, and can be executed by the storage element test circuit of the present invention or its equivalent. Without affecting the full disclosure and implementability of the method invention, the following description of the method invention will focus on the steps rather than the hardware.

[0017] In the following description, a high level indicates that a signal is active, and a low level indicates that it is inactive. Enabling / de-assertifying a signal means pulling the signal level high / low. However, this is merely an implementation or illustrative example and is not intended to limit the invention. In other words, in different implementations, a high level may represent inactive, and a low level may represent active, while enabling / de-assertifying a signal may represent pulling the signal level low / high. Level transitions or logic level transitions represent a signal changing from enabled (active) to de-assert (inactive), or vice versa.

[0018] Figure 1 This is a functional block diagram of an embodiment of the self-test circuit built into the storage element of the present invention. The storage element test circuit 20 is coupled to the storage element 30 and is used to test the storage element 30. The storage element test circuit 20 includes a storage circuit 210, a control circuit 220, and a comparator circuit 230 that are coupled to each other. The storage element 30 can be a memory, a retention register, or other elements or circuits with data storage capabilities. The storage circuit 210 stores test data Test_D (i.e., the test vector, or data background).

[0019] Under normal operation, logic circuit 10 (which may include storage element control circuitry) controls storage element 30 using address signal ADDR, enable / disable signal ME, and mode control signal PM. Input data D is the data to be written to storage element 30, and stored data Q is the data read from storage element 30.

[0020] In test mode, the control circuit 220 of the storage element test circuit 20 controls or operates the storage element 30 using the address signal Test_ADDR, the enable / disable signal Test_ME, and the mode control signal Test_PM. When the storage element 30 is enabled, it can be accessed (read and / or written); when the storage element 30 is disabled, it cannot be accessed. The mode control signals PM and Test_PM can not only control the storage element 30 to enter power mode, but also further control the storage element 30 to enter different types of power modes: light sleep mode, deep sleep mode, or shutdown mode. The control circuit 220 generates the mode control signal Test_PM based on the mode setting signal PMset. In some embodiments, the user can change the mode setting signal PMset through a configurable register.

[0021] The test start signal BIST_MODE controls the signal generated by the output logic circuit 10 of multiplexers 242, 244, 246, and 248, or the signal generated by the memory element test circuit 20, thus determining whether the memory element 30 is controlled by the logic circuit 10 (i.e., normal operation) or by the control circuit 220 (i.e., test mode). The clock BIST_CLK is the clock provided to the memory element 30 by the memory element test circuit 20 when testing the memory element 30. The reset signal BIST_RSTN is used to reset the memory element test circuit 20.

[0022] Figures 2A to 2B This is a flowchart of an embodiment of the storage element testing method of the present invention. Figure 3 yes Figure 1 A timing diagram of one embodiment of the main signals, wherein the mode control signal Test_PM includes a light sleep mode control signal Test_LS (corresponding to light sleep mode), a deep sleep mode control signal Test_DS (corresponding to deep sleep mode), and a shutdown mode control signal Test_SD (corresponding to shutdown mode). For example, when the user sets the mode setting signal PMset={1, 0, 1}, the storage element test circuit 20 tests the light sleep mode and the shutdown mode; when the user sets the mode setting signal PMset={0, 1, 1}, the storage element test circuit 20 tests the deep sleep mode and the shutdown mode; when the user sets the mode setting signal PMset={1, 1, 1}, the storage element test circuit 20 tests three power modes.

[0023] The following combinations Figure 2A , Figure 2B and Figure 3 This invention describes the testing method for storage elements. Figure 2A and Figure 2B It includes the following steps.

[0024] Step S205: Start testing the storage element 30 (time point t1) by using the enable test start signal BIST_MODE, and reset the storage element test circuit 20 by using the de-enable reset signal BIST_RSTN.

[0025] Step S210: Control circuit 220 enables test notification signal START_PAUSE to notify user that storage element 30 is about to enter power mode (time point t3).

[0026] Step S215: Control circuit 220 controls storage element 30 to enter the off mode (time point t4), and after the first reference time R1, controls storage element 30 to leave the off mode (time point t5).

[0027] Step S220: After the first wake-up time W1, the control circuit 220 controls the storage element 30 to leave the power mode and enter the function mode according to the recovery signal TEST_RESUME input by the user (time point t6). In response to the recovery signal TEST_RESUME enabling at time point t6, the control circuit 220 sends a de-enabling test notification signal START_PAUSE at time point t7 to notify the user that the storage element 30 has left the power mode.

[0028] Step S225: Control circuit 220 enables storage element 30 via enable / disable signal Test_ME (time point t7) to write test data Test_D, and disables storage element 30 after writing test data Test_D, and enables test notification signal START_PAUSE to notify the user that storage element 30 is about to enter power mode (time point t8). At this time, storage element 30 stores test data Test_D.

[0029] Step S230: The control circuit 220 controls the storage element 30 to enter the first sleep mode (i.e., one of the light sleep mode and the deep sleep mode) via the light sleep mode control signal Test_LS or the deep sleep mode control signal Test_DS. Figure 3 In the example, the first sleep mode is light sleep mode (time point t9).

[0030] Step S235: After waiting for the second reference time R2, the control circuit 220 controls the storage element 30 to leave the first sleep mode (time point t10).

[0031] Step S240: Control circuit 220 determines whether to continue testing the second sleep mode. If yes, proceed to step S245; otherwise, proceed to step S255.

[0032] Step S245: After the second wake-up time W2, the control circuit 220 controls the storage element 30 to enter the second sleep mode (in the light sleep mode control signal Test_LS or the deep sleep mode control signal Test_DS). Figure 3 In the example, the second sleep mode is deep sleep mode (time point t11).

[0033] Step S250: After waiting for the third reference time R3, the control circuit 220 controls the storage element 30 to leave the second sleep mode (time point t12).

[0034] Step S255: After the third wake-up time W3, the storage element test circuit 20 controls the storage element 30 to leave the power mode and enter the function mode according to the recovery signal TEST_RESUME input by the user (time point t13). In response to the recovery signal TEST_RESUME enabling at time point t13, the control circuit 220 sends a de-enabled test notification signal START_PAUSE at time point t14 to notify the user that the storage element 30 has left the power mode.

[0035] Step S260: Control circuit 220 enables storage element 30 (time point t14) through enable / disable signal Test_ME, and reads stored data Q from storage element 30.

[0036] Step S265: Control circuit 220 controls comparator circuit 230 to compare test data Test_D and stored data Q to generate test result BIST_FAIL. When test data Test_D equals stored data Q, storage element 30 passes the test (test result BIST_FAIL is low). Conversely, when test data Test_D does not equal stored data Q, storage element 30 fails the test (test result BIST_FAIL is high, indicating that storage element 30 cannot correctly return from power mode to functional mode).

[0037] Step S270: Control circuit 220 determines whether to continue testing with the inverted data of test data Test_D. If yes, proceed to step S275; otherwise, proceed to step S280. Logic 1 and logic 0 are the inverted data of each other.

[0038] Step S275: Control circuit 220 uses the inverted data of the original test data Test_D as the new test data Test_D, and then repeats steps S225 to S265 (see [link]). Figure 3The time points t14 to t21 correspond to the time points t7 to t14 respectively. For example, if the first execution of step S225 is to write "1010...1010", then the second execution of step S225 is to write "0101...0101".

[0039] Step S280: The storage element test circuit 20 enables the test end signal BIST_DONE to indicate the end of the test.

[0040] Please see Figure 4 , Figure 4 yes Figure 1 Timing diagram of another embodiment of the main signal. Figure 4 The embodiments correspond to the first sleep mode in step S230 and the second sleep mode in step S245, respectively, the deep sleep mode (between time point t9 and time point t10 and between time point t16 and time point t17) and the light sleep mode (between time point t11 ​​and time point t12 and between time point t18 and time point t19).

[0041] It should be noted that when steps S245 and S255 are skipped (i.e., when step S240 is not), Figure 3 and Figure 4 The time points t10 and t12 become the same time point, and the time points t17 and t19 become the same time point.

[0042] In summary, the storage element test circuit 20 of the present invention uses a single test vector (i.e., in a single test procedure) to test two power modes (i.e., the off mode and the light sleep mode or the deep sleep mode, steps S215 to S240 and steps S255 to S265) or three power modes (i.e., the off mode, the light sleep mode and the deep sleep mode, steps S215 to S265), which not only simplifies the complexity of storage element testing, but also saves test time.

[0043] In some embodiments, Figure 2A Steps S215 to S220 can be omitted (i.e., the off mode is not tested), but the second sleep mode is tested (step S240 is yes), so that two power modes (i.e., light sleep mode and deep sleep mode) can be tested in a single test procedure.

[0044] The lengths of the first reference time R1, the first wake-up time W1, the second reference time R2, the second wake-up time W2, the third reference time R3, and the third wake-up time W3 are related to the design, application, and / or testing requirements of the storage element 30, and can be set by the user (e.g., by writing to a register). Furthermore, the user can modify the storage element test circuit 20 to control the storage element 30 during the period when the test notification signal START_PAUSE is high (e.g., ...). Figure 3 The system enters power mode between time points t3 and t7, t8 and t14, and t15 and t21, allowing users to flexibly adjust the lengths of the test notification signal START_PAUSE, the first wake-up time W1, the second wake-up time W2, and the third wake-up time W3.

[0045] Please see Figure 5 , Figure 5 This is a flowchart of an embodiment of the error diagnosis method of the present invention. When Figure 2B If the test result BIST_FAIL in step S265 indicates that the storage element 30 has failed the test, the storage element test circuit 20 can proceed to further execute... Figure 5 The process is used to determine whether the error occurred in the off mode, light sleep mode, or deep sleep mode.

[0046] First, the storage element test circuit 20 tests only the first power mode of the storage element 30 (step S510). When the test result BIST_FAIL indicates that the storage element 30 has failed the test (step S520 is No), it can be determined that the first power mode of the storage element 30 has an error (step S530). When the test result BIST_FAIL indicates that the storage element 30 has passed the test (step S520 is Yes), the storage element test circuit 20 then tests only the second power mode of the storage element 30 (step S540). When the test result BIST_FAIL indicates that the storage element 30 has failed the test (step S550 is No), it can be determined that the second power mode of the storage element 30 has an error (step S570); otherwise (step S550 is No), it can be determined that the third power mode of the storage element 30 has an error (step S560).

[0047] Figure 5 The first, second, and third power modes can be combinations of light sleep mode, deep sleep mode, and off mode. For example, the first, second, and third power modes can be light sleep mode, deep sleep mode, and off mode, or off mode, light sleep mode, and deep sleep mode, respectively.

[0048] Please see Figure 6 , Figure 6 yes Figure 1Timing diagram of another embodiment of the main signal. Figure 6 The example corresponds to testing only the shallow sleep mode of storage element 30. In the mode control signal Test_PM, only the shallow sleep mode control signal Test_LS undergoes a level transition, while the deep sleep mode control signal Test_DS and the off mode control signal Test_SD remain low during the test. Those skilled in the art can then... Figure 6 This generates the mode control signal Test_PM, which corresponds to testing only the deep sleep mode and only the off mode.

[0049] Although the foregoing embodiments use light sleep mode, deep sleep mode and off mode as examples, this is not a limitation of the present invention. Those skilled in the art can appropriately apply the present invention to other types of power modes based on the disclosure of the present invention.

[0050] Since those skilled in the art can understand the implementation details and variations of the method invention in this case through the disclosure of the device invention, to avoid redundancy, repeated descriptions are omitted here without affecting the disclosure requirements and implementability of the method invention. Please note that the shapes, sizes, and proportions of the elements in the foregoing figures are merely illustrative and are intended for those skilled in the art to understand the invention, and are not intended to limit the invention. Furthermore, in some embodiments, the order of the steps mentioned in the foregoing flowchart can be adjusted according to actual operation, and they can even be performed simultaneously or partially simultaneously.

[0051] While the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention. Those skilled in the art can make changes to the technical features of the present invention based on the explicit or implicit content of the present invention. All such changes may fall within the scope of patent protection sought by the present invention. In other words, the scope of patent protection of the present invention shall be determined by the scope of the patent application in this specification.

[0052] [Symbol Explanation]

[0053] 10: Logic Circuits

[0054] 20: Storage Component Test Circuit

[0055] 210: Storage circuit

[0056] 220: Control circuit

[0057] 230: Comparator Circuit

[0058] 242, 244, 246, 248: Multiplexers

[0059] 30: Storage element

[0060] ADDR, Test_ADDR: Address signals

[0061] BIST_CLK: Clock

[0062] BIST_DONE: Test completion signal

[0063] BIST_FAIL: Test Results

[0064] BIST_MODE: Test startup signal

[0065] BIST_RSTN: Reset signal

[0066] D: Input data

[0067] ME, Test_ME: Enable / Disable signal

[0068] PM, Test_PM: Mode control signals

[0069] PMset: Mode setting signal

[0070] Q: Storing data

[0071] START_PAUSE: Test notification signal

[0072] Test_D: Test data

[0073] TEST_RESUME: Recovery signal

[0074] S205, S210, S215, S220, S225, S230, S235, S240, S245, S250, S255, S260, S265, S270, S275, S280, S510, S520, S530, S540, S550, S560, S570: Steps

[0075] R1: First Reference Time

[0076] R2: Second Reference Time

[0077] R3: Third Reference Time

[0078] t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15, t16, t17, t18, t19, t20, t21: Time points

[0079] Test_DS: Deep sleep mode control signal

[0080] Test_LS: Light sleep mode control signal

[0081] Test_SD: Mode control signal off

[0082] W1: First wake-up time

[0083] W2: Second wake-up time

[0084] W3: Third wake-up time.

Claims

1. A memory element test circuit for testing a memory element, comprising: A storage circuit is used to store test data; A comparator circuit is coupled to the storage circuit; A control circuit, coupled to the storage circuit, the comparator circuit, and the storage element, is used to perform the following steps in a single test procedure to test the storage element: A controls the storage element to enter a first power mode, and then controls the storage element to leave the first power mode; B writes the test data into the storage element; C controls the storage element to enter a second power mode, and then controls the storage element to leave the second power mode; and D compares the stored data of the storage element with the test data.

2. The storage element test circuit of claim 1, wherein, The first power mode is a shutdown mode, the second power mode is a light sleep mode, step A precedes step B, and step B precedes step C.

3. The storage element test circuit according to claim 1, wherein, The first power mode is a shutdown mode, the second power mode is a deep sleep mode, step A precedes step B, and step B precedes step C.

4. The storage element test circuit according to claim 3, wherein, The control circuit also performs the following steps: E controls the storage element to enter a light sleep mode, and then controls the storage element to leave the light sleep mode; Step B occurs before step E.

5. The storage element test circuit according to claim 4, wherein, Step C occurs before step E.

6. The storage element test circuit according to claim 4, wherein, Step E occurs before step C.

7. The storage element test circuit according to claim 1, wherein, The first power mode is a deep sleep mode, the second power mode is a light sleep mode, and step B occurs before steps A and C.

8. The storage element test circuit according to claim 7, wherein, Step A occurs before step C.

9. The storage element test circuit according to claim 7, wherein, Step C occurs before step A.

10. A method for testing a storage element, comprising the following steps in a single test procedure: A controls the storage element to enter a first power mode, and then controls the storage element to leave the first power mode; B writes test data into the storage element; C controls the storage element to enter a second power mode, and then controls the storage element to leave the second power mode; and D compares the stored data of the storage element with the test data.

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