Encoder with flash memory controller

Abstract

This invention relates to an encoder and a flash memory controller, wherein the encoder includes: a barrel shift module, a circular convolution calculation circuit, and a compensation circuit. The barrel shift module processes multiple data blocks to sequentially generate multiple local check data blocks. The circular convolution calculation circuit is coupled to the barrel shift module and performs a circular convolution operation on the multiple local check data blocks to generate multiple convolution results. The compensation circuit is coupled to the circular convolution calculation circuit and performs a compensation operation on the multiple convolution results to generate multiple check data blocks, wherein the compensation operation is causal. The multiple data blocks and the multiple check data blocks are written into a flash memory.

Description

Technical Field

[0001] This invention relates to flash memory, and more particularly to an encoder for performing error correction coding in a flash memory storage device, and a related flash memory controller. Background Technology

[0002] Typical encoders rely on a parity-check matrix to verify the correctness of the parity data generated by the encoder. For example, after the encoder encodes data to generate parity data, it multiplies the data and parity data by the parity-check matrix, producing a multiplication result. If the multiplication result equals "0", the encoding is considered correct; if the result is not equal to "0", the encoding is considered incorrect. Instead of the parity-check matrix, the encoder relies on a corresponding parity generation matrix to generate appropriate parity data. However, in some cases, a parity generation matrix may not be available. In such situations, the encoder needs to perform numerous matrix multiplications, compensation operations, and / or adjustment operations to obtain similar parity data (compared to the parity data generated directly using the parity generation matrix). This increases the encoder's complexity, especially since compensation operations are often non-causal, which significantly increases the encoder's hardware cost and circuit complexity. Summary of the Invention

[0003] This invention provides a low-density parity-check (LDPC) encoder architecture that utilizes a tesseract-like parity check matrix with a two-level cyclic structure. This tesseract-like parity check matrix is ​​obtained through an isomorphic transformation of a general quasi-cyclic (QC)-LDPC parity check matrix. Furthermore, the tesseract-like parity check matrix can be decomposed into a hierarchical structure of first-level and second-level submatrices. In one embodiment, one or more non-zero first-level submatrices are block circulant matrices composed of second-level submatrices, and each non-zero second-level submatric is a circulant permutation matrix. The LDPC encoder of this invention, based on the tesseract-like parity check matrix, divides the input data into multiple data blocks, generates corresponding local parity data blocks through a barrel shifter module, and then performs cyclic convolution operations to obtain intermediate results. Next, a compensation circuit is applied to compensate for the intermediate results in order to generate the final verification data block.

[0004] Furthermore, due to the structural characteristics of the four-dimensional hypercube-like parity check matrix, compensation operations can be implemented based on a causal circuit architecture. In this architecture, compensation for each intermediate result depends only on one or more previously generated intermediate results. Compared to conventional non-causal circuit architectures that require buffering all intermediate results before compensation operations, this causal relationship allows the encoder to perform encoding with less latency, lower memory requirements, and more streamlined control logic.

[0005] Embodiments of the present invention provide an encoder comprising: a first barrel shifter module, a first calculation circuit, an adjustment circuit, a first circular convolution calculation circuit, a compensation circuit, and a second calculation circuit. The first barrel shifter module processes multiple data blocks to sequentially generate multiple local check data blocks, wherein each local check data block includes a first portion and a second portion, the first portion being generated earlier than the second portion, and the first portion containing fewer local check data blocks than the second portion. The first calculation circuit, coupled to the first barrel shifter module, generates a first calculation result based on the first portion. The adjustment circuit adjusts the second portion of the multiple local check data blocks based on the first calculation result to generate an adjusted second portion. The first circular convolution calculation circuit, coupled to the adjustment circuit, performs a circular convolution operation on the adjusted first portion to generate a second check data block. The compensation circuit is coupled to the first circular convolution calculation circuit and is used to perform a compensation operation on the second part of the check data block to generate a compensated second part of the check data block, wherein the compensation operation is causal. The second calculation circuit is coupled to the first circular convolution calculation circuit and is used to generate a first part of the check data block based at least on the compensated second part of the check data block. The first part of the check data block and the compensated second part of the check data block are multiple check data blocks generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple check data blocks are written into a flash memory.

[0006] Embodiments of the present invention provide an encoder comprising: a barrel shifter module, an adjustment circuit, a circulant convolution calculation circuit, a compensation circuit, and a calculation circuit. The barrel shifter module processes multiple data blocks to generate multiple local check data blocks, wherein each local check data block includes a first portion and a second portion, the first portion being generated earlier than the second portion, and the first portion containing fewer local check data blocks than the second portion. The adjustment circuit adjusts the second portion of the multiple local check data blocks based on the first portion to generate an adjusted second portion. The circulant convolution calculation circuit is coupled to the adjustment circuit and performs a circulant convolution operation on the adjusted second portion to generate a check data block for the second portion. The compensation circuit is coupled to the circular convolution calculation circuit to perform a compensation operation on the second part of the check data block to generate a compensated second part of the check data block, wherein the compensation operation is causal. The calculation circuit is coupled to the circular convolution calculation circuit to generate a second part of the check data block, at least based on the compensated second part of the check data block. The first part of the check data block and the compensated second part of the check data block are multiple check data blocks generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple check data blocks are written into a flash memory.

[0007] An embodiment of the present invention provides an encoder comprising: a barrel shifting module, a circular convolution calculation circuit, and a compensation circuit. The barrel shifting module processes multiple data blocks to sequentially generate multiple partial parity data blocks. The circular convolution calculation circuit, coupled to the barrel shifting module, performs a circular convolution operation on the multiple partial parity data blocks to generate multiple convolution results. The compensation circuit, coupled to the circular convolution calculation circuit, performs a compensation operation on the multiple convolution results to generate multiple parity data blocks, wherein the compensation operation is causal. The multiple data blocks and the multiple parity data blocks are written into a flash memory. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the architecture of a data storage device and its corresponding memory controller according to an embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram of a parity check matrix of a four-dimensional hypercube-like structure according to an embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram of the QC-LDPC parity check matrix according to an embodiment of the present invention.

[0011] Figure 4 This is a schematic diagram of a parity check matrix and a parity check generator matrix in the form of a four-dimensional hypercube.

[0012] Figure 5 This is a schematic diagram of the encoder according to the first embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram of the encoder according to the second embodiment of the present invention.

[0014] Figure 7 This is a schematic diagram of the encoder according to the third embodiment of the present invention.

[0015] Figure 8 This is a schematic diagram of the encoder according to the fourth embodiment of the present invention.

[0016] Figure 9 This is a schematic diagram of a parity check matrix of a four-dimensional hypercube type and its isomorphic matrix.

[0017] Figure 10 This is a schematic diagram of the encoder according to the fifth embodiment of the present invention.

[0018] Figure 11 This is a schematic diagram of a decoder according to an embodiment of the present invention.

[0019] Figure 12 This is a schematic diagram of the architecture of the shift circuit used to implement the barrel shifter in an embodiment of the present invention.

[0020] [Symbol Explanation]

[0021] 10: Electronic devices

[0022] 50: Main unit

[0023] 52: Processor

[0024] 54: Random Access Memory

[0025] 100: Data storage devices

[0026] 110: Memory controller

[0027] 112: Processing Unit

[0028] 112C: Program Code

[0029] 41, 112M: Read-Only Memory

[0030] 113 Internal Memory

[0031] 114: Control Logic

[0032] 118: Interface Logic

[0033] 120: Flash memory

[0034] 122_1~122_N memory elements

[0035] 130: ECC processing circuit

[0036] 30, 131, 300, 400, 600: Encoder

[0037] 132, 700: Decoder

[0038] 31, 310, 326, 352, 410, 422, 424, 452, 610: Barrel shifter modules

[0039] 32~36, 311~315, 411~415, 612~615, 712~715, 802_1~802_3: Barrel-type shifter

[0040] 37_1~37_5, 317_1~317_5, 332, 334, 336, 357, 358: Accumulation circuit

[0041] 417_1~417_5, 432, 434, 436, 438: Accumulation circuit

[0042] 617_1~617_5, 632, 634, 636, 638, 717_1~717_5: Accumulation circuit

[0043] 320, 420: First computing circuit

[0044] 38, 322, 340, 354, 440, 640: Circular convolution calculation circuits

[0045] 39, 324, 342, 356, 442, 642: Compensation circuits

[0046] 42: Multiplexer

[0047] 43: Calculator

[0048] 330, 430, 630: Adjustment circuit

[0049] 350, 450: Second calculation circuit

[0050] 454: Output Circuit

[0051] 650: Computational Circuit

[0052] 700: Decoder

[0053] 720: LDPC decoding circuit

[0054] 800: Shift circuit

[0055] 801: Upper Shifter

[0056] BLK: Block

[0057] DB_1~DB_43: Data blocks

[0058] D1~DN: Read data blocks

[0059] PPB_1~PPB_5: Local verification data blocks

[0060] IPB_1~IPB_5: Intermediate check data blocks

[0061] PB_1~PB_5: Verification data blocks

[0062] S_1~S_5: Decoding Symptoms

[0063] ID: Input data

[0064] ISD: Intermediate Shift Data

[0065] OSD: Output shift data Detailed Implementation

[0066] Embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the inventive concept can be embodied in various different forms and should not be construed as limited to the embodiments shown. Rather, these embodiments are provided to make this disclosure thorough and complete, and to fully convey the inventive concept to those skilled in the art. Therefore, known processes, elements, and techniques relating to some embodiments of the inventive concept will not be described. Unless otherwise stated, the same reference numerals in the drawings and written description denote the same elements and are therefore not repeated. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0067] The terms "an embodiment" or "an example" used in this specification mean that a particular feature, structure, or characteristic shown in that embodiment or example will be included in at least one embodiment of the invention. Therefore, the terms "in an embodiment" or "in an example" appearing throughout this specification do not all refer to the same embodiment. Furthermore, specific features, structures, or characteristics of the invention may be combined in any suitable combination and / or sub-combination to be implemented in one or more embodiments.

[0068] Figure 1 This diagram illustrates the architecture of an electronic device and a data storage device according to an embodiment of the present invention. As shown, the electronic device 10 includes a host device 50 and a data storage device 100. The host device 50 may include at least one processor 52 for controlling the operation of the host device 50, and a random-access memory (RAM) 54 for storing data and information required by the processor 52. Examples of the host device 50 may include (but are not limited to): smartphones, tablets, wearable devices, personal computers (such as desktop computers or laptops), image capturing devices (such as digital cameras or camcorders), game consoles, in-vehicle navigation systems, printers, scanners, or server systems. Examples of the data storage device 100 may include, but are not limited to: portable storage devices, solid-state drives, and various embedded storage devices.

[0069] In different embodiments of the present invention, the data storage device 100 may include a memory controller 110 and further include non-volatile (NV) memory 120. NV memory 120 may include one or more NV memory elements, such as a plurality of NV memory elements (MUs) 122-1-122_N. In some embodiments, NV memory 120 may be NAND flash memory, and NV memory elements 122_1-122_N may be a plurality of NAND flash memory packages or a plurality of NAND flash memory dies, but the present invention is not limited thereto.

[0070] In some embodiments, the NV memory 120 may include multiple memory blocks (BLKs), which may be grouped into multiple superblocks (SBLKs). A memory block (BLK) may be a physical block containing multiple memory cells. A superblock (SBLK) may be a unit of logical memory region used by the memory controller 110 to manage the NV memory 120. Furthermore, the composition of a superblock (SBLK) may span NV memory dies 122_1 to 122_N. A memory block (BLK) may be an array of memory cells, with multiple memory cells forming a two-dimensional or three-dimensional array structure. A memory cell may be programmed as a single-level memory cell with one bit of information, or as a multi-level memory cell with two or more bits of information (e.g., a two-level, three-level, or four-level memory cell). Additionally, a memory block (BLK) may contain multiple pages, where a page may consist of memory cells coupled to the same word line. Additionally, a memory block (BLK) may be the unit of an erase operation, while a page may be the unit of a program or read operation.

[0071] In some embodiments, each NV memory die 122_1 to 122_N is equipped with control circuitry for executing memory operation commands issued by the memory controller 110. Each NV memory die 122_1 to 122_N may contain multiple planes, each plane having multiple blocks and associated column and row control circuitry. Through multi-plane operation commands, various memory operations can be performed in parallel on different planes to perform multi-plane read, write, or erase operations.

[0072] The memory controller 110 may include a processing unit 112, a read-only memory (ROM) 112M, internal memory 113, a transmission interface circuit 118, and an error correction code (ECC) processing circuit 130. At least a portion of these circuits and components may be coupled to each other via a bus. The internal memory 113 may be implemented by one or more RAM devices. For example, the internal memory 113 may include static RAM (SRAM) and / or dynamic RAM (DRAM). The internal memory 113 may be used to provide internal storage space for the memory controller 110, such as temporarily storing information like data, addresses, commands, mapping information, variables, and / or parameters. In some embodiments, the memory controller 110 may not include DRAM. Instead, the memory controller 110 may rely on host memory buffer (HMB) technology. Using HMB technology, the memory controller 110 can utilize the host device 50's RAM 54 (e.g., DRAM) as all, part, or an extension of the internal memory 113, thereby improving the read and write performance of the data storage device 100.

[0073] Furthermore, in this embodiment, ROM 112M is used to store program code 112C, and processing unit 112 is used to execute program code 112C to control access to NV memory 120. Program code 112C may contain one or more program modules, such as boot loader code. When data storage device 100 obtains power from host device 50, processing unit 112 can initiate the initialization process of data storage device 100 by executing program code 112C. During the initialization process, microprocessor 112 can load a set of in-system programming (ISP) code from NV memory 120. Microprocessor 112 can execute ISP code, enabling data storage device 100 to perform various functions. According to one embodiment of the present invention, the ISP code may include, but is not limited to, one or more program modules related to memory access (e.g., reading, programming, and erasing), such as a read operation module, a lookup table module, a wear-leveling module, a read refresh module, a read reclaim module, a garbage collection module, and a sudden power-off recovery (SPOR) module. These modules are used to perform corresponding read, lookup table, wear-leveling, read refresh, read reclaim, garbage collection, SPOR, and other operations.

[0074] The memory controller 110 can control the reading, writing, and erasing of the NV memory 120. In addition, the memory controller 110 can simultaneously process host commands from the host device 50 to write data, and read and rewrite valid data from the NV memory 120 through garbage collection and / or wear leveling operations. The transmission interface circuit 118 may conform to specific communication specifications, such as Universal Serial Bus (USB), Secure Digital (SD) interface or its subsequent upgrades, Ultra High Speed-I (UHS-I) interface, Ultra High Speed-II (UHS-II) and its subsequent upgrades, Compact Flash (CF) interface and its subsequent upgrades, Multimedia Card (MMC) interface, Embedded Multimedia Card (eMMC) specification, Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Peripheral Component Interconnect Express (PCI-E), and Universal Flash Storage (UFS) specification, and may communicate with the host device 50 according to the specific communication specifications.

[0075] Typically, host device 50 may indirectly access memory device 100 by transmitting host commands and corresponding logical addresses to memory controller 110. Memory controller 110 receives host commands and logical addresses, translates host commands into memory operation commands, and further uses memory operation commands to control NV memory 120 to perform read, program, or erase operations on memory storage cells or data pages with physical addresses within NV memory 120.

[0076] In one embodiment, the ECC processing circuit 130 includes an encoder 131 and a decoder 132, whose encoding and decoding operations are based on a parity-check matrix to generate or verify codewords. Specifically, the encoder 131 uses a generation matrix derived from the parity-check matrix to encode user data received from the host device 50 and outputs corresponding codewords for storage in the NV memory 120. On the other hand, the decoder 132 uses the parity-check matrix to verify the integrity of the codewords retrieved from the NV memory 120 and performs bit error correction if necessary. According to various embodiments of the present invention, the encoder 131 and decoder 132 may be QC-LDPC encoders and decoders for performing quasi-cyclic low-density parity-check (QC-LDPC) encoding and decoding.

[0077] refer to Figure 2 The parity check matrix used in the ECC operation of encoder 131 and decoder 132 may have a tesseract-like structure exhibiting two-level cyclic characteristics. In this embodiment, the tesseract-like parity check matrix H1 can be decomposed into 5×7 first-level submatrixes (FSMs), each FSM being a 96×96 matrix (i.e., Z=96). Each first-level submatrix FSM can be further decomposed into 6×6 second-level submatrixes (SSMs), each SSM being a 16×16 matrix (Z2=16). Although specific matrix dimensions and decompositions are shown in the figures for the purpose of explaining the inventive concept, the invention is not limited thereto.

[0078] like Figure 2As shown, one or more of the first-level submatrices FSM are block circulant matrices. In a block circulant first-level submatrice FSM, each row or column contains only one non-zero second-level submatrice SSM, while all other second-level submatrices SSM are zero matrices. Furthermore, the non-zero second-level submatrices SSM in each row or column are essentially circulant permutation matrices (CPMs). As shown, each subsequent column of a block circulant first-level submatrice FSM is a circulant shift of the previous column (e.g., a circulant shift one position to the right), thus forming a regular cyclic pattern throughout the matrix. Moreover, a circulant permutation matrix is ​​a binary matrix in square row form, where each column is a right circulant shift of one position from its preceding column. A circulant permutation matrix contains exactly one logical "1" element in each column and each row, while all other elements are logical "0". Based on the above arrangement, the parity check matrix H1, which is a four-dimensional hypercube, presents a two-level cyclic structure, including an outer block-wise cyclic permutation and an inner element-wise cyclic permutation.

[0079] In some embodiments, the four-dimensional hypercube-like parity check matrix H1 is isomorphic to the QC-LDPC parity check matrix H0. That is, there is a structural isomorphism between the four-dimensional hypercube-like parity check matrix H1 and the general QC-LDPC parity check matrix H0, where the isomorphic transformation of the two matrices preserves the same basic error correction properties, while enabling more efficient hardware implementation with lower complexity. Figure 3 This illustration depicts a general QC-LDPC parity check matrix according to an embodiment of the present invention. In the illustrated embodiment, the general QC-LDPC parity check matrix H0 can be decomposed into 5×7 submatrices SM, each SM being a 96×96 matrix (Z=96). Furthermore, one or more submatrices SM can be cyclic permutation matrices. In an embodiment of the present invention, a four-dimensional hypercube-like parity check matrix H1 can be obtained by performing an isomorphic transformation on the general QC-LDPC parity check matrix H0. Note that although specific matrix dimensions and decompositions are shown in the figures for the purpose of explaining the inventive concept, the present invention is not limited thereto.

[0080] Figure 4This paper demonstrates the practical principle of ECC encoding based on a four-dimensional hypercube-like parity check matrix H1. As shown in the figure, assume the four-dimensional hypercube-like parity check matrix H1 is c. For a matrix t (e.g., c=5, t=48), the parity check matrix H1 in the form of a four-dimensional hypercube can be decomposed into the left side c The matrix M of (tc) and the right-hand side c To find the parity generation matrix K corresponding to the parity check matrix H1 of the four-dimensional hypercube-like form, we first need to find the inverse matrix K of matrix K. -1 Subsequently, the inverse matrix K... -1 Multiplying matrix M by matrix P yields matrix P, and the transpose of matrix P can be used as the parity generation matrix corresponding to the four-dimensional hypercube-like parity check matrix H1. In other words, after finding the transpose of matrix P, encoder 131 can multiply the input data from host device 50 by the transpose of matrix P to obtain the parity data of the input data. Furthermore, by multiplying the input data and the generated parity data by the four-dimensional hypercube-like parity check matrix H1, the correctness of the encoding can be determined. For example, if the multiplication result is equal to "0", the encoding is considered correct; if the multiplication result is not equal to "0", the encoding is considered incorrect. After determining that the encoding is correct, the input data and the corresponding parity bits will be written into a page or super page in NV memory 120.

[0081] However, in some cases, the inverse matrix K -1 It may not be easy to find. Therefore, encoder 131 needs to perform multiple matrix multiplication operations, compensation operations, and / or adjustment operations to obtain the inverse matrix K. -1 Similar matrices are used to obtain a parity generation matrix to generate parity bits. In view of this, the present invention provides, as follows: Figure 5 The encoder circuit architecture shown is used to perform the above operations.

[0082] like Figure 5As shown, the encoder 30 includes a barrel shifter module 31, a circulant convolution calculation circuit 38, a compensation circuit 39, a ROM (random-access memory) 41, and a multiplexer (MUX) 42. In this embodiment, the barrel shifter module 31 may include multiple barrel shifters 32, 33, 34, 35, and 36, and multiple accumulation circuits 37_1 to 37_5. Furthermore, the encoder 30 can divide the input data from the host device 50 into multiple data blocks (e.g., 43 data blocks DB_1 to DB_43 in this embodiment), and encode these 43 data blocks DB_1 to DB_43 to generate multiple check data blocks (e.g., check data blocks PB_1 to PB_5 in this embodiment). It should be noted that the size of the data blocks is the same as the size of the check data blocks, and the size of the data blocks can be determined by the designer (e.g., 192). (192 bits).

[0083] In the operation of encoder 30, barrel shifter module 31 can sequentially receive and process data blocks DB_1 to DB_43 to generate multiple local verification data blocks PPB_1 to PPB_5. Specifically, barrel shifter 32 can sequentially shift data blocks DB_1 to DB_43, and accumulation circuit 37_1 can accumulate 43 shifted data blocks to obtain local verification data block PPB_1. Barrel shifter 33 sequentially shifts data blocks DB_1 to DB_43, and accumulation circuit 37_2 adds the 43 shifted data blocks to obtain local verification data block PPB_2. Similarly, barrel shifters 34, 35, and 36 can sequentially shift data blocks DB_1 to DB_43, and accumulation circuits 37_3, 37_4, and 37_5 can add the 43 shifted data blocks to obtain local check data blocks PPB_3, PPB_4, and PPB_5.

[0084] The circular convolution calculation circuit 38 can perform circular convolution operations on each local parity data block PPB_1 to PPB_5 to generate convolution results corresponding to the local parity data blocks PPB_1 to PPB_5 (i.e., intermediate parity data blocks IPB_1 to IPB_5). Specifically, the circular convolution calculation circuit 38 can use one of the circular convolution calculation auxiliary information INF_1 and INF_2 read from ROM 41 (selected by MUX 42) to generate intermediate parity data blocks IPB_1 to IPB_5.

[0085] If needed (i.e., the inverse matrix K mentioned above) -1 When it is difficult to calculate, the compensation circuit 39 will perform compensation operations on the intermediate check data blocks IPB_1 to IPB_5 to generate check data blocks PB_1 to PB_5. The compensation circuit 39 will generate check data blocks PB_1-PB_5 using a causal operation. Specifically, the compensation circuit 39 will perform compensation operations on the intermediate check data block of the target based on one or more other intermediate check data blocks IPB_1-IPB_5 that were generated earlier than the target's intermediate check data block. For example, the compensation circuit 39 performs compensation operations on intermediate check data block IPB_2 based on intermediate check data block IPB_1, which was generated earlier than intermediate check data block IPB_2; it performs compensation operations on intermediate check data block IPB_3 based on at least one of intermediate check data blocks IPB_1 and IPB_2, which was generated earlier than intermediate check data block IPB_3; it performs compensation operations on intermediate check data block IPB_4 based on at least one of intermediate check data blocks IPB_1, IPB_2, and IPB_3, which was generated earlier than intermediate check data block IPB_4, and so on.

[0086] Advantageously, by transforming the general QC-LDPC parity check matrix into a four-dimensional hypercube-like parity check matrix H1 with a two-level cyclic structure, the compensation circuit 39 can be implemented in a causal circuit architecture, where the compensation operation for each given intermediate result (e.g., an intermediate check data block) is performed only based on one or more previously generated intermediate results. Therefore, the compensation circuit 39 does not need to access intermediate results that have not yet been generated, which avoids buffering all intermediate results before performing the compensation operation. This causal feature enables the encoder 30 to perform sequential operations, further reducing latency, memory usage, and logical complexity compared to conventional non-causal architectures. This is because in conventional non-causal architectures, compensation for the first check data block may require all intermediate results to be obtained before the operation.

[0087] It should be noted that the encoding process in encoder 30 involves many complex mathematical operations. However, since the focus of this invention is on the design of the circuit architecture, the details of the relevant matrix contents and derivation process are omitted here.

[0088] Figure 6 Another implementation of the encoder 30 according to an embodiment of the present invention is shown. In the illustrated embodiment, the ROM 41 may only store the circular convolution calculation auxiliary information INF_1, and the calculator 43 may be used to generate the circular convolution calculation auxiliary information INF_2.

[0089] To reduce the computational overhead and circuit complexity of the circular convolution calculation circuit and encoder, this invention also proposes the following alternative architecture. (See reference...) Figure 7 This is a schematic diagram of the encoder 300 according to an embodiment of the present invention, wherein the encoder 300 can be used as... Figure 1 The encoder 131 is shown. (As shown) Figure 7 As shown, the encoder 300 includes a barrel shifter module 310, a first calculation circuit 320, an adjustment circuit 330, a circular convolution calculation circuit 340, a compensation circuit 342, and a second calculation circuit 350. In this embodiment, the barrel shifter module 310 includes multiple barrel shifters 311-315 and multiple accumulation circuits 317_1-317_5. The first calculation circuit 320 includes a circular convolution calculation circuit 322, a compensation circuit 324, and a barrel shifter module 326. The adjustment circuit 330 includes multiple accumulation circuits 332, 334, and 336. The second calculation circuit 350 includes a barrel shifter module 352, a circular convolution calculation circuit 354, a compensation circuit 356, and an output circuit composed of accumulation circuits 357 and 358. In this embodiment, the encoder 300 divides a piece of data from the host device 50 into multiple data blocks (43 data blocks DB_1~DB_43 in this embodiment), and encodes the multiple data blocks DB_1~DB_43 to generate multiple check data blocks (5 check data blocks PB_1~PB_5 in this embodiment). It should be noted that the size of the data blocks and the check data blocks is the same, and the size of the data blocks can be determined by the designer, for example, 192. 192 bits.

[0090] In the operation of encoder 300, firstly, barrel shifter module 310 receives data blocks DB_1~DB_43 in sequence and processes them to generate multiple partial parity data blocks PPB_1~PPB_5. Specifically, the barrel shifter 311 can sequentially shift data blocks DB_1 to DB_43, and the 43 shifted data blocks are summed by the accumulator circuit 317_1 to obtain the local parity data block PPB_1; the barrel shifter 312 can sequentially shift data blocks DB_1 to DB_43, and the 43 shifted data blocks are summed by the accumulator circuit 317_2 to obtain the local parity data block PPB_2; similarly, the barrel shifters 313, 314, and 315 can sequentially shift data blocks DB_1 to DB_43, and the 43 shifted data blocks are summed by the accumulator circuits 317_3, 317_4, and 317_5 to obtain the local parity data blocks PPB_3, PPB_4, and PPB_5, respectively.

[0091] The local check data blocks PPB_1 to PPB_5 are divided into two parts for different processing. The first part contains two local check data blocks PPB_1 and PPB_2, while the second part contains three local check data blocks PPB_3 to PPB_5. In the operation of the first calculation circuit 320, the circular convolution calculation circuit 322 performs a circular convolution operation on the local check data blocks PPB_1 and PPB_2 to generate two intermediate blocks. The compensation circuit 324 is an optional component used to compensate for the two intermediate blocks output by the circular convolution calculation circuit 322. In one embodiment, when compensation is necessary, the compensation circuit 324 performs compensation operations on the two intermediate blocks in a causal manner. For example, the compensation circuit 324 performs compensation operations on the intermediate block corresponding to the local check data block PPB_2 based on the intermediate block corresponding to the local check data block PPB_1 (which was generated earlier than the local check data block PPB_2).

[0092] The barrel shifter module 326 can be used to process two intermediate blocks (possibly compensated by the compensation circuit 324, or uncompensated) to produce two result blocks. In this embodiment, since the barrel shifter module 326 produces three result blocks based on the two intermediate blocks, the barrel shifter module 326 may contain six barrel shifters (2... 3=6).

[0093] The accumulator circuits 332, 334, and 336 in the adjustment circuit 330 add the three calculation result blocks generated by the barrel shifter module 326 to the local verification data blocks PPB_3 to PPB_5 in the second part, respectively, to generate the adjusted local verification data blocks.

[0094] Next, the circular convolution calculation circuit 340 performs a circular convolution operation on the adjusted local parity data blocks and generates parity data blocks PB_3 to PB_5 through the compensation circuit 342. In one embodiment, if a compensation operation is required, the compensation circuit 342 performs a compensation operation on the result generated by the circular convolution calculation circuit 340 in a causal manner. For example, the compensation circuit 342 performs a compensation operation on the convolution result corresponding to the local parity data block PPB_4 (generated by the circular convolution calculation circuit 340) based on the convolution result corresponding to the local parity data block PPB_3 (which was generated earlier than the local parity data block PPB_4), and performs a compensation operation on the convolution result corresponding to the local parity data block PPB_5 (generated by the circular convolution calculation circuit 340) based on the convolution result corresponding to at least one of the local parity data blocks PPB_3 and PPB_4 (both of which were generated earlier than the local parity data block PPB_5). It should be noted that the compensation circuit 342 is an optional component and can be removed from the encoder 300 without affecting its operation if compensation calculation is not required.

[0095] Next, in the operation of the second calculation circuit 350, the barrel shifter module 352 processes the check data blocks PB_3~PB_5 to generate two processed blocks. The circular convolution calculation circuit 354 performs circular convolution calculation on the two processed blocks to generate two output blocks. The compensation circuit 356 is an optional component and is used to compensate the two output blocks output by the circular convolution calculation circuit 354 based on causal operation. The accumulation circuits 357 and 358 respectively add the intermediate block generated by the circular convolution calculation circuit 322 or compensated by the compensation circuit 324 to the two output blocks generated by the circular convolution calculation circuit 354 or compensated by the compensation circuit 356 to generate check data blocks PB_1 and PB_2. In this embodiment, since the barrel shifter module 352 generates two processed blocks based on three check data blocks PB_3~PB_5, the barrel shifter module 352 may contain 6 barrel shifters (3 2=6)

[0096] After generating the check data blocks PB_1~PB_5, the encoder 300 multiplies the data blocks DB_1~DB_43 together with the check data blocks PB_1~PB_5 by a parity check matrix (e.g., a four-dimensional hypercube-like parity check matrix H1) to determine if the check data blocks PB_1~PB_5 are correct. If correct, the memory controller 110 writes the data blocks DB_1~DB_43 together with the check data blocks PB_1~PB_5 into a page or a superpage of the NV memory 120.

[0097] exist Figure 7 In the circuit architecture shown, the barrel shifter module 310 can be compared to... Figure 4 The matrix M shown is used to generate a matrix similar to the matrix M in the diagram. The first calculation circuit 320, the adjustment circuit 330, the circular convolution calculation circuit 340, the compensation circuit 342, and the second calculation circuit 350 are used to generate a matrix similar to the matrix M in the diagram. Figure 4 The inverse matrix K shown -1 The content is such that the inverse matrix K cannot be calculated precisely. -1 In this case, verification data blocks PB_1~PB_5 are generated. Furthermore, the encoder 300 has three circular convolution calculation circuits 322, 340, and 354, among which the circular convolution calculation circuit 322 calculates 2... Multiplying two circular matrices / blocks, the circular convolution calculation circuit 340 calculates 3 Multiplying 3 circular matrices / blocks, and calculating 354 circular convolutions using circuit 2. In total, the encoder 300 requires 17 cyclic matrix / block multiplication operations (i.e., 4 + 9 + 4 = 17) to perform 2 cyclic matrix / block multiplication operations. Therefore, since the encoder 300 only needs to perform 17 cyclic matrix / block multiplication operations to generate five check data blocks, this is far fewer than the 25 calculations required by the cyclic convolution calculation circuit 38 in the encoder 30 (5... 5) Circular matrix / block multiplication operations, so the above architecture can indeed reduce the hardware cost and circuit complexity of the encoder.

[0098] In this embodiment, in practice, the encoder 300 processes data blocks DB_1 to DB_43 sequentially, and local verification data blocks PPB_1 to PPB_5 are also generated sequentially. That is, the local verification data blocks PPB_1 and PPB_2 of the first part are generated earlier than the local verification data blocks PPB_3 to PPB_5 of the second part. Therefore, by setting the number of local verification data blocks in the first part to be less than the number of local verification data blocks in the second part, the encoder 300 can be made more efficient in execution. Specifically, by having the first calculation circuit 320 process the first part of local verification data blocks PPB_1 and PPB_2, which are generated earlier, the first calculation circuit 320 can generate three calculation result blocks earlier for the adjustment circuit 330 to use, thereby improving overall efficiency.

[0099] Please refer to Figure 8 This is a schematic diagram of an encoder 400 according to another embodiment of the present invention, wherein the encoder 400 can be used as... Figure 1 The encoder 131 is shown. (As shown) Figure 8 As shown, the encoder 400 includes a barrel shifter module 410, a first calculation circuit 420, an adjustment circuit 430, a circular convolution calculation circuit 440, a compensation circuit 442, and a second calculation circuit 450. In this embodiment, the barrel shifter module 410 includes multiple barrel shifters 411-415 and multiple accumulation circuits 417_1-417_5. The first calculation circuit 420 includes two barrel shifter modules 422 and 424. The adjustment circuit 430 includes multiple accumulation circuits 432, 434, 436, and 438. The second calculation circuit 450 includes a barrel shifter module 452 and an output circuit 454. In this embodiment, the encoder 400 divides a piece of data from the host device 50 into multiple data blocks (43 data blocks DB_1~DB_43 in this embodiment), and encodes the data blocks DB_1~DB_43 to generate multiple check data blocks (5 check data blocks PB_1~PB_5 in this embodiment). It should be noted that the size of the data blocks and the check data blocks is the same, and the size of the data blocks can be determined by the designer, for example, 192. 192 bits.

[0100] In the operation of encoder 400, firstly, barrel shifter module 410 processes data blocks DB_1~DB_43 to generate multiple partial parity data blocks PPB_1~PPB_5. Specifically, the barrel shifter 411 can shift data blocks DB_1 to DB_43 respectively, and add the 43 shifted data blocks together through the accumulation circuit 417_1 to obtain the local parity data block PPB_1; the barrel shifter 412 can shift data blocks DB_1 to DB_43 respectively, and add the 43 shifted data blocks together through the accumulation circuit 417_2 to obtain the local parity data block PPB_2; similarly, the barrel shifters 413, 414, and 415 can shift data blocks DB_1 to DB_43 respectively, and add the 43 shifted data blocks together through the accumulation circuits 417_3, 417_4, and 417_5 to obtain the local parity data blocks PPB_3, PPB_4, and PPB_5 respectively.

[0101] The local check data blocks PPB_1 to PPB_5 are divided into two parts for different processing. The first part contains one local check data block PPB_1, while the second part contains four local check data blocks PPB_2 to PPB_5. In the operation of the first calculation circuit 420, the barrel shifter module 422 shifts the local check data block PPB_1 to generate an intermediate block, and the barrel shifter module 424 processes the intermediate block to generate four calculation result blocks.

[0102] The accumulator circuits 432, 434, 436, and 438 in the adjustment circuit 430 add the four calculation result blocks generated by the barrel shifter module 424 to the local verification data blocks PPB_2 to PPB_5 respectively to generate multiple adjusted local verification data blocks.

[0103] Next, the circular convolution calculation circuit 440 performs a circular convolution operation on the adjusted local parity data blocks (i.e., PPB_2~PPB_5) of the second part, and generates parity data blocks PB_2~PB_5 through the compensation circuit 442. In one embodiment, the compensation circuit 442 performs a compensation operation on the convolution result generated by the circular convolution calculation circuit 440 using a causal operation. For example, the compensation circuit 442 will: perform compensation operations on the convolution result (generated by the circular convolution calculation circuit 440) corresponding to the local verification data block PPB_3 based on the convolution result corresponding to the local verification data block PPB_2 (which was generated earlier than the local verification data block PPB_3); perform compensation operations on the convolution result (generated by the circular convolution calculation circuit 440) corresponding to the local verification data block PPB_4 based on the convolution result corresponding to at least one of the local verification data blocks PPB_2 and PPB_3 (both of which were generated earlier than the local verification data block PPB_4); and perform compensation operations on the convolution result (generated by the circular convolution calculation circuit 440) corresponding to the local verification data block PPB_5 based on the convolution result corresponding to at least one of the local verification data blocks PPB_2, PPB_3, and PPB_4 (both of which were generated earlier than the local verification data block PPB_5). It should be noted that the compensation circuit 442 is an optional component, meaning that it can be removed from the encoder 400 without affecting its operation if compensation calculation is not required.

[0104] Next, in the operation of the second calculation circuit 450, the barrel shifter module 452 processes the verification data blocks PB_1~PB_4 to generate a processed block; the output circuit 454 adds the intermediate block generated by the barrel shifter module 422 to the processed block generated by the barrel shifter module 452 to generate the verification data block PB_1.

[0105] After generating the check data blocks PB_1~PB_5, the encoder 400 multiplies the data blocks DB_1~DB_43 together with the check data blocks PB_1~PB_5 by a four-dimensional hypercube-like parity check matrix H1 to determine if the check data blocks PB_1~PB_5 are correct. If correct, the memory controller 110 writes the data blocks DB_1~DB_43 together with the check data blocks PB_1~PB_5 into a page or a superpage of the NV memory 120.

[0106] exist Figure 8 In the circuit architecture shown, the barrel shifter module 410 can be compared to... Figure 4The matrix M shown is used to generate a matrix similar to the matrix M in the diagram. The first calculation circuit 420, the adjustment circuit 430, the circular convolution calculation circuit 440, the compensation circuit 442, and the second calculation circuit 450 are used to generate a matrix similar to the matrix M in the diagram. Figure 4 The inverse matrix K shown -1 The content of this problem makes it impossible to accurately calculate the inverse matrix K. -1 In this case, verification data blocks PB_1~PB_5 are generated. Furthermore, the encoder 400 has only one circular convolution calculation circuit 440, which is responsible for calculating 4... Multiplying 4 cyclic matrices / blocks results in less than 5 units required by encoder 30. Five cyclic matrix / block multiplications are performed. Therefore, the encoder 400 only needs to perform 16 cyclic matrix / block multiplication operations to generate five check data blocks, effectively reducing the hardware cost and circuit complexity of the encoder.

[0107] In this embodiment, in practice, the encoder 400 processes data blocks DB_1 to DB_43 sequentially, and local verification data blocks PPB_1 to PPB_5 are also generated sequentially. That is, the generation time of the first part of local verification data block PPB_1 is earlier than the generation time of the second part of local verification data blocks PPB_2 to PPB_5. Therefore, by setting the number of the first part of local verification data blocks to be less than the number of the second part of local verification data blocks, the encoder 400 can be made more efficient in execution. Specifically, by having the first calculation circuit 420 process the first part of local verification data block PPB_1, which was generated earlier, the first calculation circuit 420 can generate four calculation result blocks earlier for the adjustment circuit 430 to use, thereby improving the overall efficiency.

[0108] In one embodiment, the designer can transform the four-dimensional hypercube-like parity check matrix H1 to produce an isomorphic matrix, thereby further simplifying the circuit architecture of the encoder 131. Specifically, refer to... Figure 9 This figure locally illustrates the isomorphic matrix of the parity check matrix H1, which is quasi-four-dimensional hypercube-like. For example... Figure 9 As shown, the matrix on the left is a part of a four-dimensional hypercube-like parity check matrix H1 (as in the aforementioned matrix K). Each symbol σ represents a submatrix, and the superscript of the symbol σ indicates how many bits the submatrix has been rotated, for example, "σ 136The symbol "σ" indicates that the submatrix has been rotated by 136 bits. In this embodiment, matrix K can be transformed so that the submatrixes in the top column and leftmost row are converted into an identity matrix. Specifically, the designer can first adjust the rotation number of each submatrix in each column based on the rotation number of the submatrix in the first row (for example, subtract "136" from the rotation number of each submatrix in the first column), gradually so that each submatrix in the first row of matrix K becomes an identity matrix (i.e., "σ"). 0 Next, the designer adjusts the rotation number of each submatrix in each row based on the rotation number of the submatrix in the first column (for example, the rotation number of each submatrix in the second row is reduced by the rotation number of the submatrix in the first column), so that each submatrix in the first column of matrix K becomes an identity matrix (i.e., "σ"). 0 The isomorphic matrix obtained by transforming the local matrix K of the parity check matrix H1 in the form of a four-dimensional hypercube can be as follows: Figure 9 As shown in the right figure, where the superscript S 00 ~S 33 This refers to the number of rotation bits in an isomorphic matrix.

[0109] refer to Figure 10 This is a schematic diagram of an encoder 600 according to another embodiment of the present invention. The encoder 600 can be used as... Figure 1 The encoder 131 is shown. (As shown) Figure 10 As shown, the encoder 600 includes a barrel shifter module 610, an adjustment circuit 630, a circular convolution calculation circuit 640, a compensation circuit 642, and a calculation circuit 650. In this embodiment, the barrel shifter module 610 includes multiple barrel shifters 612-615 and multiple accumulation circuits 617_1-617_5. In this embodiment, the encoder 600 divides a piece of data from the host device 50 into multiple data blocks (43 data blocks DB_1-DB_43 in this embodiment), and encodes the multiple data blocks DB_1-DB_43 to generate multiple check data blocks (5 check data blocks PB_1-PB_5 in this embodiment). It should be noted that the size of the data blocks and the check data blocks is the same, and the size of the data blocks can be determined by the designer, for example, 192. 192 bits.

[0110] In the operation of encoder 600, firstly, barrel shifter module 610 processes data blocks DB_1~DB_43 to generate multiple partial parity data blocks PPB_1~PPB_5. Accumulator circuit 617_1 can directly add 43 data blocks to obtain local parity data block PPB_1. Bucket shifter 612 can shift data blocks DB_1 to DB_43 respectively, and add the 43 shifted data blocks through accumulator circuit 617_2 to obtain local parity data block PPB_2. Similarly, bucket shifters 613, 614, and 615 can shift data blocks DB_1 to DB_43 respectively, and add the 43 shifted data blocks through accumulator circuits 617_3, 617_4, and 617_5 to obtain local parity data blocks PPB_3, PPB_4, and PPB_5 respectively.

[0111] The local check data blocks PPB_1 to PPB_5 are divided into two parts for different processing. The first part contains one local check data block PPB_1, while the second part contains four local check data blocks PPB_2 to PPB_5. The accumulation circuits 632, 634, 636, and 638 in the adjustment circuit 630 add the local check data block PPB_1 to the local check data blocks PPB_2 to PPB_5 respectively to generate the adjusted local check data blocks.

[0112] Next, the circular convolution calculation circuit 640 performs a circular convolution operation on the adjusted second part of the local verification data blocks (i.e., PPB_2~PPB_5), and generates verification data blocks PB_2~PB_5 through the compensation circuit 642. In one embodiment, the compensation circuit 642 performs a compensation operation on the convolution result generated by the circular convolution calculation circuit 640 in a causal manner. For example, the compensation circuit 642 will perform a compensation operation on the convolution result corresponding to the target local verification data block based on one or more convolution results corresponding to one or more other local verification data blocks generated earlier than the target local verification data block. It should be noted that the compensation circuit 642 is an optional component, that is, it can be removed from the encoder 600 without affecting its operation if the compensation operation is not required.

[0113] Next, the calculation circuit 650 adds the local check data block PPB_1 to the check data blocks PB_2~PB_5 to generate the check data block PB_1. After generating the check data blocks PB_1~PB_5, the encoder 600 multiplies the data blocks DB_1~DB_43 together with the check data blocks PB_1~PB_5 by the four-dimensional hypercube-like parity check matrix H1 to determine whether the check data blocks PB_1~PB_5 are correct. If correct, the memory controller 110 writes the data blocks DB_1~DB_43 together with the check data blocks PB_1~PB_5 into a page or a superpage of the NV memory 120.

[0114] exist Figure 10 In the circuit architecture shown, the barrel shifter module 610 can be compared to... Figure 4 The matrix M shown is used to generate a matrix similar to the one described above. The adjustment circuit 630, the circular convolution calculation circuit 640, the compensation circuit 642, and the calculation circuit 650 are all used to generate a matrix similar to the one described above. Figure 4 The inverse matrix K shown -1 The content of this problem makes it impossible to accurately calculate the inverse matrix K. -1 In this case, verification data blocks PB_1~PB_5 are generated. Furthermore, the encoder 600 has only one circular convolution calculation circuit 640, wherein the circular convolution calculation circuit 640 calculates 4... Four cyclic matrix / block multiplications, which is less than the 5 required by encoder 30. Five cyclic matrix / block multiplications. Since the encoder 600 only needs to perform 16 cyclic matrix / block multiplications to generate five check data blocks, the above architecture does indeed reduce the hardware cost and circuit complexity of the encoder. On the other hand, compared to Figure 8 In this embodiment, since some components in the first calculation circuit 420 and the second calculation circuit 450 are omitted, and the barrel shifter module 610 has one less barrel shifter than the barrel shifter module 410, the cost and circuit complexity can be further reduced.

[0115] Furthermore, if adopt Figure 10 The encoder 600 shown allows for further reduction in the circuit architecture of the decoder 132, thus lowering circuit complexity. (Reference) Figure 11 The diagram shows a decoder 700 according to another embodiment of the present invention. The decoder 700 can be used as... Figure 1 The decoder 132 is shown. (As shown) Figure 11As shown, the decoder 700 includes multiple barrel shifters 712-715, multiple accumulator circuits 717_1-717_5, and an LDPC decoding circuit 720. In this embodiment, the decoder 700 receives read data from the NV memory 120, divides the read data into multiple read data blocks D1-DN, calculates multiple read data blocks D1-DN to generate multiple decoding syndromes S_1-S_5, and then transmits the decoding syndromes S_1-S_5 to the LDPC decoding circuit 720 for decoding to correct erroneous bits in the read data.

[0116] In the operation of decoder 700, firstly, accumulator circuit 717_1 can directly add the read data blocks D1~DN to obtain decoding symptom S_1. Bucket shifter 712 can perform shift operations on read data blocks D1~DN respectively, and add multiple shifted read data blocks through accumulator circuit 717_2 to obtain decoding symptom S_2. Similarly, bucket shifters 713, 714, and 715 can perform shift operations on read data blocks D1~DN respectively, and add multiple shifted data blocks through accumulator circuits 717_3, 717_4, and 717_5 to obtain decoding symptom S_3~S_5 respectively.

[0117] Furthermore, since a barrel shifter is not required in the process of generating the decoding symptom S1, the decoder 700 can have fewer components in its circuitry, thereby reducing manufacturing costs.

[0118] In some embodiments, one or more of the barrel shifters 32-36, 311-315, 411-415, 612-615, and 712-715 can be implemented using a hierarchical shift circuit. Please refer to... Figure 12 This illustrates a schematic diagram of a hierarchical shift circuit according to an embodiment of the present invention. Figure 12 As shown, the shift circuit 800 can be used to implement one of the barrel shifters 32~36, 311~315, 411~415, 612~615 and 712~715 in the above embodiments, thereby performing the data shifting operation required for the calculation related to the parity check matrix H1 of the above-mentioned four-dimensional hypercube.

[0119] As shown in the figure, the shift circuit 800 includes an upper shifter 801 and multiple barrel shifters 802_1 to 802_3. The number of barrel shifters can vary depending on the design requirements of the encoder 131 or decoder 132 and / or the structure of the four-dimensional hypercube-like parity check matrix H1. The upper shifter 801 performs a coarse-grained cyclic shift operation on the input data IND (e.g., one of the data blocks DB_1-DB_43) to produce intermediate shifted data ISD. The barrel shifters 802_1 to 802_3 are respectively used to receive a portion of the intermediate shifted data ISD and perform a fine-grained cyclic shift operation on a portion of the intermediate shifted data ISD to produce a portion of the output shifted data.

[0120] Specifically, barrel shifter 802_1 receives the first portion ISD_1 of the intermediate shifted data ISD and performs a fine-grained cyclic shift operation on the first portion ISD_1 to generate the first portion OSD_1 of the output shifted data OSD. Barrel shifter 802_2 receives the second portion ISD_2 of the intermediate shifted data ISD and performs a fine-grained cyclic shift operation on the second portion ISD_2 to generate the second portion OSD_2 of the output shifted data OSD. Barrel shifter 802_3 receives the third portion ISD_3 of the intermediate shifted data ISD and performs a fine-grained cyclic shift operation on the third portion ISD_3 to generate the third portion OSD_3 of the output shifted data OSD.

[0121] Furthermore, barrel shifters 802_1 to 802_3 are used to perform bit-wise cyclic shift operations on each part of the intermediate shifted data ISD. For example, barrel shifter 802_1 performs a bit-wise cyclic shift on the first part ISD_1 of the intermediate shifted data ISD, thereby rotating or cyclically shifting the bits within the first part ISD_1 bit by bit to generate the first part OSD_1 of the output shifted data OSD. Barrel shifter 802_2 performs a bit-wise cyclic shift on the second part ISD_2 of the intermediate shifted data ISD, thereby rotating or cyclically shifting the bits within the second part ISD_2 bit by bit to generate the second part OSD_2 of the output shifted data OSD. The barrel shifter 802_3 is used to perform bit-level cyclic shifting on the third portion ISD_3 of the intermediate shifted data ISD, thereby performing bit-by-bit rotation or cyclic shifting on the bits within the third portion ISD_3 to generate the third portion OSD_3 of the output shifted data OSD. Please note that the number of barrel shifters 802_1 to 802_3 and the number of segments in the input data IND described above are for illustrative purposes only and are not intended to limit the scope of the invention.

[0122] In summary, this invention provides a four-dimensional hypercube-like parity check matrix, which is isomorphic to the general QC-LDPC parity check matrix. This four-dimensional hypercube-like parity check matrix retains basic error correction properties while achieving a more efficient hardware implementation architecture and reducing circuit complexity. In other words, due to the structural characteristics of the four-dimensional hypercube-like parity check matrix, compensation operations can be implemented based on a causal circuit architecture. Compared to conventional non-causal circuit architectures that require buffering all intermediate results before compensation operations, this causal relationship allows the encoder to perform encoding operations with less latency, lower memory requirements, and simplified control logic.

[0123] Embodiments of the present invention can be implemented as an apparatus, method, or computer program product. Accordingly, embodiments of the present invention may take the form of a completely hardware implementation, a completely software implementation, or a combination of software and hardware aspects, all of which are collectively referred to as "modules" or "systems" in this specification. Furthermore, embodiments of the present invention may take the form of a computer program product embodied in any tangible medium containing computer-usable program code. In terms of hardware, the present invention can be implemented by applying any of the following techniques or related combinations: individual operation logic having logic gates capable of performing logical functions based on data signals, and application-specific integrated circuits (ASICs), programmable gate arrays (PGAs), or field-programmable gate arrays (FPGAs) having appropriate combinatorial logic.

[0124] The flowcharts and block diagrams illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of program code, containing one or more executable instructions for implementing a specified logical function. It should also be noted that each block in the block diagram and / or flowchart description, and combinations of blocks in the block diagram and / or flowchart description, may be implemented by a dedicated hardware system that performs the specified function or action, or a combination of dedicated hardware and computer instructions. These computer program instructions may be stored in a computer-readable medium that can direct a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable medium produce an article of manufacture containing means of instruction to implement the functions / actions specified in the blocks of the flowchart and / or block diagram.

[0125] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

Claims

1. An encoder comprising: A first bucket shifter module is used to process multiple data blocks to sequentially generate multiple partial parity data blocks, wherein the multiple partial parity data blocks include a first part and a second part, the first part is generated earlier than the second part, and the number of partial parity data blocks included in the first part is less than the number of partial parity data blocks included in the second part. A first calculation circuit, coupled to the first barrel shifter module, is used to generate a first calculation result based on the first part; An adjustment circuit is used to adjust the second portion of the plurality of local verification data blocks according to the first calculation result, so as to produce an adjusted second portion; A first circulant convolution calculation circuit, coupled to the adjustment circuit, is used to perform a circulant convolution operation on the adjusted first part to generate a second part of the check data block. A compensation circuit, coupled to the first circular convolution calculation circuit, is used to perform a compensation operation on the second part of the check data block to generate a compensated second part of the check data block, wherein the compensation operation is causal. A second calculation circuit, coupled to the compensation circuit, is used to generate a first part of the verification data block based at least on the compensated second part of the verification data block. The first part of the verification data block and the compensated second part of the verification data block are multiple verification data blocks generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple verification data blocks are written into a flash memory.

2. The encoder as described in claim 1, characterized in that, The compensation circuit is used to perform the compensation operation on a convolution result corresponding to each of the second parts of the plurality of local verification data blocks respectively; the compensation circuit compensates the convolution result corresponding to the target local verification data block based on the convolution result corresponding to one or more other local verification data blocks that are generated earlier than the target local verification data block.

3. The encoder as described in claim 1, characterized in that, The first portion of the plurality of local check data blocks includes C1 local check data blocks, and the second portion of the plurality of local check data blocks includes C2 local check data blocks, where C1 is less than C2; the first calculation circuit includes: A second circular convolution calculation circuit is used to perform circular convolution operations on C1 local parity data blocks to generate C1 intermediate blocks; and A second barrel shifter module, coupled to the second cyclic convolution calculation circuit, is used to process the C1 intermediate blocks to generate C2 calculation result blocks as the first calculation result; The adjustment circuit adds the C2 calculation result blocks to the C2 local verification data blocks to generate the adjusted second part.

4. The encoder as described in claim 3, characterized in that, The compensated second part of the verification data block contains C2 compensated verification data blocks, and the second calculation circuit includes: A third barrel shifter module is used to process the C2 compensated verification data blocks to generate C1 processed blocks; A third cyclic convolution calculation circuit, coupled to the third barrel shifter module, is used to perform cyclic convolution operations on C1 processed blocks to generate C1 output blocks. An output circuit, coupled to the third cyclic convolution calculation circuit, is used to adjust the C1 output blocks according to the C1 intermediate blocks to generate C1 check data blocks as the check data blocks of the first part.

5. The encoder as described in claim 3, characterized in that, C1 equals 2, C2 equals 3.

6. The encoder as described in claim 5, characterized in that, Each of the first computing circuit and the second computing circuit includes a compensation circuit that performs a compensation operation in a causal manner.

7. The encoder as claimed in claim 1, characterized in that, A low-density parity check (LDPC) code encoding circuit in a flash memory controller.

8. The encoder as claimed in claim 1, characterized in that, The encoder is used to perform LDPC encoding on multiple data blocks based on a tesseract-like parity check matrix that is isomorphic to a quasi-cyclic (QC)-LDPC parity check matrix.

9. A flash memory controller comprising the encoder as claimed in claim 1.

10. An encoder comprising: A bucket shifter module is used to process multiple data blocks to generate multiple partial parity data blocks, wherein the multiple partial parity data blocks include a first part and a second part, the first part is generated earlier than the second part, and the number of partial parity data blocks included in the first part is less than the number of partial parity data blocks included in the second part. An adjustment circuit is used to adjust the second portion of the plurality of local check data blocks based on the first portion of the plurality of local check data blocks to generate an adjusted second portion. A circulant convolution computation circuit, coupled to the adjustment circuit, is used to perform a circulant convolution operation on the adjusted second part to generate a check data block for the second part. A compensation circuit, coupled to the circular convolution calculation circuit, is used to perform a compensation operation on the second part of the check data block to generate a compensated second part of the check data block, wherein the compensation operation is causal. as well as A computational circuit, coupled to the circular convolution computational circuit, is used to generate a second part of the verification data block based at least on the compensated second part of the verification data block. The first part of the verification data block and the compensated second part of the verification data block are multiple verification data blocks generated by the encoder for the multiple data blocks, and the multiple data blocks and the multiple verification data blocks are written into a flash memory.

11. The encoder as claimed in claim 10, characterized in that, The compensation circuit is used to perform the compensation operation on a convolution result corresponding to each of the second parts of the plurality of local verification data blocks respectively; the compensation circuit compensates the convolution result corresponding to the target local verification data block based on the convolution result corresponding to one or more other local verification data blocks that are generated earlier than the target local verification data block.

12. The encoder as claimed in claim 9, characterized in that, The first part of the multiple local check data blocks contains only one local check data block.

13. The encoder as claimed in claim 10, characterized in that, It is a low-density parity check (LDPC) code encoding circuit in a flash memory controller.

14. The encoder as claimed in claim 10, characterized in that, The encoder is used to perform LDPC encoding on multiple data blocks based on a tesseract-like parity check matrix that is isomorphic to a quasi-cyclic (QC)-LDPC parity check matrix.

15. The encoder as claimed in claim 10, characterized in that, The encoder is used to perform LDPC encoding on multiple data blocks based on a parity check matrix, wherein each submatrix in the first column and the first row of the parity check matrix is ​​an identity matrix.

16. A flash memory controller comprising the encoder as claimed in claim 10.

17. An encoder comprising: A bucket-type shift module is used to process multiple data blocks to sequentially generate multiple partial parity data blocks; A circular convolution calculation circuit, coupled to the bucket shifter module, is used to perform circular convolution operations on multiple local parity data blocks to generate multiple convolution results; and A compensation circuit, coupled to the circular convolution calculation circuit, is used to perform a compensation operation on the multiple convolution results to generate multiple verification data blocks, wherein the compensation operation is causal. in, The multiple data blocks and the multiple check data blocks are written into a flash memory.

18. The encoder as claimed in claim 17, characterized in that, The compensation circuit is used to perform the compensation operation on a convolution result corresponding to each of the plurality of local verifications respectively; the compensation circuit compensates the convolution result corresponding to the target local verification data block based on the convolution result corresponding to one or more other local verification data blocks that are generated earlier than the target local verification data block.

19. The encoder as claimed in claim 17, characterized in that, The encoder is used to perform LDPC encoding on multiple data blocks based on a tesseract-like parity check matrix that is isomorphic to a quasi-cyclic (QC)-LDPC parity check matrix.

20. A flash memory controller comprising the encoder as claimed in claim 17.

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