An integrated dual-frequency power division matching system
By integrating RF circuits and control systems, the high cost and large space occupation problems in dual-frequency multi-channel application scenarios are solved. The integrated dual-band power matching system achieves high integration and low cost RF matching and power distribution, and improves process uniformity and stability.
Patent Information
- Application Number
- CN202611206208.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-10
- Publication Date
- 2026-11-06
AI Technical Summary
Existing technologies require a large number of discrete matching units and RF power supplies in dual-frequency, multi-channel applications, resulting in high costs, large space requirements, complex systems, and poor process uniformity and stability.
An integrated dual-frequency power divider matching system is provided, which integrates radio frequency circuits and control systems. Through matching modules and power divider modules for high-frequency and low-frequency paths, combined with a heterogeneous control architecture of FPGA and DSP, it realizes software-programmable dynamic allocation and precise control of multi-channel power.
It significantly reduces the cost and size of the RF subsystem of semiconductor equipment, improves process uniformity and stability, ensures process uniformity at different locations on the wafer, and improves product yield.
Smart Images
Figure CN123053803A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor process equipment technology, and in particular to an integrated dual-frequency power divider matching system applied in semiconductor processes such as plasma etching and chemical vapor deposition. Background Technology
[0002] In semiconductor process equipment (such as plasma etching and chemical vapor deposition), radio frequency (RF) energy is widely used to excite and sustain plasma in process cavities. To achieve efficient energy transfer between the RF source and the dynamically changing plasma load, impedance matching networks are essential. Traditional matching schemes are mainly based on the following classic passive networks: 1. L-type matching network: As the most basic matching unit, it consists of two reactive elements, offering simple design and low insertion loss. However, its main drawback is the uniqueness of the matching solution, meaning the system bandwidth and quality factor (Q value) are entirely determined by the impedance ratio of the source and load. Designers cannot flexibly adjust it according to requirements, making it only suitable for narrowband applications with low impedance transformation ratios and low bandwidth requirements. 2. Π-type matching network: Composed of three reactive elements, it provides multiple possible combinations of element values to achieve the same impedance matching target, giving designers the ability to control system bandwidth and Q value by selecting different solutions. Its inherent low-pass filter characteristics help suppress harmonics. However, the circuit is sensitive to the parasitic effects of components, especially parallel capacitors. 3. T-type matching network: It is also a three-element structure and has multiple solutions. Its frequency response usually exhibits high-pass characteristics, which may allow higher harmonics to pass through. It is sensitive to parasitic inductance.
[0003] However, as semiconductor manufacturing technology advances towards higher capacity and lower costs, multi-cavity integrated equipment has become the mainstream trend. Against this backdrop, applications requiring multiple RF excitation points within a single process cavity, or the simultaneous use of two different RF power supplies (e.g., high frequency for precise ion energy control, low frequency for high-density plasma generation), are increasingly common. If traditional technology is used to achieve a "dual-frequency, four-channel" excitation scheme, four complete RF power supplies (four high-frequency and four low-frequency) and eight independent matching units are required. This discrete approach has the following significant drawbacks: 1. High cost: RF power supplies and matching units are the core, expensive components of the equipment; doubling their number leads to a sharp increase in cost. 2. Large space occupation: Multiple independent modules occupy a significant amount of internal space, contradicting the design principles of miniaturization and integration. 3. System complexity and poor consistency: Multiple independent loops are difficult to synchronize and distribute power precisely, resulting in poor process uniformity between different process cavities or different points within the same cavity, affecting product yield.
[0004] Therefore, how to provide a highly integrated and low-cost integrated solution for RF matching and power distribution is a problem that urgently needs to be solved in this field. Summary of the Invention
[0005] This application provides an integrated dual-frequency power divider matching system, which solves the problems of high cost, large space occupation, and system complexity caused by the need for a large number of discrete matching units and RF power supplies in dual-frequency multi-channel application scenarios in the prior art. It achieves a significant reduction in system cost and size, and combined with software-programmable dynamic allocation of multi-channel power, it effectively improves the uniformity and stability of semiconductor process.
[0006] This application provides an integrated dual-band power division matching system, including radio frequency circuitry and a control system; The radio frequency circuit includes a high-frequency path and a low-frequency path, which are integrated into a single cavity. Each path integrates a matching module, a power divider module, and a filtering unit. The high-frequency path includes a high-frequency main circuit and at least two parallel high-frequency branch circuits. The high-frequency path receives high-frequency input through the high-frequency main circuit and outputs through each of the high-frequency branch circuits. The high-frequency main circuit is equipped with a high-frequency main adjustable capacitor, and each of the high-frequency branch circuits is connected in series with a high-frequency branch adjustable capacitor and a high-pass filter unit. The high-frequency main adjustable capacitor, together with all the high-frequency branch adjustable capacitors and the high-pass filter unit, constitutes a high-frequency matching module, and all the high-frequency branch adjustable capacitors together constitute a high-frequency power divider module. The low-frequency path includes a low-frequency main circuit and at least two parallel low-frequency branch circuits. The low-frequency path receives low-frequency input through the low-frequency main circuit and outputs through each of the low-frequency branch circuits. The low-frequency main circuit is equipped with a low-frequency main adjustable capacitor, and each of the low-frequency branch circuits is equipped with a low-frequency branch adjustable capacitor and a low-pass filter unit connected in series. The low-frequency main adjustable capacitor, together with all the low-frequency branch adjustable capacitors and the low-pass filter unit, constitutes a low-frequency matching module, and all the low-frequency branch adjustable capacitors together constitute a low-frequency power divider module. The control system is used to control the motors of each adjustable capacitor for matching control and power distribution.
[0007] The beneficial effects of the above embodiments are as follows: The RF circuit of this system utilizes adjustable capacitors in both the high-frequency and low-frequency branches to simultaneously function as matching elements in the high-frequency matching module and power distribution adjustment elements in the power divider module. This significantly reduces the number of components and circuit complexity, achieving a high degree of integration between matching and power division, thereby greatly reducing the cost and size of the RF subsystem in semiconductor equipment. The power distribution of each branch circuit can be achieved by independently adjusting the capacitance value of the corresponding adjustable capacitor, providing a hardware foundation for fine-tuning process uniformity.
[0008] Based on the above embodiments, this application can be further improved as follows: In one embodiment of this application, the number of high-frequency branch circuits is four, the capacitance range of each high-frequency branch adjustable capacitor is the same, and each high-pass filter unit is a fixed capacitor with the same capacitance value; the number of low-frequency branch circuits is four, the capacitance range of each low-frequency branch adjustable capacitor is the same, and each low-pass filter unit is a fixed inductor with the same inductance value.
[0009] Technical effect: By setting the adjustable capacitors in each branch circuit to the same capacitance range and the fixed capacitors and fixed inductors to the same parameters, the consistency of the electrical characteristics of each branch circuit is ensured. This makes the power distribution of each branch circuit equal when the adjustable capacitors are adjusted to the same capacitance value, simplifies the power distribution control model, and improves the power distribution accuracy.
[0010] In one embodiment of this application, the high-frequency main adjustable capacitor is C1, and the high-frequency branch adjustable capacitors are C2, C3, C4, and C5, respectively. The high-pass filter units are fixed capacitors C11, C12, C13, and C14, respectively. One end of C1 is grounded, and the other end is connected to the high-frequency input terminal. At the same time, the other end of C1 is also connected to C2, C3, C4, and C5, respectively. C2 and C11 are connected in series and then connected to output channel one. C3 and C12 are connected in series and then connected to output channel two. C4 and C13 are connected in series and then connected to output channel three. C5 and C14 are connected in series and then connected to output channel four. The low-frequency main adjustable capacitor is C6, and the low-frequency branch adjustable capacitors are C7, C8, C9, and C10, respectively. The low-pass filter units are fixed inductors L1, L2, L3, and L4, respectively. One end of C6 is connected to the low-frequency input terminal, and the other end is connected to C7, C8, C9, and C10, respectively. C7 is connected in series with L1 and then connected to the first output channel. C8 is connected in series with L2 and then connected to the second output channel. C9 is connected in series with L3 and then connected to the third output channel. C10 is connected in series with L4 and then connected to the fourth output channel. Among them, C2, C3, C4, and C5 have the same capacitance range; C11, C12, C13, and C14 have the same capacitance; C7, C8, C9, and C10 have the same capacitance range; and L1, L2, L3, and L4 have the same inductance.
[0011] Technical benefits: It clarifies the connection relationships and parameter configurations of each adjustable capacitor and fixed component, providing a clear and feasible solution for circuit design, ensuring consistent electrical characteristics of each branch circuit, and facilitating mass production and debugging.
[0012] In one embodiment of this application, when the capacitance values of C2, C3, C4, and C5 are the same, the output power ratio of each high-frequency branch circuit is in an equal-sharing mode; when the capacitance values of C2, C3, C4, and C5 are different, the output power ratio of each high-frequency branch circuit is in a programmable non-equal-sharing mode.
[0013] In one embodiment of this application, when the capacitance values of C7, C8, C9, and C10 are the same, the output power ratio of each low-frequency branch circuit is in an equal-sharing mode; when the capacitance values of C7, C8, C9, and C10 are different, the output power ratio of each low-frequency branch circuit is in a programmable non-equal-sharing mode.
[0014] Technical benefits: By independently and continuously adjusting the adjustable capacitors of each branch circuit, the system can flexibly switch between equal and non-equal distribution modes and achieve arbitrary power allocation. It actively compensates for the effects of cavity asymmetry or process fluctuations, and directly improves the process uniformity of different positions on the wafer.
[0015] In one embodiment of this application, the control system includes an FPGA and a DSP. The FPGA is used to drive the motors of each adjustable capacitor, collect sensor data, and communicate with the DSP through a parallel interface. The DSP is used to calculate the target capacitance value of each adjustable capacitor in real time and send control commands to the FPGA.
[0016] Technical benefits: The system employs a heterogeneous control architecture using FPGA and DSP. The FPGA is responsible for high-speed parallel hardware tasks (motor drive, sensor data acquisition and preprocessing), while the DSP is responsible for complex mathematical operations and core control algorithms (impedance calculation, matching algorithm solution, and power distribution PID closed-loop control). The two communicate through an ultra-high-speed parallel interface, achieving fast, decoupled, and precise control of multiple degrees of freedom, ensuring the synchronous and stable operation of the two closed loops of matching and power distribution.
[0017] In one embodiment of this application, the control system further includes a sensor assembly, which includes: an input sensor disposed at each radio frequency input terminal for detecting reflected power; and an output sensor disposed at each output channel for detecting forward power; the data collected by the input sensor and the output sensor are both sent to the FPGA.
[0018] Technical effect: By detecting reflected power through an input sensor to trigger a matching closed loop, and detecting positive power through an output sensor to form a power distribution closed loop, precise control of matching and power distribution is achieved.
[0019] In summary, this invention integrates three major functional modules—dual-frequency matching, four-channel power divider, and inter-band isolation filtering—into a single sealed cavity. This transforms a previously bulky system requiring four high-frequency power supplies, four low-frequency power supplies, and eight matching units into a single high-frequency power supply, one low-frequency power supply, and the matching system described in this invention. This significantly reduces the cost and size of the RF subsystem of semiconductor equipment, shrinking its space footprint by over 70%. Furthermore, by precisely setting the power allocation ratio of each channel through software, it actively compensates for cavity asymmetry or process fluctuations, ensuring process uniformity at different locations on the wafer and directly improving product yield. Attached Figure Description
[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. The elements or parts in the drawings are not necessarily drawn to scale.
[0021] Figure 1 This is an overall architecture diagram of the radio frequency circuit in the embodiments of this application; Figure 2 This is a circuit diagram of the high-frequency path in an embodiment of the present invention; Figure 3 This is a circuit diagram of the low-frequency path in an embodiment of the present invention; Figure 4 This is a structural block diagram of the control system in an embodiment of the present invention; Figure 5 This is a block diagram showing the distribution of sensors in an embodiment of the present invention. Detailed Implementation
[0022] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.
[0023] It should be noted that, in the description of this invention, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0024] In the description of this invention, the illustrative expressions of the terms used above do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this invention, as well as the features of those different embodiments or examples, without contradiction.
[0025] Example: An integrated dual-band power divider and matching system includes radio frequency circuitry and a control system.
[0026] like Figure 1 As shown, the radio frequency circuit is physically a single unit, encapsulated in a single sealed cavity, but electrically it is clearly divided into two independent signal chains: a low-frequency path and a high-frequency path. The outputs of the high-frequency path and the low-frequency path merge to form a mixer output, which is applied together to the load (such as a plasma electrode).
[0027] High-frequency path: like Figure 2 As shown, the high-frequency path includes a high-frequency main circuit and four parallel high-frequency branch circuits. The high-frequency path receives high-frequency input (HF IN) through the high-frequency main circuit and outputs it through each high-frequency branch circuit.
[0028] The high-frequency main circuit includes a high-frequency adjustable capacitor C1, and each high-frequency branch circuit has a high-frequency branch adjustable capacitor and a high-pass filter unit connected in series. Specifically: The first high-frequency branch circuit consists of a series-connected high-frequency branch adjustable capacitor C2 and a fixed capacitor C11 serving as a high-pass filter unit, and is output through output channel one. The second high-frequency branch circuit consists of a series-connected high-frequency branch adjustable capacitor C3 and a fixed capacitor C12 serving as a high-pass filter unit, and is output through output channel two. The third high-frequency branch circuit consists of a series-connected high-frequency branch adjustable capacitor C4 and a fixed capacitor C13 serving as a high-pass filter unit, and is output through the three output channels. The fourth high-frequency branch circuit consists of a series-connected high-frequency branch adjustable capacitor C5 and a fixed capacitor C14 serving as a high-pass filter unit, and is output through output channel four. Among them, C2, C3, C4, and C5 have the same capacitance range, while C11, C12, C13, and C14 have the same capacitance.
[0029] The high-frequency main adjustable capacitor C1, together with all the high-frequency branch adjustable capacitors C2 to C5 and the high-pass filter units C11 to C14, constitute a high-frequency matching module, used for impedance matching of high-frequency input signals. All the high-frequency branch adjustable capacitors C2 to C5 together constitute a high-frequency power divider module, used to distribute high-frequency signals to each high-frequency branch circuit, and to adjust the power distribution ratio of each branch circuit by adjusting the capacitance value of each high-frequency branch adjustable capacitor.
[0030] When the capacitance values of C2 to C5 are the same, the entire network is a four-part network with a power ratio of 1:1:1:1 for the four branches. C2 to C5 can be controlled independently and continuously, achieving adjustable process uniformity.
[0031] The high-pass filter unit in each high-frequency branch circuit consists of a fixed capacitor. Based on the characteristic that a capacitor passes through a high-frequency circuit while having low impedance, the capacitor acts as a pass-through in the high-frequency circuit. Selecting an appropriate capacitor value can suppress low-frequency signals of different frequencies, thereby preventing low-frequency signals from interfering with the high-frequency power supply through the high-frequency branch circuit and avoiding damage to the high-frequency power supply.
[0032] Low-frequency path: like Figure 3 As shown, the low-frequency path includes a low-frequency main circuit and four parallel low-frequency branch circuits. The low-frequency path receives low-frequency input (LF IN) through the low-frequency main circuit and outputs through each low-frequency branch circuit.
[0033] The low-frequency main circuit includes a low-frequency main adjustable capacitor C6, and each low-frequency branch circuit has a low-frequency branch adjustable capacitor and a low-pass filter unit connected in series. Specifically: The first low-frequency branch circuit consists of a low-frequency branch adjustable capacitor C7 connected in series and a fixed inductor L1 serving as a low-pass filter unit, and is output through output channel one. The second low-frequency branch circuit consists of a low-frequency branch adjustable capacitor C8 connected in series and a fixed inductor L2 serving as a low-pass filter unit, and is output through output channel two. The third low-frequency branch circuit consists of a low-frequency branch adjustable capacitor C9 connected in series and a fixed inductor L3 serving as a low-pass filter unit, and is output through the three output channels. The fourth low-frequency branch circuit consists of a low-frequency branch adjustable capacitor C10 connected in series with a fixed inductor L4, which serves as a low-pass filter unit, and outputs through output channel four. Among them, C7, C8, C9, and C10 have the same capacitance range, and L1, L2, L3, and L4 have the same inductance.
[0034] The low-frequency main adjustable capacitor C6, together with all low-frequency branch adjustable capacitors C7 to C10 and low-pass filter units L1 to L4, constitute a low-frequency matching module, used for impedance matching of the low-frequency input signal. All low-frequency branch adjustable capacitors C7 to C10 together constitute a low-frequency power divider module, used to distribute the low-frequency signal to each low-frequency branch circuit, and adjust the power distribution ratio of each branch circuit by adjusting the capacitance value of each low-frequency branch adjustable capacitor.
[0035] When the capacitance values of C7 to C10 are the same, the entire network is a four-part network with a power ratio of 1:1:1:1 for the four branches. C7 to C10 can be controlled independently and continuously, which is the key to achieving adjustable process uniformity.
[0036] The low-pass filter unit in each low-frequency branch circuit consists of a fixed inductor. Due to the high DC resistance of the inductor, it acts as a pass circuit for the low-frequency circuit. By selecting an appropriate inductance value, high-frequency signals of different frequencies can be suppressed, thereby preventing high-frequency signals from entering the low-frequency power supply through crosstalk in the low-frequency branch circuit and avoiding damage to the low-frequency power supply.
[0037] like Figure 4 As shown, the control system includes FPGA, DSP and sensor components, based on a heterogeneous computing architecture of FPGA and DSP to achieve high-speed and high-precision real-time control.
[0038] FPGA: FPGAs are responsible for high-speed, parallel hardware logic tasks, including: 1. Motor drive: Communicates directly with all ten motor drivers that control adjustable capacitors, and quickly executes position commands calculated by the DSP.
[0039] 2. Sensor data acquisition: Collect raw data from all sensors and perform preliminary digital filtering and preprocessing.
[0040] 3. Communication Interface: Data exchange with the DSP is carried out through the UPP (Universal Parallel Port) ultra-high-speed parallel interface to ensure low-latency transmission of control commands and sensor data.
[0041] DSP: The DSP is responsible for complex mathematical operations and core control algorithms, including: 1. Impedance Calculation: Receives preprocessed data from the FPGA and calculates the input and output impedance, forward power, and reflected power of each channel in real time.
[0042] 2. Matching Algorithm: Run the matching control algorithm to find the optimal combination of capacitance values for the ten adjustable capacitors based on the calculated impedance values, so as to minimize the reflected power.
[0043] 3. Power Distribution Algorithm: Receive feedback from the output power sensor and compare it with the preset power values of each channel. Through PID control, dynamically adjust the adjustable capacitors on the power branch circuit to achieve closed-loop control of power distribution.
[0044] It should be noted that the algorithm involved in the DSP is not the focus of the improvement of this invention, and can be implemented according to conventional practices in the field, as long as matching control and power distribution can be achieved.
[0045] Sensor components: like Figure 5 As shown, sensor networks are the foundation for achieving closed-loop control, including input sensors and output sensors.
[0046] 1. Input Sensors: These include high-frequency input sensors located at the high-frequency input terminal and low-frequency input sensors located at the low-frequency input terminal. The input sensors are primarily used to detect reflected power. When a change in load impedance causes mismatch, the reflected power increases, and the control system immediately activates the matching algorithm, driving the adjustable capacitor of the matching module to bring the system back to a matched state.
[0047] 2. Output Sensors: Located in each output channel, these sensors are primarily used to detect forward power. Their detected values are directly fed back to the DSP's power allocation algorithm, where they are compared with the set values to form a closed-loop power allocation control system.
[0048] The technical solutions described in the embodiments of this application above have at least the following technical effects or advantages: 1. Extremely high integration and cost savings: By integrating the three functions of matching, power division and filtering, the original huge system that required 4 high-frequency power supplies, 4 low-frequency power supplies and 8 matching units is integrated into 1 high-frequency power supply, 1 low-frequency power supply and 1 matching system described in this invention, which greatly reduces the cost and size of the radio frequency subsystem of semiconductor equipment.
[0049] 2. Significant space optimization: The integrated design significantly reduces the number of RF connectors and cables, shrinking the space footprint by more than 70%, and providing greater flexibility for the design of other modules in the device.
[0050] 3. Excellent process consistency and controllability: By precisely setting the power allocation ratio of each channel through software, it can actively compensate for cavity asymmetry or process fluctuations, ensuring process uniformity at different locations on the wafer and directly improving product yield.
[0051] 4. Improved system stability and reliability: The system reduces numerous external connection points and independent control units, lowering the failure rate. Intelligent algorithms enable rapid response to drastic changes in plasma load, maintaining system stability and minimizing process interruptions.
[0052] It should be understood that the specific embodiments described above are only for explaining the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. An integrated dual-frequency power divider matching system, characterized in that: Including radio frequency circuits and control systems; The radio frequency circuit includes a high-frequency path and a low-frequency path, and each path integrates a matching module, a power divider module and a filtering unit; The high-frequency path includes a high-frequency main circuit and at least two parallel high-frequency branch circuits. The high-frequency path receives high-frequency input through the high-frequency main circuit and outputs through each of the high-frequency branch circuits. The high-frequency main circuit is equipped with a high-frequency main adjustable capacitor, and each of the high-frequency branch circuits is connected in series with a high-frequency branch adjustable capacitor and a high-pass filter unit. The high-frequency main adjustable capacitor, together with all the high-frequency branch adjustable capacitors and the high-pass filter unit, constitutes a high-frequency matching module, and all the high-frequency branch adjustable capacitors together constitute a high-frequency power divider module. The low-frequency path includes a low-frequency main circuit and at least two parallel low-frequency branch circuits. The low-frequency path receives low-frequency input through the low-frequency main circuit and outputs through each of the low-frequency branch circuits. The low-frequency main circuit is equipped with a low-frequency main adjustable capacitor, and each of the low-frequency branch circuits is equipped with a low-frequency branch adjustable capacitor and a low-pass filter unit connected in series. The low-frequency main adjustable capacitor, together with all the low-frequency branch adjustable capacitors and the low-pass filter unit, constitutes a low-frequency matching module, and all the low-frequency branch adjustable capacitors together constitute a low-frequency power divider module. The control system is used to control the motors of each adjustable capacitor for matching control and power distribution.
2. The integrated dual-frequency power divider matching system according to claim 1, characterized in that: The number of high-frequency branch circuits is four, the capacitance range of each high-frequency branch adjustable capacitor is the same, and each high-pass filter unit is a fixed capacitor with the same capacitance value; the number of low-frequency branch circuits is four, the capacitance range of each low-frequency branch adjustable capacitor is the same, and each low-pass filter unit is a fixed inductor with the same inductance value.
3. The integrated dual-frequency power divider matching system according to claim 2, characterized in that: The high-frequency main adjustable capacitor is C1, and the high-frequency branch adjustable capacitors are C2, C3, C4, and C5, respectively. The high-pass filter units are fixed capacitors C11, C12, C13, and C14, respectively. One end of C1 is grounded, and the other end is connected to the high-frequency input terminal. At the same time, the other end of C1 is also connected to C2, C3, C4, and C5, respectively. C2 and C11 are connected in series and then connected to output channel one. C3 and C12 are connected in series and then connected to output channel two. C4 and C13 are connected in series and then connected to output channel three. C5 and C14 are connected in series and then connected to output channel four.
4. The integrated dual-frequency power divider matching system according to claim 2, characterized in that: The low-frequency main adjustable capacitor is C6, and the low-frequency branch adjustable capacitors are C7, C8, C9, and C10, respectively. The low-pass filter units are fixed inductors L1, L2, L3, and L4, respectively. One end of C6 is connected to the low-frequency input terminal, and the other end is connected to C7, C8, C9, and C10, respectively. C7 is connected in series with L1 and then connected to output channel one. C8 is connected in series with L2 and then connected to output channel two. C9 is connected in series with L3 and then connected to output channel three. C10 is connected in series with L4 and then connected to output channel four.
5. The integrated dual-frequency power divider matching system according to claim 3, characterized in that: When the capacitance values of C2, C3, C4, and C5 are the same, the output power ratio of each high-frequency branch circuit is in an equal-sharing mode; when the capacitance values of C2, C3, C4, and C5 are different, the output power ratio of each high-frequency branch circuit is in a programmable non-equal-sharing mode.
6. The integrated dual-frequency power divider matching system according to claim 4, characterized in that: When the capacitance values of C7, C8, C9, and C10 are the same, the output power ratio of each low-frequency branch circuit is in an equal-sharing mode; when the capacitance values of C7, C8, C9, and C10 are different, the output power ratio of each low-frequency branch circuit is in a programmable non-equal-sharing mode.
7. The integrated dual-frequency power divider matching system according to claim 1, characterized in that: The control system includes an FPGA and a DSP. The FPGA is used to drive the motors of each adjustable capacitor, collect sensor data, and communicate with the DSP through a parallel interface. The DSP is used to calculate the target capacitance value of each adjustable capacitor in real time and send control commands to the FPGA.
8. The integrated dual-frequency power divider matching system according to claim 7, characterized in that: The control system also includes a sensor assembly, which includes: an input sensor disposed at each radio frequency input terminal for detecting reflected power; and an output sensor disposed at each output channel for detecting forward power. The data collected by the input and output sensors are sent to the FPGA.