Bus equalization circuit and power electronic converter system

Abstract

The application discloses a bus voltage equalization circuit and a power electronic converter system, which is applied to a power electronic converter. The circuit comprises: a first charge-discharge circuit connected at two ends of a first capacitor; and a second charge-discharge circuit connected at two ends of a second capacitor. The first charge-discharge circuit and the second charge-discharge circuit are connected in series. The first capacitor and the second capacitor are connected in series to form a DC bus of the power electronic converter. A power supply device is connected in parallel with the DC bus to initialize the first capacitor and the second capacitor to have the same voltage. When the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter works, the first charge-discharge circuit is used for discharging the first capacitor, and the first charge-discharge circuit and the second charge-discharge circuit are used for charging the first capacitor and the second capacitor based on the discharge of the first capacitor, so that the first capacitor and the second capacitor have the same voltage.

Description

Technical Field

[0001] This application relates to the field of power electronic converter technology, and more particularly to a bus voltage equalization circuit and a power electronic converter system. Background Technology

[0002] In a power electronic converter, the DC side of the DC bus is often composed of electrolytic capacitors or film capacitors connected in series, divided into an upper half and a lower half. Initially, the upper and lower half capacitors have the same voltage, indicating voltage balance. The connection terminals of the upper and lower half capacitors correspond to the midpoint of the DC bus and are connected to the power electronic converter.

[0003] After the power electronic converter starts operating, due to software control errors or errors in the hardware parameters themselves, an imbalance may occur between the voltage of the upper and lower half of the bus capacitor, i.e., a DC bias exists, resulting in a DC component in the bus midpoint voltage. If this DC component is severe, it can cause voltage divergence between the upper and lower half of the bus capacitor, leading to risks such as overvoltage failure of the half-bus capacitor and overvoltage breakdown failure of the power switching devices.

[0004] To eliminate the DC bias voltage between the upper and lower bus capacitors and ensure that the half-bus voltage is convergent and free of DC components that cause voltage divergence, a bus voltage equalization circuit is typically added between the upper and lower bus capacitors to balance their voltages. Existing bus voltage equalization circuits control the discharge of the half-bus capacitor with the higher voltage, while charging the other half-bus capacitor with the lower voltage.

[0005] The upper and lower half-bus capacitors must operate in pairs; when one is charging, the other must discharge, and the capacitor with the higher voltage can only transfer energy to the capacitor with the lower voltage. This results in limited energy transfer and low energy utilization efficiency for the half-bus capacitors. Summary of the Invention

[0006] The purpose of this application is to provide a bus voltage equalization circuit and a power electronic converter system to solve the problems of limited energy transfer and low utilization efficiency of the half-bus capacitor in existing bus voltage equalization circuits.

[0007] To solve the above-mentioned technical problems, this specification is implemented as follows: In a first aspect, a bus voltage equalization circuit is provided for use in a power electronic converter, the circuit comprising: The first charging and discharging circuit is connected across the first capacitor. The second charging and discharging circuit is connected across the second capacitor. The first charging and discharging circuit and the second charging and discharging circuit are connected in series. The first capacitor and the second capacitor are connected in series to form the DC bus of the power electronic converter. The power supply equipment is connected in parallel with the DC bus to initialize the first capacitor and the second capacitor to have the same voltage. The first charging and discharging circuit includes a first power switching device, a third power switching device, a first inductor, a first diode, and a third diode; the second charging and discharging circuit includes a second power switching device, a fourth power switching device, a second inductor, and a fourth diode. One end of the first diode is connected to one end of the second power switching device and one end of the second inductor, respectively; the other end of the first diode is connected to one end of the first power switching device and one end of the first inductor, respectively. One end of the third power switch is connected to one end of the fourth power switch, the other end of the third power switch is connected to the other end of the first inductor, and is connected to the other end of the first power switch and the first capacitor via the third diode; the other end of the fourth power switch is connected to the other end of the second inductor, and is connected to the other end of the second power switch and the second capacitor via the fourth diode. When the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter is working, the first charging and discharging circuit is used to discharge the first capacitor. The first charging and discharging circuit and the second charging and discharging circuit are used together to charge the DC bus composed of the first capacitor and the second capacitor based on the discharge of the first capacitor, so that the first capacitor and the second capacitor have the same voltage.

[0008] Secondly, a power electronic converter system is provided, comprising: As described in the first aspect, the bus equalization circuit; and The power electronic converter, power supply equipment, and drive circuit; Wherein, when the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter is working, the driving circuit controls the first charging and discharging circuit to discharge the first capacitor, and controls the first charging and discharging circuit and the second charging and discharging circuit to jointly charge the first capacitor and the second capacitor based on the discharge of the first capacitor; and / or When the voltage of the second capacitor is higher than the voltage of the first capacitor after the power electronic converter is working, the driving circuit controls the second charging and discharging circuit to discharge the second capacitor, and controls the first charging and discharging circuit and the second charging and discharging circuit to charge the first capacitor and the second capacitor based on the discharge of the second capacitor.

[0009] In this embodiment, when the voltage of the first capacitor is higher than that of the second capacitor, the first capacitor is first discharged through the first charging and discharging circuit of the bus voltage equalization circuit. Then, based on the discharge of the first capacitor, the first and second charging and discharging circuits of the bus voltage equalization circuit jointly charge the first and second capacitors, achieving voltage equalization between the first and second capacitors. Thus, during voltage equalization, energy transfer from the high-voltage first capacitor to the entire bus capacitor (first and second capacitors) can be achieved. The transferred energy can be directly utilized by other parts of the electronic power system, resulting in high recycling efficiency. Furthermore, it facilitates smooth and continuous energy transfer, extending the service life of the bus capacitors. In addition, the upper and lower half-bus capacitors do not need to operate in pairs, making the voltage equalization strategy more flexible. However, this also leads to limited energy transfer and low energy utilization efficiency in the half-bus capacitors. Attached Figure Description

[0010] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural block diagram of a bus voltage equalization circuit according to an embodiment of this application.

[0011] Figure 2 This is a structural block diagram of a bus voltage equalization circuit according to another embodiment of this application.

[0012] Figures 3 to 5 This is a schematic diagram of the charging and discharging current path of a charging and discharging circuit according to an embodiment of this application.

[0013] Figures 6 to 8 This is a schematic diagram of the charging and discharging current path of a charging and discharging circuit according to another embodiment of this application.

[0014] Figures 9 to 10 This is a schematic diagram of the charging and discharging current path of a charging and discharging circuit according to another embodiment of this application.

[0015] Figure 11 This is a schematic diagram of the circuit structure of the control unit in an embodiment of this application; Figures 12 to 15 These are structural block diagrams of power electronic converter systems according to different embodiments of this application. Detailed Implementation

[0016] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. The drawing numbers in this application are only used to distinguish the various steps in the solution and are not used to limit the execution order of the various steps. The specific execution order is subject to the description in the specification.

[0017] To address the problems existing in the prior art, this application provides a bus voltage equalization circuit applied to a power electronic converter. The DC side of the power electronic converter in this application includes a DC bus, which is composed of two capacitors connected in series and used as the upper and lower half of the bus, respectively. The series connection terminals of the two capacitors correspond to the midpoint of the DC bus.

[0018] In one embodiment, the bus equalization circuit of this application includes: a first charging and discharging circuit connected across a first capacitor; and a second charging and discharging circuit connected across a second capacitor. The first charging and discharging circuit and the second charging and discharging circuit are connected in series. The first capacitor and the second capacitor are connected in series to form the DC bus of the power electronic converter. A power supply device is connected in parallel with the DC bus to initialize the first capacitor and the second capacitor to have the same voltage. Wherein, when the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter is working, the first charging and discharging circuit is used to discharge the first capacitor. The first charging and discharging circuit and the second charging and discharging circuit are used together to charge the first capacitor and the second capacitor based on the discharge of the first capacitor.

[0019] like Figure 1 As shown in the embodiment, the bus equalization circuit 10 includes a first charging and discharging circuit 100 and a second charging and discharging circuit 200. The DC side of the power electronic converter 24 includes a DC bus composed of a first capacitor C1 and a second capacitor C2 connected in series. The power supply device 30 is connected in parallel with the DC bus.

[0020] The first charging and discharging circuit 100 is connected across the first capacitor C1, and the second charging and discharging circuit 200 is connected across the second capacitor C2. The first charging and discharging circuit 100 and the second charging and discharging circuit 200 are connected in series.

[0021] The power electronic converter 24 includes a bidirectional DC-DC converter and a bidirectional DC-AC converter for bidirectional AC-DC conversion. When the power supply device 30 discharges, it supplies DC power to the power electronic converter 24 through the DC bus, which then converts it to DC or AC power to supply power to the corresponding load. Alternatively, the power electronic converter 24 converts the corresponding DC or AC power to DC power and then charges the power supply device 30 through the DC bus.

[0022] When the power supply device 30 discharges, the first capacitor C1 and the second capacitor C2 of the DC bus are initialized with voltage. Theoretically, the initial voltage values ​​of the first capacitor C1 and the second capacitor C2 are the same.

[0023] During the operation of the power electronic converter 24, due to potential software control accuracy errors, hardware circuit parameter errors, or the user connecting a half-wave load to the AC side of the power electronic converter system, the DC components of the voltages on the first capacitor C1 and the second capacitor C2 of the upper and lower half-buses may become uneven or unequal. For example, the voltage of the first capacitor C1 may be higher than the voltage of the second capacitor C2, or vice versa.

[0024] In severe cases, it can cause voltage divergence in the first capacitor C1 and the second capacitor C2, leading to risks such as overvoltage failure of the half-bus capacitor and overvoltage breakdown failure of the main power switching device of the power electronic converter 24.

[0025] In this embodiment, when the voltage of the first capacitor C1 is higher than the voltage of the second capacitor C2, the first capacitor C1 is first discharged through the first charging and discharging circuit of the bus voltage equalization circuit. Then, based on the discharge of the first capacitor C1, the first charging and discharging circuit and the second charging and discharging circuit of the bus voltage equalization circuit jointly charge the first capacitor C1 and the second capacitor C2, thereby achieving voltage equalization between the first capacitor C1 and the second capacitor C2.

[0026] Therefore, during voltage equalization, energy transfer can be achieved from the high-voltage first capacitor C1 to the full bus capacitors (first capacitor C1 and second capacitor C2). The transferred energy can be directly utilized by other parts of the electronic power system, resulting in high recycling efficiency. Furthermore, it facilitates smooth and continuous energy transfer, extending the lifespan of the bus capacitors. In addition, the upper and lower half-bus capacitors do not need to operate in pairs, making the voltage equalization strategy more flexible. However, this also limits energy transfer and reduces energy utilization efficiency in the half-bus capacitors.

[0027] In one embodiment, the first charging and discharging circuit includes a first power switching device, a third power switching device, a first inductor, a first diode, and a third diode; The first terminal of the first power switch is connected to the first terminal of the first capacitor, the second terminal of the first power switch is connected to the first terminal of the first inductor, and the third terminal of the first power switch is connected to the driving circuit. The first terminal of the third power switch is connected to the second terminal of the first inductor, the second terminal of the third power switch is connected to the second terminal of the first capacitor, and the third terminal of the third power switch is connected to the driving circuit. The first end of the first diode is connected to the first end of the first inductor, and the second end of the first diode is connected to the second charging and discharging circuit. The first end of the third diode is connected to the first end of the first capacitor, and the second end of the third diode is connected to the second end of the first inductor.

[0028] like Figure 1 As shown, the first charging and discharging circuit 100 includes a first power switching device Q1, a third power switching device Q3, a first inductor L1, a first diode D1, and a third diode D3.

[0029] The first terminal of the first power switch Q1 corresponds to the output terminal, the second terminal of the first power switch Q1 corresponds to the input terminal, and the third terminal of the first power switch Q1 corresponds to the control terminal.

[0030] Similarly, the first terminal of the third power switch Q3 corresponds to the output terminal, the second terminal of the third power switch Q3 corresponds to the input terminal, and the third terminal of the third power switch Q3 corresponds to the control terminal.

[0031] The end of the first capacitor C1 that is not connected to the second capacitor C2 is called the first end, which is connected to either the positive or negative voltage output terminal of the power supply device 30. The end of the first capacitor C1 that is connected to the second capacitor C2 is called the second end, which is connected to the first end of the second capacitor C2 and forms the midpoint O of the DC bus.

[0032] Correspondingly, the end of the second capacitor C2 connected to the first capacitor C1 is the first end; the end of the second capacitor C2 not connected to the first capacitor C1 is the second end, which is connected to the negative voltage output terminal or the positive voltage output terminal of the power supply device 30. Figure 1 In this embodiment, the first end of the first capacitor C1 is connected to the positive voltage output terminal of the power supply device 30, and the second end of the second capacitor C2 is connected to the negative voltage output terminal of the power supply device 30.

[0033] Specifically, the first terminal of the first power switch device Q1 is connected to the first terminal of the first capacitor C1, the second terminal of the first power switch device Q1 is connected to the first terminal of the first inductor L1, and the third terminal of the first power switch device Q1 is connected to the drive circuit.

[0034] The first terminal of the third power switch Q3 is connected to the second terminal of the first inductor L1, the second terminal of the third power switch Q3 is connected to the second terminal of the first capacitor C1, and the third terminal of the third power switch Q3 is connected to the drive circuit.

[0035] The drive circuit is used to control the on and off of the first power switching device Q1 and the third power switching device Q3 in the first charging and discharging circuit 100.

[0036] The first terminal of the first diode D1 corresponds to the cathode, and the second terminal of the first diode D1 corresponds to the anode; similarly, the first terminal of the third diode D3 corresponds to the cathode, and the second terminal of the third diode D3 corresponds to the anode.

[0037] Specifically, the first terminal of the first diode D1 is connected to the first terminal of the first inductor L1, and the second terminal of the first diode D1 is connected in series with the second charging and discharging circuit 200. The first terminal of the third diode D3 is connected to the first terminal of the first capacitor C1, and the second terminal of the third diode D3 is connected to the second terminal of the first inductor L1.

[0038] That is, one end of the first inductor L1 is connected to the first diode D1 and the first power switch Q1, and the other end of the first inductor L1 is connected to the third diode D3 and the third power switch Q3.

[0039] In one embodiment, the second charging and discharging circuit includes a second power switching device, a fourth power switching device, a second inductor, and a fourth diode; The first terminal of the second power switch is connected to the second terminal of the second inductor, the second terminal of the second power switch is connected to the second terminal of the second capacitor, and the third terminal of the second power switch is connected to the drive circuit. The first terminal of the fourth power switch is connected to the first terminal of the second capacitor, the second terminal of the fourth power switch is connected to the first terminal of the second inductor, and the third terminal of the fourth power switch is connected to the drive circuit. The second terminal of the second inductor is connected to the second terminal of the first diode; The first terminal of the fourth diode is connected to the first terminal of the second inductor, and the second terminal of the fourth diode is connected to the second terminal of the second capacitor. The second end of the first capacitor is connected to the first end of the second capacitor and forms the midpoint of the DC bus connection to the power electronic converter.

[0040] like Figure 1 As shown, the second charging and discharging circuit includes a second power switching device Q2, a fourth power switching device Q4, a second inductor L2, and a fourth diode D4.

[0041] The first terminal of the second power switch Q2 corresponds to the output terminal, the second terminal of the second power switch Q2 corresponds to the input terminal, and the third terminal of the second power switch Q2 corresponds to the control terminal.

[0042] Similarly, the first terminal of the fourth power switch Q4 corresponds to the output terminal, the second terminal of the fourth power switch Q4 corresponds to the input terminal, and the third terminal of the fourth power switch Q4 corresponds to the control terminal.

[0043] Specifically, the first terminal of the second power switch Q2 is connected to the second terminal of the second inductor L2, the second terminal of the second power switch Q2 is connected to the second terminal of the second capacitor C2, and the third terminal of the second power switch Q2 is connected to the drive circuit.

[0044] The first terminal of the fourth power switch Q4 is connected to the first terminal of the second capacitor C2, the second terminal of the fourth power switch Q4 is connected to the first terminal of the second inductor L2, and the third terminal of the fourth power switch Q4 is connected to the drive circuit.

[0045] The drive circuit is also used to control the on and off of the second power switch Q2 and the fourth power switch Q4 within the second charging and discharging circuit 200.

[0046] The first terminal of the fourth diode D4 corresponds to the cathode, and the second terminal of the fourth diode D4 corresponds to the anode.

[0047] Specifically, the first terminal of the fourth diode D4 is connected to the first terminal of the second inductor L2, and the second terminal of the fourth diode D4 is connected to the second terminal of the second capacitor C2. The second terminal of the second inductor L2 is connected to the second terminal of the first diode D1 in the first charging and discharging circuit 100.

[0048] The second end of the first capacitor C1 is connected to the first end of the second capacitor C2, forming the midpoint of the DC bus, which is connected to the power electronic converter 24.

[0049] That is, one end of the second inductor L2 is connected to the first diode D1 and the second power switch Q2, and the other end of the second inductor L2 is connected to the fourth diode D4 and the fourth power switch Q4.

[0050] In one embodiment, the second charging and discharging circuit further includes a second diode, the first end of which is connected to the second end of the first diode, and the second end of which is connected to the second end of the second inductor.

[0051] Combination Figure 2 ,and Figure 1In contrast, the second charging and discharging circuit 200 also includes a second diode D2, with its first end connected to the second end of the first diode D1 and its second end connected to the second end of the second inductor L2.

[0052] In this embodiment, by adding a second diode D2 to the second charging and discharging circuit 200 and connecting it in series with the first diode D1 of the first charging and discharging circuit 100, the corresponding voltage pressure can be shared by multiple diodes during the subsequent charging and discharging processes of the first charging and discharging circuit 100 and the second charging and discharging circuit 200, thereby achieving the effect of sharing the voltage stress among multiple diodes and reducing the voltage stress of the corresponding power switching device.

[0053] The bus voltage equalization circuit with the above structure will be described below in conjunction with different industrial control systems.

[0054] In one embodiment, when the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter is working, the drive circuit controls the second power switch and the fourth power switch to remain off, and controls the first power switch and the third power switch to be turned on or off simultaneously. When the first power switching device and the third power switching device are turned on simultaneously, the first capacitor discharges to charge the first inductor through the first power switching device and the third power switching device, and the first inductor stores energy. When the first power switch and the third power switch are turned off simultaneously, the first inductor releases energy to charge the first capacitor and the second capacitor through the second power switch, the first diode, and the third diode.

[0055] After the power electronic converter starts working, if the voltage of the first capacitor C1 is detected to be higher than the voltage of the second capacitor C2, indicating uneven voltage distribution on the DC bus, the drive circuit can control the corresponding power switching devices to turn on and off through the drive signal, thereby controlling the first charging and discharging circuit 100 and the second charging and discharging circuit 200 to perform the corresponding charging and discharging.

[0056] Figures 3 to 5 The current path during the operation of the bus voltage equalization circuit is shown. When the voltage of the first capacitor C1 is higher than the voltage of the second capacitor C2, the drive circuit controls the second power switch Q2 and the fourth power switch Q4 of the second charging and discharging circuit 200 to remain off, and controls the first power switch Q1 and the third power switch Q3 of the first charging and discharging circuit 100 to be turned on or off at the same time.

[0057] Figure 3A schematic diagram of the circuit path when the first power switch Q1 and the third power switch Q3 are simultaneously turned on, with the second power switch Q2 and the fourth power switch Q4 kept off.

[0058] like Figure 3 As shown, the first capacitor C1 discharges and charges the first inductor L1 through the communication between the first power switch Q1 and the third power switch Q3, and the first inductor L1 stores energy.

[0059] Figure 4 and Figure 5 This is a schematic diagram of the circuit path when the first power switch Q1 and the third power switch Q3 are simultaneously turned off, with the second power switch Q2 and the fourth power switch Q4 kept off, respectively.

[0060] like Figure 4 and Figure 5 As shown, the first inductor L1 releases energy to charge the first capacitor C1 and the second capacitor C2 through the second power switching device Q2, the second diode D2, the first diode D1, and the third diode D3.

[0061] Figure 4 and Figure 5 The only difference is the type of the second power switching device Q2 used, which corresponds to the charging current flowing through different components of the second power switching device Q2.

[0062] Specifically, the second power switching device is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT); when the second power switching device is a MOSFET, the corresponding charging current flows from the source of the MOSFET to the drain of the MOSFET; when the second power switching device is an IGBT, the corresponding charging current flows from the anode of the body diode of the IGBT to the cathode of the body diode of the IGBT.

[0063] like Figure 4 As shown, when the second power switching device Q2 is a MOSFET transistor, the corresponding charging current flows through the channel from the source (S) of the channel of the second power switching device Q2 to the drain (D) of the second power switching device Q2.

[0064] like Figure 5 As shown, when the second power switching device Q2 is an IGBT transistor, the corresponding charging current flows through the body diode from the anode of the body diode of the second power switching device Q2 to the cathode of the body diode of the second power switching device Q2.

[0065] The conduction loss generated by the same current flowing through the channel of a MOSFET transistor is significantly lower than the switching loss generated by the body diode of the MOSFET transistor. For example, when the current is 10A, the loss of the body diode can reach 7W, while the loss of the channel is only 0.2W.

[0066] Therefore, to reduce the high-frequency switching losses of the power switching devices, in one embodiment, when the second power switching device is a MOSFET, controlling both the second and fourth power switching devices to remain off is replaced by controlling the fourth power switching device to remain off while the second power switching device remains on; or When the second power switch is a MOSFET, controlling the second power switch and the fourth power switch to remain off is replaced by controlling the fourth power switch to remain off, and the on / off states of the second power switch and the first power switch and the third power switch are complementary.

[0067] In this embodiment, if the second power switch Q2 is a MOSFET transistor, then in order to reduce switching losses, the second power switch Q2 can be controlled to remain on. Alternatively, the on / off state of the second power switch Q2 can be controlled to be complementary to the on / off states of the first power switch Q1 and the third power switch Q3.

[0068] The complementary on / off states include: if the first power switch Q1 and the third power switch Q3 are both on, then the second power switch Q2 is off; if the first power switch Q1 and the third power switch Q3 are both off, then the second power switch Q2 is on.

[0069] In the above alternative embodiment, the fourth power switch Q4 remains off and is not changed.

[0070] Furthermore, when the second power switch Q2 is an IGBT transistor, due to the high conduction loss of the body diode, the replacement of the second power switch Q2 will not be performed in order to reduce the switching loss, and the second power switch Q2 will remain off.

[0071] In summary, when the second power switching device Q2 is an IGBT transistor, because the current of the IGBT transistor cannot flow from the emitter to the collector of the channel, and the current only passes through the body diode, the second power switching device Q2 remains off when the voltage of the first capacitor C1 is higher than the voltage of the second capacitor C2. This can reduce the switching loss of the second power switching device Q2.

[0072] When the second power switch Q2 is a MOSFET transistor, because the current of the MOSFET transistor can flow from the source to the drain of the channel, the conduction loss of the current through the channel is lower than that through the body diode. Therefore, when the voltage of the first capacitor C1 is higher than the voltage of the second capacitor C2, the second power switch Q2 can remain off, remain on, or complement the on / off state of the corresponding first power switch Q1 and third power switch Q3.

[0073] If the on / off states of the second power switch Q2 are complementary to those of the first power switch Q1 and the third power switch Q3, the switching losses of the second power switch Q2 will increase. Therefore, it is not suitable for applications with high efficiency requirements.

[0074] In one embodiment, when the voltage of the second capacitor is higher than the voltage of the first capacitor after the power electronic converter is operating, the second charging and discharging circuit is used to discharge the second capacitor. The first charging and discharging circuit and the second charging and discharging circuit are used together to charge the first capacitor and the second capacitor based on the discharge of the second capacitor, so that the first capacitor and the second capacitor have the same voltage.

[0075] As mentioned above, when the power supply device 30 discharges, the first capacitor C1 and the second capacitor C2 of the DC bus are initialized with voltage. Theoretically, the initial voltage values ​​of the first capacitor C1 and the second capacitor C2 are the same.

[0076] During the operation of the power electronic converter 24, due to potential software control accuracy errors, hardware circuit parameter errors, or the user connecting a half-wave load to the AC side of the power electronic converter system, the DC components of the voltages on the first capacitor C1 and the second capacitor C2 of the upper and lower half-buses may become uneven or unequal. For example, the voltage of the second capacitor C2 may be higher than the voltage of the first capacitor C1.

[0077] In this embodiment, when the voltage of the second capacitor C2 is higher than the voltage of the first capacitor C1, the second capacitor C2 is first discharged through the second charging and discharging circuit 200 of the bus voltage equalization circuit. Then, based on the discharge of the second capacitor C2, the first capacitor C1 and the second capacitor C2 are charged together through the first charging and discharging circuit and the second charging and discharging circuit of the bus voltage equalization circuit, thereby achieving voltage equalization between the first capacitor C1 and the second capacitor C2.

[0078] Therefore, during voltage equalization, energy transfer can be achieved from the high-voltage second capacitor C2 to the full bus capacitor (first capacitor C1 and second capacitor C2). The transferred energy can be directly utilized by other parts of the electronic power system, resulting in high recycling efficiency. Furthermore, it facilitates smooth and continuous energy transfer, extending the lifespan of the bus capacitors. In addition, the upper and lower half-bus capacitors do not need to operate in pairs, making the voltage equalization strategy more flexible. However, this also limits energy transfer and reduces energy utilization efficiency in the half-bus capacitors.

[0079] In one embodiment, when the voltage of the second capacitor is higher than the voltage of the first capacitor after the power electronic converter is working, the drive circuit controls the first power switch and the third power switch to remain off, and controls the second power switch and the fourth power switch to be turned on or off simultaneously. When the second power switch and the fourth power switch are turned on simultaneously, the second capacitor discharges to charge the second inductor through the second power switch and the fourth power switch, and the second inductor stores energy. When the second power switch and the fourth power switch are turned off simultaneously, the second inductor releases energy to charge the first capacitor and the second capacitor through the first diode, the first power switch, and the fourth diode.

[0080] After the power electronic converter starts working, if the voltage of the second capacitor C2 is detected to be higher than the voltage of the first capacitor C1, indicating an uneven voltage distribution on the DC bus, the drive circuit can control the corresponding power switching device to turn on and off through the drive signal, thereby controlling the first charging and discharging circuit 100 and the second charging and discharging circuit 200 to perform the corresponding charging and discharging.

[0081] Figures 6 to 8 The current path during the operation of the bus voltage equalization circuit is shown. When the voltage of the second capacitor C2 is higher than the voltage of the first capacitor C1, the drive circuit controls the first power switch Q1 and the third power switch Q3 to remain off, and controls the second power switch Q2 and the fourth power switch Q4 to be turned on or off at the same time.

[0082] Figure 6 A schematic diagram of the circuit path when the first power switch Q1 and the third power switch Q3 are kept off, and the second power switch Q2 and the fourth power switch Q4 are simultaneously turned on.

[0083] like Figure 6 As shown, the second capacitor C2 discharges and charges the second inductor L2 through the communication between the second power switch Q2 and the fourth power switch Q4, and the second inductor L2 stores energy.

[0084] Figure 7 and Figure 8 This is a schematic diagram of the circuit path when the first power switch Q1 and the third power switch Q3 are kept off, and the second power switch Q2 and the fourth power switch Q4 are simultaneously turned off.

[0085] like Figure 7 and Figure 8 As shown, the second inductor L2 releases energy to charge the first capacitor C1 and the second capacitor C2 through the second diode D2, the first diode D1, the first power switching device Q1, and the fourth diode D4.

[0086] Figure 7 and Figure 8 The only difference is the type of the first power switching device Q1 used, which corresponds to the charging current flowing through different components of the first power switching device Q1.

[0087] Specifically, the first power switching device Q1 is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT); when the first power switching device Q1 is a MOSFET, the corresponding charging current flows from the source of the MOSFET to the drain of the MOSFET; when the first power switching device Q1 is an IGBT, the corresponding charging current flows from the anode of the body diode of the IGBT to the cathode of the body diode of the IGBT.

[0088] like Figure 7 As shown, when the first power switching device Q1 is a MOSFET transistor, the corresponding charging current flows through the channel from the source (S) of the channel of the first power switching device Q1 to the drain (D) of the first power switching device Q1.

[0089] like Figure 8 As shown, when the first power switching device Q1 is an IGBT transistor, the corresponding charging current flows through the body diode from the anode of the body diode of the first power switching device Q1 to the cathode of the body diode of the first power switching device Q1.

[0090] As mentioned above, the conduction loss generated by the same current flowing through the channel of a MOSFET transistor is significantly lower than the switching loss generated by the body diode of the MOSFET transistor.

[0091] Therefore, to reduce the high-frequency switching losses of power switching devices, in one embodiment, when the first power switching device is a MOSFET, controlling both the first and third power switching devices to remain off is replaced by controlling the third power switching device to remain off while the first power switching device remains on; or When the first power switching device is a MOSFET, controlling the first power switching device and the third power switching device to remain off is replaced by controlling the third power switching device to remain off, and the on / off states of the first power switching device are complementary to those of the second and fourth power switching devices.

[0092] In this embodiment, if the first power switch Q1 is a MOSFET transistor, then in order to reduce switching losses, the first power switch Q1 can be controlled to remain on. Alternatively, the on / off state of the first power switch Q1 can be controlled to be complementary to the on / off states of the second power switch Q2 and the fourth power switch Q4.

[0093] The complementary on / off states include: if the second power switch Q2 and the fourth power switch Q4 are both on, then the first power switch Q1 is off; if the second power switch Q2 and the fourth power switch Q4 are both off, then the first power switch Q1 is on.

[0094] In the above alternative embodiment, the third power switch Q3 remains off and is not changed.

[0095] Furthermore, when the first power switching device Q1 is an IGBT transistor, due to the high conduction loss of the body diode, the replacement of the first power switching device Q1 will not be performed in order to reduce the switching loss, and the first power switching device Q1 will remain off.

[0096] In summary, when the first power switching device Q1 is an IGBT transistor, because the current of the IGBT transistor cannot flow from the emitter to the collector of the channel, and the current only passes through the body diode, the first power switching device Q1 remains off when the voltage of the second capacitor C2 is higher than the voltage of the first capacitor C1. This can reduce the switching loss of the first power switching device Q1.

[0097] When the first power switch Q1 is a MOSFET transistor, because the current of the MOSFET transistor can flow from the source to the drain of the channel, the conduction loss of the current through the channel is lower than that through the body diode. Therefore, when the voltage of the second capacitor C2 is higher than the voltage of the first capacitor C1, the first power switch Q1 can remain off, remain on, or complement the on / off states of the corresponding second power switch Q2 and fourth power switch Q4.

[0098] If the on / off states of the first power switch Q1 are complementary to those of the second power switch Q2 and the fourth power switch Q4, the switching loss of the first power switch Q1 will increase. Therefore, it is not suitable for applications with high efficiency requirements.

[0099] During the operation of the first charging and discharging circuit 100 and the second charging and discharging circuit 200 of the bus equalization circuit 10, both the first power switching device Q1 and the second power switching device Q2 are in a high-frequency switching state. The voltage stress of their switching on / off varies between 0 and the bus voltage of the corresponding DC bus. Under high-frequency switching, there are switching losses.

[0100] For example, when the voltage of the first capacitor C1 is higher than the voltage of the second capacitor C2, the first power switch Q1 and the third power switch Q3 perform high-frequency switching actions of simultaneously turning on or off, the fourth power switch Q4 remains off, and the second power switch Q2 can remain off, remain on, or complement the on / off state of the first power switch Q1 and the third power switch Q3.

[0101] Below, in conjunction with Figures 3 to 5 The switching voltage stress corresponding to each power switching device is described.

[0102] (1) When the drive signal for keeping the second power switch Q2 off is at a constant low level, that is, when the second power switch Q2 is kept off, Figure 4 The charging process of the first capacitor C1 and the second capacitor C2 ends and becomes Figure 3 During the discharge process of the first capacitor C1, the voltage stress of the first power switch Q1 changes from the full bus voltage (i.e., the sum of the voltages of the first capacitor C1 and the second capacitor C2) to 0, and the voltage stress of the third power switch Q3 changes from the half bus voltage (i.e., the voltage of the first capacitor C1) to 0; the sum of the voltage stress of the second power switch Q2 and the voltage stress of the first diode D1 and the second diode D2 is the full bus voltage; the sum of the voltage stress of the fourth power switch Q4 and the voltage stress of the fourth diode D4 is the half bus voltage (i.e., the voltage of the second capacitor C2).

[0103] Figure 3 The first capacitor C1 completes its discharge process and becomes Figure 4 During the charging process of the first capacitor C1 and the second capacitor C2, the voltage stress of the first power switch device Q1 changes from 0 to the full bus voltage, and the stress of the third power switch device Q3 changes from 0 to half bus voltage (i.e., the voltage of the first capacitor C1); the sum of the voltage stress of the second power switch device Q2 and the voltage stress of the first diode D1, the second diode D2, and the third diode D3 is the full bus voltage; the sum of the voltage stress of the fourth power switch device Q4 and the voltage stress of the fourth diode D4 is half bus voltage (i.e., the voltage of the second capacitor C2).

[0104] (2) When the drive signal of the second power switch Q2 is always high, that is, when the second power switch Q2 remains on, Figure 5The charging process of the first capacitor C1 and the second capacitor C2 ends and becomes Figure 3 During the discharge process of the first capacitor C1, the voltage stress of the first power switching device Q1 changes from the full bus voltage to 0, and the voltage stress of the third power switching device Q3 changes from the half bus voltage to 0.

[0105] Figure 3 The first capacitor C1 completes its discharge process and becomes Figure 5 During the charging process of the first capacitor C1 and the second capacitor C2, the voltage stress of the first power switching device Q1 changes from 0 to the full bus voltage, and the voltage stress of the third power switching device Q3 changes from 0 to half bus voltage.

[0106] (3) When the on / off states of the second power switch Q2 and the first power switch Q1 and the third power switch Q3 are complementary, that is, when the first power switch Q1 and the third power switch Q3 are high-level on, the second power switch Q2 is low-level off; when the first power switch Q1 and the third power switch Q3 are low-level off, the second power switch Q2 is high-level on. Figure 5 The charging process of the first capacitor C1 and the second capacitor C2 ends and becomes Figure 3 During the discharge process of the first capacitor C1, the voltage stress of the first power switching device Q1 changes from the full bus voltage to 0, and the voltage stress of the third power switching device Q3 changes from the half bus voltage to 0.

[0107] Figure 3 The first capacitor C1 completes its discharge process and becomes Figure 5 During the charging process of the first capacitor C1 and the second capacitor C2, the voltage stress of the first power switching device Q1 changes from 0 to the full bus voltage, and the stress of the third power switching device Q3 changes from 0 to half bus voltage.

[0108] Correspondingly, when the voltage of the second capacitor C2 is higher than the voltage of the first capacitor C1, the second power switch Q2 and the fourth power switch Q4 perform high-frequency switching operations of simultaneously turning on or off, the third power switch Q3 remains off, and the first power switch Q1 can remain off, remain on, or complement the on / off state of the second power switch Q2 and the fourth power switch Q4.

[0109] Below, in conjunction with Figures 6 to 8 The switching voltage stress corresponding to each power switching device is described.

[0110] (1) When the drive signal for keeping the first power switch Q1 off is at a constant low level, that is, when the first power switch Q1 is kept off, Figure 7 The charging process of the first capacitor C1 and the second capacitor C2 ends and becomes Figure 6 During the discharge process of the second capacitor C2, the voltage stress of the second power switch Q2 changes from the full bus voltage (i.e., the sum of the voltages of the first capacitor C1 and the second capacitor C2) to 0, and the voltage stress of the fourth power switch Q4 changes from the half bus voltage (i.e., the voltage of the second capacitor C2) to 0; the sum of the voltage stress of the first power switch Q1 and the voltage stress of the first diode D1 and the second diode D2 is the full bus voltage; the sum of the voltage stress of the third power switch Q3 and the voltage stress of the third diode D3 is the half bus voltage (i.e., the voltage of the second capacitor C2).

[0111] Figure 6 The discharge process of the second capacitor C2 ends and becomes Figure 7 During the charging process of the first capacitor C1 and the second capacitor C2, the voltage stress of the second power switch Q2 changes from 0 to the full bus voltage, and the stress of the fourth power switch Q4 changes from 0 to half bus voltage (i.e., the voltage of the second capacitor C2). The sum of the voltage stress of the first power switch Q1 and the voltage stress of the first diode D1, the second diode D2, and the third diode D3 is the full bus voltage. The sum of the voltage stress of the third power switch Q3 and the voltage stress of the third diode D3 is the half bus voltage (i.e., the voltage of the second capacitor C2).

[0112] (2) When the drive signal of the first power switch Q1 is always high, that is, when the first power switch Q1 remains on, Figure 8 The charging process of the first capacitor C1 and the second capacitor C2 ends and becomes Figure 6 During the discharge process of the second capacitor C2, the voltage stress of the second power switch Q2 changes from the full bus voltage to 0, and the voltage stress of the fourth power switch Q4 changes from the half bus voltage to 0.

[0113] Figure 6 The discharge process of the second capacitor C2 ends and becomes Figure 8 During the charging process of the first capacitor C1 and the second capacitor C2, the voltage stress of the second power switch device Q2 changes from 0 to the full bus voltage, and the voltage stress of the fourth power switch device Q4 changes from 0 to half bus voltage.

[0114] (3) When the on / off states of the first power switch Q1, the second power switch Q2, and the fourth power switch Q4 are complementary, that is, when the second power switch Q2 and the fourth power switch Q4 are high-level on, the first power switch Q1 is low-level off; when the second power switch Q2 and the fourth power switch Q4 are low-level off, the first power switch Q1 is high-level on. Figure 8 The charging process of the first capacitor C1 and the second capacitor C2 ends and becomes Figure 6During the discharge process of the second capacitor C2, the voltage stress of the second power switch Q2 changes from the full bus voltage to 0, and the voltage stress of the fourth power switch Q4 changes from the half bus voltage to 0.

[0115] Figure 6 The first capacitor C1 completes its discharge process and becomes Figure 8 During the charging process of the first capacitor C1 and the second capacitor C2, the voltage stress of the second power switch device Q2 changes from 0 to the full bus voltage, and the voltage stress of the fourth power switch device Q4 changes from 0 to half bus voltage.

[0116] Therefore, it can be seen that in the above process, regardless of whether the voltage of the first capacitor C1 is higher than that of the second capacitor C2, or vice versa, under any operating condition, at least one of the power switching devices Q1, Q3, Q2, and Q4 will always experience a voltage stress that varies between 0 and half the bus voltage. Furthermore, only half of the circuit is operational, while the other half only serves as a freewheeling current inductor, thus reducing the high-frequency switching losses of the power switching devices.

[0117] Compared to existing bus voltage equalization circuits where high-voltage capacitors can only transfer energy to low-voltage capacitors (where the voltage stress of the power switch varies between 0 and the full bus voltage), the embodiments of this application always have a power switch whose voltage stress varies between 0 and half the bus voltage. This reduces the voltage stress of the power switch and can significantly reduce the switching losses of the power switch.

[0118] Furthermore, in this embodiment of the application, when the voltage of the first capacitor C1 is higher than the voltage of the second capacitor C2, the first power switch Q1 and the third power switch Q3 are driven to be turned on or off simultaneously; when the voltage of the second capacitor C2 is higher than the voltage of the first capacitor C1, the second power switch Q2 and the fourth power switch Q4 are driven to be turned on or off simultaneously.

[0119] Therefore, under any operating condition, the power switching devices of the two high-frequency switches are in the same on and off state simultaneously, eliminating the need to design a dead time to avoid the risk of short circuit caused by simultaneous conduction, thus improving the circuit's processing speed and reliability.

[0120] In one embodiment, when the first power switch, the second power switch, the third power switch, and the fourth power switch are all turned on simultaneously, the first capacitor discharges to charge the first inductor through the first power switch and the third power switch, and the first inductor stores energy; at the same time, the second capacitor discharges to charge the second inductor through the second power switch and the fourth power switch, and the second inductor stores energy. When the charging current corresponding to the first inductor and the charging current corresponding to the second inductor exceed a preset current threshold, the driving circuit controls the first power switch and the third power switch to turn off simultaneously, and controls the second power switch and the fourth power switch to turn off simultaneously. The first inductor and the second inductor release energy to charge the first capacitor and the second capacitor through the first diode, the third diode, and the fourth diode.

[0121] The above embodiments describe the charging and discharging process of the bus equalization circuit when the drive signals of the first power switch device Q1, the second power switch device Q2, the third power switch device Q3, and the fourth power switch device Q4 are simultaneously turned on.

[0122] For example, during the operation of the bus equalization circuit 10, if interference or an error in the pulse width modulation (PWM) wave sent by the drive circuit causes the drive signals of the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 to be at a high level simultaneously and to be turned on at the same time.

[0123] The following is combined with Figure 9 and Figure 10 The charging and discharging paths corresponding to the above embodiments are described below.

[0124] like Figure 9 As shown, when the first power switch Q1, the second power switch Q2, the third power switch Q3 and the fourth power switch Q4 are simultaneously turned on, the first capacitor C1 discharges and charges the first inductor L1 through the first power switch Q1 and the third power switch Q3, and the first inductor L1 stores energy.

[0125] Simultaneously, the second capacitor C2 discharges and charges the second inductor L2 through the second power switch Q2 and the fourth power switch Q4, and the second inductor L2 stores energy.

[0126] That is, the first charging and discharging circuit 100 and the second charging and discharging circuit 200 each perform the discharge operation of the corresponding capacitor.

[0127] During capacitor discharge, the inductance current of the first inductor L1 and the second inductor L2 is monitored in real time to see if it exceeds the maximum allowable inductance current, that is, whether the charging current of the first inductor L1 and the charging current of the second inductor L2 exceed the preset current threshold.

[0128] If the current corresponding to any inductor exceeds the maximum inductor current, the overcurrent protection is triggered. The drive circuit controls all power switching devices in the charging and discharging circuit of the corresponding inductor to turn off, thereby stopping the operation of the corresponding charging and discharging circuit.

[0129] For example, if the charging current corresponding to the first inductor L1 exceeds the preset current threshold, the drive circuit stops sending PWM waves to control each power switching device, the overall interference disappears, and the drive signal of each power switching device returns to low level by default and is immediately turned off.

[0130] After that, as Figure 10 As shown, the freewheeling of the first inductor L1 and the second inductor L2 transforms into a process of inductor discharge charging the first capacitor C1 and the second capacitor C2. During the freewheeling process, the voltage stress of the first power switch Q1, the second power switch Q2, the third power switch Q3, and the fourth power switch Q4 are all half the bus voltage, thus reducing switching losses.

[0131] Furthermore, based on the connection structure of each power switching device in the embodiments of this application, even if all four power switching devices are turned on simultaneously, there will be no risk of bus short circuit caused by shoot-through.

[0132] Furthermore, because there is an inductor in the through-loop, and the magnitude of the inductor current is monitored in real time, the circuit has stronger protection capabilities and higher reliability.

[0133] In one embodiment, the drive circuit includes a control unit and a drive unit; The control unit is used to output control commands based on the voltage levels of the first capacitor and the second capacitor, combined with the real-time collected voltages of the first capacitor and the second capacitor, as well as the charging current of the first inductor and the second inductor. The drive unit is connected to the control unit and the first power switch, the second power switch, the third power switch, and the fourth power switch, respectively. It is used to generate corresponding drive signals based on the control command and to control the first power switch, the second power switch, the third power switch, and the fourth power switch to turn on and off through the drive signals.

[0134] In this embodiment, the control unit monitors the voltage levels of the first capacitor C1 and the second capacitor C2, specifically whether the voltage of the first capacitor is higher than that of the second capacitor, or the voltage of the second capacitor C2 is higher than that of the first capacitor C1, during the current operation of the power converter. Based on the real-time collected charging current of the first and second inductors, the control unit outputs control commands.

[0135] The drive unit generates appropriate drive signals according to the control command to control the first power switch Q1, the second power switch Q2, the third power switch Q3 and the fourth power switch Q4 to turn on and off.

[0136] In one embodiment, the control unit includes: A voltage feedback loop is used to output corresponding voltage compensation feedback values ​​based on the real-time acquired voltages of the first and second capacitors. A current feedback loop, connected to the voltage feedback loop, is used to output a first current compensation feedback value corresponding to the first inductor and a second current compensation feedback value corresponding to the second inductor, based on the real-time acquired charging currents of the first and second inductors and the voltage compensation feedback values. A signal modulation circuit, connected to the current feedback loop, is used to generate control commands for corresponding pulse width modulation (PWM) signals based on the voltage levels of the first and second capacitors, combined with the first and second current compensation feedback values.

[0137] Combination Figure 11 The circuit structure of the control unit in an embodiment of this application is shown. The first capacitor C1 and the second capacitor C2 correspond to the collected voltage values, and the first inductor and the second inductor correspond to the collected inductor currents that participate in the corresponding loop control in real time.

[0138] like Figure 11 As shown, the voltage feedback loop includes a subtractor, a feedback arithmetic unit 1, and a PI (proportional-integral) controller 11. The positive input terminal of the subtractor is connected to the voltage value collected by the first capacitor C1, and the negative input terminal of the subtractor is connected to the voltage value collected by the second capacitor C2. The voltage values ​​can be collected by setting a differential operational amplifier circuit across the corresponding capacitors.

[0139] 0 is the given input value of feedback arithmetic unit 1 in the voltage feedback loop. The voltage difference between the first capacitor C1 and the second capacitor C2 after being processed by the subtractor is used as the feedback value and input to feedback arithmetic unit 1. The output of feedback arithmetic unit 1 is connected to PI controller 11, and finally outputs the corresponding voltage compensation feedback value to the current feedback loop.

[0140] The current feedback loop includes current feedback loop 61 and current feedback loop 62, wherein current feedback loop 61 includes feedback arithmetic unit 2 and PI controller 21; current feedback loop 62 includes feedback arithmetic unit 3 and PI controller 31.

[0141] The voltage compensation feedback value output by the PI controller 11 in the voltage feedback loop is used as the given input value for the current feedback loop 61 and the current feedback loop 62, respectively. The output of the PI controller 11 and the current value of the first inductor L1 are processed by the feedback arithmetic unit 2 and used as the input of the PI controller 21; the output of the PI controller 11 and the current value of the second inductor L2 are processed by the feedback arithmetic unit 3 and used as the input of the PI controller 31. The current value can be acquired by a Hall sensor connected in series at one end of each inductor. By using two inductors, the inductor current sampling only needs to be collected in one direction, that is, the positive inductor current is sampled, which not only reduces the circuit cost, but also achieves a narrow sampling range, thereby improving the sampling accuracy of the inductor current.

[0142] The PI controller 21 of the current feedback loop 61 and the PI controller 31 of the current feedback loop 62 output corresponding current compensation feedback values ​​as inputs to the signal modulation circuit.

[0143] The signal modulation circuit includes comparators 41, 42, and 43, as well as AND, NOT, and AND operations 51 and 52. The positive input of comparator 41 receives the current compensation feedback value output from the PI controller 21 of the current feedback loop 61, and the positive input of comparator 42 receives the current compensation feedback value output from the PI controller 31 of the current feedback loop 62. The negative inputs of comparators 41 and 42 receive a triangular carrier wave.

[0144] For example, the peak value of the triangular carrier wave is 1, the valley value is -1, that is, the peak-to-peak value is 2, the frequency is fsw (configurable, generally the same as the switching frequency of the power electronic converter 24), and the duty cycle is 0.5.

[0145] The current compensation feedback value and triangular carrier wave output by PI controller 21 are passed through comparator 41, and comparator 41 outputs a PWM signal; the current compensation feedback value and triangular carrier wave output by PI controller 31 are passed through comparator 43, and comparator 43 outputs a PWM signal.

[0146] After the voltage values ​​of the first capacitor C1 and the second capacitor C2 are passed through comparator 42, when the voltage value of the first capacitor C1 is higher than the voltage value of the second capacitor C2, comparator 42 outputs a high level, and when the voltage value of the first capacitor C1 is lower than the voltage value of the second capacitor C2, comparator 42 outputs a low level.

[0147] The PWM signals output by comparator 41 and comparator 42 are ANDed by AND operation 51 to obtain the control commands for the PWM signals of the first power switch Q1 and the third power switch Q3.

[0148] The output of comparator 42 is NOT operated on, and then ANDed with the output of comparator 43 by AND operation 52 to obtain the control commands for the PWM signals of the second power switch Q2 and the fourth power switch Q4.

[0149] When the voltage of the first capacitor C1 is higher than that of the second capacitor C2, the comparator 42 outputs a high level. After performing an AND operation with the PWM signal output by the comparator 41, the PWM drive signals of the first power switch Q1 and the third power switch Q3 are obtained. The first power switch Q1 and the third power switch are turned on and off at the same time.

[0150] The high level output of comparator 42 is NOT processed to obtain a low level, which is then ANDed with the PWM signal output by comparator 43 to obtain a low level, meaning that the second power switch Q2 and the fourth power switch Q4 remain off. When the first power switch Q1 and the third power switch Q3 are both on, the first capacitor C1 charges the first inductor L1; when the first power switch Q1 and the third power switch Q3 are both off, the first inductor L1 charges the first capacitor C1 and the second capacitor C2 through the freewheeling circuit.

[0151] When the voltage of the second capacitor C2 is higher than that of the first capacitor C1, the comparator 42 outputs a low level. After performing an AND operation with the PWM signal output by the comparator 41, a low level is obtained, that is, the first power switch Q1 and the third power switch Q3 remain off.

[0152] The low-level output of comparator 42 is NOT processed to obtain a high-level signal. This high-level signal is then ANDed with the PWM signal output from comparator 43 to obtain the PWM drive signals for the second power switch Q2 and the fourth power switch Q4. The second power switch Q2 and the fourth power switch Q4 are simultaneously on and off. When both power switches Q2 and Q4 are on, the second capacitor C2 charges the second inductor L2. When both power switches Q2 and Q4 are off, the second inductor L2 charges the first capacitor C1 and the second capacitor C2 through a freewheeling circuit.

[0153] In this embodiment, the bus voltage equalization circuit uses a first charging / discharging circuit and a second charging / discharging circuit. When the voltage of the first capacitor is higher than that of the second capacitor, the first charging / discharging circuit discharges the first capacitor, and the first and second charging / discharging circuits jointly charge the first and second capacitors based on the discharge of the first capacitor. This achieves voltage equalization between the first and second capacitors. During voltage equalization, energy transfer can be achieved from the capacitor with the higher voltage to the entire bus capacitor. The transferred energy can be directly utilized by other parts of the electronic power system, resulting in high recycling efficiency. Furthermore, it facilitates smooth and continuous energy transfer, extending the service life of the bus capacitors.

[0154] Furthermore, the upper and lower half-bus capacitors do not need to work in pairs, making the voltage equalization strategy more flexible. However, this results in limited energy transfer and low energy utilization efficiency of the half-bus capacitors.

[0155] Optionally, embodiments of this application also provide a power electronic converter system comprising: Bus equalization circuit 10 as described in any of the above embodiments; and The power electronic converter 24, the power supply device 30, and the drive circuit; Wherein, when the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter is working, the driving circuit controls the first charging and discharging circuit to discharge the first capacitor, and controls the first charging and discharging circuit and the second charging and discharging circuit to jointly charge the first capacitor and the second capacitor based on the discharge of the first capacitor; and / or When the voltage of the second capacitor is higher than the voltage of the first capacitor after the power electronic converter is working, the driving circuit controls the second charging and discharging circuit to discharge the second capacitor, and controls the first charging and discharging circuit and the second charging and discharging circuit to charge the first capacitor and the second capacitor based on the discharge of the second capacitor.

[0156] Optionally, the power electronic converter includes a bidirectional DC-DC converter and a bidirectional DC-AC converter; the power supply device includes a battery and a power supply power electronic converter, wherein the power supply power electronic converter includes a bidirectional DC-DC converter and a bidirectional AC-DC converter.

[0157] Figure 12 In the power electronic converter system shown, the power supply device is the battery BAT, and the power electronic converter is the bidirectional three-level DC-AC converter 22 in the energy storage converter (PCS), which is connected to the three-phase power grid G ​​through the corresponding LCL filter circuit in the energy storage converter.

[0158] In this circuit, inductor L3, capacitor C3, relay K3, and inductor L6 form a single-phase LCL filter circuit; inductor L4, capacitor C4, relay K4, and inductor L7 form a single-phase LCL filter circuit; inductor L5, capacitor C5, relay K5, and inductor L8 form a single-phase LCL filter circuit; and N is the neutral point constructed by capacitors C3, C4, and C5 in the three-phase filter circuit.

[0159] Figure 13 In the power electronic converter system shown, the power supply device is battery 32, and the bus equalization circuit 10 is connected between battery 32 and power electronic converter 24.

[0160] Figure 14In the power electronic converter system shown, the power supply device is a power electronic converter 34 used for power supply, which includes a bidirectional DC-DC converter and a bidirectional AC-DC converter. A bus equalization circuit 10 is connected between the power electronic converter 34 and the power electronic converter 24.

[0161] Figure 15 The power electronic converter system shown is Figure 14 The only difference is that the midpoint O of the DC bus is also connected to the power electronic converter 34 used for power supply.

[0162] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0163] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0164] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A bus voltage equalization circuit, characterized by, The circuit, applied in a power electronic converter, includes: The first charging and discharging circuit is connected across the first capacitor. The second charging and discharging circuit is connected across the second capacitor. The first charging and discharging circuit and the second charging and discharging circuit are connected in series. The first capacitor and the second capacitor are connected in series to form the DC bus of the power electronic converter. The power supply equipment is connected in parallel with the DC bus to initialize the first capacitor and the second capacitor to have the same voltage. The first charging and discharging circuit includes a first power switching device, a third power switching device, a first inductor, a first diode, and a third diode; the second charging and discharging circuit includes a second power switching device, a fourth power switching device, a second inductor, and a fourth diode. One end of the first diode is connected to one end of the second power switching device and one end of the second inductor, respectively; the other end of the first diode is connected to one end of the first power switching device and one end of the first inductor, respectively. One end of the third power switch is connected to one end of the fourth power switch, the other end of the third power switch is connected to the other end of the first inductor, and is connected to the other end of the first power switch and the first capacitor via the third diode; the other end of the fourth power switch is connected to the other end of the second inductor, and is connected to the other end of the second power switch and the second capacitor via the fourth diode. When the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter is working, the first charging and discharging circuit is used to discharge the first capacitor. The first charging and discharging circuit and the second charging and discharging circuit are used together to charge the DC bus composed of the first capacitor and the second capacitor based on the discharge of the first capacitor, so that the first capacitor and the second capacitor have the same voltage.

2. The circuit as described in claim 1, characterized in that, The first terminal of the first power switch is connected to the first terminal of the first capacitor, the second terminal of the first power switch is connected to the first terminal of the first inductor, and the third terminal of the first power switch is connected to the driving circuit. The first terminal of the third power switch is connected to the second terminal of the first inductor, the second terminal of the third power switch is connected to the second terminal of the first capacitor, and the third terminal of the third power switch is connected to the driving circuit. The first end of the first diode is connected to the first end of the first inductor, and the second end of the first diode is connected to the second charging and discharging circuit. The first end of the third diode is connected to the first end of the first capacitor, and the second end of the third diode is connected to the second end of the first inductor.

3. The circuit as described in claim 2, characterized in that, The first terminal of the second power switch is connected to the second terminal of the second inductor, the second terminal of the second power switch is connected to the second terminal of the second capacitor, and the third terminal of the second power switch is connected to the drive circuit. The first terminal of the fourth power switch is connected to the first terminal of the second capacitor, the second terminal of the fourth power switch is connected to the first terminal of the second inductor, and the third terminal of the fourth power switch is connected to the drive circuit. The second terminal of the second inductor is connected to the second terminal of the first diode; The first terminal of the fourth diode is connected to the first terminal of the second inductor, and the second terminal of the fourth diode is connected to the second terminal of the second capacitor. The second end of the first capacitor is connected to the first end of the second capacitor and forms the midpoint of the DC bus connection to the power electronic converter.

4. The circuit as described in claim 3, characterized in that, The second charging and discharging circuit also includes a second diode. The first end of the second diode is connected to the second end of the first diode, and the second end of the second diode is connected to the second end of the second inductor.

5. The circuit as described in claim 3, characterized in that, When the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter is working, the driving circuit controls the second power switching device and the fourth power switching device to remain off, and controls the first power switching device and the third power switching device to be turned on or off at the same time. When the first power switching device and the third power switching device are turned on simultaneously, the first capacitor discharges to charge the first inductor through the first power switching device and the third power switching device, and the first inductor stores energy. When the first power switch and the third power switch are turned off simultaneously, the first inductor releases energy to charge the first capacitor and the second capacitor through the second power switch, the first diode, and the third diode.

6. The circuit as described in claim 5, characterized in that, The second power switching device is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT); When the second power switching device is a MOSFET, the corresponding charging current flows from the source of the MOSFET to the drain of the MOSFET; When the second power switching device is an IGBT, the corresponding charging current flows from the anode of the body diode of the IGBT to the cathode of the body diode of the IGBT.

7. The circuit as described in claim 6, characterized in that, When the second power switching device is a MOSFET, controlling both the second and fourth power switching devices to remain off is replaced by controlling the fourth power switching device to remain off while the second power switching device remains on; or When the second power switch is a MOSFET, controlling the second power switch and the fourth power switch to remain off is replaced by controlling the fourth power switch to remain off, and the on / off states of the second power switch and the first power switch and the third power switch are complementary.

8. The circuit as described in claim 3, characterized in that, When the voltage of the second capacitor is higher than the voltage of the first capacitor after the power electronic converter is working, the second charging and discharging circuit is used to discharge the second capacitor. The first charging and discharging circuit and the second charging and discharging circuit are used together to charge the first capacitor and the second capacitor based on the discharge of the second capacitor, so that the first capacitor and the second capacitor have the same voltage.

9. The circuit as described in claim 8, characterized in that, When the voltage of the second capacitor is higher than the voltage of the first capacitor after the power electronic converter is working, the drive circuit controls the first power switch and the third power switch to remain off, and controls the second power switch and the fourth power switch to be turned on or off at the same time. When the second power switch and the fourth power switch are turned on simultaneously, the second capacitor discharges to charge the second inductor through the second power switch and the fourth power switch, and the second inductor stores energy. When the second power switch and the fourth power switch are turned off simultaneously, the second inductor releases energy to charge the first capacitor and the second capacitor through the first diode, the first power switch, and the fourth diode.

10. The circuit as described in claim 9, characterized in that, The first power switching device is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated-gate bipolar transistor (IGBT); When the first power switching device is a MOSFET, the corresponding charging current flows from the source of the MOSFET to the drain of the MOSFET; When the first power switching device is an IGBT, the corresponding charging current flows from the anode of the body diode of the IGBT to the cathode of the body diode of the IGBT.

11. The circuit as claimed in claim 10, characterized in that, When the first power switching device is a MOSFET, controlling both the first and third power switching devices to remain off is replaced by controlling the third power switching device to remain off while the first power switching device remains on; or When the first power switching device is a MOSFET, controlling the first power switching device and the third power switching device to remain off is replaced by controlling the third power switching device to remain off, and the on / off states of the first power switching device are complementary to those of the second and fourth power switching devices.

12. The circuit as described in claim 7 or 11, characterized in that, When the first power switch, the second power switch, the third power switch, and the fourth power switch are all turned on simultaneously, the first capacitor discharges to charge the first inductor through the first power switch and the third power switch, and the first inductor stores energy; at the same time, the second capacitor discharges to charge the second inductor through the second power switch and the fourth power switch, and the second inductor stores energy. When the charging current corresponding to the first inductor and the charging current corresponding to the second inductor exceed a preset current threshold, the driving circuit controls the first power switch and the third power switch to turn off simultaneously, and controls the second power switch and the fourth power switch to turn off simultaneously. The first inductor and the second inductor release energy to charge the first capacitor and the second capacitor through the first diode, the third diode, and the fourth diode.

13. The circuit as described in claim 12, characterized in that, The drive circuit includes a control unit and a drive unit; The control unit is used to output control commands based on the voltage levels of the first capacitor and the second capacitor, combined with the real-time collected voltages of the first capacitor and the second capacitor, as well as the charging current of the first inductor and the second inductor. The drive unit is connected to the control unit and the first power switch, the second power switch, the third power switch, and the fourth power switch, respectively. It is used to generate corresponding drive signals based on the control command and to control the first power switch, the second power switch, the third power switch, and the fourth power switch to turn on and off through the drive signals.

14. The circuit as described in claim 13, characterized in that, The control unit includes: A voltage feedback loop is used to output a corresponding voltage compensation feedback value based on the real-time collected voltages of the first capacitor and the second capacitor. A current feedback loop, connected to the voltage feedback loop, is used to output a first current compensation feedback value corresponding to the first inductor and a second current compensation feedback value corresponding to the second inductor based on the real-time collected charging current corresponding to the first inductor and the second inductor and the voltage compensation feedback value. A signal modulation circuit, connected to the current feedback loop, is used to generate a control command for a corresponding pulse width modulation (PWM) signal based on the voltage of the first capacitor and the high / low voltage of the second capacitor, combined with the first current compensation feedback value and the second current compensation feedback value.

15. A power electronic converter system, characterized in that, include: Busbar equalization circuit as described in any one of claims 1-14; as well as The power electronic converter, power supply equipment, and drive circuit; Wherein, when the voltage of the first capacitor is higher than the voltage of the second capacitor after the power electronic converter is working, the driving circuit controls the first charging and discharging circuit to discharge the first capacitor, and controls the first charging and discharging circuit and the second charging and discharging circuit to jointly charge the first capacitor and the second capacitor based on the discharge of the first capacitor; and / or When the voltage of the second capacitor is higher than the voltage of the first capacitor after the power electronic converter is working, the driving circuit controls the second charging and discharging circuit to discharge the second capacitor, and controls the first charging and discharging circuit and the second charging and discharging circuit to charge the first capacitor and the second capacitor based on the discharge of the second capacitor.

16. The system as described in claim 15, characterized in that, The power electronic converter includes a bidirectional DC-DC converter and a bidirectional DC-AC converter; The power supply device includes a battery and a power electronic converter, which includes a bidirectional DC-DC converter and a bidirectional AC-DC converter.

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