Transient phase superimposed dc-dc converter with self-balancing switch node and conversion method

Abstract

The application discloses a kind of transient phase superimposed DC-DC converters and conversion methods of switch node self-balancing, belong to voltage conversion technical field.For solving the defects such as existing DSD, CCC two-phase flying capacitor topology exists transient response, light load ZCD detection is easy to misjudge, flying capacitor voltage misadjustment needs additional calibration circuit, output generates big and small wave, etc.The application is realized nine kinds of switch states and four kinds of working modes by six-way power tube combination switching;Special transient phase superimposed state is set, two-phase inductance is synchronized to output power when load suddenly rises, voltage undershoot is greatly inhibited, and recovery time is shortened;Only SW B Node unilaterally samples, generates two-phase inductance zero-crossing signal in combination with timing logic deduction, realizes unilateral sampling double-sided ZCD detection, and reduces backflow loss;Built-in native switch node self-balancing mechanism, relies on two-phase current control to realize flying capacitor period charge-discharge charge automatic offset, without additional voltage calibration loop.

Description

Technical Field

[0001] This invention belongs to the field of voltage conversion technology, specifically relating to a transient superimposed DC-DC converter with self-balancing switching nodes and a conversion method. Background Technology

[0002] As semiconductor processes continue to iterate towards 7nm, 5nm, and more advanced processes, the core operating voltage of core computing chips such as CPUs, GPUs, FPGAs, high-end SOCs, and network switching chips continues to decrease. Currently, the rated power supply voltage of mainstream processor cores has generally dropped to the range of 0.8V to 1.1V, with 1V being the industry-standard core power supply node. At the same time, hardware systems such as server motherboards, desktop computers, industrial control equipment, vehicle-mounted smart terminals, and edge computing boxes all use 12V as the primary bus input voltage. The overall power supply architecture is unified as a high-voltage bus centralized power supply and an onboard multi-stage step-down secondary power supply mode. Therefore, the direct step-down of the 12V DC bus to 1V low-voltage high-current output has become an indispensable power conversion link in current power systems.

[0003] Traditional single-phase synchronous Buck buck converter topologies have several intractable technical shortcomings when dealing with large voltage drop conditions from 12V to 1V: First, under extremely low duty cycle operating conditions, the turn-on time of the upper MOSFET is too short, and the minimum conduction time of existing controllers has a physical limit, making it prone to pulse loss and output voltage runaway. Second, the ripple current of the single-phase synchronous Buck inductor is large, and the ripple voltage at the low-voltage output terminal is difficult to suppress, failing to meet the ultra-low ripple power supply requirements of the chip core. Third, each MOSFET needs to withstand extremely high voltage and switching stress, resulting in concentrated heat generation and a limited upper limit on the single-channel output current, which cannot support the ultra-high current output required by servers and high-end graphics cards.

[0004] To meet the power management requirements of processors, current high-conversion-ratio, high-current output step-down DC-DC converters are trending towards multi-phase hybrid topologies. In recent years, research on 12V to 1V applications has led to the development of a two-phase three-level converter with flying capacitor cross-coupling (2-phase 3-level with XC). fly Novel topologies such as 2P3L, double step-down (DSD), and flying capacitor cross-connected (CCC) converters have been developed, but these topologies still have problems in some application scenarios.

[0005] DSD has the following problems: It cannot achieve a two-phase superposition working state, and the transient switching undershoot is severe with a long recovery time; ZCD cannot be detected correctly; under light load, FCCM mode suffers significant power loss.

[0006] CCC has the following problems: Deviations in external flying capacitors can cause voltage misalignment on them; ZCD cannot be detected correctly; under light load, FCCM mode suffers significant power loss.

[0007] In addition, common hybrid topologies such as basic three-level circuits, DSD, and two-phase three-level circuits require V-type capacitance adjustments to the flying capacitor. CF Voltage calibration: If the voltage across the capacitor deviates from 1 / 2 of the input voltage, it will cause an imbalance in the switching node voltage within two phases or two cycles, which will manifest as large and small waves in the output voltage, thus increasing the output voltage ripple. Summary of the Invention

[0008] To address the aforementioned problems in the prior art, this invention provides a transient superimposed phase DC-DC converter with self-balancing switching nodes and a conversion method thereof. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a transient superimposed phase DC-DC converter with self-balancing switching nodes, comprising: Power conversion main circuit and control circuit; The power conversion main circuit includes: a first power transistor A1, a second power transistor A2, a third power transistor A3, a fourth power transistor B1, a fifth power transistor B2, a sixth power transistor B3, and a flying capacitor C. F1 Flying capacitor C F2 Inductor L1 and inductor L2; The source terminal of the first power transistor A1 is connected to input ground GND, and the drain terminal is connected to the source terminal of the second power transistor A2 and the flying capacitor C. F1 One end of the inductor L1 is connected to the other end of the inductor L1 to form the switching node SW. A ; The drain of the second power transistor A2 and the drain of the fifth power transistor B2, and the flying capacitor C F2 One end is connected to form the switch node SW D ; The source terminal of the third power transistor A3 and the flying capacitor C F1 The other end, the drain of the sixth power transistor B3, is connected to form the switching node SW. C The drain terminal is connected to the input voltage VIN; The source terminal of the fourth power transistor B1 is connected to the input ground GND, and its drain terminal is connected to the source terminals of the fifth power transistor B2, the sixth power transistor B3, and one end of the inductor L2, forming the switching node SW. B ; The flying capacitor C F2 The other end is connected to the input ground GND; Inductor L1 in series with DC equivalent resistance R DCR1 Inductor L2 in series with DC equivalent resistance R DCR2 R DCR1 With R DCR2 The other end is connected to form the output voltage node V. O ; The control circuit uses V 2 The ACOT architecture includes an error amplifier EA, an RC filter circuit, a multi-input transconductor gm, a turn-on comparator, an ACOT Ton generation circuit, logic circuits, and a gate drive circuit. The error amplifier EA is based on the output voltage node V. O The corresponding output feedback voltage V FB and bandgap reference V REF Output control voltage V C ; The RC filter circuits respectively draw from the switching node SW A SW B The inductor current sampling signal R is obtained by sampling. sen I L1 R sen I L2 Perform ripple compensation; The multi-input transconductor gm will V FB V REF V C R sen I L1 R sen I L2 The current is converted and superimposed, and then a comparator is used to generate an on-control signal. The ACOT Ton generation circuit generates an adaptive constant on-time T based on the DCR sampling of L1 and L2 and the frequency-divided signal of the turn-on control signal. on To achieve uniform flow between the two phases; The logic circuit outputs drive logic based on the turn-on control signal, load conditions, and constant on-time. The gate drive circuit is connected to the gates of the six power transistors in the main power conversion circuit. According to the drive logic, it drives the operating state of the six power transistors and controls the transient superimposed DC-DC converter to work in the corresponding operating mode so as to output a stable conversion voltage.

[0009] In one embodiment of the present invention, six power transistors in the power conversion main circuit are combined to form nine switching states S1 to S9; the conduction logic corresponding to each switching state includes: Switch state S1: A2, A3, B1 are on, A1, B2, B3 are off, C F1 Charging, C F2 Charge first, then discharge; L1 is split into two paths, and L2 discharges via B1. Switch state S2: A1 and B1 are on, A2, A3, B2, and B3 are off, C F1 C F2 The voltage is maintained, and L1 and L2 freewheel to ground through A1 and B1, respectively; Switch state S3: A1, B2, B3 are on, A2, A3, B1 are off, C F1 First, C F2 The charging and power supply to L2 are combined, and L1 continues to ground through A1; Switch state S4: A2, A3, B2 are on, A1, B1, B3 are off, C F1 Charging, C F2 Discharge, SW A With SW B Equipotential, L2 is caused by C F2 Power supply, achieving two-phase superposition; Switch state S5: Only A1 is on, A2, A3, B1, B2, and B3 are off, L1 freewheels to ground, and L2 has no current. Switch state S6: Only B1 is on, A1, A2, A3, B2, and B3 are off, L2 freewheels to ground, and L1 has no current. Switching state S7: All six power transistors are turned off, the current in L1 and L2 is zero, and the load is freewheeled by the output capacitor Co; Switch state S8: A2 and A3 are on, A1, B1, B2, and B3 are off, C F1 Charging, C F2 During discharge, only L1 has a shunt current, while L2 has no current. Switch state S9: Only B2 is on, A1, A2, A3, B1, and B3 are off, C F2 The discharge supplies power to L2, and there is no current in L1.

[0010] In one embodiment of the present invention, the operating modes of the transient phase-multiplexed DC-DC converter include: CCM continuous conduction mode, TRANS transient enhancement mode, Light DCM shallow discontinuous conduction mode, and Deep DCM deep discontinuous conduction mode; The corresponding switching states during the working cycle of the CCM continuous conduction mode are as follows: S1, S2, S3, S2; The corresponding switching states during the duty cycle of the TRANS transient enhancement mode are as follows: Activate S4 to interrupt any existing switch state when a transient enhancement signal is detected, thereby achieving superimposed phase compensation of two-phase inductors; The corresponding switching states during the working cycle of the Light DCM shallow intermittent conduction mode are as follows: S1, S2, S5, S3, S2, S6; The corresponding switching states during the working cycle of the Deep DCM deep discontinuous conduction mode are as follows: S8, S5, S7, S3, S9, S6, S7.

[0011] In one embodiment of the present invention, in the Deep DCM deep discontinuous conduction mode, C in steady state F1 With C F2 There is an offset voltage, which varies over a fixed period of time. T on The on-resistance R of B2 B2 The on-resistance R of B3 B3 Inductance value L, input voltage VIN, output voltage V OUT Jointly decided; among them, This refers to the operating duration of switch state S3 in Deep DCM (Deep Discontinuous Conduction Mode).

[0012] In one embodiment of the present invention, the transient multiphase DC-DC converter further includes a single-sided sampling double-sided ZCD detection module; the single-sided sampling double-sided ZCD detection module includes: SW B Sampling comparison branch, capacitor storage branch, logic shielding branch; The SW B Sampling comparison branch to switch node SW B Single-ended sampling is performed to generate a zcdB zero-crossing signal; The capacitor storage branch stores the voltage V corresponding to the conduction time of L2 current through two capacitors C1 and C2. save1 V save2 As a capacitor, it stores voltage; The logic shielding branch generates shielding signals shield1_1, shield1_2, shield2_1, and shield2_2 based on the frequency division of hsonA and pwm2. Combined with the capacitor storage voltage, it triggers zcdA_1 and zcdA_2 in a time-division manner. Then, the shielding signals zcdA_pass1 and zcdA_pass2 are used to perform AND and OR logic operations to output zcdA double-sided zero-crossing signals that are adapted to A1, A2, and A3.

[0013] In one embodiment of the present invention, the single-sided sampling double-sided ZCD detection module has a mode-adaptive shielding function. When the transient superimposed DC-DC converter is in the CCM continuous conduction mode, the inductor current is continuously greater than zero, the zcdB zero-crossing signal disappears, and the shielding signals zcdA_pass1 and zcdA_pass2 are completely turned off, preventing the false triggering of the zcdA double-sided zero-crossing signal. The transient superimposed DC-DC converter can normally output the zcdA double-sided zero-crossing signal and the zcdB zero-crossing signal during the startup phase, the Light DCM shallow discontinuous conduction mode, and the Deep DCM deep discontinuous conduction mode.

[0014] In one embodiment of the present invention, the switching state S4 of the transient multiphase DC-DC converter in TRANS transient enhancement mode is a two-phase multiphase operating state, SW A With SW B The potentials are all VIN / 2, C F1 Continuous charging, C F2 Energy is simultaneously supplied to both L1 and L2 inductors.

[0015] In one embodiment of the present invention, when the transient phase-multiplexed DC-DC converter operates in steady-state CCM continuous conduction mode, the switching node SW A SW B The voltage is automatically balanced to V CF2 C in Deep DCM mode F2 There is an offset voltage. After the transient switch from light to heavy load to CCM continuous conduction mode, the switching node SW... A SW B The voltage automatically rebalances and returns to V. CF2 .

[0016] In a second aspect, the present invention provides a transient superimposed phase DC-DC conversion method with self-balancing switching nodes, applied to the transient superimposed phase DC-DC converter with self-balancing switching nodes as described in the first aspect. The transient superimposed phase DC-DC conversion method includes: The power conversion main circuit, under the control of the control circuit, operates at the output voltage node V. O Output stable conversion voltage; The ripple of the output feedback voltage is obtained by the control circuit based on the output feedback voltage and the reference voltage corresponding to the conversion voltage, and is used as the voltage fast loop signal. The ripple of the voltage fast loop signal is superimposed by the switching node SW. A SW B The filtered compensation ripple is used to generate the ripple of the output feedback voltage after ripple compensation. The control voltage V is obtained using the error amplifier EA based on the output feedback voltage and the reference voltage. C, as a voltage slow loop signal; When the ripple of the output feedback voltage after ripple compensation decreases and touches the voltage slow loop signal, an on-control signal is generated. The turn-on control signal is frequency divided and combined with the clamping of the two-phase current sharing loop to generate an adaptive constant conduction time. The driving logic is generated based on the turn-on control signal, load conditions, and constant conduction time to drive the operating states of the six power transistors in the main power conversion circuit, so that the transient multiphase DC-DC converter can operate in the corresponding operating mode and output a stable conversion voltage.

[0017] The beneficial effects of this invention are: In the solution provided by this invention, the voltages of switching nodes SWA and SWB are self-balanced under CCM steady-state conditions. Current sharing between the two phases is achieved through the ACOT Ton generation circuit, automatically canceling the charge discharge cycle of the flying capacitor without the need for an additional voltage calibration loop. When the load suddenly increases, the two-phase inductors synchronously replenish the output, resulting in a small output voltage drop and fast recovery, significantly improving transient response. Furthermore, this invention introduces a single-sided sampling, double-sided ZCD detection module to eliminate interference from the flying capacitor on ZCD sampling. The converter can operate stably under light loads in both Light DCM shallow discontinuous conduction mode and Deep DCM deep discontinuous conduction mode, avoiding inductor backflow losses in FCCM and significantly improving light-load energy efficiency. In Deep DCM deep discontinuous conduction mode, this invention uses a fixed-duration switching state S3 for charge compensation, controlling capacitor voltage offset within a safe range and eliminating the risk of charge accumulation and breakdown. Furthermore, this invention reduces the switching / conduction stress of single-channel devices by multi-phase shunt, reduces inductor ripple current, and solves the problems of limited minimum conduction time, low upper limit of output current, and excessive ripple in traditional single-phase synchronous Buck converters. Attached Figure Description

[0018] Figure 1 The circuit diagram shows the operating states of the DSD and CCC sections; Figure 2 Waveform diagram of the existing topology ZCD detection problem; Figure 3 The diagram shows a topology of a self-balancing transient phase-multiplexed DC-DC converter with switching nodes provided in an embodiment of the present invention. Figure 4 A schematic diagram of the switching state of a self-balancing transient phase-multiplexed DC-DC converter in CCM continuous conduction mode, provided in an embodiment of the present invention. Figure 5A schematic diagram of the switching state of a self-balancing transient phase-multiplexed DC-DC converter in TRANS transient enhancement mode, provided in an embodiment of the present invention; Figure 6 Simulation waveforms of inductor current and output voltage before the transient phase-multiplexed DC-DC converter with self-balancing switching node provided in the embodiment of the present invention in TRANS transient enhancement mode; Figure 7 A schematic diagram of the switching state of a self-balancing transient phase-over DC-DC converter in the shallow discontinuous conduction mode of Light DCM, provided in an embodiment of the present invention. Figure 8 A schematic diagram of the switching state of a self-balancing transient phase-over DC-DC converter in Deep DCM mode, provided in an embodiment of the present invention. Figure 9 This is a schematic diagram of the switching node voltage self-balancing principle of a transient superimposed DC-DC converter with self-balancing switching nodes provided in an embodiment of the present invention. Figure 10 The simulation waveforms before voltage self-balancing auxiliary verification and before the switching node voltage of a transient superimposed DC-DC converter with self-balancing switching node provided in the embodiment of the present invention are shown. Figure 11 The following are pre-simulation waveforms of inductor current and power transistor gate drive signal in Deep DCM and TRANS transient enhancement modes, respectively, for an embodiment of the present invention. Figure 12 The transient superimposed phase DC-DC converter with self-balancing switching node provided in this embodiment of the invention operates under the flying capacitor C in Deep DCM (deep discontinuous conduction) mode. F1 With C F2 Voltage variation curve; Figure 13 The transient superimposed phase DC-DC converter with self-balancing switching node provided in this embodiment of the invention provides a flying capacitor C during light-load / heavy-load transient switching. F1 With C F2 Simulation waveform before voltage change; Figure 14 A schematic diagram of the transistor-level circuit of a single-side sampling double-side ZCD detection module in a transient superimposed phase DC-DC converter with self-balancing switching nodes provided in an embodiment of the present invention; Figure 15The control waveform diagram of the single-side sampling double-side ZCD detection module of a self-balancing transient phase-multiplexed DC-DC converter with switching nodes provided in the embodiments of the present invention in Light DCM shallow discontinuous conduction mode and Deep DCM deep discontinuous conduction mode is shown. Figure 16 The following are pre-simulation waveforms of a switching node self-balancing transient phase-over DC-DC converter provided in an embodiment of the present invention, showing partial signals of the single-sided sampling bilateral ZCD detection module when the overall circuit starts up and when the circuit leaves the DCM and enters the CCM. Figure 17 This is a schematic diagram illustrating the steps of a transient superimposed phase DC-DC conversion method for self-balancing switching nodes provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] Circuit diagrams showing the operating states of the DSD and CCC sections, as follows: Figure 1 As shown, Figure 1 (a) shows the three operating states of the DSD, with the inductor current I... L2 Taking the decline as an example, I L2 During the current ZCD detection phase (lson), the circuit operating state can be either Sa-Sb-Sc or Sa-Sb depending on different load conditions. As can be seen from the current flowing through power transistor B in the diagram, V... SWB State S3 is the desired ZCD detection state. However, due to the flying capacitor in state Sb, an additional current flows through power transistor B, creating a voltage drop across the transistor. At this point, the SWB voltage in state Sb will exhibit a downward step, leading to a false ZCD detection. Figure 2 As shown. Figure 1 In Figure (b), the CCC operating state is shown. The switching of the CCC operating state is similar. The SW nodes of both the DSD and CCC phases are interference points affected by the flying capacitor, making it difficult to achieve conventional ZCD detection. Therefore, existing products (TPS54a20) or papers based on this topology are all in FCCM mode rather than DCM mode under light load.

[0021] To address the problems of existing two-phase hybrid topologies, embodiments of the present invention provide a transient superimposed phase DC-DC converter and conversion method with self-balancing switching nodes.

[0022] Below, we will first introduce a transient superimposed DC-DC converter with self-balancing switching nodes provided by an embodiment of the present invention.

[0023] The present invention provides a self-balancing transient superimposed phase DC-DC converter with switching nodes, such as... Figure 3 As shown, it may include: Power conversion main circuit and control circuit; The main power conversion circuit includes: a first power transistor A1, a second power transistor A2, a third power transistor A3, a fourth power transistor B1, a fifth power transistor B2, a sixth power transistor B3, and a flying capacitor C. F1 Flying capacitor C F2 Inductor L1 and inductor L2; The source terminal of the first power transistor A1 is connected to input ground GND, and the drain terminal is connected to the source terminal of the second power transistor A2 and the flying capacitor C. F1 One end of the inductor L1 is connected to the other end of the inductor L1 to form the switching node SW. A ; The drain of the second power transistor A2 is connected to the drain of the fifth power transistor B2, and the flying capacitor C. F2 One end is connected to form the switch node SW D ; The source of the third power transistor A3 and the flying capacitor C F1 The other end, the drain of the sixth power transistor B3, is connected to form the switching node SW. C The drain terminal is connected to the input voltage VIN; The source of the fourth power transistor B1 is connected to the input ground GND, and its drain is connected to the source of the fifth power transistor B2, the source of the sixth power transistor B3, and one end of the inductor L2, forming the switching node SW. B ; Flying capacitor C F2 The other end is connected to the input ground GND; Inductor L1 in series with DC equivalent resistance R DCR1 Inductor L2 in series with DC equivalent resistance R DCR2 R DCR1 With R DCR2 The other end is connected to form the output voltage node V. O ; The control circuit uses V 2 The ACOT architecture includes an error amplifier EA, an RC filter circuit, a multi-input transconductor gm, a turn-on comparator, an ACOT Ton generation circuit, logic circuits, and a gate drive circuit. Error amplifier EA is based on output voltage node V O The corresponding output feedback voltage V FB and bandgap reference V REF Output control voltage V C ; The RC filter circuits respectively start from the switching node SW ASW B The inductor current sampling signal R is obtained by sampling. sen I L1 R sen I L2 Perform ripple compensation; The multi-input transconductor gm will V FB V REF V C R sen I L1 R sen I L2 The current is converted and superimposed, and then a comparator is used to generate an on-control signal. The ACOT Ton generation circuit generates an adaptive constant on-time T based on the DCR sampling of L1 and L2 and the frequency-divided signal of the turn-on control signal. on To achieve uniform flow between the two phases; The logic circuit outputs drive logic based on the turn-on control signal, load conditions, and constant on-time. The gate drive circuit is connected to the gates of the six power transistors in the main power conversion circuit. According to the drive logic, it drives the operating state of the six power transistors and controls the transient superimposed DC-DC converter to work in the corresponding operating mode so as to output a stable conversion voltage.

[0024] In this embodiment of the invention, by controlling the operating states of the first power transistor A1, the second power transistor A2, the third power transistor A3, the fourth power transistor B1, the fifth power transistor B2, and the sixth power transistor B3, the transient multiphase DC-DC converter is made to operate in the corresponding operating modes, thereby realizing different circuit operating modes and corresponding functions.

[0025] Among them, the first power transistor A1 switches the node SW according to the drive control signal of its gate. A Connected to or disconnected from input ground GND. The second power transistor A2 switches node SW according to the drive control signal of its gate. A With switch node SW D Connect or disconnect. The third power transistor A3 switches node SW according to the drive control signal of its gate. C It is connected or disconnected from the input voltage VIN. The fourth power transistor B1 switches node SW according to the drive control signal of its gate. B Connected to or disconnected from input ground GND. The fifth power transistor B2 switches node SW according to the drive control signal of its gate. B With switch node SW D Connect or disconnect. The sixth power transistor B3 switches node SW according to the drive control signal of its gate. B With switch node SWC Connected or disconnected.

[0026] The control circuit is V 2 The ACOT architecture may include: the output feedback voltage V corresponding to the transient phase-multiplexed DC-DC converter. FB and the bandgap reference V generated by the bandgap reference circuit Bandgap REF Compare and output control voltage V C Error amplifier EA; from SW A Filtering yields R sen I L1 From SW B Filtering yields R sen I L2 And an RC filter circuit used for ripple compensation; R sen I L1 R sen I L2 V FB V REF and V C The system includes a multi-input transconductance transducer gm that converts current into superposition; a comparator for generating a turn-on control signal; an ACOT Ton generation circuit that samples and shares the current of inductors L1 and L2 using DCR; and logic circuits and gate drive circuits that control the operating state of the transient superimposed DC-DC converter. The enable signal EN controls the enable and startup circuits EN&Startup to generate a startup signal, which in turn controls the bandgap reference circuit Bandgap to generate the bandgap reference V. REF .

[0027] The six power transistors in the power conversion main circuit combine to form nine switching states S1 to S9; the conduction logic corresponding to each switching state may include: Switch state S1: A2, A3, B1 are on, A1, B2, B3 are off, C F1 Charging, C F2 Charge first, then discharge; L1 is split into two paths, and L2 discharges via B1. Switch state S2: A1 and B1 are on, A2, A3, B2, and B3 are off, C F1 C F2 The voltage is maintained, and L1 and L2 freewheel to ground through A1 and B1, respectively; Switch state S3: A1, B2, B3 are on, A2, A3, B1 are off, C F1 First, C F2 The charging and power supply to L2 are combined, and L1 continues to ground through A1; Switch state S4: A2, A3, B2 are on, A1, B1, B3 are off, C F1 Charging, CF2 Discharge, SW A With SW B Equipotential, L2 is caused by C F2 Power supply, achieving two-phase superposition; Switch state S5: Only A1 is on, A2, A3, B1, B2, and B3 are off, L1 freewheels to ground, and L2 has no current. Switch state S6: Only B1 is on, A1, A2, A3, B2, and B3 are off, L2 freewheels to ground, and L1 has no current. Switching state S7: All six power transistors are turned off, the current in L1 and L2 is zero, and the load is freewheeled by the output capacitor Co; Switch state S8: A2 and A3 are on, A1, B1, B2, and B3 are off, C F1 Charging, C F2 During discharge, only L1 has a shunt current, while L2 has no current. Switch state S9: Only B2 is on, A1, A2, A3, B1, and B3 are off, C F2 The discharge supplies power to L2, and there is no current in L1.

[0028] Depending on the gate drive signal of the power transistor, the transient cascaded DC-DC converter provided in this embodiment of the invention includes four operating modes. The operating modes of the transient cascaded DC-DC converter include: CCM continuous conduction mode, TRANS transient enhancement mode, Light DCM shallow discontinuous conduction mode, and Deep DCM deep discontinuous conduction mode; The corresponding switching states during the duty cycle of CCM continuous conduction mode are as follows: S1, S2, S3, S2; The corresponding on / off states during the duty cycle of TRANS transient enhancement mode are as follows: Activate S4 to interrupt any existing switch state when a transient enhancement signal is detected, thereby achieving superimposed phase compensation of two-phase inductors; The corresponding switching states during the duty cycle of the Light DCM shallow discontinuous conduction mode are as follows: S1, S2, S5, S3, S2, S6; The corresponding switching states during the duty cycle of Deep DCM deep discontinuous conduction mode are as follows: S8, S5, S7, S3, S9, S6, S7.

[0029] During the operation of this transient multiphase DC-DC converter, when the load current is large, the transient multiphase DC-DC converter is in CCM continuous conduction mode; as the load current decreases, when the critical condition is triggered, the transient multiphase DC-DC converter will enter DCM mode; for DCM mode, when the preset judgment condition is greater than or equal to 50%, it enters Light DCM shallow discontinuous conduction mode, and when the preset judgment condition is less than 50%, it enters Deep DCM deep discontinuous conduction mode; when the load current jumps from low to high, the transient multiphase DC-DC converter enters TRANS transient enhancement mode.

[0030] The preset judgment conditions are as follows: ; in, This indicates the charging time of the switch node SW. This indicates the discharge time of the switch node SW. This indicates the time during which the load current is supplied by the output capacitor when all power transistors are turned off.

[0031] For example, one can choose to enter the CCM continuous conduction mode when the load current is greater than 1A, and can choose to enter the TRANS transient enhancement mode when the load current jumps from 0.2A to 4.2A within 20ns.

[0032] The switching state diagram of the transient phase-multiplexed DC-DC converter in CCM continuous conduction mode provided in this embodiment of the invention is as follows: Figure 4 As shown, based on the above nine switching states, the working cycle corresponding to the CCM continuous conduction mode can be divided into four stages: S1, S2, S3, and S2.

[0033] like Figure 4 As shown in (a), in switching state S1, power transistors A2, A3, and B1 are turned on, while A1, B2, and B3 are turned off, and flying capacitor C... F1 The other end is connected to VIN via A3, with capacitor C flying across it. F2 One end is connected to SW via A2 A SW B Connected to GND via B1. In switch state S1, the flying capacitor C... F1 Charging, flying capacitor C F2 Charge first, until C F1 Voltage and C F2 The discharge occurs after the sum of the voltages reaches VIN. The current in inductor L1 splits into two paths; one path flows sequentially through A3 and the flying capacitor C. F1 The other current flows sequentially through the flying capacitor C. F2 A2; the current in inductor L2 discharges through B1.

[0034] like Figure 4 As shown in (b) and (d), in switch state S2, power transistors A1 and B1 are turned on, while A2, A3, B2, and B3 are turned off. SW A Connect to GND via A1, SW B Connected to GND via B1. In switch state S2, the flying capacitor C... F1 With flying capacitor C F2 Keep the voltage constant. The current in inductor L1 discharges through A1, and the current in inductor L2 discharges through B1.

[0035] like Figure 4 As shown in (c), in switch state S3, power transistors A1, B2, and B3 are turned on, while A2, A3, and B1 are turned off. SW A Connected to GND via A1, flying capacitor C F1 One end is connected to SW via B3 B Flying capacitor C F2 One end is connected to SW via B2 B In switch state S3, the flying capacitor C F1 First, let's consider the flying capacitor C. F2 While charging, it also provides current to inductor L2. At this time, the current in B3 is divided into two paths, one of which flows through B2 as C. F2 Charging occurs via another path through inductor L2. This is followed by the flow through the flying capacitor C. F1 With flying capacitor C F2 After balancing, both supply current to inductor L2 simultaneously. At this point, the current in inductor L2 splits into two paths, with one path flowing sequentially through the flying capacitor C. F1 B3, and another current flows sequentially through the flying capacitor C. F2 B2. The current in inductor L1 discharges through A1.

[0036] A schematic diagram of the switching states of this transient multiphase DC-DC converter in TRANS transient enhancement mode is shown below. Figure 5 As shown, in TRANS transient enhancement mode, the transient superimposed DC-DC converter enters switching state S4. When a transient enhancement signal is detected, this operating state can interrupt any other operating state.

[0037] In switch state S4, power transistors A2, A3, and B2 are turned on, while A1, B1, and B3 are turned off, and flying capacitor C... F1 One end is connected to VIN via A3, and the switch node SW A SW B With flying capacitor C F2 One end of each capacitor is connected together via A2 and B2. In switch state S4, the flying capacitor C... F1 Charging, flying capacitor CF2 Discharge. The current in inductor L1 splits into two paths; one path flows sequentially through A3 and the flying capacitor C. F1 The other current flows sequentially through the flying capacitor C. F2 A2; The current in inductor L2 flows through B2 from the flying capacitor C. F2 Charge.

[0038] In the TRANS transient enhancement mode, the switching state S4 of the transient multiphase DC-DC converter is a two-phase multiphase operation state, SW A With SW B The potentials are all VIN / 2, C F1 Continuous charging, C F2 Energy is simultaneously supplied to both L1 and L2 inductors.

[0039] Figure 6 The simulation waveforms of the transient tandem DC-DC converter before transient switching inductor current and output voltage are shown below under the following conditions: 12V to 1V, light load current 0.2A, heavy load current 4.2A, load shedding time 20ns, output inductor 740nH, and output capacitor 10.6uF. It can be seen that thanks to the two-phase current superposition compensation in the switching state S4, the output voltage undershoot is only 93mV, and the recovery time is 10.5us.

[0040] A schematic diagram of the switching states of this transient multiphase DC-DC converter in the Light DCM shallow discontinuous conduction mode is shown below. Figure 7 As shown, based on the above nine switching states, the working cycle corresponding to the Light DCM shallow intermittent conduction mode can be divided into six stages: S1, S2, S5, S3, S2, S6.

[0041] In switching state S5, power transistor A1 is turned on, and transistors A2, A3, B1, B2, and B3 are turned off, and the switching node SW... A Connected to GND via A1. In switch state S5, inductor L1 discharges through A1, and inductor L2 has no current.

[0042] In switch state S6, power transistor B1 is turned on, and transistors A1, A2, A3, B2, and B3 are turned off, and switch node SW... B Connected to GND via B1. In switch state S6, inductor L2 discharges through B1, and there is no current in inductor L1.

[0043] The other switch states S1, S2, and S3 are as described above.

[0044] A schematic diagram of the switching states of this transient multiphase DC-DC converter in Deep DCM (deep discontinuous conduction mode) is shown below. Figure 8As shown, based on the above nine switching states, the working cycle corresponding to the Deep DCM deep discontinuous conduction mode can be divided into seven stages: S8, S5, S7, S3, S9, S6, and S7.

[0045] In switch state S7, power transistors A1, A2, A3, B1, B2, and B3 are all turned off. At this time, there is no current in inductors L1 and L2, and the load current freewheels through the output capacitor Co.

[0046] In switch state S8, power transistors A2 and A3 are turned on, while A1, B1, B2, and B3 are turned off, and flying capacitor C... F1 One end is connected to VIN via A3, and the switch node SW A Connect A2 to the flying capacitor C F2 One end. In switch state S8, the flying capacitor C F1 Charging, flying capacitor C F2 Discharge. The current in inductor L1 splits into two paths; one path flows sequentially through A3 and the flying capacitor C. F1 The other current flows sequentially through the flying capacitor C. F2 A2; Inductor L2 has no current.

[0047] In switch state S9, power transistor B2 is turned on, and transistors A1, A2, A3, B1, and B3 are turned off, and switch node SW... B Connect B2 to the flying capacitor C F2 One end, flying across capacitor C F2 Discharge. In switch state S9, inductor L2 discharges through B2 from flying capacitor C. F2 During charging, there is no current flowing through inductor L1.

[0048] The other switch states S3, S5, and S6 are as described above.

[0049] Understandably, in switch state S1, switch node SW A Voltage is V CF2 Switch node SW B Voltage is GND, switching node SW C The voltage is VIN. In switch state S2, the switch node SW... A Voltage is GND, switching node SW B The voltage is GND. In switch state S3, the switch node SW... A Voltage is GND, switching node SW B Voltage is V CF2 Switch node SW C Voltage is V CF2 In switch state S4, switch node SW A Voltage is V CF2Switch node SW B Voltage is V CF2 Switch node SW C The voltage is VIN. In switch state S5, the switch node SW... A Voltage is GND, switching node SW B Voltage is V OUT In switch state S6, switch node SW A Voltage is V OUT Switch node SW B The voltage is GND. In switch state S7, the switch node SW... A Voltage is V OUT Switch node SW B Voltage is V OUT In switch state S8, switch node SW A Voltage is V CF2 Switch node SW B Voltage is V OUT Switch node SW C The voltage is VIN. In switch state S9, the switch node SW... A Voltage is GND, switching node SW B Voltage is V CF2 Switch node SW C Voltage is V CF2 .

[0050] The transient multiphase DC-DC converter provided in this invention has a self-balancing characteristic of switching node voltage under inductor current sharing control, eliminating the need for an additional flying capacitor calibration module. The following is a theoretical analysis of the self-balancing of switching node voltage: The schematic diagram of the self-balancing principle of the switching node voltage for a transient multiphase DC-DC converter, as shown below. Figure 9 As shown, the flying capacitor C is illustrated under different switching states during the first cycle of the CCM continuous conduction mode. F1 C F2 The voltage change waveform is analyzed, neglecting the switching impedance of the power transistor. In the first cycle, during switching state S1, it is assumed that the voltage changes from the flying capacitor C... F2 The amount of charge flowing out is The charge flowing out of inductor L1 After the switch state S1 ends, the switch state S2 contains: ; ; ; ; in, Indicates the flying capacitor CF1 The voltage maintained during state S2 after switching state S1. Indicates the flying capacitance C during the first cycle F1 With C F2 The same voltage is maintained after the final charge sharing in switch state S3. Indicates the flying capacitor C F1 The capacitance value, Indicates the flying capacitor C F1 The voltage maintained in state S2 after switching state S1.

[0051] Due to current sharing control, the charge flowing out of inductor L2 is also... The following can be calculated after the switch state S3 ends: ; ; in, Indicates the flying capacitance C during the second cycle F1 With C F2 The same voltage is maintained after the final charge sharing in switch state S3. Indicates the flying capacitor C F2 The capacitance value, due to the flying capacitor C F1 With C F2 With equal capacitance values, we will use the same method from now on. express.

[0052] The second cycle is calculated using the same method, assuming the capacitor C is flying across the circuit. F2 The amount of charge flowing out is When switch state S2 ends, we have: ; ; ; ; Simplifying, we get: ; ; Continuing to calculate the switch state S3, we can obtain: ; .

[0053] in, Indicates the flying capacitance C during the third cycle F1 With C F2 The same voltage is maintained after the final charge sharing in switch state S3. Indicates the switching capacitor in the second cycle. The amount of charge flowing out during switch state S3.

[0054] The flying capacitor C can be found through recursive calculation. F2 The charging and discharging are balanced during the state switch S1 and S3 phases respectively, and the voltage on it remains unchanged.

[0055] Figure 10 (a) shows the pre-simulation waveform of the transient superimposed DC-DC converter in CCM continuous conduction mode before voltage self-balancing verification. In the pre-simulation, the flying capacitor C can be seen. F2 The current is balanced during charging and discharging, and its voltage remains constant, consistent with the results of theoretical analysis.

[0056] Figure 10 Figure (b) shows the simulation waveform of the transient phase-multiplexed DC-DC converter before the switching node voltage in the CCM continuous conduction mode. It can be seen that the switching node voltage remains consistent between the two phases in the CCM continuous conduction mode, which proves that the transient phase-multiplexed DC-DC converter provided by the present invention has the characteristic of self-balancing switching node voltage under current sharing control.

[0057] In Deep DCM deep discontinuous conduction mode, under steady state C F1 With C F2 There is an offset voltage, which varies over a fixed period of time. T on The on-resistance R of B2 B2 The on-resistance R of B3 B3 Inductance value L, input voltage VIN, output voltage V OUT Jointly decided; among them, This refers to the operating duration of switch state S3 in Deep DCM (Deep Discontinuous Conduction Mode).

[0058] The pre-simulation waveforms of the inductor current and power transistor gate drive signal of the transient multiphase DC-DC converter in Deep DCM mode are shown below. Figure 11 As shown in (a), in Deep DCM deep discontinuous conduction mode, in order to compensate for the flying capacitor C F2 The charge prevents the capacitor C from flying across. F2 The system crash caused by only outflowing and not inflowing charge is addressed in this embodiment by artificially introducing a switching state S3 before switching state S9. This results in a slight reverse current flowing through inductor L1 in switching state S3. The pre-simulation waveforms of the inductor current and the power transistor gate drive signal in TRANS transient enhancement mode are shown below. Figure 11 As shown in (b). Assume that the charging time for both phase inductors in each cycle is T. ON The duration of switch state S3 is The duration of switch state S9 is T. ON - It can be foreseen that, due to the asymmetry between switch state S8 and switch states S3 and S9, the flying capacitor C... F1 With C F2 After the Deep DCM (Deep Discontinuous Conduction Mode) system stabilizes, a certain offset voltage exists. In reality, this offset voltage is affected by a fixed set duration. The impact, as long as T is set properly fix This ensures that the system can still function well even when the offset voltage is within a suitable range. The following section discusses the flying capacitor C in Deep DCM (deep discontinuous conduction) mode. F1 With C F2 A detailed quantitative calculation of the steady-state average voltage is performed: Figure 12 For transient superimposed DC-DC converters in Deep DCM (deep discontinuous conduction mode), the flying capacitor C F1 With C F2 Voltage change curve, where the flying capacitor C F1 Charging in state S8 and discharging in state S3, V at the beginning and end of one cycle. CF1 Assuming that state S3 remains unchanged, the capacitor C flies across the capacitor. F1 voltage drop .

[0059] In switch state S3, first calculate the switch node SW. B The voltage, according to the switching node SW B The average current relationships are as follows: ; in, This indicates that switch state S3 is from the flying capacitor C F1 The average current flowing out of the upper part, This represents the average current flowing through inductor L2 in switch state S3. This indicates that switch state S3 is from the flying capacitor C F2 The average current flowing out of the upper part.

[0060] Assume the on-resistance of B2 is R B2 The on-resistance of B3 is R B3 We can obtain: ; in, Indicates the flying capacitor C F1 The average voltage on, Indicates the switch node SW within state S3 B average voltage, This represents the inductance value of inductor L2. This indicates the set fixed duration. Indicates the flying capacitor C F2 The average voltage on.

[0061] Simplify to obtain the switch node SW B The average voltage is: ; According to the switch node SW B The voltage can be calculated to obtain the flying capacitor C under switch state S3. F1 Average discharge current for: ; in, Indicates the switch node SW B The average voltage.

[0062] Therefore, the flying capacitor C can be obtained. F1 The voltage drop on for: ; In switch state S8, according to switch node SW A The average current relationships are as follows: ; in, This represents the average current flowing through inductor L1 in switch state S8. This indicates that switch state S8 is from the flying capacitor C F1 The average current flowing out of the upper part, This indicates that switch state S8 is from the flying capacitor C F2 The average current flowing out of the upper part.

[0063] After the system stabilizes, the capacitor C jumps within one cycle. F2 When charging and discharging reach charge balance, we obtain the equation: ; The previously calculated , , Substituting into the above equation, we get: ; Simplifying, we get: ; if: ; ; ; ; ; ; ; The calculation yielded: .

[0064] When the transient multiphase DC-DC converter operates in steady-state CCM continuous conduction mode, the switching node SW A SW B The voltage is automatically balanced to V CF2 C in Deep DCM mode F2 There is an offset voltage. After the transient switch from light to heavy load to CCM continuous conduction mode, the switching node SW... A SW B The voltage automatically rebalances and returns to V. CF2 .

[0065] Figure 13 For transient multiphase DC-DC converters, the flying capacitor C during light-load / heavy-load transient switching... F1 With C F2 The simulation waveform before the voltage change shows that in Deep DCM (Deep Discontinuous Conduction Mode) with a load current of 0.2A, the flying capacitor C... F2 The actual simulation result for the voltage is 5.5V, which is within an acceptable range. Figure 13 After a 4ms transient switch to 4.2A, the system enters CCM continuous conduction mode, at which point the flying capacitor C... F1 With C F2 Restore charging and discharging under current sharing control, C F2 The voltage remains constant during the two-phase period, the switching node voltage is self-balancing, and the inductor current and power transistor gate drive signal during transient switching are as follows: Figure 11 As shown in (b).

[0066] The transient multiphase DC-DC converter may also include a single-sided sampling double-sided ZCD detection module; the single-sided sampling double-sided ZCD detection module may include: SW B Sampling comparison branch, capacitor storage branch, logic shielding branch; SW B Sampling comparison branch to switch node SW B Single-ended sampling is performed to generate a zcdB zero-crossing signal; The capacitor storage branch stores the voltage V corresponding to the duration of L2 current conduction through two capacitors C1 and C2. save1 V save2 As a capacitor, it stores voltage; The logic shielding branch generates shielding signals shield1_1, shield1_2, shield2_1, and shield2_2 based on the frequency division of hsonA and pwm2. Combined with the capacitor storage voltage, it triggers zcdA_1 and zcdA_2 in a time-division manner. Then, the shielding signals zcdA_pass1 and zcdA_pass2 are used to perform AND and OR logic operations to output the zcdA double-sided zero-crossing signal adapted to A1, A2, and A3.

[0067] Existing DSD, CCC topology SW A SW B Both are affected by the interference of the flying capacitor current, making direct sampling impossible to achieve accurate ZCD; in the embodiments of this invention, SW B The node has no additional capacitive current disturbance, only affecting SW. B By performing single-sided sampling and obtaining the two-phase inductor zero-crossing signals zcdA and zcdB through logical timing deduction, single-sided sampling and double-sided ZCD detection are achieved, completely solving the problem of misjudgment of ZCD under light load.

[0068] SW B Sampling comparison branch with SW B The voltage is the sampling object. A fixed bias current I1 and voltage divider resistors R1, R2, and R3 are configured to sample SW. B The voltage is converted to the comparator input. When the L2 inductor current I L2 Reduced to threshold I1 R1 / R B1 At this time, the comparator flips to generate an accurate and interference-free B-phase zero-crossing signal zcdB.

[0069] Utilizing the timing correlation characteristics of two-phase PWM, the L2 current timing signal pwm2 is frequency-divided to generate a shielding signal, and the zero-crossing duration of L2 is stored in sampling capacitors C1 and C2. Then, combined with the L1 upper transistor turn-on timing hsonA, capacitor charging and discharging comparison is performed to generate two sub-zero-crossing signals zcdA_1 and zcdA_2 in a time-division manner. Enable shielding signals zcdA_pass1 and zcdA_pass2 are generated through zcdB, and AND and OR logic operations are performed with the two sub-signals to output the final A-phase zero-crossing signal zcdA. zcdA is a double-sided zero-crossing signal adapted to A1, A2, and A3.

[0070] The single-sided sampling double-sided ZCD detection module has a mode-adaptive shielding function. When the transient multiphase DC-DC converter is in the CCM continuous conduction mode, the inductor current is continuously greater than zero, the zcdB zero-crossing signal disappears, and the shielding signals zcdA_pass1 and zcdA_pass2 are completely turned off, preventing the false triggering of the zcdA double-sided zero-crossing signal. The transient multiphase DC-DC converter can normally output the zcdA double-sided zero-crossing signal and the zcdB zero-crossing signal during the startup phase, the Light DCM shallow discontinuous conduction mode, and the Deep DCM deep discontinuous conduction mode.

[0071] When the load increases and the transient superimposed DC-DC converter enters the CCM continuous conduction mode, the inductor current remains greater than 0, the zcdB signal no longer flips, and the shielding signal directly blocks the zcdA path, preventing false triggering of ZCD in the CCM continuous conduction mode and ensuring the stability of the heavy-load loop.

[0072] Figure 14 The following is a schematic diagram of the transistor-level circuit of the single-sided sampling double-sided ZCD detection module, and its specific working principle is as follows: The switching node SW in the transient multiphase DC-DC converter provided in this embodiment of the invention B Unaffected by flying capacitors, it can correctly detect the zcdB signal. Based on this, a correct zcdA signal can be modulated from the zcdB signal, avoiding interference with the switching node SW. A Direct detection.

[0073] Switch node SW B The zero-crossing detection circuit structure is as follows Figure 14 As shown on the left, the inverting input of the comparator is connected to KGND. When the voltage at the non-inverting input is V... B When the value is greater than KGND, the output zcdB is triggered.

[0074] Voltage for: ; in, This indicates the current flowing through MP1. This represents the current flowing through MN1. This indicates the resistance value of the voltage divider resistor R3.

[0075] Simplifying, we get: ; in, This indicates the resistance value of the voltage divider resistor R2.

[0076] Therefore voltage for: ; in >> and >> ,therefore: ; The critical condition for the zcdB output of the inductor L2 branch to flip is: ; After obtaining the zcdB signal, with Figure 15 Taking the single-sided sampling bilateral ZCD detection of the Light DCM shallow discontinuous conduction mode shown in Figure (a) as an example, the specific implementation method of zcdA generation is described: Signal pwm2 is the trigger signal for the current hson of inductor L2. It is frequency-divided to obtain shielding signals shield2_1 and shield2_2. The shield2_1 signal and the lsonB ​​signal are ANDed together to store the duty cycle of one phase in lsonB ​​by charging capacitor C1 with a fixed current, resulting in signal V. save1 The shield2_2 signal and the lsonB ​​signal are ANDed together to charge capacitor C2 with a fixed current and store the duty cycle of another phase in lsonB, thus obtaining signal V. save2 .

[0077] Signal hsonA is the trigger signal for the rising current in inductor L1. The falling edge of signal hsonA is divided to obtain shielding signals shield1_1 and shield1_2. Shield1_1 serves as the trigger signal for one phase of the inductor L1 current, lsonA. At this time, the circuit charges capacitor C4 with a constant current, the charging time depending on signal V. save2 The height, that is, the previously stored inductor current lsonB ​​of inductor L2 is loaded through C4, at the signal V save2 With signal V load2 When the phases are equal (theoretical analysis does not consider offset voltage), zcdA_2 is triggered as a one-phase zcdA signal.

[0078] On the other hand, the shield1_2 signal serves as the trigger signal for another phase, lsonA, in the current of inductor L1. The circuit charges capacitor C3 through a constant current, and the charging time depends on the signal V. save1 The height of the signal V save1 With signal V load1 When they are equal, zcdA_1 is triggered as another zcdA signal.

[0079] Using zcdB as the trigger signal and pwm2 as the turn-off signal, we obtain the zcdA_pass1 and zcdA_pass2 signals. We then perform AND and OR logic operations on signals zcdA_1, zcdA_2 and signals zcdA_pass1, zcdA_pass2 respectively to obtain the complete zcdA signal, thus preventing accidental triggering of signals zcdA_1 and zcdA_2.

[0080] Similarly, the control waveform diagram of the single-sided sampling double-sided ZCD detection module in Deep DCM deep discontinuous conduction mode is as follows: Figure 15 As shown in (b), this logic control strongly correlates the triggering of signal zcdA with signal zcdB. As the load current increases, after the system transitions from Deep DCM (deep discontinuous conduction mode) to CCM (continuous conduction mode), signal zcdB is no longer generated, and shielding signals zcdA_pass1 and zcdA_pass2 are completely turned off, preventing the generation of the zcdA signal. This ensures that the zcdA signal in CCM mode will not be falsely triggered. The pre-simulation waveforms of the single-sided sampling of the bilateral ZCD module signals during overall circuit startup and the pre-simulation waveforms of the single-sided sampling of the bilateral ZCD module signals when the circuit transitions from DCM to CCM are shown below. Figure 16 As shown.

[0081] Secondly, corresponding to the above embodiments, this embodiment of the invention also provides a transient superimposed phase DC-DC conversion method with self-balancing switching nodes, applied to the transient superimposed phase DC-DC converter with self-balancing switching nodes in the first aspect. This transient superimposed phase DC-DC converter, such as... Figure 17 As shown, it may include: S1, the power conversion main circuit, under the control of the control circuit, at the output voltage node V... O Output stable conversion voltage; S2, the control circuit obtains the ripple of the output feedback voltage based on the output feedback voltage and reference voltage corresponding to the conversion voltage, and uses it as the voltage fast loop signal; S3, superimposed on the ripple of the voltage fast loop signal by the switching node SW A SW B The filtered compensation ripple is used to generate the ripple of the output feedback voltage after ripple compensation; this is used to solve the fast loop instability problem caused by the phase shift of the output voltage ripple due to the low ESR ceramic capacitor. S4, using error amplifier EA, the control voltage V is obtained based on the output feedback voltage and the reference voltage. C As a slow-loop voltage signal, it is used to adjust the output voltage accuracy to reduce the system offset of the output voltage. S5, when the ripple of the output feedback voltage after ripple compensation decreases and touches the voltage slow loop signal, an on-control signal is generated. S6 performs frequency division processing on the turn-on control signal and, combined with the clamping of the two-phase current sharing loop, generates an adaptive constant conduction time. S7 generates drive logic based on the turn-on control signal, load conditions, and constant conduction time, driving the operating states of the six power transistors in the power conversion main circuit so that the transient multiphase DC-DC converter operates in the corresponding operating mode and outputs a stable conversion voltage.

[0082] When the ripple of the output feedback voltage after ripple compensation decreases and touches the slow loop voltage signal, the comparator flips as T. ON The comparator's output signal is generated. Frequency division is achieved using two sets of RS flip-flops, and clamping with two-phase current-sharing rings further enables 180° phase splitting of the comparator's output signal. The comparator's output signal is then transmitted to ACOTT. ON The generating circuit produces a constant on-time T. ON Proportional to the output voltage V OUT Inversely proportional to the input voltage V IN This is to ensure that the switching frequency does not change with variations in input and output voltages under steady-state conditions. ON Transmitted to the driver circuit to turn on a specific power transistor, T ON After the process ends, the converter returns to the discharge state of A1 and B1. The converter repeats this process to maintain a stable output voltage.

[0083] The embodiments of the present invention have the following advantages: Transient response capability is greatly improved: S4 phase-in-phase operation in switching state, when the load suddenly increases, the two-phase inductors synchronously replenish the output, the output voltage drop is small and the recovery speed is fast, which meets the high-speed load switching power supply requirements of high-end processors; High-efficiency operation across the entire load range: This embodiment of the invention relies on a single-sided sampling and double-sided ZCD detection scheme to eliminate the interference of the flying capacitor branch on ZCD sampling. The transient superimposed DC-DC converter can operate stably in DCM mode under light load, avoiding the inductor backflow loss of FCCM and significantly improving the light load energy efficiency. Switching node voltage self-balancing, flyaway capacitor voltage offset controllable: no additional V CF Voltage calibration circuit, switching node SW under CCM steady state A With SW B Voltage self-balancing; Deep DCM can control capacitor voltage offset within a safe range through a fixed-duration S3 charge compensation state, eliminating the risk of charge accumulation and collapse; Transient phase-multiplexed DC-DC converters are suitable for 12V to 1V high-dropout, low-voltage, high-current scenarios: multi-phase shunt reduces the switching / conduction stress of single-channel devices, reduces inductor ripple current, and solves the defects of traditional single-phase synchronous Buck converters, such as limited minimum conduction time, low upper limit of output current, and excessive ripple.

[0084] To address the shortcomings of existing DSD and CCC two-phase flying capacitor topologies, such as poor transient response, easy misjudgment of ZCD detection under light load, the need for additional calibration circuitry due to flying capacitor voltage offset, and output waveform variations, this invention proposes a novel six-transistor dual-flying capacitor two-phase hybrid Buck topology. This topology achieves nine switching states and four operating modes—CCM continuous conduction mode, TRANS transient enhancement mode, Light DCM shallow discontinuous conduction mode, and Deep DCM deep discontinuous conduction mode—through the combined switching of six power transistors. A dedicated transient phase overlap state is set up, allowing both phase inductors to simultaneously supply power to the output during load surges, significantly suppressing voltage downscaling and shortening recovery time. This topology only applies to SWs without capacitor current interference. B Single-sided sampling at nodes, combined with timing logic deduction, generates two-phase inductor zero-crossing signals, achieving single-sided sampling and double-sided ZCD detection. This enables stable DCM operation under light loads and reduces return current losses. The topology incorporates a native self-balancing mechanism for switching nodes. In CCM mode, two-phase current sharing control automatically cancels the charge cancellation during the periodic charging and discharging of the flying capacitor, eliminating the need for an additional voltage calibration loop. In deep DCM mode, a fixed-duration S3 charge compensation state actively replenishes the charge of the flying capacitor, keeping capacitor voltage offset within a safe range and preventing unidirectional charge accumulation failure and output large / small fluctuations. This invention is suitable for 12V to 0.6V~2.3V low-voltage high-current processor power supply scenarios, combining excellent transient performance, high efficiency under full load, and the advantages of self-balancing switching nodes, while reducing chip control complexity and hardware costs.

[0085] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A transient superimposed phase DC-DC converter with self-balancing switching nodes, characterized in that, include: Power conversion main circuit and control circuit; The power conversion main circuit comprises a first power transistor A1, a second power transistor A2, a third power transistor A3, a fourth power transistor B1, a fifth power transistor B2, a sixth power transistor B3, a flying capacitor C F1 , a flying capacitor C F2 , an inductor L1 and an inductor L2; The source terminal of the first power transistor A1 is connected to input ground GND, and the drain terminal is connected to the source terminal of the second power transistor A2 and the flying capacitor C. F1 One end of the inductor L1 is connected to the other end of the inductor L1 to form the switching node SW. A ; The drain of the second power transistor A2 and the drain of the fifth power transistor B2, and the flying capacitor C F2 One end is connected to form the switch node SW D ; The source terminal of the third power transistor A3 and the flying capacitor C F1 The other end, the drain of the sixth power transistor B3, is connected to form the switching node SW. C The drain terminal is connected to the input voltage VIN; The source terminal of the fourth power transistor B1 is connected to the input ground GND, and its drain terminal is connected to the source terminals of the fifth power transistor B2, the sixth power transistor B3, and one end of the inductor L2, forming the switching node SW. B ; The flying capacitor C F2 The other end is connected to the input ground GND; Inductor L1 in series with DC equivalent resistance R DCR1 Inductor L2 in series with DC equivalent resistance R DCR2 R DCR1 With R DCR2 The other end is connected to form the output voltage node V. O ; The control circuit uses V 2 The ACOT architecture includes an error amplifier EA, an RC filter circuit, a multi-input transconductor gm, a comparator comp, an ACOT Ton generation circuit, logic circuits, and a gate drive circuit. The error amplifier EA is based on the output voltage node V. O The corresponding output feedback voltage V FB and bandgap reference V REF Output control voltage V C ; The RC filter circuits respectively draw from the switching node SW A SW B The inductor current sampling signal R is obtained by sampling. sen I L1 R sen I L2 Perform ripple compensation; The multi-input transconductor gm will V FB V REF V C R sen I L1 R sen I L2 The current is converted and superimposed, and then a comparator is used to generate an on-control signal. The ACOT Ton generation circuit generates an adaptive constant on-time T based on the DCR sampling of L1 and L2 and the frequency-divided signal of the turn-on control signal. on To achieve uniform flow between the two phases; The logic circuit outputs drive logic based on the turn-on control signal, load conditions, and constant on-time. The gate drive circuit is connected to the gates of the six power transistors in the main power conversion circuit. According to the drive logic, it drives the operating state of the six power transistors and controls the transient superimposed DC-DC converter to work in the corresponding operating mode so as to output a stable conversion voltage.

2. The self-balancing transient superimposed phase DC-DC converter with switching nodes according to claim 1, characterized in that, The six power transistors in the power conversion main circuit combine to form nine switching states S1 to S9; the conduction logic corresponding to each switching state includes: Switch state S1: A2, A3, B1 are on; A1, B2, B3 are off; C F1 Charging, C F2 Charge first, then discharge; L1 is split into two paths, and L2 discharges via B1. Switch state S2: A1 and B1 are on, A2, A3, B2, and B3 are off, C F1 C F2 The voltage is maintained, and L1 and L2 freewheel to ground through A1 and B1, respectively; Switch state S3: A1, B2, B3 are on, A2, A3, B1 are off, C F1 First, C F2 The charging and power supply to L2 are combined, and L1 continues to ground through A1; Switch state S4: A2, A3, B2 are on, A1, B1, B3 are off, C F1 Charging, C F2 Discharge, SW A With SW B Equipotential, L2 is caused by C F2 Power supply, achieving two-phase superposition; Switch state S5: Only A1 is on, A2, A3, B1, B2, and B3 are off, L1 freewheels to ground, and L2 has no current. Switch state S6: Only B1 is on, A1, A2, A3, B2, and B3 are off, L2 freewheels to ground, and L1 has no current. Switching state S7: All six power transistors are turned off, the current in L1 and L2 is zero, and the load is freewheeled by the output capacitor Co; Switch state S8: A2 and A3 are on, A1, B1, B2, and B3 are off, C F1 Charging, C F2 During discharge, only L1 has a shunt current, while L2 has no current. Switch state S9: Only B2 is on, A1, A2, A3, B1, and B3 are off, C F2 The discharge supplies power to L2, and there is no current in L1.

3. The self-balancing transient superimposed phase DC-DC converter with switching nodes according to claim 2, characterized in that, The operating modes of the transient cascaded DC-DC converter include: CCM continuous conduction mode, TRANS transient enhancement mode, Light DCM shallow discontinuous conduction mode, and Deep DCM deep discontinuous conduction mode; The corresponding switching states during the working cycle of the CCM continuous conduction mode are as follows: S1, S2, S3, S2; The corresponding switching states during the duty cycle of the TRANS transient enhancement mode are as follows: Activate S4 to interrupt any existing switch state when a transient enhancement signal is detected, thereby achieving superimposed phase compensation of two-phase inductors; The corresponding switching states during the working cycle of the Light DCM shallow intermittent conduction mode are as follows: S1, S2, S5, S3, S2, S6; The corresponding switching states during the working cycle of the Deep DCM deep discontinuous conduction mode are as follows: S8, S5, S7, S3, S9, S6, S7.

4. The self-balancing transient superimposed phase DC-DC converter with switching nodes according to claim 3, characterized in that, In the Deep DCM deep discontinuous conduction mode, C in steady state F1 With C F2 There is an offset voltage, which varies over a fixed period of time. T on The on-resistance R of B2 B2 The on-resistance R of B3 B3 Inductance value L, input voltage VIN, output voltage V OUT Jointly decided; among them, This refers to the operating duration of switch state S3 in Deep DCM (Deep Discontinuous Conduction Mode).

5. The self-balancing transient superimposed phase DC-DC converter with switching nodes according to claim 3, characterized in that, The transient phase-multiplexed DC-DC converter further includes a single-sided sampling double-sided ZCD detection module; the single-sided sampling double-sided ZCD detection module includes: SW B Sampling comparison branch, capacitor storage branch, logic shielding branch; The SW B Sampling comparison branch to switch node SW B Single-ended sampling is performed to generate a zcdB zero-crossing signal; The capacitor storage branch stores the voltage V corresponding to the conduction time of L2 current through two capacitors C1 and C2. save1 V save2 It is used to store voltage as a capacitor; The logic shielding branch generates shielding signals shield1_1, shield1_2, shield2_1, and shield2_2 based on the frequency division of hsonA and pwm2. Combined with the capacitor storage voltage, it triggers zcdA_1 and zcdA_2 in a time-division manner. Then, the shielding signals zcdA_pass1 and zcdA_pass2 are used to perform AND and OR logic operations to output zcdA double-sided zero-crossing signals that are adapted to A1, A2, and A3.

6. The self-balancing transient superimposed phase DC-DC converter with switching nodes according to claim 5, characterized in that, The single-sided sampling double-sided ZCD detection module has a mode-adaptive shielding function. When the transient multiphase DC-DC converter is in the CCM continuous conduction mode, the inductor current is continuously greater than zero, the zcdB zero-crossing signal disappears, and the shielding signals zcdA_pass1 and zcdA_pass2 are completely turned off, preventing the false triggering of the zcdA double-sided zero-crossing signal. The transient multiphase DC-DC converter can normally output the zcdA double-sided zero-crossing signal and the zcdB zero-crossing signal during the startup phase, the Light DCM shallow discontinuous conduction mode, and the Deep DCM deep discontinuous conduction mode.

7. The self-balancing transient superimposed phase DC-DC converter with switching nodes according to claim 3, characterized in that, The transient multiphase DC-DC converter operates in a two-phase multiphase state in TRANS transient enhancement mode, S4. A With SW B The potentials are all VIN / 2, C F1 Continuous charging, C F2 Energy is simultaneously supplied to both L1 and L2 inductors.

8. The self-balancing transient superimposed phase DC-DC converter with switching nodes according to claim 3, characterized in that, When the transient multiphase DC-DC converter operates in steady-state CCM continuous conduction mode, the switching node SW A SW B The voltage is automatically balanced to V CF2 C in Deep DCM mode F2 There is an offset voltage. After the transient switch from light to heavy load to CCM continuous conduction mode, the switching node SW... A SW B The voltage automatically rebalances and returns to V. CF2 .

9. A method for transient tandem DC-DC conversion with self-balancing switching nodes, applied to the transient tandem DC-DC converter with self-balancing switching nodes as described in any one of claims 1 to 8, characterized in that, include: The power conversion main circuit, under the control of the control circuit, operates at the output voltage node V. O Output stable conversion voltage; The ripple of the output feedback voltage is obtained by the control circuit based on the output feedback voltage and the reference voltage corresponding to the conversion voltage, and is used as the voltage fast loop signal. The ripple of the voltage fast loop signal is superimposed by the switching node SW. A SW B The filtered compensation ripple is used to generate the ripple of the output feedback voltage after ripple compensation. The control voltage V is obtained using the error amplifier EA based on the output feedback voltage and the reference voltage. C , as a voltage slow loop signal; When the ripple of the output feedback voltage after ripple compensation decreases and touches the voltage slow loop signal, an on-control signal is generated. The turn-on control signal is frequency divided and combined with the clamping of the two-phase current sharing loop to generate an adaptive constant conduction time. The driving logic is generated based on the turn-on control signal, load conditions, and constant conduction time to drive the operating states of the six power transistors in the main power conversion circuit, so that the transient multiphase DC-DC converter can operate in the corresponding operating mode and output a stable conversion voltage.

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