Controller for controlling a converter

Abstract

This disclosure provides a controller for controlling a converter including a switch and an inductor, and converting power between an input voltage and an output voltage. The controller includes: a current ripple detection circuit for detecting the current ripple of the inductor; a conduction interval control circuit for generating a duty cycle end signal; and a duty cycle control circuit for generating a duty cycle control signal for controlling the duty cycle of the converter based on the inductor current ripple and the duty cycle end signal. The duty cycle control signal can indicate the start and end times of a conduction interval, which is an interval in which the inductor current increases. The start time of the conduction interval can be determined based on the inductor current ripple, and the end time of the conduction interval can be determined based on the duty cycle end signal.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2025-0114297, filed with the Korean Intellectual Property Office on August 18, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This invention relates to a controller for controlling a converter. More specifically, it relates to a controller that can reduce frequency fluctuations when controlling converters used for power conversion, such as buck-boost converters. Background Technology

[0003] Power converters, such as buck-boost converters, are widely used within mobile devices to convert voltage for charging batteries or managing system power. To control these power converters, it is often necessary to sense the current flowing through components within the converter (e.g., inductors). The most common approach is to use a DC current sense resistor external to the chip containing the controller. This DC current sense resistor is one that can simultaneously sense both the DC component and the ripple component of the current. While such DC current sense resistors are commonly used, the significant power dissipation caused by the direct flow of current through the sense resistor not only reduces overall efficiency but also results in a large size due to the heat generated by the power dissipation. This problem is exacerbated in mobile applications where space constraints and low-voltage, high-current operation necessitate alternative solutions.

[0004] Power converters typically operate by alternating between two states (and possibly more than three states depending on the situation) through the on / off action of internal switches. Within these states, the period during which energy accumulates in the inductors within the converter is called the on-state (when multiple switches are present, there may also be off switches within the on-state; therefore, the on-state does not mean that all internal switches are on. The on-state can be distinguished based on whether the inductor energy increases; however, in cases with more than three states, a different definition may be needed). The period during which the energy accumulated in the inductors is discharged is called the off-state. The sum of the on-state and off-state is the switching period, and the value obtained by dividing the on-state by the switching period is usually called the duty cycle.

[0005] In power converters, the relationship between the input and output voltages can be adjusted by changing the relative lengths of the on and off intervals. For example, with a fixed input voltage, increasing the on interval will increase the output voltage. The converter can adjust the output voltage in this way. Various methods exist for changing the relative lengths of the on and off intervals, among which the fixed on interval control method, which fixes the on interval and adjusts the off interval, is widely used.

[0006] In the fixed on-section control method, the on-section is fixed, and the output voltage is adjusted by regulating the off-section. If the on-section is fixed while the off-section changes, the switching period (i.e., the switching frequency) also changes. When the operating range of the input and output voltages is wide, the fluctuation range of the switching period increases. In particular, widely used multi-mode buck-boost converters, which can operate in buck, boost, and buck-boost modes, have the advantage of being able to operate over a wide input and output voltage range, but this may exacerbate the switching frequency fluctuation problem. Summary of the Invention

[0007] One of the problems that this invention aims to solve is to perform current control by embedding a component that detects the ripple component of the current inside the chip instead of using a DC current sensing resistor, thereby reducing the size and manufacturing cost.

[0008] One of the problems to be solved by the present invention is to control a power converter that operates under a wide range of input and / or output voltages using an adaptive conduction range control method, thereby reducing the fluctuation range of the switching frequency.

[0009] One of the problems to be solved by this invention is to control a multi-mode buck-boost converter that operates in buck mode, boost mode and buck-boost mode using an adaptive conduction interval control method, thereby reducing the fluctuation range of the switching frequency.

[0010] The problems to be solved by the present invention are not limited to those described above, and various problems not mentioned herein may also be included in this specification.

[0011] One aspect of the present invention is a controller for controlling a converter, the converter including a switch and an inductor, and converting power between an input voltage and an output voltage, the controller comprising: a current ripple detection circuit that detects the current ripple of the inductor; a conduction interval control circuit that generates a duty cycle end signal; and a duty cycle control circuit that generates a duty cycle control signal for controlling the duty cycle of the converter based on the current ripple of the inductor and the duty cycle end signal.

[0012] As one embodiment, the duty cycle control signal can indicate the start and end time points of the conduction interval, which is the interval in which the current of the inductor increases. The start time point of the conduction interval can be determined based on the current ripple of the inductor, and the end time point of the conduction interval can be determined based on the duty cycle end signal.

[0013] As one embodiment, the duty cycle control circuit can, in order to control the output voltage detection signal to follow the output voltage reference signal, amplify the error between the output voltage detection signal and the output voltage reference signal to generate an output voltage control signal; generate an inductor current detection signal based on the current ripple of the inductor; and compare the inductor current detection signal with the output voltage control signal to indicate the start of the conduction interval.

[0014] As one embodiment, the inductor current detection signal can be generated by superimposing an offset voltage corresponding to the output voltage onto a current ripple detection voltage corresponding to the magnitude of the inductor's current ripple.

[0015] As one embodiment, the current ripple detection circuit may include: a first detection resistor, one end of which is connected to one end of the inductor; a detection capacitor, one end of which is connected to the other end of the first detection resistor; a second detection resistor, one end of which is connected to the other end of the detection capacitor, and the other end of which is connected to the other end of the inductor; a first detection switch connected in parallel with the first detection resistor; and a second detection switch connected in parallel with the second detection resistor; wherein the current ripple detection circuit generates a current ripple detection voltage based on the voltage applied across the detection capacitor.

[0016] As one embodiment, the converter may be a converter that operates in at least one of buck mode, boost mode, or buck-boost mode; in the buck mode, the first detection switch may be turned off and the second detection switch may be turned on; in the boost mode, the first detection switch may be turned on and the second detection switch may be turned off; and in the buck-boost mode, both the first detection switch and the second detection switch may be turned off.

[0017] As one embodiment, the first detection resistor, the second detection resistor, the first detection switch, the second detection switch, and the detection capacitor can all be implemented within the semiconductor chip that implements the controller.

[0018] As one embodiment, the converter can operate in at least one of buck mode, boost mode, or buck-boost mode.

[0019] As one embodiment, when the converter operates in the buck mode, the conduction interval control circuit can operate in a manner that decreases the conduction interval when the input voltage increases, and can operate in a manner that increases the conduction interval when the output voltage increases.

[0020] As an example, when the converter operates in the buck mode, the conduction interval control circuit can generate a ramp reference voltage with a magnitude corresponding to the output voltage, generate a ramp voltage with a slope corresponding to the input voltage, and compare the ramp voltage with the ramp reference voltage to generate the duty cycle end signal indicating the end of the conduction interval.

[0021] As one embodiment, the ramp reference voltage may be substantially proportional to the output voltage, and the slope of the ramp voltage may be substantially proportional to the input voltage.

[0022] As one embodiment, when the converter operates in the boost mode, the conduction interval control circuit can operate in a manner that reduces the conduction interval when the input voltage increases, and can operate in a manner that increases the conduction interval when the output voltage increases.

[0023] As an example, when the converter operates in the boost mode, the conduction interval control circuit can generate a ramp reference voltage with a magnitude corresponding to the value obtained by subtracting the input voltage from the output voltage, generate a ramp voltage with a slope corresponding to the output voltage, and compare the ramp voltage with the ramp reference voltage to generate the duty cycle end signal indicating the end of the conduction interval.

[0024] As one embodiment, the ramp reference voltage may be substantially proportional to the value obtained by subtracting the input voltage from the output voltage, and the slope of the ramp voltage may be substantially proportional to the output voltage.

[0025] As one embodiment, when the converter operates in the buck-boost mode, the conduction interval control circuit can operate in a manner that reduces the conduction interval when the input voltage increases, and can operate in a manner that increases the conduction interval when the output voltage increases.

[0026] As an example, when the converter operates in the buck-boost mode, the conduction interval control circuit can generate a ramp reference voltage with a magnitude corresponding to the value obtained by subtracting the product of the input voltage and a predetermined constant from the output voltage, generate a ramp voltage with a slope corresponding to the output voltage, and compare the ramp voltage with the ramp reference voltage to generate the duty cycle end signal indicating the end of the conduction interval.

[0027] As an example, the ramp reference voltage can be substantially proportional to the value obtained by subtracting the product of the input voltage and a predetermined constant from the output voltage, and the slope of the ramp voltage can be substantially proportional to the output voltage.

[0028] As one embodiment, the conduction interval control circuit can generate the duty cycle end signal based on both the input voltage and the output voltage, and operate in a manner that increases the conduction interval when the duty cycle of the converter, determined by the input voltage and the output voltage, increases, and operates in a manner that decreases the conduction interval when the duty cycle of the converter, determined by the input voltage and the output voltage, decreases, thereby reducing the fluctuation of the switching cycle of the converter.

[0029] As one embodiment, the converter may be a buck-boost converter operating in at least two of the following modes: buck mode, boost mode, and buck-boost mode; the conduction interval control circuit may include: a first current source supplying a current substantially proportional to the input voltage; a second current source supplying a current substantially proportional to the output voltage; and a third current source supplying a current substantially proportional to the output voltage; the conduction interval control circuit may generate a ramp voltage having a slope determined by the current supplied from either the first or second current source according to the operating mode; a mode correction voltage preset according to the operating mode may be subtracted from the voltage generated based on the current supplied by the third current source to generate a ramp reference voltage; and the ramp voltage may be compared with the ramp reference voltage to generate a duty cycle end signal indicating the end of the conduction interval.

[0030] As an example, in the buck mode, the mode correction voltage can be 0; in the boost mode, the mode correction voltage can be the input voltage; and in the buck-boost mode, the mode correction voltage can be the value obtained by multiplying the input voltage by a predetermined constant.

[0031] According to the embodiment, instead of using a DC current sensing resistor, a component for sensing the ripple component of the current is built into the chip to perform current control, thereby reducing size and manufacturing cost.

[0032] According to an embodiment, an adaptive conduction range control method is used to control a power converter that operates over a wide range of input and / or output voltages, thereby reducing the fluctuation range of the switching frequency.

[0033] According to the embodiment, an adaptive conduction interval control method is used to control a multi-mode buck-boost converter that operates in buck mode, boost mode, and buck-boost mode, thereby reducing the fluctuation range of the switching frequency.

[0034] The effects of the present invention are not limited to those described above, and various effects not mentioned herein may also be included in this specification. Attached Figure Description

[0035] The accompanying drawings, which are included in and form part of this specification, are provided to give a further understanding of the present disclosure. The drawings illustrate embodiments of the present disclosure and, together with the specification, serve to explain the principles of the present disclosure.

[0036] Figure 1 This is one embodiment of a controller used to control a converter.

[0037] Figure 2 An example of a multi-mode buck-boost converter is shown as an embodiment of a converter for power conversion.

[0038] Figure 3 This is an embodiment of a current ripple detection circuit.

[0039] Figure 4 This is an embodiment of a conduction interval control circuit.

[0040] Figure 5 This is an embodiment of a duty cycle control circuit.

[0041] Figures 6 to 8 This example illustrates the buck mode operation of a multi-mode buck-boost converter.

[0042] Figures 9 to 11 This example illustrates the boost mode operation of a multi-mode buck-boost converter.

[0043] Figures 12 to 15 This example illustrates the buck-boost mode operation of a multi-mode buck-boost converter.

[0044] Figure 16 Another embodiment of the conduction interval control circuit is shown. Detailed Implementation

[0045] Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary accompanying drawings. It should be noted that when affixing reference numerals to the constituent elements of each drawing, the same constituent elements will be labeled identically, even if shown in different drawings. Furthermore, in describing the present invention, detailed descriptions of relevant well-known structures or functions will be omitted if it is determined that such detailed descriptions may obscure the spirit of the present invention.

[0046] Furthermore, when describing the constituent elements of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only used to distinguish the constituent element from other constituent elements and do not limit the nature, order, or sequence of the corresponding constituent elements. When a constituent element is described as being "connected," "combined," or "continuing" with another constituent element, it should be understood that the constituent element can be directly connected to or continued to the other constituent element; however, another constituent element can also be "connected," "combined," or "continuing" between constituent elements.

[0047] Figure 1 This is one embodiment of a converter controller.

[0048] Reference Figure 1 The controller 100 may optionally include at least a portion of the current ripple detection circuit 110, the conduction interval control circuit 120, the duty cycle control circuit 130, and the drive circuit 140.

[0049] The controller 100 can control the converter 10 (hereinafter referred to as the "converter") used for power conversion. The converter 10 may include switches and inductors internally, and converts power between the input voltage VIN and the output voltage VOUT. The converter 10 may be one of various converters that convert and transfer voltage or power, such as a buck converter, a boost converter, or a buck-boost converter. The converter 10 is known technology, therefore its detailed description is omitted in this specification.

[0050] The current ripple detection circuit 110 can detect the current ripple (fluctuation component) flowing through the components included inside the converter 10. As one embodiment, the current ripple detection circuit 110 can detect the current ripple of the inductor included inside the converter 10. The current ripple detected by the current ripple detection circuit 110 can be provided to the duty cycle control circuit 130 in the form of a voltage signal VRS. To detect the current ripple, the current ripple detection circuit 110 can receive the voltages VL1 and VL2 across the inductor terminals from the converter 10.

[0051] The conduction interval control circuit 120 can generate a duty cycle end signal RESET. The duty cycle end signal RESET can be provided to the duty cycle control circuit 130, which can then generate a signal indicating the end of the duty cycle. To generate the duty cycle end signal RESET, the conduction interval control circuit 120 can receive input voltage VIN and output voltage VOUT information.

[0052] The duty cycle control circuit 130 can generate a duty cycle control signal CONT for controlling the duty cycle of the converter 10 based on the inductor's current ripple and the duty cycle end signal RESET. To this end, the duty cycle control circuit 130 can receive a voltage signal VRS corresponding to the current ripple from the current ripple detection circuit 110 and a duty cycle end signal RESET from the conduction interval control circuit 120.

[0053] As one embodiment, the duty cycle control signal CONT may include a first state and a second state. When the duty cycle control signal CONT is in the first state, the inductor current inside the converter 10 may increase; when the duty cycle control signal CONT is in the second state, the inductor current may decrease. The start time of the first state may be determined based on the inductor current ripple, and the end time of the first state may be determined based on the duty cycle end signal RESET.

[0054] As one embodiment, the duty cycle control signal CONT may include a first state, a second state, and a third state. When the duty cycle control signal CONT is in the first state, the inductor current inside the converter 10 can increase; when the duty cycle control signal CONT is in the third state, the inductor current can decrease. In the second state, the inductor current can increase or decrease depending on the operating environment. The start time of the first state can be determined based on the inductor current ripple, and the end time of the first state can be determined based on the duty cycle end signal RESET.

[0055] The drive circuit 140 can receive a duty cycle control signal CONT from the duty cycle control circuit 130, and generate a drive signal DQn based on the duty cycle control signal CONT to drive the switch inside the converter 10. The drive signal DQn can be applied to the control terminal (e.g., the gate terminal of a MOSFET) of the switch inside the converter 10 to drive the switch.

[0056] Figure 2 An example of a multi-mode buck-boost converter is shown as an embodiment of converter 10.

[0057] Reference Figure 2 The converter 10 may include a first switch to a fourth switch Q1, Q2, Q3, Q4 and an inductor L. Figure 2For ease of explanation, only the main components of converter 10 are briefly shown. Converter 10 may also include various components such as smoothing capacitors, switching drive components, and detection components.

[0058] The first switch Q1 and the second switch Q2 can be connected in series between the input voltage VIN and the reference potential GND. The third switch Q3 and the fourth switch Q4 can be connected in series between the output voltage VOUT and the reference potential GND. One end of the inductor L can be connected to the connection node of the first switch Q1 and the second switch Q2, and the other end of the inductor L can be connected to the connection node of the third switch Q3 and the fourth switch Q4.

[0059] The driving signals DQ1, DQ2, DQ3, and DQ4 generated by the driving circuit 140 can be applied to the control terminals (e.g., gate terminals) of the first to fourth switches Q1, Q2, Q3, and Q4, respectively, to drive the first to fourth switches Q1, Q2, Q3, and Q4.

[0060] As mentioned earlier, the voltages VL1 and VL2 across the terminals of inductor L can be provided to the current ripple detection circuit 110 to extract the current ripple information of inductor L.

[0061] Figure 2 The illustrated converter 10 is a buck-boost converter capable of operating in at least one of buck mode, boost mode, and buck-boost mode. As one embodiment, Figure 2 The illustrated buck-boost converter 10 can operate in buck mode, boost mode, and buck-boost mode. Typically, buck mode is used when the input voltage VIN is higher than the output voltage VOUT, boost mode is used when the input voltage VIN is lower than the output voltage VOUT, and buck-boost mode can be used regardless of the relationship between the input voltage VIN and the output voltage VOUT.

[0062] Converter 10 can receive power from input voltage VIN and transfer it to output voltage VOUT. Alternatively, converter 10 can also receive power from output voltage VOUT and transfer it to input voltage VIN. Alternatively, converter 10 can also transfer power bidirectionally between input voltage VIN and output voltage VOUT.

[0063] Figure 3 This is an embodiment of a current ripple detection circuit.

[0064] Reference Figure 3The current ripple detection circuit 110 may include: a first detection resistor RS1, one end of which is connected to one end of an inductor L; a detection capacitor CS, one end of which is connected to the other end of the first detection resistor RS1; a second detection resistor RS2, one end of which is connected to the other end of the detection capacitor CS, and the other end of which is connected to the other end of the inductor L; a first detection switch SS1, which is connected in parallel with the first detection resistor RS1; and a second detection switch SS2, which is connected in parallel with the second detection resistor RS2.

[0065] The current ripple detection circuit 110 can receive the voltage VL1 at one end of the inductor through the first detection resistor RS1 and the voltage VL2 at the other end of the inductor through the second detection resistor RS2.

[0066] The current ripple detection circuit 110 can generate a current ripple detection voltage VRS based on the voltages VCS1 and VCS2 applied across the detection capacitor CS. As one embodiment, the first amplifier AMP1 can receive and amplify the voltages VCS1 and VCS2 applied across the detection capacitor CS through its input terminals, thereby outputting the current ripple detection voltage VRS.

[0067] As previously mentioned, converter 10 can be a converter capable of operating in at least one of buck mode, boost mode, and buck-boost mode. In this case, the first detection switch SS1 and the second detection switch SS2 can be selectively turned on or off according to the operating mode.

[0068] As an example, in buck mode, the first detection switch SS1 can be turned off, and the second detection switch SS2 can be turned on. In buck mode, the first switch Q1 and the second switch Q2 of the converter 10 can be alternately turned on / off, the third switch Q3 can remain on, and the fourth switch Q4 can remain off (see reference). Figure 6 and Figure 7 That is, the voltage VL1 at one end of inductor L can alternate between the input voltage VIN and the reference potential GND, while the voltage VL2 at the other end of inductor L can remain at the output voltage VOUT. Therefore, in order to filter and extract the voltage VL1 at one end of inductor L, the first detection switch SS1 can be turned off and the second detection switch SS2 can be turned on.

[0069] As an example, in boost mode, the first detection switch SS1 can be turned on, and the second detection switch SS2 can be turned off. In boost mode, the first switch Q1 of the converter 10 can remain on, the second switch Q2 can remain off, and the third switch Q3 and the fourth switch Q4 can alternately turn on / off (see reference). Figure 9 and Figure 10That is, the voltage VL1 at one end of inductor L can be maintained at the input voltage VIN, while the voltage VL2 at the other end of inductor L can alternate between the output voltage VOUT and the reference potential GND. Therefore, in order to filter and extract the voltage VL2 at the other end of inductor L, the first detection switch SS1 can be turned on, and the second detection switch SS2 can be turned off.

[0070] As an example, in buck-boost mode, both the first detection switch SS1 and the second detection switch SS2 can be turned off. In buck-boost mode, the first switch Q1 and the second switch Q2 of the converter 10 can alternately turn on / off, and the third switch Q3 and the fourth switch Q4 can also alternately turn on / off (see reference). Figures 12 to 14 In this scenario, the voltage VL1 at one end of inductor L can alternate between the input voltage VIN and the reference potential GND, while the voltage VL2 at the other end of inductor L can alternate between the output voltage VOUT and the reference potential GND. Therefore, in order to filter and extract both the voltage VL1 at one end of inductor L and the voltage VL2 at the other end, both the first detection switch SS1 and the second detection switch SS2 can be turned off.

[0071] As one embodiment, the current ripple detection circuit 110 can be implemented within the semiconductor chip that implements the controller 100. That is, the first detection resistor RS1, the second detection resistor RS2, the first detection switch SS1, the second detection switch SS2, the detection capacitor CS, and the first amplifier AMP1 can all be implemented within the semiconductor chip that implements the controller 100. For DC current detection resistors that detect the DC component of the current, there are heat generation and size issues due to the current flowing through the detection resistor, making it difficult to implement within the chip. However, in this embodiment, the current ripple detection circuit 110 does not directly flow through the current, thus reducing heat generation and minimizing component size, allowing it to be implemented within the chip. When the current ripple detection circuit 110 is implemented within the chip, the size of the device can be reduced and the manufacturing cost can be lowered. However, in this case, the DC component of the current cannot be detected, therefore a controller that can control the converter 10 even without this information is needed, which will be described in detail below.

[0072] Figure 4 This is an embodiment of a conduction interval control circuit.

[0073] As previously mentioned, the converter 10 can operate in at least one of the following modes: buck mode, boost mode, or buck-boost mode. Figure 4The illustrated conduction interval control circuit 120 can control the end time of the conduction interval regardless of whether the converter 10 is operating in buck mode, boost mode or buck-boost mode, so as to reduce the fluctuation of the switching cycle (i.e., switching frequency) of the converter 10.

[0074] As one embodiment, the conduction interval control circuit 120 can generate a duty cycle end signal RESET based on both the input voltage VIN and the output voltage VOUT. It operates in a manner that increases the conduction interval when the duty cycle of the converter 10, determined by the input voltage VIN and the output voltage VOUT, increases, and operates in a manner that decreases the conduction interval when the duty cycle of the converter 10, determined by the input voltage VIN and the output voltage VOUT, decreases. This reduces the fluctuation of the switching cycle within the range of the input voltage VIN and the output voltage VOUT in which the converter 10 operates.

[0075] As one embodiment, the conduction interval control circuit 120 may optionally include at least a portion of the following: a first current source I1 supplying a current of magnitude (k1·VIN) substantially proportional to the input voltage VIN; a second current source I2 supplying a current of magnitude (k2·VOUT) substantially proportional to the output voltage VOUT; a third current source I3 supplying a current of magnitude (k3·VOUT) substantially proportional to the output voltage VOUT; and a fourth current source I4 supplying a current of magnitude (k4·VIN) substantially proportional to the input voltage VIN. The proportionality constants k1, k2, k3, and k4 used by the four current sources I1, I2, I3, and I4 may all be substantially the same.

[0076] Each of the first to fourth current sources I1, I2, I3, I4 can be connected in series with a first to fourth current source switch SI1, SI2, SI3, SI4 to control whether the first to fourth current sources I1, I2, I3, I4 are operational. For example, the first current source I1 can be connected in series with a first current source switch SI1. If the first current source switch SI1 is on, the current from the first current source I1 can be supplied to the current mirror 121; if the first current source switch SI1 is off, the current from the first current source I1 may not be supplied to the current mirror 121. Alternatively, as an embodiment, the current source switches SI1, SI2, SI3, SI4 may not be used, and instead, the current sources I1, I2, I3, I4 themselves can be controlled to supply current or not supply current as needed.

[0077] The current supplied by the first current source I1 or the second current source I2 can be replicated in the current mirror 121 and supplied to the ramp capacitor CR. Depending on the circumstances, the current source I1 or I2 can be supplied directly to the ramp capacitor CR without using the current mirror 121.

[0078] If a constant current flows into the ramp capacitor CR from either the first current source I1 or the second current source I2, the ramp voltage RAMP can increase substantially linearly. The ramp switch SR can be turned on at a predetermined time to discharge the ramp capacitor CR and initialize the ramp voltage RAMP. The ramp voltage RAMP can be supplied to the non-inverting input terminal (+ input terminal) of the first comparator CMP1.

[0079] As one embodiment, the ramp capacitor CR can be implemented as a variable capacitor capable of changing its capacitance as needed. The slope of the ramp voltage RAMP can be determined by the magnitude of the current output from the first current source I1 or the second current source I2 and the capacitance of the ramp capacitor CR. When the ramp capacitor CR is set as a variable capacitor, it has the advantage of being able to adjust the slope of the ramp voltage RAMP more precisely.

[0080] The current source used to determine the slope of the ramp voltage RAMP can be selected via a first current source switch SI1 and a second current source switch SI2. The slope of the ramp voltage RAMP can be determined by the output current selected from either the first current source I1 or the second current source I2 according to the operating mode. Since the current of the first current source I1 is substantially proportional to the input voltage VIN, and the current of the second current source I2 is substantially proportional to the output voltage VOUT, the first current source switch SI1 and the second current source switch SI2 can ultimately be used to determine the slope of the ramp voltage RAMP by the voltage selected from either the input voltage VIN or the output voltage VOUT according to the operating mode.

[0081] The current supplied by the third current source I3 or the fourth current source I4 can flow through the resistor RI and generate a voltage VRI. The mode correction voltage VMC, which is preset according to the operating mode, can be subtracted from the voltage VRI generated by the resistor RI to generate the ramp reference voltage VRREF. The ramp reference voltage VRREF can be provided to the inverting input terminal (-input terminal) of the first comparator CMP1.

[0082] The current source used to determine the magnitude of the ramp reference voltage VRREF can be selected based on the operating mode using the third current source switch SI3 and the fourth current source switch SI4. Since the current of the third current source I3 is substantially proportional to the output voltage VOUT, and the current of the fourth current source I4 is substantially proportional to the input voltage VIN, the third current source switch SI3 and the fourth current source switch SI4 can ultimately be used to determine the magnitude of the ramp reference voltage VRREF by selecting the voltage from the input voltage VIN or the output voltage VOUT according to the operating mode.

[0083] The conduction interval control circuit 120 can generate a mode correction voltage VMC preset according to the operating mode. As one embodiment, in buck mode, the mode correction voltage VMC can be 0. As one embodiment, in boost mode, the mode correction voltage VMC can be the input voltage VIN. As one embodiment, in buck-boost mode, the mode correction voltage VMC can be the value obtained by multiplying the input voltage VIN by a predetermined constant. Setting the predetermined constant to 0.8 in buck-boost mode makes the operating frequency range of the buck-boost mode similar to that of the buck mode or boost mode, which is therefore preferred.

[0084] The first comparator CMP1 compares the ramp voltage RAMP input to the non-inverting input terminal (+ input terminal) with the ramp reference voltage VRREF input to the inverting input terminal (- input terminal) to generate a duty cycle end signal RESET. As an embodiment, when the ramp voltage RAMP becomes greater than or equal to the ramp reference voltage VRREF, a duty cycle end signal RESET indicating the end of the conduction interval can be generated. The duty cycle end signal RESET can be provided to the duty cycle control circuit 130 and used to generate the duty cycle control signal CONT.

[0085] As one embodiment, the duty cycle end signal RESET can be in a state that is normally kept at a "low level", changes to a "high level" at the time indicating the end of the duty cycle, and returns to a "low level" state after a certain period of time. In this case, it can also be regarded as the duty cycle end signal RESET being continuously generated. However, in this specification, the conversion to a "high level" signal indicating the end of the duty cycle will also be described as "generating the duty cycle end signal RESET".

[0086] Depending on the operating environment of the converter 10, some of the first to fourth current sources I1, I2, I3, and I4 may be unused. In this case, the current source switches corresponding to the unused current sources may also be unused. As an example, when the converter 10 does not use the reverse power transfer from the output voltage VOUT to the input voltage VIN, the fourth current source I4 and the fourth current source switch SI4 may be unused.

[0087] Figure 5 This is an embodiment of a duty cycle control circuit.

[0088] Reference Figure 5 The duty cycle control circuit 130 may optionally include a second amplifier AMP2, a third amplifier AMP3, a second comparator CMP2, and a latch 132.

[0089] The second amplifier AMP2 can receive the output voltage detection signal VOS through its non-inverting input terminal and buffer it to generate a signal VOS' with a magnitude substantially the same as the output voltage detection signal VOS. The output voltage detection signal VOS can be generated by dividing the output voltage VOUT by multiple resistors RO1 and RO2.

[0090] The inductor current detection signal RPP can be obtained by adding the output voltage detection signal VOS' to the current ripple detection voltage VRS. That is, the inductor current detection signal RPP is obtained by superimposing the voltage offset corresponding to the output voltage VOUT onto the current ripple detection voltage VRS corresponding to the inductor current ripple. Since the current ripple detection circuit 110 detects the fluctuation component (ripple) while excluding the DC component of the inductor current, it can be understood as being used to compensate for the DC component of the inductor current.

[0091] The third amplifier AMP3 can receive the output voltage detection signal VOS through the inverting input terminal and the output voltage reference signal VOREF through the non-inverting input terminal, and generate the output voltage control signal VC. Although not shown in the accompanying drawings, the third amplifier AMP3 may be an error amplifier that also includes a compensation circuit composed of resistors and / or capacitors. As one embodiment, the compensation circuit may be a proportional-integral (PI) compensation circuit or a proportional-integral-derivative (PID) compensation circuit, but is not limited thereto. For example, the third amplifier AMP3 can perform negative feedback for controlling the output voltage VOUT in the following manner: when the output voltage detection signal VOS is lower than the output voltage reference signal VOREF, the output voltage control signal VC is gradually increased; when the output voltage detection signal VOS is higher than the output voltage reference signal VOREF, the output voltage control signal VC is gradually decreased. That is, the third amplifier AMP3 can amplify the difference between the output voltage detection signal VOS and the output voltage reference signal VOREF to generate the output voltage control signal VC, so that the output voltage detection signal VOS follows the output voltage reference signal VOREF. The term "gradually" means that the output voltage control signal VC increases or decreases more slowly than the switching frequency. That is, the output voltage control signal VC can increase or decrease slowly over multiple switching cycles. In this case, it can be assumed that the output voltage control signal VC remains almost unchanged within a single switching cycle to analyze the operation of the converter 10 and the controller 100.

[0092] The second comparator CMP2 can receive the inductor current detection signal RPP through its inverting input terminal and the output voltage control signal VC through its non-inverting input terminal. Based on the inductor current detection signal RPP and the output voltage control signal VC, it generates a duty cycle start signal SET. As an example, when the inductor current detection signal RPP becomes less than or equal to the output voltage control signal VC, a duty cycle start signal SET indicating the start of the first state (the state where the inductor current increases) can be generated.

[0093] The latch 132 can receive a duty cycle start signal SET through the set terminal S, a duty cycle end signal RESET through the reset terminal R, and output a duty cycle control signal CONT through the output terminal Q. As an example, if the latch 132 receives a "high level" signal from the duty cycle start signal SET through the set terminal S, it outputs a "high level" duty cycle control signal CONT through the output terminal Q, thus indicating the start of the duty cycle; if it receives a "high level" signal from the duty cycle end signal RESET through the reset terminal R, it outputs a "low level" duty cycle control signal CONT through the output terminal Q, thus indicating the end of the duty cycle.

[0094] The duty cycle control signal CONT generated by latch 132 can be provided to drive circuit 140 to drive the switches included in converter 10.

[0095] Figures 6 to 8 This illustrates the buck mode operation of a multi-mode buck-boost converter. Specifically, Figure 6 This example illustrates the operation in the first state of buck mode (the state where the inductor current increases, also known as the "conduction zone"). Figure 7 This example illustrates the operation of the second state of buck mode (the state where the inductor current decreases, also known as the "turn-off interval"). Figure 8 The main waveforms in buck mode are shown.

[0096] Reference Figure 6 In the first state of buck mode, the first switch Q1 and the third switch Q3 can be turned on, while the second switch Q2 and the fourth switch Q4 can be turned off. In this case, an input voltage VIN can be applied to one end VL1 of inductor L, and an output voltage VOUT can be applied to the other end VL2 of inductor L. Since buck mode operates when the input voltage VIN is higher than the output voltage VOUT, the current in inductor L increases (in this specification, the current in inductor L is...). Figure 6 The current flows from left to right as the reference direction. Therefore, if the voltage VL1 at one end of inductor L is higher than the voltage VL2 at the other end, the current flowing from left to right increases, which can be considered as an increase in the current of inductor L.

[0097] Reference Figure 7 In the second state of buck mode, the second switch Q2 and the third switch Q3 can be turned on, while the first switch Q1 and the fourth switch Q4 can be turned off. In this case, a reference potential GND can be applied to one end VL1 of the inductor L, and an output voltage VOUT can be applied to the other end VL2 of the inductor L. In this case, the current of the inductor L decreases.

[0098] In buck mode Figure 6 The first state and Figure 7 The second state can be executed alternately. The time required for each of the first and second states to be executed once is the switching cycle TS. When the first and second states are executed once within one switching cycle TS... Figure 6 The duration of the first state is called the conduction interval TON. Figure 7 When the duration of the second state is called the off interval TOFF, the switching period TS and duty cycle D can be represented as shown in mathematical formulas 1 and 2.

[0099] [Mathematical Expression 1]

[0100] [Mathematical Expression 2]

[0101] In steady state, the increase and decrease of the current in inductor L are the same within one cycle (if the increase and decrease are different within one cycle, it is transient). Using this principle, the relationship between the input voltage VIN and the output voltage VOUT in steady state can be expressed mathematically using the duty cycle D. If we express the same increase in current of inductor L during the first state and the same decrease in current of inductor L during the second state mathematically, we can derive equation 3.

[0102] [Mathematical Expression 3]

[0103] By rearranging Equation 3, as shown in Equation 4, we can see that the duty cycle D is determined by the input voltage VIN and the output voltage VOUT.

[0104] [Mathematical Expression 4]

[0105] By reorganizing mathematical formula 4 from the perspective of the switching period TS, mathematical formula 5 can be derived.

[0106] [Mathematical Expression 5]

[0107] Referring to Equation 5, when the conduction interval TON remains constant, if the input voltage VIN or the output voltage VOUT changes, the switching period TS will also change accordingly. For example, with the conduction interval TON and the output voltage VOUT unchanged, if the input voltage VIN doubles, the switching period TS will also double. A large change in the switching period TS means a large fluctuation in the switching frequency, which is therefore not preferred.

[0108] Figure 4 The illustrated conduction interval control circuit 120 causes the conduction interval TON to adaptively fluctuate according to the input voltage VIN and the output voltage VOUT, thereby reducing the fluctuation of the switching period TS even if the input voltage VIN and the output voltage VOUT fluctuate. This part will be described in detail below.

[0109] Referring to mathematical formula 5, in buck mode, if the conduction interval TON decreases when the input voltage VIN increases and increases when the output voltage VOUT increases, then even if the input voltage VIN and the output voltage VOUT fluctuate, the fluctuation of the switching period TS can be reduced. The conduction interval control circuit 120 utilizes this principle.

[0110] In buck mode, the first current source switch SI1 and the third current source switch SI3 can be turned on, while the second current source switch SI2 and the fourth current source switch SI4 can be turned off. As an embodiment, when using only buck mode, the second current source I2, the fourth current source I4, the second current source switch SI2, and the fourth current source switch SI4 may not be included in the conduction interval control circuit 120. In buck mode, the mode correction voltage VMC can be set to "0". In this case, the slope of the ramp voltage RAMP can be determined based on the input voltage VIN, and the ramp reference voltage VRREF can be determined based on the output voltage VOUT. As an embodiment, the slope of the ramp voltage RAMP can be substantially proportional to the input voltage VIN as shown in Equation 6, and the ramp reference voltage VRREF can be substantially proportional to the output voltage VOUT as shown in Equation 7.

[0111] [Mathematical Expression 6]

[0112] [Mathematical Expression 7]

[0113] Figure 8 The example illustrates the operating waveform when the input voltage VIN changes from a first voltage VIN1 to a second voltage VIN2 in buck mode. It is assumed that the output voltage VOUT remains constant.

[0114] The inductor current sensing signal RPP has a similar shape to the inductor current, and therefore can increase during the on-interval TON and decrease during the off-interval TOFF. If the inductor current sensing signal RPP decreases to less than or equal to the output voltage control signal VC, the duty cycle control signal CONT can transition to a "high" state indicating the start of the duty cycle (i.e., the start of the on-interval) (e.g., time t1). If the duty cycle control signal CONT becomes "high," the on-interval TON begins, and the ramp voltage RAMP can increase substantially linearly. If the ramp voltage RAMP becomes greater than or equal to the ramp reference voltage VRREF, the duty cycle control signal CONT can transition to a "low" state indicating the end of the duty cycle (i.e., the end of the on-interval) (e.g., time t2). If the duty cycle control signal CONT transitions to "low," the ramp switch SR turns on, discharging the ramp capacitor CR, and the ramp voltage RAMP can return to its initial value (e.g., the reference potential). If the duty cycle control signal CONT goes low, the inductor current detection signal RPP can decrease because the inductor current decreases. If the inductor current detection signal RPP decreases to be less than or equal to the output voltage control signal VC again, the duty cycle control signal CONT goes high, indicating the start of the duty cycle (i.e., the start of the conduction interval), and the switching action can be repeated.

[0115] As mentioned earlier, the output voltage control signal VC can be designed to change at a slower rate than the switching frequency. That is, output voltage VOUT control using the output voltage control signal VC can be understood as a relatively slow voltage control loop. Conversely, current control using the inductor current detection signal RPP adjusts the current magnitude within each switching cycle, and therefore can be understood as a relatively faster current control loop than the voltage control loop. In other words, the controller 100 of this embodiment can simultaneously implement both a slower-responding voltage control loop and a faster-responding current control loop, thereby improving the controller's control performance.

[0116] The conduction interval TON is, for example, the time interval between the end time t2 and the start time t1 of the conduction interval TON. That is, the conduction interval TON can be understood as the time required for the ramp voltage RAMP to increase from its initial value to the ramp reference voltage VRREF. Therefore, the conduction interval TON can be determined based on the slope of the ramp voltage RAMP and the ramp reference voltage VRREF. As an embodiment, the conduction interval TON can be inversely proportional to the slope of the ramp voltage RAMP and directly proportional to the ramp reference voltage VRREF, as shown in Equation 8.

[0117] [Mathematical Expression 8]

[0118] If we use mathematical formulas 6 and 7 to replace the slope of the ramp voltage RAMP and the ramp reference voltage VRREF in mathematical formula 8 with the input voltage VIN and the output voltage VOUT, then the conduction interval TON in buck mode can be represented as shown in mathematical formula 9.

[0119] [Mathematical Expression 9]

[0120] Therefore, the conduction interval control circuit 120 can operate in buck mode such that the conduction interval TON is inversely proportional to the input voltage VIN and directly proportional to the output voltage VOUT. That is, the conduction interval control circuit 120 can operate in a way that makes the conduction interval TON adaptively change according to the input voltage VIN and the output voltage VOUT.

[0121] As described above with reference to mathematical formula 5, in buck mode, when the conduction interval TON is fixed, the switching period TS has a relationship that is directly proportional to the input voltage VIN and inversely proportional to the output voltage VOUT. The conduction interval control circuit 120, as shown in mathematical formula 9, operates in a way that makes the conduction interval TON inversely proportional to the input voltage VIN and directly proportional to the output voltage VOUT, thereby canceling the influence of the input voltage VIN and the output voltage VOUT on the switching period TS and reducing the fluctuation of the switching period TS.

[0122] The following is for reference Figure 8 Exemplarily examine this function of the conduction interval control circuit 120. Figure 8 An example is given where the input voltage VIN increases from a relatively low first voltage VIN1 to a relatively high second voltage VIN2. For instance, assuming the second voltage VIN2 is twice the first voltage VIN1, according to Equation 5, since the input voltage VIN doubles, the switching period TS can also double (when the conduction interval TON is constant). However, as shown in Equations 6 and 9, the conduction interval control circuit 120, in buck mode, doubles the slope of the ramp voltage RAMP if the input voltage VIN doubles, reducing the conduction interval TON to approximately half, thereby reducing the fluctuation of the switching period TS.

[0123] In summary, when converter 10 operates in buck mode, the conduction interval control circuit 120 generates a ramp reference voltage VRREF with a magnitude corresponding to the output voltage VOUT, and a ramp voltage RAMP with a slope corresponding to the input voltage VIN. When the ramp voltage RAMP becomes greater than or equal to the ramp reference voltage VRREF, a duty cycle end signal RESET indicating the end of the conduction interval is generated. As an embodiment, the ramp reference voltage VRREF can be substantially proportional to the output voltage VOUT (Equation 7), and the slope of the ramp voltage RAMP can be substantially proportional to the input voltage VIN (Equation 6). In this case, the conduction interval TON is substantially inversely proportional to the input voltage VIN and substantially proportional to the output voltage VOUT (Equation 9), thereby offsetting the switching period TS fluctuation caused by fluctuations in the input voltage VIN and the output voltage VOUT, and reducing the fluctuation of the switching frequency.

[0124] Figures 9 to 11 This illustrates the boost mode operation of a multi-mode buck-boost converter. Specifically, Figure 9 This example illustrates the operation in the first state of boost mode (the state where the inductor current increases). Figure 10 This example illustrates the operation in the second state of boost mode (the state where the inductor current decreases). Figure 11 The main waveforms in boost mode are shown in the example.

[0125] Reference Figure 9 In the first state (conduction interval) of boost mode, the first switch Q1 and the fourth switch Q4 can be turned on, while the second switch Q2 and the third switch Q3 can be turned off. In this case, an input voltage VIN can be applied to one end VL1 of inductor L, and a reference potential GND can be applied to the other end VL2 of inductor L. Since the voltage VL1 at one end of inductor L is higher than the voltage VL2 at the other end of inductor L in the first state, the current in inductor L increases.

[0126] Reference Figure 10 In the second state (off interval) of boost mode, the first switch Q1 and the third switch Q3 can be turned on, while the second switch Q2 and the fourth switch Q4 can be turned off. In this case, an input voltage VIN can be applied to one end VL1 of inductor L, and an output voltage VOUT can be applied to the other end VL2 of inductor L. Since boost mode operates when the input voltage VIN is lower than the output voltage VOUT, the current in inductor L decreases.

[0127] In boost mode, execution can be alternated. Figure 9 The first state and Figure 10 The second state. When... Figure 9The duration of the first state is called the conduction interval TON. Figure 10 When the duration of the second state is called the off interval TOFF, the switching period TS is the sum of the on interval TON and the off interval TOFF. Similar to the buck mode, utilizing the principle that the increase and decrease of the current in the inductor L are the same in one cycle under steady state, the duty cycle D can be determined by the input voltage VIN and the output voltage VOUT as shown in Equation 10 under steady state.

[0128] [Mathematical Expression 10]

[0129] By reorganizing mathematical formula 10 from the perspective of the switching period TS, mathematical formula 11 can be derived.

[0130] [Mathematical Expression 11]

[0131] Referring to mathematical formula 11, when the conduction interval TON remains constant, if the input voltage VIN or the output voltage VOUT changes, the switching period TS will also change accordingly. As mentioned earlier, a larger change in the switching period TS means a wider operating range of the switching frequency, which is not preferred.

[0132] Figure 4 The illustrated conduction interval control circuit 120 also causes the conduction interval TON to fluctuate adaptively according to the input voltage VIN and the output voltage VOUT in boost mode, thereby reducing the fluctuation of the switching period TS even if the input voltage VIN and the output voltage VOUT fluctuate.

[0133] In boost mode, the second current source switch SI2 and the third current source switch SI3 can be turned on, while the first current source switch SI1 and the fourth current source switch SI4 can be turned off. As an embodiment, when using only boost mode, the first current source I1, the fourth current source I4, the first current source switch SI1, and the fourth current source switch SI4 may not be included in the conduction interval control circuit 120. In boost mode, the mode correction voltage VMC can be set to the input voltage VIN. In this case, the slope of the ramp voltage RAMP can be determined based on the output voltage VOUT, and the ramp reference voltage VRREF can be determined based on the value obtained by subtracting the input voltage VIN from the output voltage VOUT. As an embodiment, the slope of the ramp voltage RAMP can be substantially proportional to the output voltage VOUT as shown in Equation 12, and the ramp reference voltage VRREF can be substantially proportional to the value obtained by subtracting the input voltage VIN from the output voltage VOUT as shown in Equation 13.

[0134] [Mathematical Expression 12]

[0135] [Mathematical Expression 13]

[0136] Figure 11 The following example illustrates the operating waveform when the input voltage VIN changes from the first voltage VIN1 to the second voltage VIN2 in boost mode. Assume the output voltage VOUT remains constant. The principle for generating the duty cycle control signal CONT can be applied using the methods explained earlier in the buck mode.

[0137] The conduction interval TON in boost mode can also be determined based on the slope of the ramp voltage RAMP and the ramp reference voltage VRREF, as shown in Equation 8. Through the operation of the conduction interval control circuit 120, the slope of the ramp voltage RAMP and the ramp reference voltage VRREF in boost mode can be expressed as shown in Equations 12 and 13, respectively. If, using Equations 12 and 13, the slope of the ramp voltage RAMP and the ramp reference voltage VRREF in Equation 8 are replaced with the input voltage VIN and the output voltage VOUT, then the conduction interval TON in boost mode can be expressed as shown in Equation 14.

[0138] [Mathematical Expression 14]

[0139] Therefore, in boost mode, the conduction interval control circuit 120 can operate such that the conduction interval TON is proportional to the value obtained by subtracting the input voltage VIN from the output voltage VOUT and inversely proportional to the output voltage VOUT. That is, the conduction interval control circuit 120 can operate such that the conduction interval TON changes adaptively according to the input voltage VIN and the output voltage VOUT.

[0140] As described above with reference to mathematical formula 11, in boost mode, when the conduction interval TON is fixed, the switching period TS has a relationship that is proportional to the output voltage VOUT and inversely proportional to the value obtained by subtracting the input voltage VIN from the output voltage VOUT. The conduction interval control circuit 120 operates in boost mode as shown in mathematical formula 14, so that the conduction interval TON is inversely proportional to the output voltage VOUT and proportional to the value obtained by subtracting the input voltage VIN from the output voltage VOUT. This can counteract the influence of the input voltage VIN and the output voltage VOUT on the switching period TS and reduce the fluctuation of the switching period TS.

[0141] The following is for reference Figure 11 Exemplarily examine this function of the conduction interval control circuit 120. Figure 11An example is given where the input voltage VIN increases from a relatively low first voltage VIN1 to a relatively high second voltage VIN2. In this case, according to equation 11, the denominator (the value obtained by subtracting the input voltage VIN from the output voltage VOUT) decreases, thus increasing the switching period TS (when the on-time TON is constant). However, in boost mode, if the input voltage VIN increases, the on-time control circuit 120 decreases the ramp reference voltage VRREF in a manner substantially proportional to the decrease in the value obtained by subtracting the input voltage VIN from the output voltage VOUT, thereby reducing the on-time TON and thus reducing the fluctuation of the switching period TS.

[0142] In summary, when the converter 10 operates in boost mode, the conduction interval control circuit 120 can generate a ramp reference voltage VRREF with a magnitude corresponding to the value obtained by subtracting the input voltage VIN from the output voltage VOUT, generate a ramp voltage RAMP with a slope corresponding to the output voltage VOUT, and generate a duty cycle end signal RESET indicating the end of the conduction interval when the ramp voltage RAMP becomes greater than or equal to the ramp reference voltage VRREF. As an embodiment, the ramp reference voltage VRREF can be substantially proportional to the value obtained by subtracting the input voltage VIN from the output voltage VOUT (refer to mathematical formula 13), and the slope of the ramp voltage RAMP can be substantially proportional to the output voltage VOUT (refer to mathematical formula 12). In this case, the conduction interval TON is substantially proportional to the value obtained by subtracting the input voltage VIN from the output voltage VOUT and substantially inversely proportional to the output voltage VOUT (refer to mathematical formula 14), thereby offsetting the switching period TS fluctuation factor caused by fluctuations in the input voltage VIN and the output voltage VOUT, and reducing the fluctuation of the switching frequency.

[0143] Figures 12 to 15 This illustrates the buck-boost mode operation of a multi-mode buck-boost converter. Specifically, Figure 12 This example illustrates the operation of the first state D1 (the state where the inductor current increases) in buck-boost mode. Figure 13 This example illustrates the operation of the second state D2 in buck-boost mode (a state where the inductor current can either increase or decrease depending on the input voltage VIN and the output voltage VOUT). Figure 14 This example illustrates the operation of the third state D3 (the state where the inductor current decreases) in the buck-boost mode. Figure 15 The main waveforms in buck-boost mode are shown in the example.

[0144] Reference Figure 12In the first state D1 of the buck-boost mode, the first switch Q1 and the fourth switch Q4 can be turned on, while the second switch Q2 and the third switch Q3 can be turned off. In this case, an input voltage VIN can be applied to one end VL1 of the inductor L, and a reference potential GND can be applied to the other end VL2 of the inductor L. In the first state, the current in the inductor L increases.

[0145] Reference Figure 13 In the second state D2 of the buck-boost mode, the first switch Q1 and the third switch Q3 can be turned on, while the second switch Q2 and the fourth switch Q4 can be turned off. In this case, an input voltage VIN can be applied to one end VL1 of the inductor L, and an output voltage VOUT can be applied to the other end VL2 of the inductor L. Since the buck-boost mode can operate both when the input voltage VIN is lower than the output voltage VOUT and higher than the output voltage VOUT, the current in the inductor L in the second state can increase or decrease according to the relationship between the input voltage VIN and the output voltage VOUT.

[0146] Reference Figure 14 In the third state (D3) of the buck-boost mode, the second switch Q2 and the third switch Q3 can be turned on, while the first switch Q1 and the fourth switch Q4 can be turned off. In this state, a reference potential GND can be applied to one end VL1 of the inductor L, and an output voltage VOUT can be applied to the other end VL2 of the inductor L. In the third state of the buck-boost mode, the current in the inductor L decreases.

[0147] As an example, in buck-boost mode... Figure 12 The first state Figure 13 The second state and Figure 14 The third state can be executed sequentially. Similar to buck or boost mode, it utilizes the principle that the increase and decrease of the current in inductor L are the same in one cycle under steady state. Under steady state, the relationship between the input voltage VIN and the output voltage VOUT can be represented by mathematical formula 15, expressed by the duty cycles D1, D2, and D3 from the first to the third state.

[0148] [Mathematical Expression 15]

[0149] Where D1+D2+D3=1, and k=D1+D2. That is, k is the sum of the duty cycles (time ratios) occupied by the first and second states within the switching cycle TS.

[0150] Referring to Equation 15, it can be seen that, while keeping the sum of the duty cycles k of the first and second states constant, the voltage gain (=VOUT / VIN) can be adjusted by the duty cycle D1 of the first state. The sum of the duty cycles k of the first and second states can be predetermined during the design phase. k can be set to various values, but when k=0.8, the efficiency is excellent and the transient operation during mode switching is stable, making it the most preferred option.

[0151] By reorganizing mathematical formula 15 from the perspective of the duty cycle D1 in the first state, mathematical formula 16 can be derived.

[0152] [Mathematical Expression 16]

[0153] Where TON is the duration of the first state, and TON = D1·TS.

[0154] By rearranging mathematical formula 16 from the perspective of the switching period TS, mathematical formula 17 can be derived.

[0155] [Mathematical Expression 17]

[0156] Referring to mathematical formula 17, when the conduction interval TON remains constant, if the input voltage VIN or the output voltage VOUT changes, the switching period TS will also change accordingly. As mentioned earlier, the change in the switching period TS means that the operating range of the switching frequency becomes wider, which is not the preferred option.

[0157] Figure 4 The illustrated conduction interval control circuit 120 also causes the conduction interval TON to fluctuate adaptively according to the input voltage VIN and the output voltage VOUT in buck-boost mode, thereby reducing the fluctuation of the switching period TS even if the input voltage VIN and the output voltage VOUT fluctuate.

[0158] In buck-boost mode, the second current source switch SI2 and the third current source switch SI3 can be turned on, while the first current source switch SI1 and the fourth current source switch SI4 can be turned off. As an embodiment, when using only buck-boost mode, the first current source I1, the fourth current source I4, the first current source switch SI1, and the fourth current source switch SI4 may not be included in the conduction interval control circuit 120. In buck-boost mode, the mode correction voltage VMC can be set to k times the input voltage VIN. That is, it can be set as VMC = k·VIN. Here, as mentioned earlier, k can be the sum of the duty cycles (time ratios) of the first and second states within the switching cycle TS. In this case, the slope of the ramp voltage RAMP can be determined based on the output voltage VOUT, and the ramp reference voltage VRREF can be determined based on the value obtained by subtracting the product of the input voltage VIN and a predetermined constant k from the output voltage VOUT. As an example, the slope of the ramp voltage RAMP can be substantially proportional to the output voltage VOUT as shown in Equation 18, and the ramp reference voltage VRREF can be substantially proportional to the value obtained by subtracting the product of the input voltage VIN and a predetermined constant k from the output voltage VOUT as shown in Equation 19.

[0159] [Mathematical Expression 18]

[0160] [Mathematical Expression 19]

[0161] Figure 15 The following example illustrates the operating waveform when the input voltage VIN changes from the first voltage VIN1 to the second voltage VIN2 in buck-boost mode. Assume the output voltage VOUT remains constant. The principle for generating the duty cycle control signal CONT can be applied using the methods explained earlier in the buck mode.

[0162] The conduction interval TON in buck-boost mode can also be determined based on the slope of the ramp voltage RAMP and the ramp reference voltage VRREF, as shown in Equation 8. Through the operation of the conduction interval control circuit 120, the slope of the ramp voltage RAMP and the ramp reference voltage VRREF in buck-boost mode can be expressed as shown in Equations 18 and 19, respectively. If, using Equations 18 and 19, the slope of the ramp voltage RAMP and the ramp reference voltage VRREF in Equation 8 are replaced with the input voltage VIN and the output voltage VOUT, then the conduction interval TON in buck-boost mode can be expressed as shown in Equation 20.

[0163] [Mathematical Expression 20]

[0164] Therefore, in buck-boost mode, the conduction interval control circuit 120 can operate such that the conduction interval TON is proportional to the product of the input voltage VIN and a predetermined constant k, obtained by subtracting the product from the output voltage VOUT, and inversely proportional to the output voltage VOUT. That is, the conduction interval control circuit 120 can operate in a way that adaptively changes the conduction interval TON according to the input voltage VIN and the output voltage VOUT.

[0165] As described above with reference to mathematical formula 17, in buck-boost mode, when the conduction interval TON is fixed, the switching period TS has a relationship that is proportional to the output voltage VOUT and inversely proportional to the value obtained by subtracting the product of the input voltage VIN and a predetermined constant k from the output voltage VOUT. The conduction interval control circuit 120 operates in buck-boost mode as shown in mathematical formula 20, so that the conduction interval TON is inversely proportional to the output voltage VOUT and proportional to the value obtained by subtracting the product of the input voltage VIN and a predetermined constant k from the output voltage VOUT. This can offset the influence of the input voltage VIN and the output voltage VOUT on the switching period TS and reduce the fluctuation of the switching period TS.

[0166] The following is for reference Figure 15 Exemplarily examine this function of the conduction interval control circuit 120. Figure 15 An example is given where the input voltage VIN increases from a first voltage VIN1, which is lower than the output voltage VOUT, to a second voltage VIN2, which is higher than the output voltage VOUT. In this case, according to equation 17, the denominator (the value obtained by subtracting the product of the input voltage VIN and a predetermined constant k from the output voltage VOUT) decreases, thus increasing the switching period TS (when the conduction interval TON is constant). However, in buck-boost mode, if the input voltage VIN increases, the conduction interval control circuit 120 reduces the ramp reference voltage VRREF to reduce the conduction interval TON, thereby reducing the fluctuation of the switching period TS. As an example, the ramp reference voltage VRREF can decrease substantially proportionally to the value obtained by subtracting the product of the input voltage VIN and a predetermined constant k from the output voltage VOUT.

[0167] In summary, when converter 10 operates in buck-boost mode, the conduction interval control circuit 120 can generate a ramp reference voltage VRREF with a magnitude corresponding to the product of the input voltage VIN and a predetermined constant k, which is obtained by subtracting the product of the output voltage VOUT and the input voltage VIN, and generate a ramp voltage RAMP with a slope corresponding to the output voltage VOUT. When the ramp voltage RAMP becomes greater than or equal to the ramp reference voltage VRREF, a duty cycle end signal RESET, indicating the end of the conduction interval TON, is generated. As an embodiment, the ramp reference voltage VRREF can be substantially proportional to the product of the input voltage VIN and the predetermined constant k, which is obtained by subtracting the product of the output voltage VOUT and the input voltage VIN (refer to mathematical formula 19), and the slope of the ramp voltage RAMP can be substantially proportional to the output voltage VOUT (refer to mathematical formula 18). In this case, the conduction interval TON is substantially proportional to the value obtained by subtracting the product of the input voltage VIN and the predetermined constant k from the output voltage VOUT and substantially inversely proportional to the output voltage VOUT. This can offset the switching period TS fluctuation caused by the fluctuations of the input voltage VIN and the output voltage VOUT, and reduce the fluctuation of the switching frequency.

[0168] pass Figures 12 to 15 The described buck-boost mode operation is a preferred embodiment; the controller of this invention is not necessarily limited to applications using... Figures 12 to 15 The described buck-boost operating method (i.e., switching sequence) is readily understood by those skilled in the art. The technical concepts applied in the controller of this invention can also be applied to other buck-boost modes to reduce fluctuations in the switching cycle.

[0169] Therefore, when the converter 10 operates in at least one of the buck mode, boost mode, and buck-boost mode, the controller 100 of this embodiment can adaptively adjust the conduction range according to the fluctuations of the input voltage VIN and the output voltage VOUT, thereby controlling the converter 10 while reducing switching frequency fluctuations. That is, the controller 100 of this embodiment has the advantage that it can reduce switching frequency fluctuations while enabling the converter 10 to operate over a wide range of input voltage VIN and / or a wide range of output voltage VOUT. As a control method to reduce switching frequency fluctuations, a fixed frequency duty cycle control method can be used. However, the fixed frequency duty cycle control method has the disadvantage of requiring a clock to achieve a fixed frequency, and also has the disadvantage of difficulty in performing current control when only the current ripple component is detected without using an external DC current sensing resistor. According to this embodiment, current control can be performed without using a clock and an external DC current sensing resistor, and the switching frequency fluctuations can also be reduced.

[0170] Figure 16Another embodiment of the conduction interval control circuit is shown.

[0171] Figure 16 and Figure 4 The difference is that mode-corrected current IMC is used instead Figure 4 The mode correction voltage VMC is set, and the resistor RI is connected to the inverting input terminal of the first comparator CMP1. Figure 16 In the conduction interval control circuit 1620, the current obtained by subtracting the mode correction current IMC from the current of the third current source I3 or the fourth current source I4 flows through the resistor RI, and the voltage generated therefrom can be called the ramp reference voltage VRREF. That is, the ramp reference voltage VRREF can be represented as shown in mathematical formula 21.

[0172] [Mathematical Expression 21]

[0173] In equation 21, the product of the mode correction current IMC and the resistance RI can be equivalent to Figure 4 The mode correction voltage VMC in the embodiments. Therefore, the mode correction voltage VMC mentioned in this specification can be as follows: Figure 4 The diagram shows the implementation using a voltage signal, but it can also be implemented as shown below. Figure 16 The example shown uses a current signal, or it can obviously be implemented in other different forms while using the same technical concept.

[0174] In this specification, the "high level" and "low level" states of signals are specifically described for ease of explanation. However, this is merely an example, and it should be understood that various implementation methods are possible while utilizing the technical concept of this embodiment. Furthermore, in this specification, the specific ways in which various signals are connected to the inverting and non-inverting input terminals of comparators or amplifiers are described for ease of explanation. However, this is merely an example, and those skilled in the art will clearly understand that various modifications can be made to the connection relationships between various signals and input terminals while utilizing the technical concept of this embodiment.

[0175] According to embodiments, the controller 100 may also be implemented in hardware such as an ASIC (Application Specific Integrated Circuit) or a FPGA (Field Programmable Gate Array). According to embodiments, at least some of the elements constituting the controller 100 may be implemented in software and their functions may be executed by a computing device such as a CPU while stored in a computer-readable storage medium (memory, etc.). In this case, the software-implemented configuration may be implemented as mutually distinct independent modules within the software; however, depending on the circumstances, it may also be implemented in a state where the various functions are mixed within the software without distinction between them.

[0176] Unless otherwise stated, the terms "comprising," "constituting," or "having" used above mean that the corresponding constituent element may be included therein, and therefore should be interpreted as not excluding other constituent elements, but rather including other constituent elements. All terms, including technical or scientific terms, unless otherwise defined, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. Commonly used terms, such as those defined in dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted as having an idealized or overly formalized meaning unless explicitly defined in this invention.

[0177] The above description is merely an illustrative example of the technical concept of the present invention. Those skilled in the art can make various modifications and variations without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in this invention are not intended to limit the technical concept of the present invention, but rather to illustrate the invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of this invention should be interpreted according to the following claims, and all technical concepts within the equivalent scope thereof should be interpreted as included within the scope of the claims of this invention.

[0178] [Explanation of Labels in the Attached Image]

[0179] 110: Current ripple detection circuit; 120: Conduction interval control circuit

[0180] 130: Duty cycle control circuit; 140: Drive circuit

[0181] CONT: Duty cycle control signal; CR: Ramp capacitor

[0182] CS: Detector capacitor; D: Duty cycle

[0183] DQ: Internal switch drive signal of the converter

[0184] I1~I4: First current source to fourth current source RAMP: Ramp voltage

[0185] RESET: Duty cycle end signal; RPP: Inductor current detection signal

[0186] RS1, RS2: First detection resistor, second detection resistor

[0187] SET: Duty cycle start signal; SR: Ramp switch

[0188] SI1~SI4: First current source switch to fourth current source switch

[0189] SS1, SS2: First detection switch, second detection switch

[0190] TOFF: Time of the second state; TON: Time of the first state.

[0191] TS: Switching cycle; VC: Output voltage control signal

[0192] VIN: Input voltage

[0193] VL1, VL2: Voltages across the inductor

[0194] VMC: Mode Correction Voltage

[0195] VOREF: Output voltage reference signal

[0196] VOS, VOS': Output voltage detection signal; VOUT: Output voltage.

[0197] VRREF: Ramp reference voltage; VRS: Current ripple sensing voltage

Claims

1. A controller for controlling a converter, the converter comprising a switch and an inductor, and for converting power between an input voltage and an output voltage, characterized in that, The controller includes: A current ripple detection circuit that detects the current ripple of the inductor; The conduction interval control circuit generates a duty cycle end signal; and A duty cycle control circuit generates a duty cycle control signal for controlling the duty cycle of the converter based on the current ripple of the inductor and the duty cycle end signal.

2. The controller according to claim 1, characterized in that, The duty cycle control signal indicates the start and end times of the conduction interval, which is the interval during which the current in the inductor increases. The start time of the conduction interval is determined based on the current ripple of the inductor, and the end time of the conduction interval is determined based on the duty cycle end signal.

3. The controller according to claim 2, characterized in that, The duty cycle control circuit amplifies the difference between the output voltage detection signal and the output voltage reference signal to generate an output voltage control signal so that the output voltage detection signal follows the output voltage reference signal. The inductor current detection signal is generated based on the current ripple of the inductor. The inductor current detection signal is compared with the output voltage control signal to indicate the start of the conduction interval.

4. The controller according to claim 3, characterized in that, The inductor current detection signal is generated by superimposing an offset voltage corresponding to the output voltage onto a current ripple detection voltage corresponding to the magnitude of the inductor's current ripple.

5. The controller according to claim 1, characterized in that, The current ripple detection circuit includes: The first sensing resistor has one end connected to one end of the inductor; A detection capacitor, one end of which is connected to the other end of the first detection resistor; The second detection resistor has one end connected to the other end of the detection capacitor and the other end connected to the other end of the inductor. A first detection switch, which is connected in parallel with the first detection resistor; and The second detection switch is connected in parallel with the second detection resistor; The current ripple detection circuit generates a current ripple detection voltage based on the voltage applied across the detection capacitor.

6. The controller according to claim 5, characterized in that, The converter is a converter that operates in at least one of buck mode, boost mode, or buck-boost mode; In the buck mode, the first detection switch is off and the second detection switch is on; In the boost mode, the first detection switch is turned on and the second detection switch is turned off; In the buck-boost mode, both the first detection switch and the second detection switch are turned off.

7. The controller according to claim 5, characterized in that, The first detection resistor, the second detection resistor, the first detection switch, the second detection switch, and the detection capacitor are all implemented within the semiconductor chip that implements the controller.

8. The controller according to claim 2, characterized in that, The converter operates in at least one of the following modes: buck mode, boost mode, or buck-boost mode.

9. The controller according to claim 8, characterized in that, When the converter operates in the buck mode, the conduction interval control circuit operates to decrease the conduction interval when the input voltage increases, and to increase the conduction interval when the output voltage increases.

10. The controller according to claim 9, characterized in that, When the converter operates in the buck mode The conduction interval control circuit generates a ramp reference voltage with a magnitude corresponding to the output voltage. Generate a ramp voltage with a slope corresponding to the input voltage. The ramp voltage is compared with the ramp reference voltage to generate the duty cycle end signal indicating the end of the conduction interval.

11. The controller according to claim 10, characterized in that, The ramp reference voltage is proportional to the output voltage. The slope of the ramp voltage is proportional to the input voltage.

12. The controller according to claim 8, characterized in that, When the converter operates in the boost mode, the conduction interval control circuit operates to decrease the conduction interval when the input voltage increases, and to increase the conduction interval when the output voltage increases.

13. The controller according to claim 12, characterized in that, When the converter operates in the boost mode The conduction interval control circuit generates a ramp reference voltage with a magnitude corresponding to the value obtained by subtracting the input voltage from the output voltage. Generate a ramp voltage with a slope corresponding to the output voltage. The ramp voltage is compared with the ramp reference voltage to generate the duty cycle end signal indicating the end of the conduction interval.

14. The controller according to claim 13, characterized in that, The ramp reference voltage is proportional to the value obtained by subtracting the input voltage from the output voltage. The slope of the ramp voltage is proportional to the output voltage.

15. The controller according to claim 8, characterized in that, When the converter operates in the buck-boost mode, the conduction interval control circuit operates to decrease the conduction interval when the input voltage increases, and to increase the conduction interval when the output voltage increases.

16. The controller according to claim 15, characterized in that, When the converter operates in the buck-boost mode The conduction interval control circuit generates a ramp reference voltage with a magnitude corresponding to the value obtained by subtracting the product of the input voltage and a predetermined constant from the output voltage. Generate a ramp voltage with a slope corresponding to the output voltage. The ramp voltage is compared with the ramp reference voltage to generate the duty cycle end signal indicating the end of the conduction interval.

17. The controller according to claim 16, characterized in that, The ramp reference voltage is proportional to the value obtained by subtracting the product of the input voltage and a predetermined constant from the output voltage. The slope of the ramp voltage is proportional to the output voltage.

18. The controller according to claim 2, characterized in that, The conduction interval control circuit generates the duty cycle end signal based on both the input voltage and the output voltage. It operates in a manner that increases the conduction interval when the duty cycle of the converter, determined by the input voltage and the output voltage, increases, and operates in a manner that decreases the conduction interval when the duty cycle of the converter, determined by the input voltage and the output voltage, decreases, thereby reducing the fluctuation of the switching cycle of the converter.

19. The controller according to claim 18, characterized in that, The converter is a buck-boost converter that operates in at least two of the following operating modes: buck mode, boost mode, and buck-boost mode. The conduction interval control circuit includes: A first current source supplies a current whose magnitude is proportional to the input voltage; A second current source supplies a current whose magnitude is proportional to the output voltage; and A third current source supplies a current whose magnitude is proportional to the output voltage; The conduction interval control circuit generates a ramp voltage, the ramp voltage having a slope determined by the current provided from either the first current source or the second current source according to the operating mode. The ramp reference voltage is generated by subtracting the mode correction voltage preset according to the operating mode from the voltage generated based on the current provided by the third current source. The ramp voltage is compared with the ramp reference voltage to generate the duty cycle end signal indicating the end of the conduction interval.

20. The controller according to claim 19, characterized in that, In the buck mode, the mode correction voltage is 0. In the boost mode, the mode correction voltage is the input voltage. In the buck-boost mode, the mode correction voltage is the value obtained by multiplying the input voltage by a predetermined constant.

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