High-precision low-temperature drift ring voltage-controlled oscillator

Abstract

This invention discloses a high-precision, low-temperature-drift ring voltage-controlled oscillator, comprising a switched-capacitor equivalent resistance module, an operational module, a ring oscillator, and a self-biased inverter. This invention improves frequency accuracy structurally by designing a switched-capacitor frequency closed-loop negative feedback loop, converting the oscillator frequency into resistance, and then automatically adjusting the frequency through operational amplifier closed-loop control of the bias current. Furthermore, the self-biased inverter structure enhances the stability of the oscillator output. This invention achieves the functionality of a high-precision, low-temperature-drift ring voltage-controlled oscillator.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-precision, low-temperature drift ring voltage-controlled oscillator. Background Technology

[0002] In recent years, advancements in hybrid integrated circuit (HIC) technology and the maturity of microwave integrated circuit (MIC) technology have further improved the integration and performance of VCOs, driving the development and application of integrated circuit systems. Early VCO designs primarily employed traditional LC resonant circuit structures, utilizing the junction capacitance of varactor diodes to tune the frequency with varying reverse bias voltage. This type of structure offers advantages such as high quality factor and low phase noise, but its inductor components are large, difficult to integrate, and the tuning range is easily limited by the linearity of the varactor diode. Therefore, ring voltage-controlled oscillators have gradually become the mainstream choice for on-chip integrated VCOs.

[0003] Existing ring voltage-controlled oscillators typically consist of multiple cascaded inverters forming a delay unit, and the oscillation frequency is changed by controlling the supply current or load capacitance of the delay unit. Figure 1 For the traditional VCO structure, from Figure 1 As can be seen, the op-amp applies negative feedback to the gate of P1, utilizing the op-amp's virtual short characteristic to make... V SWING = V CTRL ,but V DS1 = V DD - V CTRL Even if the current flowing into the ring oscillator changes, the drain-source voltage remains relatively constant, thus stabilizing the oscillation frequency.

[0004] However, this traditional structure has inherent flaws. First, this structure only achieves open-loop voltage-frequency regulation, and the op-amp is only stable. V SWING The voltage did not form a closed-loop regulation of the oscillation frequency itself. When there are deviations in the process angle, large fluctuations in operating temperature, or changes in the supply voltage... V DD When ripple is generated, the delay time of the delay unit will drift significantly, leading to unstable output frequency. Secondly, the operational amplifier itself has offset voltage and limited gain, which also have an impact. Furthermore, the open-loop structure lacks a compensation mechanism for device nonlinearity, making it difficult to guarantee output frequency consistency.

[0005] Therefore, it is urgent to effectively suppress the impact of changes in process technology and temperature on frequency while maintaining the advantages of ring oscillator area and tuning range. Summary of the Invention

[0006] The purpose of this invention is to provide a high-precision, low-temperature drift ring voltage-controlled oscillator to solve the problems of traditional voltage-controlled oscillators being sensitive to process conditions, having large temperature drift, and having frequency stability dependent on device characteristics.

[0007] To solve the above-mentioned technical problems, the present invention provides a high-precision, low-temperature drift ring voltage-controlled oscillator, including a switched capacitor equivalent resistance module, an arithmetic module, a ring oscillator, and a self-biased inverter; The switched capacitor equivalent resistance module converts the oscillation clock frequency into an equivalent resistance, which is then converted into a feedback voltage VM to build frequency-voltage negative feedback and suppress frequency drift caused by PVT. The arithmetic module is used to form a negative feedback loop, forcing the feedback node voltage to follow the control voltage V. Ctrl This provides a controllable power supply bias for the ring oscillator, enabling frequency adjustment; The ring oscillator is the core oscillation unit, under a bias voltage V Bias A periodic oscillating clock signal is generated under control; The self-biased inverter establishes a DC operating point through a feedback resistor, amplifies and shapes the AC oscillation signal after DC blocking, and outputs a regular square wave signal.

[0008] In one embodiment, the switched capacitor equivalent resistance module includes a first PMOS transistor, a first NMOS transistor, and a first capacitor; the source of the first PMOS transistor is connected to the operational module, the gates of the first PMOS transistor and the first NMOS transistor are both connected to the output of a self-biased inverter, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the first terminal of the first capacitor; the source of the first NMOS transistor and the second terminal of the first capacitor are both grounded to GND.

[0009] In one embodiment, the operational amplifier module includes an operational amplifier, a first resistor, a second resistor, a third resistor, and a zeroth PMOS transistor; the non-inverting input of the operational amplifier is connected to the second terminal of the first resistor and the first terminal of the second resistor, the inverting input is connected to the source of the first PMOS transistor, and the output terminal is connected to the gate of the zeroth PMOS transistor; the first terminal of the first resistor is connected to a power supply V. DD The second terminal of the second resistor is grounded (GND); the source of the zeroth PMOS transistor is connected to the power supply. V DD The drain is connected to a ring oscillator; the first terminal of the third resistor is connected to the power supply V. DD The second terminal is connected to the source of the first PMOS transistor.

[0010] In one embodiment, the ring oscillator includes a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, and a fifth NMOS transistor; The source of the third PMOS transistor is connected to the drain of the zeroth PMOS transistor, and the gates of the third PMOS transistor and the third NMOS transistor are connected together to the input signal source V. in The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor; the source of the third NMOS transistor is connected to ground (GND). The source of the fourth PMOS transistor is connected to the drain of the zeroth PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth PMOS transistor, and the gate of the fifth NMOS transistor; the source of the fourth NMOS transistor is connected to ground (GND). The source of the fifth PMOS transistor is connected to the drain of the zeroth PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fifth NMOS transistor is connected to ground (GND).

[0011] In one embodiment, the self-biased inverter includes a second capacitor, a second PMOS transistor, a second NMOS transistor, and a fourth resistor; The first end of the second capacitor is connected to the output end of the ring oscillator, and the second end is connected to the gate of the second PMOS transistor, the gate of the second NMOS transistor, and the first end of the fourth resistor. The source and power supply of the second PMOS transistor V DD Connected, the drain is connected to the second terminal of the fourth resistor, the drain of the second NMOS transistor, and the output. V osc_out The second NMOS transistor is connected to ground (GND).

[0012] This invention provides a high-precision, low-temperature drift ring voltage-controlled oscillator. By introducing a switched capacitor frequency feedback loop, the oscillator frequency is self-adjusted, solving the problems of high sensitivity of oscillation frequency to process and large temperature drift from an architectural perspective. At the same time, the circuit area is small and easy to integrate. Attached Figure Description

[0013] Figure 1 This is a circuit diagram of a traditional voltage-controlled oscillator. Figure 2 This is the overall circuit diagram of a high-precision ring voltage-controlled oscillator; Figure 3 This is a circuit diagram of a ring oscillator; Figure 4 The simulation diagram shows the oscillation waveform of the oscillator as a function of the process. Figure 5 The simulation graph shows the oscillation frequency changing with temperature. Figure 6 The oscillation frequency is the result of the Monlocat simulation. Detailed Implementation

[0014] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a high-precision, low-temperature drift ring voltage-controlled oscillator according to the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0015] This invention provides a high-precision, low-temperature-drift ring voltage-controlled oscillator, comprising a switched-capacitor equivalent resistance module, a computation module, a ring oscillator, and a self-biased inverter. The switched-capacitor equivalent resistance module converts the oscillation clock frequency into an equivalent resistance, which is then converted into a feedback voltage VM, constructing a frequency-voltage negative feedback to suppress frequency drift caused by the PVT. The computation module is used to form the negative feedback loop, forcing the feedback node voltage to follow the control voltage V. Ctrl This provides a controllable power supply bias for the ring oscillator, enabling frequency adjustment; the ring oscillator is the core oscillation unit, operating under a bias voltage V. Bias The system generates a periodic oscillating clock signal under control; the self-biased inverter establishes a DC operating point through a feedback resistor, amplifies and shapes the AC oscillation signal after DC blocking, and outputs a regular square wave signal.

[0016] The switched capacitor equivalent resistance module includes a PMOS transistor P1, an NMOS transistor N1, and a capacitor C1. The source of the PMOS transistor P1 is connected to the inverting input of the operational amplifier ANP1 in the operational amplifier module. The gates of both the PMOS transistor P1 and the NMOS transistor N1 are connected to the output of the self-biased inverter. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N1 and the first terminal of the capacitor C1. The source of the NMOS transistor N1 and the second terminal of the capacitor C1 are both grounded to GND.

[0017] The operational amplifier module includes operational amplifier AMP1, resistors R1, R2, and R3, and PMOS transistor P0. The non-inverting input of operational amplifier AMP1 is connected to the second terminal of resistor R1 and the first terminal of resistor R2. The output terminal of operational amplifier AMP1 is connected to the gate of PMOS transistor P0. The first terminal of resistor R1 is connected to the power supply V. DD The second terminal of resistor R2 is grounded to GND; the source of PMOS transistor P0 is connected to the power supply. V DD The drain is connected to a ring oscillator; the first terminal of resistor R3 is connected to the power supply V. DD The second terminal is connected to the source of PMOS transistor P1.

[0018] The ring oscillator includes PMOS transistors P3, NMOS transistors N3, PMOS transistors P4, NMOS transistors N3, PMOS transistors P5, and NMOS transistors N5. The source of PMOS transistor P3 is connected to the drain of PMOS transistor P0, and the gates of PMOS transistor P3 and NMOS transistor N3 are connected to the input signal source V. in The drain of PMOS transistor P3 is connected to the drain of NMOS transistor N3, the gate of PMOS transistor P4, and the gate of NMOS transistor N4; the source of NMOS transistor N3 is connected to ground (GND); the source of PMOS transistor P4 is connected to the drain of PMOS transistor P0, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N4, the gate of PMOS transistor P5, and the gate of NMOS transistor N5; the source of NMOS transistor N4 is connected to ground (GND); the source of PMOS transistor P5 is connected to the drain of PMOS transistor P0, and the drain of PMOS transistor P5 is connected to the drain of NMOS transistor N5; the source of NMOS transistor N5 is connected to ground (GND).

[0019] The self-biased inverter includes capacitor C2, PMOS transistor P2, NMOS transistor N2, and resistor C4; the first terminal of capacitor C2 is connected to the output terminal of the ring oscillator, and the second terminal is connected to the gate of PMOS transistor P2, the gate of NMOS transistor N2, and the first terminal of resistor C4; the source of PMOS transistor P2 is connected to the power supply. V DD Connected, the drain is connected to the second terminal of resistor C4, the drain of NMOS transistor N2, and the output. V osc_out Connected; the source of NMOS transistor N2 is connected to ground GND.

[0020] First, a switched-capacitor frequency feedback loop is constructed using a switched-capacitor equivalent resistance module, operational amplifier AMP1, PMOS transistor P0, a ring oscillator, and a self-biased inverter. This converts the output frequency of the ring oscillator into the equivalent resistance of the switched capacitor, forming a closed-loop negative feedback loop of frequency-resistance-bias current-frequency. Second, the closed-loop negative feedback using operational amplifier AMP1 enables the feedback voltage... V M track V CTRL The automatic frequency adjustment, forming a dual closed-loop structure of current and frequency feedback, eliminates the influence of deviations in MOSFET threshold voltage, temperature, and process technology on the oscillation frequency, providing a stable bias current for the ring oscillator and achieving... V CTRL The high linear relationship between the frequency and the oscillation frequency improves frequency stability.

[0021] Figure 2 In the PMOS transistor P0, which operates in the deep transistor region, it can be considered as a variable resistor, and its resistance value can be expressed as:

[0022] For carrier mobility, The capacitance per unit area of ​​the gate oxide layer, The aspect ratio of the MOSFET. This is the threshold voltage.

[0023] Operational amplifier AMP1 will connect the non-inverting input V CTRL and inverting input V M Amplify the difference and output. V Bias .when V CTRL > V M At that time, AMP1 output V Bias The reduction can be obtained from equation (1) by controlling the gate voltage of the PMOS transistor P0. V Bias Adjustable R on This changes the bias current of the ring oscillator, thereby altering the oscillation frequency. The PMOS transistor P0... R on Decreasing the drain current of PMOS transistor P0 increases the drain current of PMOS transistor P0; conversely, increasing the drain current of PMOS transistor P0 increases the drain current of PMOS transistor P0. V CTRL < V M When this occurs, the drain current of PMOS transistor P0 decreases.

[0024] Figure 3 middle V D_P0 The drain voltage of the PMOS transistor P0 is the oscillation frequency and the delay of each inverter stage for a ring oscillator composed of three inverter stages. t d related. t d Essentially, it refers to the charging and discharging time of the load capacitor at the output terminal, which can be expressed as:

[0025] in C L Load capacitance includes the gate capacitance of the next stage, intrinsic capacitance, and interconnect parasitic capacitance; current. I Through V Bias Adjust the current generated by PMOS transistor P3. In the three-stage ring oscillator, the signal completes one flip through the three inverters within half a cycle, and then returns to the initial state after another half cycle. Therefore, the oscillation period T = 6. t dRing oscillator frequency f clk The calculation is as follows:

[0026] As can be seen from equation (3), the frequency of the ring oscillator can be adjusted by controlling the current I of the PMOS transistor P0.

[0027] Because the output of a ring oscillator contains low-frequency noise, a self-biased inverter is designed in the output stage to filter out the noise. (Capacitor) C 2 is the input coupling capacitor, and the resistor is... R 4 represents the feedback resistor. R 4 and C 2 forms a first-order high-pass filter with a cutoff frequency of:

[0028] Therefore, the frequency is higher than f c High-frequency signals can pass through this structure, while low-frequency signals are attenuated. Therefore, this structure can filter out low-frequency interference and noise, retain the high-frequency oscillation signal of the ring oscillator, and shape the output of the ring oscillator, making the rising and falling edges of the output waveform steeper. The resistors... R 4. Feed the output DC potential back to the input node to stabilize the input and output nodes. V DD At position / 2, self-biasing is achieved, eliminating the need for an additional biasing circuit. Additionally, the capacitor... C In addition to serving as a high-pass filter, 2 also isolates the input DC and ensures the feedback resistor R The DC bias function of 4 ensures that the gate potentials of NMOS transistor N2 and PMOS transistor P2 are determined solely by the feedback resistor. R 4. Decision, Output Node V osc_out DC potential through resistor R 4. Feedback is provided to the gates of NMOS transistors N2 and PMOS transistor P2, forming a closed-loop DC feedback. This stabilizes the gate potentials of NMOS transistors N2 and PMOS transistor P2 at the operating point where their drain currents are equal. When NMOS transistors N2 and PMOS transistor P2 are matched, the output DC potential equals the gate potential and is unaffected by the ring oscillator output. Simultaneously, to improve the frequency accuracy of the ring oscillator and avoid frequency drift when driving subsequent loads, a push-pull structure composed of PMOS transistors P2 and NMOS transistors N2 is designed to increase output current capability and reduce output impedance.

[0029] The VCO frequency is often determined by the charging and discharging time of the internal capacitor. To achieve stable voltage-frequency control, a design consisting of a PMOS transistor P1, an NMOS transistor N1, and a switched capacitor is used. C A switched capacitor equivalent resistance module, consisting of 1, is connected to the inverting input of an operational amplifier to form a closed-loop feedback to regulate the bias current of the oscillator. The output of the ring oscillator is used as the switching frequency, and the switched capacitor... C 1 is equivalent to a resistor R eq Through the ring oscillator frequency f clk right R eq Adjustments are made to change the time constant τ= R eq C1 enables stable frequency control of voltage.

[0030] The equivalent resistance of a switched capacitor refers to the resistance from the power supply voltage V when an inverter drives a capacitive load. DD The average current equivalent resistance is observed. The inverter formed by PMOS transistor P1 and NMOS transistor N1 can be simplified to a push-pull structure, with the switching capacitor activated when the oscillator signal is input. C 1. Charging and discharging: When the signal is low, PMOS transistor P1 turns on, and the output rises to... V M Voltage on switched capacitors C 1. Charging begins; when the signal is high, NMOS transistor N1 is turned on, affecting the switched capacitor. C 1. Discharge. When the input switching frequency is... f clk At that time, within one and a half cycles, from V DD Total charge extracted Q = C 1 V DD Then the average current I It can be represented as:

[0031] T is the period, and the equivalent resistance can be obtained. R eq for:

[0032] The equivalent resistance of the switched capacitor can be seen from the above formula. R eq The frequency and capacitance of the ring oscillator alone C 1. Decision.

[0033] The above analysis yields the closed-loop feedback principle for frequency regulation of the ring oscillator: when process fluctuations reduce the PMOS transistor P0 current, the ring oscillator frequency decreases, and the switching frequency of the switched capacitor equivalent resistance module also decreases. This can be seen from equation (6). R eq Increase, then V M Increase, through the output of operational amplifier AMP1 V BIAS This decreases, and the P0 current of the PMOS transistor increases, causing... f clk This increases, creating negative feedback. Therefore, when process fluctuations cause... f clk When changes occur, it will automatically adjust. R eq Controlled by operational amplifier V BIAS It can automatically compensate for the effects of process, voltage and temperature fluctuations on the oscillation frequency, thereby improving the frequency stability of the ring oscillator and the accuracy of the ring oscillator frequency.

[0034] from Figure 1 It can be seen that, V CTRL It can be represented as:

[0035] According to the formula for the equivalent resistance of a switched capacitor. V M It can be represented as:

[0036] The frequency of the ring oscillator can be obtained as:

[0037] Simulate the circuit. Figure 4 The simulation waveforms show the oscillations of the ring oscillator at various process corners. The simulation waveforms show that the ring oscillator frequency is 306MHz at process corner TT, 288MHz at process corner SS, and 330MHz at process corner FF. The frequency variation of the ring oscillator at each process corner is 13.7%.

[0038] Figure 5 The figure shows the simulated waveform of the ring oscillation frequency as a function of temperature, ranging from -55℃ to 125℃. As can be seen from the figure, the oscillation frequency is highest at -55℃ (314MHz), lowest at 125℃ (300MHz), and lowest at room temperature (306MHz), with a temperature drift of 4.6%.

[0039] Figure 6The image shows a Monte Carlo simulation of the ring oscillator at 100 samples. The simulation waveform shows a standard deviation σ of 8.5 MHz and a relative mean fluctuation of 2.76%.

[0040] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-precision, low-temperature drift ring voltage-controlled oscillator, characterized in that, It includes a switched capacitor equivalent resistance module, an arithmetic module, a ring oscillator, and a self-biased inverter; The switched capacitor equivalent resistance module converts the oscillation clock frequency into an equivalent resistance, which is then converted into a feedback voltage VM to build frequency-voltage negative feedback and suppress frequency drift caused by PVT. The arithmetic module is used to form a negative feedback loop, forcing the feedback node voltage to follow the control voltage V. Ctrl This provides a controllable power supply bias for the ring oscillator, enabling frequency adjustment; The ring oscillator is the core oscillation unit, under a bias voltage V Bias A periodic oscillating clock signal is generated under control; The self-biased inverter establishes a DC operating point through a feedback resistor, amplifies and shapes the AC oscillation signal after DC blocking, and outputs a regular square wave signal.

2. The high-precision, low-temperature drift ring voltage-controlled oscillator as described in claim 1, characterized in that, The switched capacitor equivalent resistance module includes a first PMOS transistor, a first NMOS transistor, and a first capacitor; the source of the first PMOS transistor is connected to the operational module, the gates of the first PMOS transistor and the first NMOS transistor are both connected to the output of the self-biased inverter, the drain of the first PMOS transistor is connected to the drain of the first NMOS transistor and the first terminal of the first capacitor; the source of the first NMOS transistor and the second terminal of the first capacitor are both grounded to GND.

3. The high-precision, low-temperature drift ring voltage-controlled oscillator as described in claim 2, characterized in that, The operational amplifier module includes an operational amplifier, a first resistor, a second resistor, a third resistor, and a zeroth PMOS transistor; the non-inverting input of the operational amplifier is connected to the second terminal of the first resistor and the first terminal of the second resistor, the inverting input is connected to the source of the first PMOS transistor, and the output terminal is connected to the gate of the zeroth PMOS transistor; the first terminal of the first resistor is connected to the power supply V. DD The second terminal of the second resistor is grounded (GND); the source of the zeroth PMOS transistor is connected to the power supply. V DD The drain is connected to a ring oscillator; the first terminal of the third resistor is connected to the power supply V. DD The second terminal is connected to the source of the first PMOS transistor.

4. The high-precision, low-temperature drift ring voltage-controlled oscillator as described in claim 3, characterized in that, The ring oscillator includes a third PMOS transistor, a third NMOS transistor, a fourth PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, and a fifth NMOS transistor; The source of the third PMOS transistor is connected to the drain of the zeroth PMOS transistor, and the gates of the third PMOS transistor and the third NMOS transistor are connected together to the input signal source V. in The drain of the third PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the fourth PMOS transistor, and the gate of the fourth NMOS transistor; the source of the third NMOS transistor is connected to ground (GND). The source of the fourth PMOS transistor is connected to the drain of the zeroth PMOS transistor, and the drain of the fourth PMOS transistor is connected to the drain of the fourth NMOS transistor, the gate of the fifth PMOS transistor, and the gate of the fifth NMOS transistor; the source of the fourth NMOS transistor is connected to ground (GND). The source of the fifth PMOS transistor is connected to the drain of the zeroth PMOS transistor, the drain of the fifth PMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fifth NMOS transistor is connected to ground (GND).

5. The high-precision, low-temperature drift ring voltage-controlled oscillator as described in claim 4, characterized in that, The self-biased inverter includes a second capacitor, a second PMOS transistor, a second NMOS transistor, and a fourth resistor; The first end of the second capacitor is connected to the output end of the ring oscillator, and the second end is connected to the gate of the second PMOS transistor, the gate of the second NMOS transistor, and the first end of the fourth resistor. The source and power supply of the second PMOS transistor V DD Connected, the drain is connected to the second terminal of the fourth resistor, the drain of the second NMOS transistor, and the output. V osc_out The second NMOS transistor is connected to ground (GND).

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