Amplifier device and biasing method thereof

Abstract

This disclosure provides an amplifier device and a biasing method thereof. The amplifier device includes an input pair circuit, a bias voltage generation circuit, and a current mirror circuit. The input pair circuit is used to bias via a bias voltage and a bias current, and to generate a first output signal and a second output signal based on a first input signal and a second input signal. The bias voltage generation circuit is used to generate the bias voltage by tracking changes in the internal voltage drop in the input pair circuit based on the bias current. The current mirror circuit is coupled to the input pair circuit and the bias voltage generation circuit, and is used to generate the bias current.

Description

Technical Field

[0001] This disclosure relates to amplifier devices, and more particularly to amplifier devices and biasing methods that can adaptively generate bias voltages. Background Technology

[0002] In existing amplifiers, the main transistor used to process signals is biased via a voltage divider circuit, which is typically implemented using multiple resistors connected in series. When the amplifier is subjected to unexpected influences such as process variations, voltage variations, temperature variations, etc., the bias setting in the amplifier will shift. In the above-described technology, the voltage divider circuit formed by multiple resistors can only generate a fixed bias voltage and cannot adjust the bias voltage according to the shift. This may cause the main transistor in the amplifier to operate incorrectly in an unintended operating region (e.g., a transistor region), resulting in reduced amplifier performance. Summary of the Invention

[0003] In some embodiments, one of the objectives of this disclosure is (but not limited to) to provide an amplifier device and biasing method thereof that can adaptively generate bias voltage to improve the shortcomings of the prior art.

[0004] In some embodiments, the amplifier device includes an input pair circuit, a bias voltage generation circuit, and a current mirror circuit. The input pair circuit is used to bias via a bias voltage and a bias current, and to generate a first output signal and a second output signal based on a first input signal and a second input signal. The bias voltage generation circuit is used to generate the bias voltage by tracking changes in the internal voltage drop within the input pair circuit based on the bias current. The current mirror circuit is coupled to the input pair circuit and the bias voltage generation circuit, and is used to generate the bias current.

[0005] In some embodiments, a biasing method suitable for an amplifier device includes the following operations: biasing an input pair circuit in the amplifier device via a bias voltage and a bias current, such that the input pair circuit generates a first output signal and a second output signal based on a first input signal and a second input signal; generating the bias voltage via a bias voltage generating circuit in the amplifier device that tracks changes in the internal voltage drop of the input pair circuit based on the bias current; and generating the bias current via a current mirror circuit in the amplifier device, wherein the current mirror circuit is coupled to the input pair circuit and the bias voltage generating circuit.

[0006] The features, implementation, and effects of this disclosure are described in detail below with reference to the accompanying drawings, using preferred embodiments. Attached Figure Description

[0007] Figure 1 A schematic diagram of an amplifier device is provided according to some embodiments of the present disclosure; Figure 2 Drawings based on some embodiments of this disclosure Figure 1 A circuit diagram of the amplifier device; and Figure 3 A flowchart of a biasing method is provided according to some embodiments of this disclosure. Detailed Implementation

[0008] All terms used herein have their common meaning. The definitions of the terms used above in commonly used dictionaries, and any examples of the use of any term discussed herein, are merely illustrative and should not be construed as limiting the scope or meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.

[0009] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, the term “circuit” can refer to a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.

[0010] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, third, etc., are used herein to describe and identify individual elements. Therefore, a first element herein may also be referred to as a second element without departing from the intent of this disclosure. For ease of understanding, similar elements in the figures will be designated with the same reference numerals.

[0011] Figure 1 A schematic diagram of an amplifier device 100 is provided according to some embodiments of the present disclosure. In some embodiments, the amplifier device 100 includes a signal coupling circuit 110, an input pair circuit 120, a bias voltage generation circuit 130, and a current mirror circuit 140. The signal coupling circuit 110 couples the AC signal component of a signal IN (hereinafter referred to as input signal VI1) to the input pair circuit 120, and couples the AC signal component of a signal IP (hereinafter referred to as input signal VI2) to the input pair circuit 120. The input pair circuit 120 is biased via a bias voltage VB and a bias current I1, and generates output signals VO1 and VO2 based on input signals VI1 and VI2. The bias voltage generation circuit 130 generates the aforementioned bias voltage VB by tracking changes in the internal voltage drop in the input pair circuit 120 based on the bias current I1. In some embodiments, the bias voltage generation circuit 130 is also used to transmit the bias voltage VB to the input pair circuit 120 via the signal coupling circuit 110. Further details herein will be provided later. Figure 2Detailed description. The current mirror circuit 140 is coupled to the input pair circuit 120 and the bias voltage generation circuit 130, and is used to generate the aforementioned bias current I1.

[0012] In some embodiments, based on the technique of replica biasing, the bias voltage generation circuit 130 can be configured to simulate at least a portion of the connection relationship and related circuit settings between the input pair circuit 120 and the current mirror circuit 140, thereby generating a bias voltage VB based on the bias current I1 tracking the internal voltage drop change. In this way, even under the influence of mismatch caused by unexpected factors, the bias voltage VB can still enable the transistors in the input pair circuit 120 (e.g., [missing information]) to [missing information]. Figure 2 Transistors M1 and M2 are fixed in the saturation region so that the input pair circuit 120 can continuously and correctly generate output signals VO1 and VO2 according to input signals VI1 and VI2.

[0013] Figure 2 Drawings based on some embodiments of this disclosure Figure 1 A circuit diagram of the amplifier device 100 is shown below. In this example, the input pair circuit 120 includes transistors M1 and M2, resistors R1 and R2. Transistor M1 is coupled between resistor R1 and current mirror circuit 140, and is biased via bias voltage VB and bias current I1 to generate an output signal VO1 based on input signal VI1. Similarly, transistor M2 is coupled between resistor R2 and current mirror circuit 140, and is biased via bias voltage VB and bias current I1 to generate an output signal VO2 based on input signal VI2.

[0014] Specifically, the first terminals of both resistors R1 and R2 receive the power supply voltage VDD. The second terminal of resistor R1 is coupled to the first terminal of transistor M1 (e.g., the drain) to provide the output signal VO1, and the second terminal of resistor R2 is coupled to the first terminal of transistor M2 to provide the output signal VO2. The second terminals of transistor M1 (e.g., the source) and transistor M2 are coupled to the current mirror circuit 140. The control terminal of transistor M1 (e.g., the gate) receives the input signal VI1, and the control terminal of transistor M2 receives the input signal VI2. In some embodiments, transistors M1 and M2 can be configured as a differential input pair. For example, transistors M1 and M2 can have the same size and can be used to process signals with opposite phases (e.g., input signals VI1 and VI2).

[0015] The current mirror circuit 140 includes transistors M3 and M4, and a current source circuit 142. The current source circuit 142 receives a power supply voltage VDD and provides a reference current IREF. A first terminal of transistor M3 is coupled to the second terminals of both transistors M1 and M2, and draws a bias current I1 from transistors M1 and M2 to bias them. The control terminal of transistor M3 receives a control voltage VC, enabling it to generate a bias current I1 based on VC. The first terminal and control terminal of transistor M4 are coupled to the current source circuit 142 to receive the reference current IREF and generate the control voltage VC accordingly. The second terminals of both transistors M3 and M4 are grounded. The current source circuit 142 receives the power supply voltage VDD and provides the reference current IREF to bias transistor M4.

[0016] The bias voltage generating circuit 130 includes a resistor R3, a transistor M5, and a transistor M6. The first terminal of resistor R3 receives the power supply voltage VDD, and the second terminal of resistor R3 is coupled to the first terminal of transistor M5 to provide a bias voltage VB. The second terminal and control terminal of transistor M5 are coupled to the first terminal of transistor M6. With this configuration, transistor M5 is coupled to resistor R3 and can be configured as a diode-connected transistor. Thus, transistor M5 will operate in the saturation region, thereby generating the corresponding bias voltage VB. The control terminal of transistor M6 is coupled to the control terminal of transistor M4 to receive a control voltage VC, and the second terminal of transistor M6 is coupled to ground. Transistor M6 operates as a current source according to the control voltage VC to bias transistor M5.

[0017] As previously described, the bias voltage generation circuit 130 can be configured to simulate at least a portion of the connection relationship between the input pair circuit 120 and the current mirror circuit 140 and its associated circuit settings, thereby tracking changes in the internal voltage drop in the input pair circuit 120 based on the bias current I1. For example, the resistance value of resistor R3 can be set to be approximately the same as the resistance value of resistor R1, transistors M5 and M1 can have approximately the same dimensions (e.g., having the same aspect ratio), transistors M6 and M4 can have approximately the same dimensions, and the dimension of transistor M6 (or transistor M4) is half the dimension of transistor M3, i.e., the ratio between the aspect ratio of transistor M6 (or transistor M4) and the aspect ratio of transistor M3 is approximately 1:2. Thus, the ratio between the reference current IEF and the bias current I1 is approximately 1:2, making the current flowing through transistor M1 approximately half of the bias current I1 (i.e., the ratio between the current flowing through transistor M1 and the bias current I1 is approximately 1:2), and the current I2 flowing through transistors M4 and M6 is also approximately half of the bias current I1 (i.e., the ratio between current I2 and bias current I1 is approximately 1:2). Therefore, when the bias current I1 deviates due to unexpected variations, the current mirror circuit 140 adjusts the control voltage VC accordingly, so that the current I2 and the bias current I1 conform to the aforementioned ratio setting, and the bias voltage generating circuit 130 generates a corresponding bias voltage VB to continuously bias transistors M1 and M2 in the saturation region.

[0018] In other words, in this embodiment, the bias voltage generation circuit 130 can be configured to simulate the connection relationship between resistor R1, transistor M1, and transistor M3, and their related circuit settings, thereby generating a corresponding bias voltage VB based on the bias current I1. When a voltage difference occurs between the first and second terminals of transistor M3 due to the offset of the bias current I1, the voltage across the first and second terminals of transistor M1 will change accordingly (i.e., the aforementioned internal voltage drop change). The bias voltage generation circuit 130 can detect the aforementioned internal voltage drop change by means of the aforementioned configuration, thereby generating a more accurate bias voltage VB in real time based on the current I2 and the bias current I1, so that transistors M1 and M2 can continue to operate correctly in the saturation region. Similarly, the bias voltage generation circuit 130 can also simulate the connection relationship between resistor R2, transistor M2, and transistor M3, and their related circuit settings, thereby generating a corresponding bias voltage VB.

[0019] The signal coupling circuit 110 includes capacitors C1 and C2, and resistors R4 and R5. Resistors R4 and R5 are connected in series between capacitors C1 and C2, and the bias voltage generating circuit 130 can transmit the bias voltage VB to the input pair circuit 120 via resistors R4 and R5.

[0020] In detail, the first terminal of capacitor C1 receives the signal IN, and the second terminal of capacitor C1 outputs the input signal VI1 to the control terminal of transistor M1. Capacitor C1 can operate as an AC coupling circuit to output the AC signal component of signal IN as the input signal VI1. Similarly, the first terminal of capacitor C2 receives the signal IP, and the second terminal of capacitor C2 outputs the input signal VI2 to the control terminal of transistor M2. Capacitor C2 can operate as an AC coupling circuit to output the AC signal component of signal IP as the input signal VI2. The first terminal of resistor R4 is coupled to the second terminal of capacitor C1, the second terminal of resistor R4 is coupled to the first terminal of resistor R5 and coupled to the bias voltage generating circuit 130 to receive the bias voltage VB, and the second terminal of resistor R5 is coupled to the second terminal of capacitor C2. With the above configuration, the bias voltage generating circuit 130 can transmit the bias voltage VB to the control terminal of transistor M1 via resistor R4 to bias transistor M1. Similarly, the bias voltage generation circuit 130 can transmit the bias voltage VB to the control terminal of transistor M2 via resistor R5 to bias transistor M2. Equivalently, the signal at the second terminal of capacitor C1 can be the superposition of input signal VI1 and bias voltage VB, and the signal at the second terminal of capacitor C2 can be the superposition of input signal VI2 and bias voltage VB. In some embodiments, each of resistors R4 and R5 has a sufficiently high resistance value to improve the input signal range. In some embodiments, resistors R4 and R5, capacitors C1 and C2 form a high-pass filter. Capacitors C1 and C2, transistors M1 and M2 constitute a high impedance (i.e., the gates of both capacitors C1 and C2, and transistors M1 and M2 can constitute a high impedance, thereby not consuming direct current (DC) current).

[0021] Figure 3 A flowchart of a biasing method 300 is provided according to some embodiments of the present disclosure. In different embodiments, the biasing method 300 may be applied to... Figure 1 or Figure 2 The amplifier device 100 is not limited thereto.

[0022] In operation S310, the input pair circuit in the amplifier device is biased via a bias voltage and a bias current, causing the input pair circuit to generate a first output signal and a second output signal based on a first input signal and a second input signal. In operation S320, the bias voltage is generated by a bias voltage generating circuit in the amplifier device based on the bias current tracking the internal voltage drop change in the input pair circuit. In operation S330, the bias current is generated via a current mirror circuit in the amplifier device, wherein the current mirror circuit is coupled to the input pair circuit and the bias voltage generating circuit.

[0023] The relevant operations of the biasing method 300 can be referred to the descriptions of the foregoing embodiments, and therefore will not be repeated here. The various operations in the biasing method 300 are merely examples and are not limited to being performed in the order shown in these examples. Without departing from the operation mode and scope of the embodiments of this disclosure, the relevant operations in the biasing method 300 may be appropriately added, replaced, omitted, or performed in a different order. Alternatively, the relevant operations in the above figures may be performed simultaneously or partially simultaneously.

[0024] In summary, the amplifier devices and biasing methods provided in some embodiments of this disclosure can adaptively generate bias voltages, thereby preventing the amplifier devices from operating in the incorrect operating range due to unintended influences.

[0025] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on the express or implied content of this disclosure. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the scope of the patent application in this specification.

[0026] [Symbol Explanation] 100: Amplifier device 110: Signal coupling circuit 120: Input pair circuit 130: Bias voltage generation circuit 140: Current Mirror Circuit 142: Current Source Circuit 300: Bias method C1, C2: Capacitors I1: Bias current I2: Current IN, IP: Signals IREF: Reference Current M1, M2, M3, M4, M5, M6: Transistors R1, R2, R3, R4, R5: Resistors S310, S320, S330: Operation VB: Bias voltage VC: Control Voltage VDD: Power supply voltage VI1, VI2: Input signals VO1, VO2: Output signals

Claims

1. An amplifier device, comprising: The input pair circuit is used to bias via bias voltage and bias current, and to generate a first output signal and a second output signal based on a first input signal and a second input signal; A bias voltage generation circuit is used to track the change in the internal voltage drop of the input pair circuit based on the bias current in order to generate the bias voltage. as well as A current mirror circuit is coupled to the input pair circuit and the bias voltage generating circuit, and is used to generate the bias current.

2. The amplifier device of claim 1, wherein the bias voltage generating circuit is used to simulate a portion of the connection between the input pair circuit and the current mirror circuit, thereby generating the bias voltage based on the bias current tracking the internal voltage drop change.

3. The amplifier device of claim 1, wherein the bias voltage generating circuit comprises: resistance; A first transistor, coupled to the resistor and configured as a diode-type transistor, generates the bias voltage; as well as The second transistor is coupled to the first transistor and biases the first transistor according to a control voltage, wherein the current mirror circuit is also used to generate the bias current and the control voltage based on a reference current.

4. The amplifier device of claim 3, wherein a first terminal and a control terminal of the first transistor are coupled to the resistor and are used to output the bias voltage, a second terminal of the first transistor is coupled to the first terminal of the second transistor, a second terminal of the second transistor is coupled to ground, and a control terminal of the second transistor receives the control voltage.

5. The amplifier device of claim 3, wherein the ratio between the reference current and the bias current is 1:

2.

6. The amplifier device of claim 3, wherein the ratio between the current flowing through the first transistor and the bias current is 1:

2.

7. The amplifier device of claim 1, wherein the input pair circuitry comprises: First resistor; A first transistor is coupled between the first resistor and the current mirror circuit, and is biased by the bias voltage and the bias current to generate the first output signal according to the first input signal; Second resistor; as well as The second transistor is coupled between the second resistor and the current mirror circuit, and is biased by the bias voltage and the bias current to generate the second output signal according to the second input signal.

8. The amplifier device of claim 7, wherein the bias voltage is used to fix the first transistor and the second transistor in the saturation region.

9. The amplifier device of claim 7, wherein the bias voltage generating circuit is used to simulate the connection relationship between the first resistor, the first transistor and the current mirror circuit, thereby generating the bias voltage based on the bias current tracking the internal voltage drop change.

10. A biasing method applicable to an amplifier device, the biasing method comprising: The input pair circuit in the amplifier device is biased by a bias voltage and a bias current, so that the input pair circuit generates a first output signal and a second output signal according to the first input signal and the second input signal; The bias voltage is generated by the bias voltage generation circuit in the amplifier device based on the bias current tracking the internal voltage drop change in the input pair circuit. as well as The bias current is generated via a current mirror circuit in the amplifier device, wherein the current mirror circuit is coupled to the input pair circuit and the bias voltage generation circuit.

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