A broadband power amplifier based on GaAs IPD heterogeneous integration and a preparation method thereof

Abstract

This invention discloses a heterogeneous integrated broadband power amplifier based on GaAs IPD and its fabrication method, belonging to the field of radio frequency microwave integrated circuit technology. Addressing the problems of large size, limited bandwidth, and difficult-to-control parasitic parameters in traditional power amplifiers, this invention uses a GaN HEMT bare chip as the amplification core, combined with a high-Q GaAs IPD chip to construct a built-in input matching network. The two are interconnected by gold wire bonding and then encapsulated together in a 4mm×4mm QFN package. On the input side, IPD is used to achieve power flatness ≤±1dB in the 30MHz~1500MHz frequency band. External matching is used on the output side, balancing mass production consistency and customization requirements. Experimental results show that the device exhibits a typical power gain >15dB and drain efficiency >35% at 4W (36dBm) saturated power. This invention resolves the contradiction between broadband and miniaturization through heterogeneous integration, reducing size by 40% and cost by 30%, making it suitable for high-performance scenarios such as 5G base stations.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency microwave integrated circuit technology, and specifically relates to a plastic-encapsulated power amplifier device and its manufacturing method that heterogeneously integrates an integrated passive device (GaAs IPD) and a high electron mobility transistor (HEMT). Background Technology

[0002] Currently, RF power amplifiers are rapidly evolving towards wider bandwidth, greater integration, and lower cost. Addressing the industry pain points of large parasitic parameters in traditional matching architectures and high costs of fully integrated solutions, the industry is actively promoting heterogeneous integration technology: leveraging high-Q GaAs IPDs to solve the ultra-wideband matching problem, while plastic-encapsulated devices, with their high reliability and lightweight advantages, are rapidly replacing traditional ceramic packaging as the mainstream solution in the industry.

[0003] With the increasing demands placed on radio frequency front-end systems by applications such as 5G base stations, electronic warfare, and broadband communications, power amplifiers, as key components of radio frequency front-ends, need to provide higher output power and efficiency over a wider frequency band, while also meeting increasingly stringent requirements for miniaturization and low cost.

[0004] In the design of broadband power amplifiers, the design of the matching network is one of the most challenging aspects. For broadband circuits, the input / output impedance varies significantly under broadband conditions, rendering the conjugate matching concept of traditional narrowband amplifiers inapplicable. Impedance matching needs to be achieved over an extremely wide frequency band. Traditional matching architectures often use discrete passive components on printed circuit boards (PCBs) to implement the matching network. However, this method suffers from significant problems such as large parasitic parameters, poor consistency, and large footprint, severely limiting the broadband performance and miniaturized integration of the power amplifier.

[0005] To address these issues, the industry has attempted a monolithic microwave integrated circuit (MMIC) solution, integrating active devices and passive matching networks onto a single chip. However, this fully integrated approach requires a large amount of expensive GaN or GaAs wafer material, resulting in high costs. Furthermore, the quality factor (Q value) of passive devices in the fully integrated solution is limited by the manufacturing process, making it difficult to achieve the low insertion loss and high precision required for ultra-wideband matching.

[0006] To address the aforementioned issues, this invention provides a broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT and its fabrication method. Through an innovative internal matching + external matching hybrid architecture and a compact QFN plastic package design, it achieves a unified approach of ultra-wideband, high gain, high efficiency, and miniaturization. Summary of the Invention

[0007] This invention aims to solve the problems of large size, difficult control of parasitic parameters, and limited bandwidth of existing broadband power amplifiers. Due to the large changes in input / output impedance under broadband conditions, the concept of conjugate matching of traditional narrowband amplifiers is no longer applicable. This invention provides a broadband power amplifier based on GaAs IPD heterogeneous integration and its fabrication method to achieve ultra-wideband, high-gain, and miniaturized power amplifier devices.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] A broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT includes:

[0010] QFN package;

[0011] A GaN HEMT bare chip is disposed inside the QFN package and is used as an amplification core unit;

[0012] A GaAs IPD chip is disposed inside the QFN package and integrates an input matching network, which is used to match the radio frequency input signal to the gate of the GaN HEMT bare chip.

[0013] The GaN HEMT bare chip and the GaAs IPD chip are interconnected by gold wire bonding and are jointly encapsulated in the QFN package.

[0014] The GaAs IPD chip integrates all the input-side matching networks of the broadband power amplifier, and the output-side matching network of the broadband power amplifier is located outside the QFN package.

[0015] As a further preferred embodiment of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT of the present invention, the input matching network of the GaAs IPD chip integrated in the QFN package includes:

[0016] An RC stabilization network, consisting of a resistor R11 and a capacitor C11 connected in parallel and in series with the input terminal of the GaN HEMT bare chip, is used to enhance low-frequency stability.

[0017] A first-order LC matching network, consisting of an inductor L12 connected in series with the signal path and a capacitor C12 connected in parallel with ground, is used to match the input impedance to 50Ω.

[0018] The series LC stabilization network consists of a series inductor L13 and a parallel capacitor C13 connected to ground. It is connected to the RF input terminal to improve stability.

[0019] An inductor L11 is connected in series at the output of the GaN HEMT bare chip to match the 50Ω impedance to the die's optimal load impedance.

[0020] As a further preferred embodiment of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT of the present invention, the GaAs IPD chip adopts a three-layer metal wiring architecture, including a bottom metal layer MET1, a middle metal layer MET2 and a top metal layer MET3. Adjacent metal layers are isolated by SiN dielectric layers, and vertical interconnection is achieved between the layers through a filled via structure to form interconnection channels for MIM capacitors and low parasitic inductance.

[0021] As a further preferred embodiment of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT of the present invention, the GaN HEMT bare chip adopts a 0.25μm process and uses silicon carbide (SiC) as a substrate, with a total gate width of 1.2mm; the QFN package has a size of 4mm×4mm×0.85mm.

[0022] As a further preferred embodiment of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT of the present invention, the broadband power amplifier has a power flatness of ≤±1dB in the frequency band of 30MHz to 1500MHz, a saturated output power of ≥36dBm at a rated power output of 4W, a typical power gain of >15dB, and a drain efficiency of >35%.

[0023] A method for fabricating a broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT includes the following steps:

[0024] Step 1: Provide a GaN HEMT bare chip, which is manufactured using a 0.25μm process and uses silicon carbide (SiC) as a substrate, with a total gate width of 1.2mm;

[0025] Step 2, provide a GaAs IPD chip, on which an input matching network is integrated. The input matching network includes an RC stabilization network composed of a resistor R11 and a capacitor C11 connected in parallel, a first-order LC matching network composed of an inductor L12 and a capacitor C12, and a series LC stabilization network composed of an inductor L13 and a capacitor C13.

[0026] Step 3: The GaN HEMT bare chip is attached to the base of the QFN lead frame using nano-silver paste;

[0027] Step 4: Use gold wire to bond and interconnect the output terminal of the input matching network of the GaAs IPD chip with the gate of the GaN HEMT bare chip to achieve input matching connection of radio frequency signal;

[0028] Step 5: The GaN HEMT bare chip and the GaAs IPD chip are jointly encapsulated in a QFN package to form a 4mm×4mm package.

[0029] Step 6: Set an output-side matching network outside the QFN package. The output-side matching network is composed of external surface-mount devices.

[0030] As a further preferred embodiment of the fabrication method of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT of the present invention, in step 3, the thermal conductivity of the nano-silver paste is 150 W / (m·K); in step 4, the diameter of the gold wire is 25 μm, the purity is 99.99%, and the bonding is performed by gold wire ball bonding process.

[0031] As a further preferred embodiment of the fabrication method of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT of the present invention, in step 2, the fabrication method of the GaAs IPD chip includes:

[0032] SiN dielectric layers are sequentially deposited on a GaAs substrate to form a three-layer metal wiring architecture, including a bottom metal layer MET1, a middle metal layer MET2, and a top metal layer MET3.

[0033] Adjacent metal layers are isolated and supported by SiN dielectric layers with thicknesses of 0.15~1μm, 0.15μm, and 0.32μm, respectively.

[0034] Vertical interconnections between layers are achieved by filling the via structure with photolithography and electroplating, forming interconnect channels for MIM capacitors and low parasitic inductance.

[0035] As a further preferred embodiment of the fabrication method of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT of the present invention, the method further includes the step of constructing a bias circuit:

[0036] Fabricate a 50Ω characteristic impedance microstrip line on a microwave substrate;

[0037] A DC blocking capacitor C51 is set at the RF input terminal. The DC blocking capacitor C51 is connected in series between the RF input port RFin and the RF input pin of the QFN package.

[0038] Set up a gate bias power supply link, and connect the gate bias voltage VG to the gate bias power supply pin of the QFN package through parallel decoupling capacitors C52 and C53 and series resistor R51.

[0039] The drain bias power supply link is set up, and the drain bias voltage VD is connected to the drain bias power supply pin of the QFN package through parallel decoupling capacitors C52, C53, and C54 and series RF choke inductor L52.

[0040] As a further preferred embodiment of the fabrication method of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT of the present invention, in step 5, pins 2 and 3 of the QFN package are the RF input terminal and the gate bias power supply terminal, pins 10 and 11 of the QFN package are the RF output terminal and the drain bias power supply terminal, and the remaining non-functional pins are left floating in the internal design.

[0041] Compared with the prior art, the present invention, employing the above technical solution, has the following technical effects:

[0042] 1. This invention achieves the co-design and integration of GaAs IPD and GaN HEMT within an ultra-wideband range of 30~1500MHz. Utilizing the high precision of the IPD, it ensures power flatness (≤±1dB) and mass production consistency across the entire frequency band. Compared to traditional GaAs solutions (such as the CHA6652-98F with 33dBm saturated output power and 25% typical PAE), this invention boasts a saturated output power exceeding 37dBm (approximately 5W) and a PAE greater than 55%, demonstrating significant advantages in power capacity and energy efficiency conversion. -2-1 .

[0043] 2. This invention adopts a QFN molding process in its packaging structure, compressing the volume to 4mm×4mm, which is more than 40% smaller than traditional ceramic packaging (such as a 30.6mm×27.3mm×5.0mm metal-ceramic tube). -21 While ensuring airtightness and miniaturization, it retains the adjustability of the output external matching, taking into account both mass production consistency and customers' differentiated customization needs for harmonic suppression and efficiency indicators.

[0044] 3. In terms of performance indicators, this invention provides 4W (36dBm) saturated output power while achieving a typical power gain of over 15dB, and maintains a drain efficiency of over 35%, which can even exceed 69% in the low-frequency band, thus achieving breakthrough progress in bandwidth, gain, efficiency and manufacturability.

[0045] 4. This invention uses silicon carbide-based GaN HEMT with a thermal conductivity of 120-150 W / m·K, combined with nano silver paste with a thermal conductivity of 150 W / (m·K) as the thermal interface material, which effectively solves the problem of thermal runaway in small volume. The volume of the heat sink can be reduced by 40%, while also reducing the heat dissipation requirements and further reducing the size of the equipment.

[0046] 5. This invention, combined with standardized peripheral circuits and protection timing design, can significantly reduce the sensitivity to PCB layout, significantly improve system production yield, reduce costs by more than 30%, and is highly adaptable to mass production application scenarios such as 5G base stations and electronic countermeasures, which are highly sensitive to cost and size. Attached Figure Description

[0047] Figure 1 The matching circuit topology diagram provided for this invention illustrates the connection of the matching circuit.

[0048] Figure 2 The three-dimensional structural diagram of GaAs IPD technology provided by this invention shows the stacked structure and spatial layout of integrated devices on a GaAs substrate.

[0049] Figure 3 The simulation results provided for this invention fully verify the significant advantages of this design in terms of high power output and high energy efficiency conversion.

[0050] Figure 4 The plastic package layout diagram provided for this invention shows the optimized arrangement of the chip, interconnects and pins within a 4mm×4mm QFN package.

[0051] Figure 5 The test circuit topology provided by this invention demonstrates the cooperative connection relationship between microstrip lines, chokes, and capacitors in the bias circuit.

[0052] Figure 6 The measured results of the power amplifier provided by this invention verify the output power and efficiency indicators in the 30-1500MHz frequency band. Detailed Implementation

[0053] The technical solution of the present invention will be further described in detail below with reference to the accompanying drawings:

[0054] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention. The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. The purpose and effects of the present invention will become clearer. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0055] This invention discloses a broadband power amplifier based on the co-design of GaAs IPD and GaN HEMT, and its fabrication method. The specific technical solution is as follows:

[0056] A GaN HEMT bare chip is selected as the amplification core, and a high-Q GaAs IPD chip is used to construct the built-in input matching network. The two are interconnected by gold wire bonding and encapsulated together in a 4mm×4mm DFN package. On the output side, an innovative external surface-mount device is used to construct the matching network. This leverages the high precision of the IPD to ensure power flatness and mass production consistency across the entire 30MHz~1500MHz frequency band, while retaining the flexibility of external tuning, achieving a balance between high-performance built-in integration and low-cost external customization. Experimental results show that this design achieves a saturation power exceeding 36 dBm and a drain efficiency (PAE) greater than 35% at a rated power output of 4W. Compared to traditional GaAs solutions (such as CHA6652-98F), it has significant advantages in power capacity and energy efficiency conversion, making it suitable for miniaturized, high-performance RF front-end systems. This invention aims to solve the problems of large size, difficult-to-control parasitic parameters, and limited bandwidth in existing broadband power amplifiers. Due to the large changes in input / output impedance under broadband conditions, the concept of conjugate matching of traditional narrowband amplifiers is no longer applicable. Therefore, this invention provides a heterogeneous integration scheme based on GaAs IPD for internal input matching, GaNHEMT bare core and IPD co-encapsulation, and external output matching to achieve ultra-wideband, high-gain, and miniaturized power amplifier devices.

[0057] Among them, (1) heterogeneous integration technology: high-performance GaN HEMT bare chips are selected as the core amplification unit, and heterogeneous integration is carried out with IPD based on GaAs substrate. High-precision input matching network is fabricated by utilizing the excellent high-frequency characteristics of GaAs substrate.

[0058] (2) Plastic encapsulation structure: The GaN HEMT bare die and GaAs IPD chip are interconnected by gold wire bonding and then encapsulated together in a QFN package to form a compact 4mm×4mm×0.85mm package, which significantly reduces parasitic effects.

[0059] (3) Hybrid matching architecture: The system adopts a hybrid architecture of "internal matching + external matching". Input matching is completed by GaAsIPD within the package to ensure broadband stability and gain; output matching is reserved for external surface mount devices (SMT), which allows users to flexibly adjust the output power and efficiency according to the actual load scenario.

[0060] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0061] (1) Core design

[0062] A GaN HEMT using a 0.25 µm process with silicon carbide (SiC) as the substrate was selected. Compared to silicon-based HEMTs, SiC-based HEMTs offer a thermal conductivity of 120-150 W / m·K, exhibiting higher thermal conductivity and lower substrate loss, making them more suitable for plastic encapsulation (shorter heat dissipation path). Huawei's measured data shows that AAU devices using SiC-based GaN RF modules can reduce heat sink volume by 40%, effectively preventing thermal runaway in smaller sizes while reducing heat dissipation requirements and further minimizing device size. At a gate voltage of 28V, the power density of the GaN HEMT is approximately 4.5 W / mm. Considering circuit losses, to achieve a rated power output of 4W, this design uses a die with a total gate width of 1.2 mm.

[0063] (2) Input / output matching

[0064] Matching circuit topology as follows Figure 1 As shown. For broadband circuits, selecting a suitable chip impedance value is a core aspect of circuit design, requiring consideration of both output power and drain efficiency. Based on the chip's large-signal model, load-pull simulations were conducted, ultimately yielding the optimal load impedance for the 1.2mm die as (31.1 + j56.4) Ω. At the output of die T1, a series inductor L11 was used to match the 50Ω load impedance to the optimal value.

[0065] The input matching utilizes the more integrated GaAs IPD process. An RC circuit consisting of resistor R11 and capacitor C11 connected in parallel is first connected in series at the input of die T1 to enhance the low-frequency stability and improve the gain flatness of the power amplifier. Then, a first-order LC matching network consisting of inductor L12 (connected in series in the signal path) and capacitor C12 (connected in parallel to ground) is designed to match the input impedance to 50Ω. A series LC circuit consisting of inductor L13 (connected in series) and capacitor C13 (connected in parallel to ground) is connected in parallel at the RF input to further improve the stability of the power amplifier.

[0066] A three-dimensional structural diagram of the GaAs IPD technology is shown below. Figure 2As shown, its core structure is a three-layer metal wiring architecture: the bottom layer is a thick metal layer MET1, the middle layer is MET2, and the top layer is MET3. Adjacent metal layers are isolated and supported by highly dense SiN1 (0.15~1 μm), SiN2 (0.15 μm), and SiN3 (0.32 μm) dielectric layers, respectively. This multi-layer sandwich structure not only provides a foundation for the fabrication of high-quality factor MIM capacitors, but also provides vertical interconnect channels with extremely low parasitic inductance for high-frequency currents through through-hole structures (VIA1, VIA2, VIA3S, VIA4) filled by photolithography and electroplating between layers. Overall, it takes into account high-frequency performance, mechanical reliability, and process compatibility. Relying on this multi-layer three-dimensional architecture, complex network topologies can be realized in an extremely compact chip area, effectively breaking through the bottleneck of the self-resonant frequency limitation of traditional planar spiral inductors, and thus successfully constructing a broadband input matching circuit with flexible layout and extremely low insertion loss.

[0067] The industry commonly uses professional microwave circuit simulation software for power amplifier simulation design. DC analysis simulation is used to determine the static bias of the power transistors, load-pull and source-pull simulations are performed to obtain the optimal impedance, and then a matching circuit is designed. Finally, the harmonic balance method is used to optimize the overall circuit through simulation, thereby ensuring that the amplifier's performance indicators meet the requirements and guaranteeing excellent signal amplification capability. The results of the joint electromagnetic and circuit simulation are as follows: Figure 3 As shown, this power amplifier exhibits good overall performance across a wide bandwidth from 30 MHz to 1.5 GHz. The full-band input reflection coefficient S11 is better than -14.5 dB, achieving good input impedance matching, and the small-signal gain S21 is higher than 18.5 dB. The device's saturated output power exceeds 37 dBm (approximately 5 W), and according to the definition of drain efficiency PAE = (Pout - Pin) / Pdc, the device's PAE is greater than 55%. Compared with the 33 dBm saturated output power and 25% typical PAE of the UMS GaAs high-power amplifier CHA6652-98F, this fully demonstrates the significant advantages of this design in high power output and high energy efficiency conversion.

[0068] (3) Packaging design

[0069] The researchers integrated the input matching network (42, 43) fabricated using GaAs IPD technology with the bare die (44) and encapsulated it in a compact 4 mm × 4 mm QFN housing using a molding process. The specific layout is as follows: Figure 4As shown. To address the heat dissipation requirements brought about by high power density, nano-silver paste with a thermal conductivity of up to 150 W / (m·K) was selected as the thermal interface material in the chip bonding process, which significantly improved the heat dissipation capability of the package. At the same time, the bonding process used 25μm 99.99% high-purity gold wire (41) for gold wire ball bonding to achieve the interconnection between the chip pad and the lead frame. The chip pad is gold-plated, and gold wire is selected as the bonding wire. Compared with other metal wires, gold wire has good chemical stability and excellent electrical conductivity, thermal conductivity and mechanical properties. No intermetallic compounds will appear when the gold wire is connected to the gold-plated pad. The bonding point welding quality is stable and can complete the electrical connection well to ensure low-loss transmission of RF signals. Pins 2 and 3 are the RF input terminal and gate bias power supply terminal, and pins 11 and 10 are the RF output terminal and drain bias power supply terminal. The remaining non-functional pins are left floating in the internal design, thereby optimizing the package pin layout while meeting the RF performance requirements.

[0070] (4) Test method design

[0071] In practical RF front-end systems, bias voltages must be applied to the gate and drain to ensure that power devices operate at their predetermined quiescent operating points. The bias circuit design must not only provide a clean DC power supply path for the devices but also effectively suppress high-frequency interference and block unnecessary DC components. The entire bias link must ensure extremely high impedance (close to open circuit) to the main RF path while guaranteeing DC supply, just as a common-mode choke presents high impedance to high-frequency common-mode noise, thereby minimizing insertion loss within the operating frequency band. From the perspective of RF device specifications, the insertion loss of multi-frequency combiners is generally controlled within the 0.6-0.9 dB range, while the shunt attenuation of the high-frequency relay protection channel after the wave trap connection is required to be no more than 3 dB within the stopband, reflecting the low-loss requirements in the RF path.

[0072] Based on this, the bias circuit of this design is fabricated using microwave board material with stable dielectric constant and a thickness of 0.508 mm. Figure 5The diagram shows the topology of the test circuit. The core of the test circuit consists of a 50Ω characteristic impedance microstrip line, an RF choke inductor (L51), decoupling capacitors (C52, C53, C54), and a DC blocking capacitor (C51). The 50Ω characteristic impedance microstrip line is used to achieve low-loss transmission of RF signals. The RF choke inductor L51 is used to block RF signals and conduct DC bias. The decoupling capacitors C52, C53, and C54 are used to filter out high-frequency noise in the bias voltage. The DC blocking capacitor C51 is used to isolate DC and conduct RF signals. All components work together to build a low-loss, high-isolation bias channel within a specified frequency band. The specific connections are as follows: the RF input port RFin is connected to pins 2 / 3 of the QFN package via DC blocking capacitor C51; the gate bias voltage VG is connected to pins 2 / 3 of the QFN package via decoupling capacitors C52 and C53 (in parallel) and resistor R51 (in series); the RF output port RFout is connected to pins 10 / 11 of the QFN package via DC blocking capacitor C51; the drain bias voltage VD is connected to pins 10 / 11 of the QFN package via decoupling capacitors C52, C53, and C54 (in parallel) and inductor L52 (in series); pins 1, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, and 16 of the QFN package are grounded.

[0073] The actual test results are as follows Figure 6 As shown. This GaN-based device achieves 4W (36dBm) saturated output power and 15dB typical gain in an ultra-wide bandwidth of 30MHz~1500MHz, with a drain efficiency of over 35% across the entire frequency band and exceeding 69% in the low-frequency band.

[0074] It will be understood by those skilled in the art that the above descriptions are merely preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the invention should be included within the scope of protection of the invention. All technical features in this embodiment can be freely combined according to actual needs.

[0075] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT, characterized in that: include: QFN package; A GaN HEMT bare chip is disposed inside the QFN package and is used as an amplification core unit; A GaAs IPD chip is disposed inside the QFN package and integrates an input matching network, which is used to match the radio frequency input signal to the gate of the GaN HEMT bare chip. The GaN HEMT bare chip and the GaAs IPD chip are interconnected by gold wire bonding and are jointly encapsulated in the QFN package. The GaAs IPD chip integrates all the input-side matching networks of the broadband power amplifier, and the output-side matching network of the broadband power amplifier is located outside the QFN package.

2. The broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT according to claim 1, characterized in that: The input matching network integrated into the GaAs IPD chip within the QFN package includes: An RC stabilization network, consisting of a resistor R11 and a capacitor C11 connected in parallel and in series with the input terminal of the GaN HEMT bare chip, is used to enhance low-frequency stability. A first-order LC matching network, consisting of an inductor L12 connected in series with the signal path and a capacitor C12 connected in parallel with ground, is used to match the input impedance to 50Ω. The series LC stabilization network consists of a series inductor L13 and a parallel capacitor C13 connected to ground. It is connected to the RF input terminal to improve stability. An inductor L11 is connected in series at the output of the GaN HEMT bare chip to match the 50Ω impedance to the die's optimal load impedance.

3. The broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT according to claim 1, characterized in that: The GaAs IPD chip adopts a three-layer metal wiring architecture, including a bottom metal layer MET1, a middle metal layer MET2, and a top metal layer MET3. Adjacent metal layers are isolated by SiN dielectric layers, and vertical interconnection is achieved between the layers through filled via structures to form interconnection channels for MIM capacitors and low parasitic inductance.

4. The broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT according to claim 1, characterized in that: The GaN HEMT bare chip uses a 0.25μm process and silicon carbide (SiC) as a substrate, with a total gate width of 1.2mm; the QFN package has dimensions of 4mm × 4mm × 0.85mm.

5. The broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT according to claim 1, characterized in that, The broadband power amplifier has a power flatness of ≤±1dB in the 30MHz~1500MHz frequency band, a saturated output power of ≥36dBm at a rated power output of 4W, a typical power gain of >15dB, and a drain efficiency of >35%.

6. A method for fabricating a broadband power amplifier based on heterogeneous integration of GaAs IPD and GaN HEMT, characterized in that, Includes the following steps: Step 1: Provide a GaN HEMT bare chip, which is manufactured using a 0.25μm process and uses silicon carbide (SiC) as a substrate, with a total gate width of 1.2mm; Step 2, provide a GaAs IPD chip, on which an input matching network is integrated. The input matching network includes an RC stabilization network composed of a resistor R11 and a capacitor C11 connected in parallel, a first-order LC matching network composed of an inductor L12 and a capacitor C12, and a series LC stabilization network composed of an inductor L13 and a capacitor C13. Step 3: The GaN HEMT bare chip is attached to the base of the QFN lead frame using nano-silver paste; Step 4: Use gold wire to bond and interconnect the output terminal of the input matching network of the GaAs IPD chip with the gate of the GaN HEMT bare chip to achieve input matching connection of radio frequency signal; Step 5: The GaN HEMT bare chip and the GaAs IPD chip are jointly encapsulated in a QFN package to form a 4mm×4mm package. Step 6: Set an output-side matching network outside the QFN package. The output-side matching network is composed of external surface-mount devices.

7. The fabrication method of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT according to claim 6, characterized in that: In step 3, the thermal conductivity of the nano-silver paste is 150 W / (m·K); in step 4, the diameter of the gold wire is 25 μm, the purity is 99.99%, and the bonding is performed using a gold wire ball bonding process.

8. The fabrication method of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT according to claim 6, characterized in that: In step 2, the method for fabricating the GaAs IPD chip includes: SiN dielectric layers are sequentially deposited on a GaAs substrate to form a three-layer metal wiring architecture, including a bottom metal layer MET1, a middle metal layer MET2, and a top metal layer MET3. Adjacent metal layers are isolated and supported by SiN dielectric layers with thicknesses of 0.15~1μm, 0.15μm, and 0.32μm, respectively. Vertical interconnections between layers are achieved by filling the via structure with photolithography and electroplating, forming interconnect channels for MIM capacitors and low parasitic inductance.

9. The fabrication method of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT according to claim 6, characterized in that, It also includes the steps for building the bias circuit: Fabricate a 50Ω characteristic impedance microstrip line on a microwave substrate; A DC blocking capacitor C51 is set at the RF input terminal. The DC blocking capacitor C51 is connected in series between the RF input port RFin and the RF input pin of the QFN package. Set up a gate bias power supply link, and connect the gate bias voltage VG to the gate bias power supply pin of the QFN package through parallel decoupling capacitors C52 and C53 and series resistor R51. The drain bias power supply link is set up, and the drain bias voltage VD is connected to the drain bias power supply pin of the QFN package through parallel decoupling capacitors C52, C53, and C54 and series RF choke inductor L52.

10. The fabrication method of the broadband power amplifier based on the heterogeneous integration of GaAs IPD and GaN HEMT according to claim 6, characterized in that: In step 5, pins 2 and 3 of the QFN package are the RF input terminal and the gate bias power supply terminal, pins 10 and 11 are the RF output terminal and the drain bias power supply terminal, and the remaining non-functional pins are left floating in the internal design.

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