Millimeter wave power amplifier bias network design method and system

Abstract

The application discloses a millimeter wave power amplifier bias network design method and system, relates to the technical field of bias network design, obtains frequency domain input admittance of a target millimeter wave frequency band and first and second bias branches, adjusts admittance control parameters of the two bias branches according to the frequency domain input admittance, makes the two branches form input admittances with opposite signs of imaginary parts in the target millimeter wave frequency band and at least partially cancel each other out, and determines target bias network parameters according to real and / or imaginary part constraints of the synthesized input admittance. Since the two bias branches can reduce the synthesized input admittance by using opposite sign admittance components, the method can reduce the loading of the bias network on the target frequency band radio frequency signal. Meanwhile, the two bias branches form a parallel power supply path in the direct current state, so that the transmission demand of the bias current is considered while the target frequency band radio frequency isolation characteristic is improved.

Description

Technical Field

[0001] This invention relates to the field of bias network design technology, specifically to a method and system for designing bias networks for millimeter-wave power amplifiers. Background Technology

[0002] The bias network in a millimeter-wave power amplifier is used to provide DC operating conditions to the power transistors while reducing RF loading caused by RF signal leakage to the power supply.

[0003] Existing bias networks can utilize quarter-wavelength transmission lines to create high RF impedance, but their input impedance varies with operating frequency and transmission line size, limiting their ability to maintain low input admittance across a wide millimeter-wave band. Furthermore, the linewidth and length of a single bias path affect both RF impedance and DC equivalent resistance, creating a trade-off between the high RF impedance requirement and the low DC impedance power supply requirement within the target band. Therefore, improving the input admittance characteristics of the bias network within the target millimeter-wave band while maintaining bias current transmission capability is a problem that requires further investigation. Summary of the Invention

[0004] The purpose of this invention is to provide a design method and system for bias networks of millimeter-wave power amplifiers.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a millimeter-wave power amplifier bias network design method, the method comprising: The target millimeter-wave frequency band of the amplifier, as well as the parallel bias branches and their frequency domain input admittance, are obtained. The bias branches include a first bias branch and a second bias branch. The admittance control parameters of the first bias branch and the second bias branch are adjusted according to the frequency domain input admittance, so that the first bias branch and the second bias branch generate a composite input admittance in the target millimeter wave frequency band. The imaginary parts of the composite input admittance have opposite signs and at least partially cancel each other. The admittance control parameters include the transmission parameters of the microstrip transmission line in the first bias branch and the tuning parameters of the tuning capacitor. The admittance control parameters that enable the synthesized input admittance to meet the preset constraints are determined as the target bias network parameters and output. The preset constraints are the admittance upper limit constraints set on at least one of the real and imaginary parts of the synthesized input admittance.

[0006] A further preferred embodiment involves adjusting the admittance control parameters of the first and second bias branches based on the frequency domain input admittance, including: The reference admittance is formed using the first microstrip transmission line of the first bias branch; The tuning admittance is formed by connecting the second microstrip transmission line, the third microstrip transmission line, and the tuning capacitor grounded at the intermediate node of the second bias branch in series. Candidate admittance control parameters are determined based on the difference in the imaginary parts of the baseline admittance and the tuned admittance.

[0007] A further preferred embodiment involves determining candidate admittance control parameters based on the difference between the imaginary parts of the reference admittance and the tuned admittance, including: Adjust the third microstrip transmission line to provide inductive compensation for the tuning capacitor and change the resonant position of the second bias branch; Adjust the second microstrip transmission line to transform the combined admittance of the third microstrip transmission line and the tuning capacitor to the branch input and adjust the phase; Adjust the capacitance of the tuning capacitor so that the imaginary part of the tuning admittance converges to the imaginary part of the reference admittance.

[0008] More preferably, the imaginary parts of the synthesized input admittance have opposite signs and at least partially cancel each other out, including: Within the target millimeter-wave frequency band, the superposition result of the imaginary part of the input admittance of the first bias branch and the imaginary part of the input admittance of the second bias branch is determined. When the absolute value of the superimposed imaginary part is less than the absolute value of the imaginary part of the input admittance of at least one bias branch, the corresponding candidate admittance control parameter is determined as the cancellation parameter.

[0009] Further preferably, the preset constraints include a preset upper limit for the real part and a preset upper limit for the imaginary part, which respectively determine the real and imaginary parts of the synthesized input admittance at each frequency point within the target millimeter-wave frequency band. The cancellation parameters whose absolute value of the real part is not higher than the preset upper limit for the real part and whose absolute value of the imaginary part is not higher than the preset upper limit for the imaginary part are determined as the target bias network parameters.

[0010] More preferably, the transmission parameters include the characteristic impedance and electrical length of the microstrip transmission line, and the characteristic impedance and electrical length are changed by adjusting the line width and line length of the corresponding microstrip transmission line.

[0011] In a further preferred embodiment, when determining the synthesized input admittance, the quality factor of the tuning capacitor is also obtained, the equivalent series resistance of the tuning capacitor is determined based on the quality factor, and the active power loss corresponding to the equivalent series resistance is included in the real part of the input admittance of the second bias branch.

[0012] In a further preferred embodiment, the metal thickness of the microstrip transmission line is obtained, and the frequency domain input admittance of the first bias branch and the second bias branch is corrected based on the conductor resistance per unit length, effective characteristic impedance and electrical length change corresponding to the metal thickness. The preset constraint conditions are then verified based on the corrected frequency domain input admittance.

[0013] More preferably, the first bias branch and the second bias branch are connected in parallel between the RF / DC common bias node and the power supply decoupling node of the power transistor. In the DC state, the tuning capacitor is open, the first bias branch and the second bias branch form DC conduction paths respectively, and the DC equivalent resistance of the two DC conduction paths is in parallel.

[0014] On the other hand, this application also provides a millimeter-wave power amplifier bias network design system, characterized in that it includes: The admittance acquisition module is used to acquire the target millimeter-wave frequency band of the amplifier, as well as the first bias branch and the second bias branch connected in parallel and their frequency domain input admittance; The admittance control module is used to adjust the admittance control parameters of the first bias branch and the second bias branch according to the frequency domain input admittance, so that the imaginary parts of the input admittance of the first bias branch and the second bias branch in the target millimeter wave frequency band are opposite in sign and at least partially canceled, and to generate the composite input admittance. The parameter output module is used to determine the admittance control parameters that make the synthesized input admittance meet the preset constraints as the target bias network parameters and output them.

[0015] The technical effects and advantages provided by the present invention in the above technical solution are as follows: Compared to bias networks that utilize a single bias path to form high-impedance RF signals, this application first obtains the frequency domain input admittance of the target millimeter-wave frequency band and the first and second bias branches. Then, it adjusts the admittance control parameters of the two bias branches based on the frequency domain input admittance, causing the two branches to form input admittances with opposite imaginary signs in the target millimeter-wave frequency band and at least partially cancel each other out. Finally, it determines the target bias network parameters based on the constraints of the real and / or imaginary parts of the synthesized input admittance. Since the two bias branches can reduce the synthesized input admittance using admittance components with opposite signs, the load of the bias network on the target frequency band RF signal can be reduced. Simultaneously, the two bias branches form a parallel power supply path under DC conditions, thereby improving the RF isolation characteristics of the target frequency band while also meeting the transmission requirements of the bias current. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0017] Figure 1 This is a flowchart of the design method in this invention.

[0018] Figure 2 This is a schematic diagram of the simulation circuit structure of the dual-path admittance cancel bias network in this invention.

[0019] Figure 3 The above are simulation curves of the first bias branch, the second bias branch, and the imaginary part of the synthesized input admittance at 32GHz to 38GHz in this invention.

[0020] Figure 4The above are simulation curves of the real part of the first bias branch, the second bias branch, and the synthesized input admittance at 32GHz to 38GHz in this invention.

[0021] Figure 5 This is a schematic diagram of the RF signal transmission verification circuit structure of the dual-path admittance de-biasing network in this invention.

[0022] Figure 6 The above is a simulation curve of the RF transmission and echo scattering parameters of the bias network in the 32GHz to 38GHz range in this invention.

[0023] Figure 7 This is a schematic diagram of the overall circuit structure of the dual-path admittance de-biasing network in this invention after it is connected to a millimeter-wave power amplifier.

[0024] Figure 8 This is a simulation curve showing the power-added efficiency as a function of RF input power when the admittance de-biasing network is not used in this invention.

[0025] Figure 9 This is a simulation curve showing the power-added efficiency as a function of RF input power when using an admittance-canceling bias network in this invention.

[0026] Figure 10 The figure shows the load traction simulation results when the admittance phase-canceling bias network is not used in this invention.

[0027] Figure 11 The figure shows the load traction simulation results when using an admittance phase-dissipation bias network in this invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on the present invention. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0030] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of the invention described herein can be implemented in an order other than that illustrated or described herein.

[0031] In this embodiment of the invention, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0032] Unless otherwise defined, all technical and scientific terms used in the embodiments of this invention have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this invention is for descriptive purposes only and is not intended to limit the invention.

[0033] Before further describing the embodiments of the present invention, some terms and parameters involved in the embodiments of the present invention are explained as follows.

[0034] 1) Target millimeter-wave band: This refers to the continuous operating frequency range within which the power amplifier needs to maintain predetermined RF isolation characteristics. The target millimeter-wave band can be determined by the power amplifier's operating bandwidth, transistor type, matching network bandwidth, and system spectrum planning. In a specific example, the target millimeter-wave band is 32GHz to 38GHz, with a center frequency of 35GHz. This band is only used to illustrate one feasible parameter configuration and does not limit the application of other millimeter-wave bands.

[0035] 2) Bias Branch: This refers to the transmission path connected between the RF / DC common bias node and the power supply decoupling node of the power transistor, capable of transmitting DC bias to the power transistor and exhibiting frequency-dependent input admittance at RF frequencies. In this embodiment of the invention, a first bias branch and a second bias branch are connected in parallel. The first bias branch includes at least a first microstrip transmission line; the second bias branch includes a second microstrip transmission line and a third microstrip transmission line connected in series, with a grounded tuning capacitor connected at the intermediate node between the two microstrip transmission lines.

[0036] 3) Frequency domain input admittance: This refers to the change in complex admittance as a function of frequency, observed from the RF / DC common bias node of the power transistor towards the corresponding bias branch. For the first bias branch, the frequency domain input admittance is denoted as Y. A (f); For the second bias branch, the frequency domain input admittance is denoted as Y. B (f). The frequency domain input admittance includes real and imaginary components, where the real component is used to characterize the active power loss or equivalent conductance component in the branch, and the imaginary component is used to characterize the inductive or capacitive susceptance component of the branch at the corresponding frequency.

[0037] 4) Admittance control parameters: These refer to structural or device parameters that can alter the frequency domain input admittance of the first and second bias branches. These include the transmission parameters of the microstrip transmission line and the tuning parameters of the tuning capacitor. The transmission parameters of the microstrip transmission line include characteristic impedance and electrical length, which can be adjusted by changing the linewidth W and line length L. The tuning parameters of the tuning capacitor include at least the capacitance C. When considering non-ideal factors in actual devices, the quality factor of the tuning capacitor and the metal thickness of the microstrip transmission line can also be recorded simultaneously for verifying the frequency domain input admittance.

[0038] 5) Imaginary parts with opposite signs and at least partial cancellation: Here, opposite signs mean that the imaginary parts of the first bias branch input admittance and the second bias branch input admittance, which constitute the synthesized input admittance, are on opposite sides of zero. One branch is primarily inductive within the target frequency band, while the other is primarily capacitive. At least partial cancellation means that the residual imaginary part obtained after adding the input admittances of the two branches is less than the absolute value of the imaginary part of at least one branch before addition. By further adjusting the amplitude and phase of the two branches, the residual imaginary part can be kept small at multiple frequency points within the target millimeter-wave frequency band.

[0039] It should be noted that the synthesized input admittance corresponds to only one complex value at any given frequency, and its imaginary part itself does not have a state of "two opposite signs". In this invention, "imaginary part with opposite signs" refers to the imaginary parts of the first bias branch input admittance and the second bias branch input admittance having opposite signs; their addition forms the imaginary residual of the synthesized input admittance. The following examples use e... jωt The phasor convention is such that the imaginary part of the inductive input admittance is negative and the imaginary part of the capacitive input admittance is positive. If the simulation tool adopts the opposite phasor convention, the signs of the imaginary parts of the two branches can be reversed at the same time, but the opposite signs and cancellation relationship of the imaginary parts of the two branches remain unchanged.

[0040] To further clarify the cancellation determination object, at frequency f, the input admittance of the first bias branch is written as Y. A (f)=G A (f)+jB A (f) Write the input admittance of the second bias branch as Y B (f)=G B (f)+jB B (f) then the synthesized input admittance Y bias (f)=Y A (f)+Y B (f)=[G A (f)+G B (f)]+j[B A (f)+B B (f)]. Among them, B A (f) and B B(f) represents the imaginary part of the input admittance of each of the two branches. When B A (f)·B B When (f) < 0, it is determined that the imaginary parts of the input admittances of the two branches have opposite signs; based on this, if |B A (f)+B B (f)| <max{|B A (f)|,|B B If (f)|}, then it is determined that the imaginary parts of the two branches have at least partially canceled out. Therefore, "opposite signs" is only used to describe the imaginary parts of the input admittances of the two branches; B A (f)+B B (f) The imaginary part residual of the synthetic input admittance is used only for constraint judgment.

[0041] 6) Preset Constraints: These are the admittance limits used to determine whether a set of admittance control parameters can serve as parameters for the target bias network. Preset constraints can set upper limits for the real part, imaginary part, or both of the synthesized input admittance. In a specific example, the upper limits for the absolute values ​​of the real and imaginary parts of the synthesized input admittance can be set to 0.1 ms each, and this can be verified at multiple frequency points within the 32 GHz to 38 GHz band. If the design task only imposes a constraint on one component, only the corresponding admittance upper limit can be set.

[0042] In some embodiments, a power amplifier bias network model can be established using an RF circuit simulation environment. The model includes at least a power transistor bias node, two bias branches, a power supply decoupling node, a ground terminal, and a port for extracting the frequency domain input admittance. The frequency domain input admittance can be directly output from the simulation environment or calculated from the small-signal network parameters of the corresponding port. To avoid comparison bias caused by different reference planes, the input admittances of the first and second bias branches use the same RF / DC shared bias node as the reference plane and are calculated using the same frequency sampling points.

[0043] When extracting the admittance of two branches, the same small-signal voltage can be applied to the RF / DC shared bias node, and the branch currents flowing into the first and second bias branches can be read separately. Under the same reference ground, the same reference plane, and the same frequency point, the frequency domain input admittance of the corresponding branch is determined by the ratio of the branch current to the voltage of the shared node. Since the two bias branches are connected between the same two nodes, the total current of the shared node is equal to the sum of the currents of the two branches. Therefore, the input admittance of the entire bias network is equal to the sum of the input admittances of the two branches. For the co-simulation of the complete layout including corners, T-nodes, vias, and interconnect couplings, the total input admittance directly obtained from the ports of the complete layout is used as the final constraint verification result. The admittances of the two branches are mainly used to determine the tuning direction and cancellation relationship, thereby avoiding the direct substitution of the simple superposition result of the ideal transmission line model for the complete layout result.

[0044] To illustrate the design rationale behind the dual-branch regulation method, several bias structures can be established as comparisons when building the simulation model. The first type of structure creates an RF short circuit at the power supply end through a bypass capacitor, and then uses a quarter-wavelength microstrip transmission line to transform this short circuit into high impedance at the power amplifier's RF node. This structure can generate high impedance near the center frequency, but the impedance transformation changes when the frequency deviates from the quarter-wavelength condition. Under millimeter-wave conditions, the transmission line length, corners, T-junctions, and via parasitic effects also influence the location of the high-impedance point.

[0045] The second type of structure can use radial stubs, butterfly stubs, or fan-shaped stubs to form a good RF short circuit over a wider frequency range, and then use a quarter-wavelength transmission line or impedance transformation line to transform the short-circuit state to the high-impedance state of the power transistor bias node. This type of structure can extend the RF isolation bandwidth, but it may occupy a larger area in the layout, and the DC bias still mainly propagates along a single branch.

[0046] The third type of structure can employ a single-path stepped impedance bias line, using a combination of high and low characteristic impedance segments to achieve a higher input impedance in the bias branch near the target frequency. However, because the line length and width in a single path simultaneously affect both RF impedance and DC resistance, the degree of adjustment is limited. For example, reducing the line width or increasing the line length can improve the RF impedance at certain frequencies, but it will simultaneously increase the DC resistance; increasing the line width can enhance the DC current carrying capacity, but it may increase the RF load. Therefore, a single-path structure is prone to forming a high-resistance point at a certain frequency, and it is difficult to form a relatively flat low-admittance state across a continuous target frequency band.

[0047] Based on the above parameter relationships, this embodiment of the invention does not use the formation of high impedance independently through a single path as the sole adjustment target. Instead, it utilizes two parallel bias branches to form frequency domain input admittances with different imaginary parts of sign, and then reduces the combined input admittance through the superposition relationship of admittances between the two branches. In this way, the first bias branch and the second bias branch can undertake different RF adjustment functions, while jointly forming a bias current transmission path under DC conditions.

[0048] Example 1 This embodiment provides a millimeter-wave power amplifier bias network design method, which can be executed by an electronic device running an RF circuit simulation program. The electronic device can be a workstation, server, or computing device with electromagnetic simulation and parameter processing capabilities. The method includes steps S101 to S103.

[0049] like Figure 1As shown, this embodiment first obtains the target millimeter-wave frequency band, two parallel bias branches and their frequency domain input admittance, then adjusts the admittance control parameters of the two bias branches according to the frequency domain input admittance to form a synthetic input admittance. When the synthetic input admittance meets the preset constraint conditions, the target bias network parameters are determined and output; if the preset constraint conditions are not yet met, the admittance control parameters are adjusted and the frequency domain verification is performed again.

[0050] In step S101, the target millimeter-wave frequency band of the amplifier, the parallel bias branches, and the frequency domain input admittance of each bias branch are obtained.

[0051] Specifically, the target millimeter-wave frequency band is first determined based on the operating frequency of the power amplifier to be designed. A first bias branch and a second bias branch are then established between the RF / DC common bias node and the power supply decoupling node of the power transistor. The two bias branches have the same start and end points, thus forming a parallel relationship in the circuit topology. The first bias branch includes a first microstrip transmission line; the second bias branch includes a second microstrip transmission line and a third microstrip transmission line connected in series. An intermediate node is set between the second and third microstrip transmission lines, and one end of a tuning capacitor is connected to this intermediate node, while the other end is grounded.

[0052] In a specific simulation model, the first microstrip transmission line can correspond to the transmission line labeled TL12, the second microstrip transmission line can correspond to TL10, the third microstrip transmission line can correspond to TL11, and the tuning capacitor can correspond to C5. The power supply decoupling node can also be grounded through a bypass capacitor C4. C4 is used to make the power supply decoupling node have a lower RF impedance in the target millimeter-wave frequency band, so as to bypass the remaining RF energy leaking to the bias terminal to ground and reduce the possibility of power supply noise coupling to the power amplifier RF node.

[0053] like Figure 2 As shown, in the bias network simulation circuit, the node to the left of VAC is used to apply a small RF signal excitation to the bias network; the first bias branch Y A The reference path is formed by TL12, and the second bias branch Y B The tuning path is formed by TL10, TL11, and the tuning capacitor C5 grounded at their intermediate node. Two branches are connected in parallel between the left common node and the right power supply decoupling node. The right node is grounded through a bypass capacitor C4. Y can be extracted from this connection. A and Y B And form the synthetic input admittance Y under the same reference plane. bias .

[0054] As a set of directly reproducible parameter examples, the first microstrip transmission line TL12 has a linewidth W of 5μm and a line length L of 100μm; the second microstrip transmission line TL10 has a linewidth W of 6μm and a line length L of 120μm; and the third microstrip transmission line TL11 has a linewidth W of 10μm and a line length L of 110μm. In the capacitor model used, the tuning capacitor C5 has a model length of 52.631μm, a model width of 50μm, and a capacitance of 1pF; the bypass capacitor C4 has a model length of 78.947μm, a model width of 50μm, and a capacitance of 1.5pF. During simulation, a frequency scan can be performed first in the range of 20GHz to 45GHz with a step size of 1GHz, and then the admittance state in the target millimeter-wave band of 32GHz to 38GHz can be screened and verified. The above parameters correspond to a specific realization of a low admittance state. Under other process conditions, the linewidth, line length, and capacitance can be re-determined according to the same admittance cancellation relationship.

[0055] During frequency scanning within the target frequency band, the first bias branch and the second bias branch are observed from the common bias node, and the frequency domain input admittance Y of the first bias branch is extracted. A (f) Frequency domain input admittance Y of the second bias branch B (f). For each sampling frequency f, record Y respectively. A (f) and Y B (f) Real and imaginary parts. The frequency sampling interval can be set according to the target bandwidth and simulation accuracy; when it is necessary to evaluate the admittance change at the edge of the frequency band, the sampling density can be increased near the start of the frequency band, the center frequency, and the end of the frequency band.

[0056] Y bias (f)=Y A (f)+Y B (f) Among them, Y bias (f) represents the composite input admittance observed from the RF / DC common bias node of the power transistor toward the entire parallel bias network, Y. A (f) and Y B (f) represents the input admittance of the first bias branch and the second bias branch at frequency f, respectively.

[0057] In the schematic simulation circuit, the RF excitation can be set on one side of the power transistor bias node, and the transfer of RF energy to the power supply decoupling node and ground branch can be observed along the bias network direction. This allows us to obtain the frequency domain input admittance of the two branches as seen from the common bias node, and also to observe the leakage of the RF signal along the bias direction in subsequent scattering parameter verification.

[0058] In step S102, the admittance control parameters of the first bias branch and the second bias branch are adjusted according to the frequency domain input admittance, so that the two bias branches generate cancelable imaginary admittance components in the target millimeter wave frequency band and form a composite input admittance.

[0059] Specifically, the linewidth and length of the first microstrip transmission line can be adjusted first to make the first bias branch form a reference admittance in the target millimeter-wave frequency band. In the 32GHz to 38GHz example of this embodiment, the first bias branch can be adjusted to be mainly inductive, with its imaginary part of input admittance being negative in the target frequency band. Then, the second microstrip transmission line, the third microstrip transmission line, and the tuning capacitor of the second bias branch are adjusted to make the second bias branch mainly capacitive in the target frequency band, with its imaginary part of input admittance being positive, and the amplitudes of the imaginary parts of the two branches gradually approach each other.

[0060] The linewidth W and line length L of the first microstrip transmission line together determine the characteristic impedance and electrical length of the corresponding branch. Therefore, the admittance amplitude and phase of the first bias branch can be adjusted by changing W and L. For the second bias branch, the third microstrip transmission line is located near the tuning capacitor, which can provide inductive compensation for the capacitive susceptance generated by the tuning capacitor and change the branch resonance position. The second microstrip transmission line is located on the input side of the branch and is used to transform the admittance formed by the combination of the third microstrip transmission line and the tuning capacitor to the common bias node and change the admittance phase of the second bias branch at this reference plane. The tuning capacitor adjusts the capacitive susceptance by changing its capacitance, thereby affecting the depth and bandwidth of the cancellation between the two branches.

[0061] In some embodiments, parameter adjustments can be performed in the order of "reference first, resonance second, phase third, and finally cancellation depth." First, a smoother inductive reference admittance is formed in the first bias branch. Then, the third microstrip transmission line is adjusted so that the resonant position of the second bias branch falls within or near the center of the target frequency band. Subsequently, the second microstrip transmission line is adjusted so that the imaginary sign and phase relationship at the input of the second bias branch meets the requirement of cancellation with that of the first bias branch. Finally, the tuning capacitor is adjusted so that the imaginary amplitude of the second bias branch approaches that of the first bias branch. After each adjustment, the frequency domain input admittance of both branches is recalculated to form the data used for the next adjustment.

[0062] For any frequency, the synthesized input admittance is obtained by superimposing the input admittances of the first bias branch and the second bias branch. When the imaginary part of the first bias branch is negative and the imaginary part of the second bias branch is positive, their addition reduces the absolute value of the imaginary part of the synthesized input admittance. If the absolute value of the superimposed imaginary part is less than the absolute value of the imaginary part of at least one branch before superposition, it can be considered that at least partial cancellation has occurred at that frequency; if the amplitudes of the imaginary parts of the two branches are further close, the imaginary part of the synthesized input admittance can further approach zero.

[0063] During parameter iteration, for each sampling frequency point within the target millimeter-wave band, the following steps can be performed sequentially: branch imaginary part sign determination, imaginary part residual calculation, and synthetic admittance constraint determination: first determine B. A (f) and B B (f) Whether it is located on both sides of zero; calculate B after satisfying the opposite sign relationship. bias (f)=B A (f)+B B (f); then |B bias (f)| and |G A (f)+G B (f) Compare with the preset upper limits of the imaginary part and the real part. If any sampling frequency point that needs to satisfy the constraint does not meet the corresponding upper limit, then the frequency point and the corresponding residual are retained as the feedback basis for the next round of line width, line length or capacitance adjustment, and the current parameter combination is not determined as the target bias network parameter.

[0064] In step S103, the admittance control parameters that enable the synthesized input admittance to meet the preset constraints are determined as the target bias network parameters and output.

[0065] Specifically, for each set of candidate admittance control parameters obtained in step S102, the synthesized input admittance at each sampling frequency point within the target millimeter-wave band is calculated, and the absolute values ​​of the real and imaginary parts of the synthesized input admittance are compared with the corresponding admittance upper limits. If the design task constrains both the real and imaginary parts, both upper limits must be satisfied simultaneously; if the design task only requires controlling one of them, only the corresponding component needs to be screened. One or more sets of admittance control parameters obtained through screening can be output as target bias network parameters to the layout design program, RF circuit simulation program, or parameter logging file.

[0066] In a 32GHz–38GHz example, both the upper limit of the real part and the upper limit of the imaginary part can be set to 0.1ms. For parameter combinations that meet the conditions, the imaginary signs of the input admittances of the first and second bias branches within the target frequency band are opposite, and the residual of the imaginary part after their superposition remains within the set range, while the sum of the real parts of the two branches also remains small. As a result, the synthesized input admittance observed from the bias node of the power transistor toward the bias network decreases, and the corresponding input impedance increases, thereby reducing the loading of the bias branch on the millimeter-wave RF signal.

[0067] |Im(Y A )+Im(Y B )|<0.1ms;|Re(Y A )+Re(Y B )|<0.1mS Z bias (f)=1 / Y bias (f) When Ybias When the magnitude of (f) decreases, the bias network input impedance Z is adjusted according to the reciprocal relationship between input impedance and input admittance. bias (f) The corresponding increase. Thus, the design goal of "blocking high frequencies" can be transformed into a computable constraint on the real and imaginary parts of the synthesized input admittance within the target frequency band.

[0068] This embodiment uses the frequency domain input admittance of two bias branches as a common parameter adjustment basis, enabling the first bias branch to form a reference admittance and the second bias branch to form an adjustable admittance. The target parameters are determined by utilizing the superposition relationship of their imaginary parts with opposite signs. Compared to adjusting the line length or linewidth only around the high-impedance point of a single branch, the two branches provide additional degrees of freedom for phase and amplitude adjustment. At the same time, the target parameters are screened by the constraints of the synthesized input admittance across the entire target frequency band, enabling a direct correspondence between the determination process of the bias network parameters and the RF isolation requirements of the target frequency band.

[0069] Example 2 This embodiment further explains the process of determining the candidate admittance tuning parameters. The target millimeter-wave frequency band is still taken as 32GHz–38GHz, with a center frequency of 35GHz. The first bias branch serves as the reference path A, and the second bias branch serves as the tuning path B. During the design process, the input admittance of both paths is read at the same frequency sampling point to ensure that the reference plane and frequency position are consistent during superposition.

[0070] First, a parameter scan is performed on the first microstrip transmission line. Multiple candidate linewidths can be selected within a linewidth range that meets the layout routing and DC current carrying requirements, and multiple candidate linelengths are set for each candidate linewidth. For each set of linewidths and linelengths, the frequency domain input admittance of the first bias branch within the 32GHz–38GHz range is calculated. If the branch is inductive at most target frequencies (i.e., the imaginary part is negative and remains continuous with frequency), the corresponding parameters are retained as candidate parameters for the first stage. The resulting Y... A (f) serves as the reference for subsequent tuning path B.

[0071] Secondly, the third microstrip transmission line is adjusted in the second bias branch. The third microstrip transmission line is adjacent to the tuning capacitor, and changes in its electrical length alter the equivalent susceptance of the tuning capacitor from the midpoint towards the branch input. By changing the length and width of the third microstrip transmission line, its inductive compensation to the tuning capacitor can be adjusted, causing the resonant position of the second bias branch to shift along the frequency axis. When the resonant position is too low, the electrical length can be adjusted according to the direction of admittance change obtained from simulation; when the resonant position is too high, it is adjusted in the opposite direction, and a frequency scan is re-executed after each adjustment.

[0072] Next, the second microstrip transmission line is adjusted. Located between the common bias node and the third microstrip transmission line, the second microstrip transmission line performs transmission transformation on the combined admittance formed by the third microstrip transmission line and the tuning capacitor. Changing the characteristic impedance and electrical length of the second microstrip transmission line alters the phase and amplitude of this combined admittance mapped to the branch input. Therefore, the imaginary part of the input admittance of path B can be adjusted to have the opposite sign to that of path A, and the trend of the imaginary part of path B in the target frequency band can be made cancelably related to that of path A.

[0073] Next, adjust the capacitance of the tuning capacitor. The tuning capacitor provides capacitive admittance; as the capacitance changes, the capacitive component of path B and the destructive position both change. The imaginary residuals of paths A and B can be used as feedback to refine the capacitance search step by step. For example, a larger capacitance step size can be used to determine the interval where opposite-sign imaginary parts can be formed, and then the step size can be reduced within this interval to decrease the imaginary residuals at the center frequency and band edges. In this way, it is possible to avoid adjusting only for a single center frequency while ignoring band edge states.

[0074] In this embodiment, candidate parameters are not determined based on a single frequency point, but rather multiple sampling points within the target frequency band are evaluated simultaneously. For each set of parameters, the residual after adding the imaginary parts of the two branches at each frequency point can be calculated, and the maximum value of the residual, the residuals at both ends of the frequency band, and the residual near the center frequency can be checked. When multiple candidate parameters all meet the upper limit of admittance, parameters with relatively smooth residual changes within the frequency band can be retained first; alternatively, further screening can be conducted among candidate parameters that meet admittance constraints based on layout area, minimum microstrip line width, or DC resistance requirements.

[0075] Under a specific parameter state, the first bias branch Y A It exhibits inductive behavior within the 32GHz to 38GHz range, satisfying Im(Y) A <0; Second bias branch Y B It exhibits capacitive behavior within the corresponding frequency band, satisfying Im(Y). B The imaginary part of the synthesized input admittance is close to zero after the two paths are superimposed. For the real part, if the losses of both the first and second bias branches are small, the sum of their real parts can also remain at a low level. In this case, the synthesized input admittance forms a low admittance plateau within the continuous target frequency band, rather than forming an isolated high-impedance state only at a single frequency point.

[0076] like Figure 3 As shown, within the target millimeter-wave frequency band of 32GHz to 38GHz, the first bias branch Y A The imaginary part of the input admittance is mainly negative, and the second bias branch Y BThe imaginary part of the input admittance is mainly positive. The composite imaginary part formed by adding the imaginary parts of the two branches remains at a low level, which is used to characterize the cancellation state of the imaginary admittances with opposite signs.

[0077] like Figure 4 As shown, within the same frequency scanning range, the first bias branch Y A Second bias branch Y B The real part of the combined input admittance remains at a low level, which can be combined with Figure 3 The imaginary residuals are used to determine whether the current parameter combination meets the preset admittance constraint.

[0078] When simulating using the above parameters TL12, TL10, TL11, C5 and C4, at 32GHz, the imaginary part of the input admittance of the first bias branch is about -0.082mS, the imaginary part of the input admittance of the second bias branch is about 0.020mS, and the combined imaginary part after the two are superimposed is about -0.062mS. Figure 4 The real part of the input admittance of the first bias branch is approximately 0.004 ms, the real part of the input admittance of the second bias branch is approximately 0.014 ms, and the combined real part is approximately 0.019 ms. At 38 GHz, the imaginary parts of the two branch input admittances are approximately -0.069 ms and 0.145 ms, respectively, and the combined imaginary part is approximately 0.076 ms; the real parts of the two branch input admittances are approximately 0.003 ms and 0.023 ms, respectively, and the combined real part is approximately 0.026 ms. Since the admittance values ​​in the attached figures are displayed with finite decimal places, there may be rounding differences between the direct summation of the branch admittance values ​​and the combined admittance value. Therefore, it can be verified at both ends of the target frequency band that the absolute values ​​of the real and imaginary parts of the combined input admittance are less than 0.1 ms, and the formation of a continuous low admittance interval can be determined by combining the scanning results within the frequency band.

[0079] To clearly describe the cancellation judgment, the real part of the input admittance of the first bias branch can be denoted as G. A (f) The imaginary part is denoted as B. A (f) Let G be the real part of the input admittance of the second bias branch. B (f) The imaginary part is denoted as B. B (f). For the target frequency f, if B A (f) and B B (f) If the signs are opposite, the residual after the imaginary parts are canceled out is B. A (f)+B B (f). In the parameter selection of this embodiment, the absolute value of the residual can be required to be less than 0.1ms; at the same time, G can be required to be less than 0.1ms. A (f)+G BThe absolute value of (f) is less than 0.1 ms. The above values ​​are used to illustrate a specific screening criterion, and the actual design can be redefined according to the operating frequency of the power amplifier, the RF loading allowed by the bias node, and the device process.

[0080] Taking the existing simulation data in this embodiment as an example, at 32GHz, B A ≈-0.082mS, B B ≈0.020mS, the product of the two is less than 0, and |B A +B B |≈0.062ms, less than the larger of the absolute values ​​of the imaginary parts of the two branches, 0.082ms; at 38GHz, B A ≈-0.069mS, B B ≈0.145mS, both have opposite signs, and |B A +B B |≈0.076ms, which is less than the larger one of 0.145ms. Therefore, the cancellation state of the two sampling points at the edge of the frequency band can be determined according to the order of "the imaginary parts of the two branches have different signs - the composite imaginary part residual is controlled"; the same judgment method is used for other sampling points inside the frequency band.

[0081] When a set of parameters meets the constraint at the center frequency of 35GHz, but exceeds the admittance limit near 32GHz or 38GHz, this set of parameters is not directly used as the final output. Instead, the resonant position, phase, or capacitance of the second bias branch is adjusted. If the low-end residual is large, the resonant position can be moved by changing the electrical length of the third microstrip transmission line, and the phase can be corrected in conjunction with the second microstrip transmission line. If the residual sign is the same and the amplitude is large throughout the frequency band, the tuning capacitor can be adjusted to change the capacitive amplitude of path B as a whole. In this way, each adjustment action is triggered by the frequency domain input admittance result of the previous round and verified in the next round of frequency scanning.

[0082] In some embodiments, the linewidth or length of the first bias branch can be readjusted instead of being permanently fixed. If path B has reached the achievable adjustment boundary but still cannot form a suitable destructive relationship with path A across the entire target frequency band, the process returns to the first bias branch parameter scanning phase, changing the amplitude or frequency slope of the reference admittance, and then re-executing the resonant position, phase, and capacitance adjustment of path B. This results in a two-branch cooperative iteration, rather than concentrating all RF requirements on a single transmission line.

[0083] Once the parameter combination that satisfies the constraints is obtained, the linewidth, line length, corresponding characteristic impedance, and electrical length of the first, second, and third microstrip transmission lines, as well as the capacitance of the tuning capacitor, can be output. If the design system is connected to a layout tool, the linewidth, line length, and capacitance can also be written as layout device parameters into the layout template; if the design system is connected to an electromagnetic simulation tool, the target parameters can be written into the parameter file of the next round of electromagnetic simulation to further consider layout corners, T-junctions, vias, and interconnect parasitics.

[0084] This embodiment utilizes a third microstrip transmission line to adjust the resonant position, a second microstrip transmission line to perform combined admittance transformation and phase adjustment, and a tuning capacitor to control the capacitive amplitude and cancellation depth. This allows different devices within the second bias branch to perform interconnected tuning functions. Then, using the reference admittance of the first bias branch as a comparison, the difference in the imaginary part amplitude between the two branches is gradually reduced. This process establishes an interpretable correspondence between the adjustment of line length, linewidth, and capacitance and the admittance amplitude, phase, and resonant position, facilitating repeated calculations and parameter convergence within the target millimeter-wave frequency band.

[0085] Example 3 This embodiment further considers the non-ideal factors of actual devices and DC power supply conditions based on the above dual-branch admittance cancellation design, so as to avoid obtaining the target parameters only under the ideal lossless model.

[0086] First, consider the quality factor of the tuning capacitor. A real capacitor has an equivalent series resistance, which varies with angular frequency ω, capacitance C, and quality factor Q. c When determined, the active power loss can be characterized by the equivalent series resistance. As the quality factor decreases, the equivalent series resistance increases, and the active power loss in the second bias branch increases accordingly, potentially increasing the real part of its input admittance. Since the real part of the synthesized input admittance is composed of the real components of the two branches, even if the imaginary parts of the two branches can cancel each other out, excessive capacitance loss may still cause the real part of the synthesized input admittance to exceed the preset upper limit of the real part.

[0087] R c ≈1 / (ω·C·Q c ) Among them, R c The value represents the equivalent series resistance of the tuning capacitor, ω represents the angular frequency, C represents the capacitance of the tuning capacitor, and Q represents the capacitance of the tuning capacitor. c This represents the quality factor of the tuning capacitor at the corresponding frequency. This relationship is used to illustrate the trend of increasing equivalent series loss as the quality factor decreases, and is reflected in the simulation model as a change in the real part of the input admittance of the second bias branch.

[0088] During parameter verification, several quality factor states can be set based on the nominal quality factor of the candidate tuning capacitors, and the frequency domain input admittance of the second bias branch can be recalculated for each state. If the real part of the synthesized input admittance exceeds the upper limit of the example of 0.1 ms in the target frequency band after the quality factor decreases, then this parameter combination is no longer considered a preferred output. Alternatively, the quality factor of the selected capacitor can be increased, or the second and third microstrip transmission lines can be readjusted to change the mapping state of the loss components at the branch input. Through this process, the loss effect of the tuning capacitor can be incorporated into the selection of target parameters.

[0089] Secondly, consider the metal thickness of the microstrip transmission line. Decreasing the metal thickness typically increases the conductor resistance and propagation loss per unit length, thus altering the real parts of the input admittances of the first and second bias branches. Simultaneously, metal thickness variations can also change the effective characteristic impedance and propagation constant of the microstrip transmission line, causing a shift in the electrical length corresponding to the same physical line length, further deviating the imaginary amplitude or phase relationship of the two paths from the nominal state. Therefore, variations in metal thickness can both worsen the real part constraint and increase the imaginary residual.

[0090] To address the impact of metal thickness, multiple process states can be established based on the allowable thickness range of the adopted process. For each process state, the effective characteristic impedance, electrical length, and propagation loss of the three microstrip transmission lines are re-extracted, and Y is calculated. A (f), Y B (f) and its synthesized input admittance. If a set of nominal parameters only meets the constraints at the nominal metal thickness, but exceeds the admittance limit over a large area under reasonable thickness deviations, then the parameter adjustment process can be returned to, and the linewidth, line length or capacitance can be appropriately changed so that the two branches still retain a certain amount of cancellation margin under different process conditions.

[0091] Besides metal thickness, parasitic parameters such as microstrip transmission line corners, T-junctions, grounding vias, pads, and device interconnects can also be introduced into the electromagnetic simulation model in the millimeter-wave band. The quarter-wavelength condition is sensitive to changes in electrical length at high frequencies, and the dual-branch scheme in this embodiment also needs to ensure that the admittance relationship of the two branches in the actual layout is consistent with the circuit model. Therefore, after the initial selection of circuit-level parameters, the corresponding layout structure can be imported into an electromagnetic simulation tool for co-simulation, and the frequency domain input admittance obtained from the electromagnetic simulation can be used to replace the result of the ideal transmission line model to re-verify the preset constraints.

[0092] Consider the DC state again. For the DC power supply, both the grounding tuning capacitor C5 and the power supply decoupling capacitor C4 are open circuits, and no continuous DC current path is formed to ground. In this case, the first microstrip transmission line in the first bias branch forms the first DC conduction path from the power supply decoupling node to the power transistor bias node; the second and third microstrip transmission lines in the second bias branch are connected in series to form the second DC conduction path. Since the two paths are connected between the same two nodes, the equivalent resistances of the two DC paths are in parallel.

[0093] Let R be the equivalent resistance of the first DC conduction path. A The equivalent resistance of the second DC conduction path is R. B The DC equivalent resistance R when the two paths share the power supply DC By R A With R B The parallel result is determined. For a positive resistor R... A and R B R DC The resistance value is less than that of any single path. Therefore, at radio frequency, the combined input admittance can be reduced by utilizing the imaginary parts of the two paths with opposite signs, while in DC state both paths can bear the bias current, without having to limit the entire DC current to a narrow microstrip line.

[0094] Combination Figure 2 In the dual-branch circuit structure shown, both the tuning capacitor C5 and the bypass capacitor C4 are open-circuited under DC conditions. The first bias branch and the second bias branch correspond to the equivalent resistance R, respectively. A and R B Two DC conduction paths are connected between the same two nodes, and their equivalent DC resistance R after parallel connection is... DC By R A With R B The parallel relationship is determined.

[0095] R DC =R A ·R B / (R A +R B ) Among them, R DC R represents the equivalent DC resistance of two DC conduction paths connected in parallel. A R represents the DC equivalent resistance of the first bias branch. B This represents the DC equivalent resistance of the second bias branch.

[0096] In DC calibration, the DC resistance of each path can be estimated based on the microstrip transmission line's material resistivity, linewidth, metal thickness, and actual trace length. The voltage drop and allowable current density of the power transistor under rated bias current are also checked. If increasing the linewidth of a microstrip line to reduce DC resistance leads to a change in RF admittance, the updated transmission parameters are recalculated in the frequency domain, and the phase and capacitance of another branch are adjusted collaboratively. In this way, RF and DC constraints are jointly calibrated using the same set of geometric parameters.

[0097] In some embodiments, C4 of the power supply decoupling node can be selected as a bypass device with low impedance to ground in the target frequency band. Its main function is not to form a destructive element between the two branches, but to provide an RF reference ground for the end of the bias network away from the power transistor. Residual RF components leaking to the power supply decoupling node can be bypassed to ground through C4, thereby reducing the amount of RF energy that continues to enter the DC power network; at the same time, high-frequency noise generated at the power supply end is also suppressed by this decoupling structure before entering the power transistor bias node.

[0098] This embodiment incorporates the quality factor of the tuning capacitor, the microstrip metal thickness, and the admittance offset caused by layout parasites into parameter verification, and simultaneously checks the DC parallel power supply state on the same structure. This avoids determining parameters solely based on the ideal imaginary cancellation result, while ignoring the influence of active power loss, process deviation, and DC resistance on the actual bias network, ensuring that the output target bias network parameters have both feasible RF and DC physical basis.

[0099] Example 4 This embodiment illustrates the simulation verification process of a dual-branch bias network and an implementation method of the corresponding design system.

[0100] During the RF verification phase, the target bias network parameters determined in Examples 1 to 3 were written into the simulation model, and a frequency scan was performed from 32 GHz to 38 GHz. For the first bias branch, the curve of its imaginary part of input admittance changing with frequency was observed; for the second bias branch, the corresponding imaginary part curve was observed. In a set of simulation results, the first bias branch Y... A The imaginary part is mainly less than zero within the target frequency band, exhibiting inductive properties; the second bias branch Y B The imaginary part of the susceptance is mainly greater than zero within the target frequency band, exhibiting capacitive behavior. The combined imaginary part obtained by adding the corresponding frequency points of the two curves is close to zero, indicating that the two opposite-sign susceptance components cancel each other out within the target frequency band.

[0101] Simultaneously observe Y A and Y BThe real part curve. If the conductor loss and capacitance loss of the two branches are at a low level, the combined real part after the real parts of the two branches are superimposed will also remain small. By checking the real and imaginary parts at the same time, it is possible to distinguish between two states: "the imaginary parts have canceled each other but the loss is too large" and "the real part is small but the imaginary part has not canceled each other". Only the parameter combination that meets the admittance constraints set in the current design is used as the target bias network parameters.

[0102] In another verification model, RF ports can be configured at both ends of the bias network, and the leakage state of the RF signal from the RF input to the DC power supply line can be observed using scattering parameters. In this RF verification model, dB(S(2,1)) is used to characterize the magnitude of the RF signal leakage to the DC power supply line, and dB(S(1,1)) is used to characterize the return coefficient of the RF input port. In a set of simulation results, dB(S(2,1)) is below -20dB in the 32GHz to 38GHz range, and dB(S(1,1)) is close to 0dB. This result is consistent with the low synthesized input admittance state, indicating that the bias network exerts a weak load on the RF nodes within the target frequency band.

[0103] like Figure 5 As shown, RF can be set on both sides of the dual-path admittance canceling bias network. in and RF out RF port, where RF in Located on the RF input side, RF out Located on the side of the bias network facing the DC power supply line; the radio frequency signal is generated by RF in To RF out Direction transmission, TL12 constitutes Y A The path, TL10, TL11, and C5 constitute Y. B The path, C4, is used to form an RF bypass at the power supply decoupling terminal, thereby verifying the RF leakage and reflection of the bias network corresponding to the target parameters.

[0104] like Figure 6 As shown, the amount of RF signal leakage to the DC power supply line in dB(S(2,1)) and the RF input port echo coefficient in dB(S(1,1)) can be observed by the change of scattering parameters with frequency. The smaller dB(S(2,1)) and the dB(S(1,1)) close to 0 dB in the target millimeter wave band are used together to verify the RF isolation state corresponding to the low synthesized input admittance.

[0105] In the above set of simulation results, at 32 GHz, dB(S(2,1)) is approximately -21.353 dB and dB(S(1,1)) is approximately -0.158 dB; at 38 GHz, dB(S(2,1)) is approximately -22.123 dB and dB(S(1,1)) is approximately -0.171 dB. Specifically, under the conventional definition of scattering parameters with a port reference impedance of 50 Ω, dB(S(1,1)) close to 0 dB indicates that the reflection coefficient amplitude is close to 1, corresponding to a state of high reflection and low RF loading observed at the RF input terminal, but does not indicate that the port has achieved 50 Ω matching; dB(S(2,1)) below -20 dB characterizes a small component of the RF signal leaking along the bias network to the DC power supply line. Therefore, the verification of scattering parameters should be interpreted in conjunction with the results of the real and imaginary parts of the synthesized input admittance.

[0106] like Figure 7 As shown, the dual-path admittance destructive bias network determined according to Examples 1 to 3 can be connected to a complete millimeter-wave power amplifier circuit at the RF input terminal. in Power transistors and RF output terminals out The overall structure maintains the connection between the bias network and the DC power supply node, and the overall circuit simulation is performed without changing the bias voltage and matching network. Using this overall model, the power-added efficiency (PAE), output power, and load pulling results before and after adopting the admittance cancellation bias network can be further compared to verify the impact of reducing the RF loading of the bias network on the operating state of the complete power amplifier.

[0107] like Figure 8 As shown, in the baseline model without an admittance decomposition bias network, the power-added efficiency (PAE) can be obtained as a function of the RF input power (RF). power A set of varying simulation curves; illustrated in the RF diagram. power At a voltage of 10 dBm, a representative PAE curve has a labeled value of approximately 26.088%, which serves as a reference for comparison under the same bias voltage and matching network conditions.

[0108] like Figure 9 As shown, while maintaining and Figure 8 With the same bias voltage, matching network, and input power settings, a dual-path admittance canceling bias network can be used to obtain the corresponding power-added efficiency simulation curve; in the illustrated RF... power At a value of 10 dBm, the corresponding labeled value of a representative PAE curve is approximately 27.268%. Combined with... Figure 8 and Figure 9As can be seen, under the specific simulation conditions, the PAE shows an improving trend after adopting the admittance phase-canceling bias network. This result is used to illustrate the verification effect of the parameter combination in this embodiment and is not intended to limit other devices or other frequency bands to have the same improvement.

[0109] Furthermore, while keeping the bias voltage and output matching network unchanged, the same load pulling settings were applied to the control model without admittance cancellation bias network and the model with target dual-branch parameters, respectively, and the power-added efficiency (PAE) and output power as a function of load impedance were compared.

[0110] like Figure 10 As shown, without the use of an admittance-canceling bias network, under the given bias voltage and matching network conditions, the maximum power-added efficiency (PAE) is approximately 26.11% and the maximum output power is approximately 14.76 dBm in the load traction results obtained.

[0111] like Figure 11 As shown, with the same bias voltage, matching network, and load pull settings, using a dual-path admittance canceling bias network, the maximum power-added efficiency (PAE) is approximately 27.13%, and the maximum output power is approximately 14.93 dBm. Figure 10 and Figure 11 By comparing under the same conditions, it can be verified that after reducing the RF loading of the bias network under this specific parameter combination, the efficiency and output power of the complete power amplifier are not adversely affected and are even improved to a certain extent; the above values ​​only correspond to the device and simulation conditions of this embodiment.

[0112] In terms of system implementation, the millimeter-wave power amplifier bias network design system can include an admittance acquisition module, an admittance control module, and a parameter output module. Each module can be implemented by executing different program segments on the same processor, or by multiple processing units working together. The system may also include memory, a simulation interface, and a parameter database to store the target millimeter-wave frequency band, microstrip line candidate parameters, capacitor candidate parameters, input admittances in each frequency domain, and the final output parameters.

[0113] The admittance acquisition module is used to read the target millimeter-wave frequency band in the design task and to build or call the parallel first bias branch and second bias branch models. The admittance acquisition module controls the simulation interface to perform a small-signal scan at preset frequency sampling points, obtaining Y... A (f) and Y B (f) and establish corresponding records between the real and imaginary parts of each frequency point and the current linewidth, line length, and capacitance. If the system is connected to electromagnetic simulation results, the frequency domain admittance data derived from the layout electromagnetic model can also be read directly.

[0114] The admittance control module generates the next set of admittance control parameters based on the current frequency domain input admittance. Specifically, it first adjusts the reference admittance of the first bias branch, and then adjusts the resonant position, input phase, and capacitive amplitude of the second bias branch sequentially. After each set of parameters is generated, the admittance control module calls the admittance acquisition module to recalculate the frequency domain input admittance, and determines whether to continue the search based on the imaginary part sign, imaginary part residual, and synthesized real part of the two branches. The admittance control module can also read the capacitance quality factor and metal thickness status to perform non-ideal condition checks on candidate parameters.

[0115] In a specific software-based implementation, the admittance control module can generate an intermediate result for each sampling frequency point, including at least an out-of-sign flag and an imaginary residual, wherein the out-of-sign flag is determined by B. A (f)·B B (f) < 0 is determined, and the imaginary residual is B. bias (f)=B A (f)+B B (f) The parameter output module does not rely on the "opposite signs of the imaginary parts of the synthesized input admittance" for judgment. Instead, it first confirms the cancellation relationship between the two branches based on the opposite sign flag, and then relies on B. bias (f) and whether the real part of the synthesis satisfies the preset upper limit to determine whether the candidate parameter should be retained.

[0116] The parameter output module is used to perform preset constraint judgments on candidate parameters. The output results can include the linewidth, line length, characteristic impedance, and electrical length of the first to third microstrip transmission lines, the capacitance of the tuning capacitor, and the statistical results of the synthesized input admittance within the corresponding target frequency band. For ease of verification, the target frequency band, frequency sampling interval, upper limit of the real part, upper limit of the imaginary part, capacitor quality factor, and metal thickness status used during parameter generation can also be written into the design record.

[0117] In one software implementation, the memory can be configured with a task configuration area, a candidate parameter area, a frequency domain result area, and an output result area. The task configuration area stores the target frequency band and constraints; the candidate parameter area stores W, L, and C to be simulated in each round; and the frequency domain result area stores Y according to the parameter combinations. A and Y B The frequency response is recorded; the output result area only stores parameter combinations that satisfy preset constraints. The processor sequentially reads candidate parameters, calls the simulation interface, obtains frequency domain results, performs cancellation judgment and constraint judgment, until the target parameters that meet the conditions are obtained or the preset search range is reached.

[0118] The system can generate candidate parameters using parameter traversal, hierarchical scanning, or a coarse-to-fine local search. Taking hierarchical scanning as an example, the first and third microstrip transmission lines are first scanned with a large step size to determine the reference admittance range and the resonant position of the second bias branch; then the step size of the second microstrip transmission line is reduced to adjust the input phase of path B; finally, the capacitance step size of the tuning capacitor is reduced to adjust the cancellation depth. Regardless of the search method used, whether candidate parameters are retained is determined by the actual calculated frequency domain input admittance and the preset admittance constraints.

[0119] When the target frequency band, transistor process, or layout constraints change, the corresponding task parameters can be reloaded and the same design flow can be executed. For example, after the target frequency band changes, the system re-acquires the frequency domain input admittance of the two branches within the new frequency band, instead of directly using the absolute line length or capacitance from the 32GHz–38GHz example; instead, it redetermines the relationship between the opposite signs of the imaginary parts of the two branches based on the new frequency domain input admittance. Thus, the core constraint of the design flow remains the coordinated adjustment of the frequency domain admittance of the two branches, while the specific device parameters are re-determined according to the application conditions.

[0120] This embodiment performs multi-layer verification of the target bias network parameters using frequency domain admittance curves, scattering parameters, the complete power amplifier circuit, power-added efficiency curves, and load pulling results. It also presents the data flow between the admittance acquisition, parameter tuning, and parameter output modules. The system outputs a set of realizable parameters that meet the synthetic input admittance constraints in the target millimeter-wave frequency band, rather than simply providing the theoretical impedance value for a single center frequency. Furthermore, DC parallel power supply, device losses, and process deviations can all be used as verification conditions within the same parameter flow, thus forming an implementation method applicable to the design and verification of millimeter-wave power amplifier bias networks.

[0121] The above description is merely an embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for designing a bias network for a millimeter-wave power amplifier, characterized in that, The method includes: The target millimeter-wave frequency band of the amplifier, as well as the parallel bias branches and their frequency domain input admittance, are obtained. The bias branches include a first bias branch and a second bias branch. The admittance control parameters of the first bias branch and the second bias branch are adjusted according to the frequency domain input admittance to generate a composite input admittance in the first bias branch and the second bias branch within the target millimeter-wave frequency band. The imaginary parts of the composite input admittance have opposite signs and at least partially cancel each other out. The admittance control parameters include the transmission parameters of the microstrip transmission lines in the first bias branch and the second bias branch, as well as the tuning parameters of the tuning capacitors. The admittance control parameters that enable the synthesized input admittance to satisfy the preset constraints are determined as target bias network parameters and output. The preset constraints are upper limit constraints on at least one of the real and imaginary parts of the synthesized input admittance.

2. The millimeter-wave power amplifier bias network design method as described in claim 1, characterized in that, The step of adjusting the admittance control parameters of the first bias branch and the second bias branch according to the frequency domain input admittance includes: The reference admittance is formed using the first microstrip transmission line of the first bias branch; The tuning admittance is formed by connecting the second microstrip transmission line, the third microstrip transmission line, and the tuning capacitor grounded at the intermediate node of the second bias branch in series. Candidate admittance control parameters are determined based on the difference in the imaginary parts of the reference admittance and the tuned admittance.

3. The millimeter-wave power amplifier bias network design method as described in claim 2, characterized in that, The step of determining candidate admittance tuning parameters based on the difference in the imaginary part of the reference admittance and the tuning admittance includes: Adjust the third microstrip transmission line to provide inductive compensation for the tuning capacitor and change the resonant position of the second bias branch; Adjust the second microstrip transmission line to transform the combined admittance of the third microstrip transmission line and the tuning capacitor to the branch input terminal and adjust the phase. Adjust the capacitance of the tuning capacitor so that the imaginary part of the tuning admittance converges to the imaginary part of the reference admittance.

4. The millimeter-wave power amplifier bias network design method as described in claim 3, characterized in that, The imaginary parts of the synthesized input admittance have opposite signs and at least partially cancel each other out, including: Within the target millimeter-wave frequency band, the superposition result of the imaginary part of the input admittance of the first bias branch and the imaginary part of the input admittance of the second bias branch is determined. When the absolute value of the superimposed imaginary part is less than the absolute value of the imaginary part of the input admittance of at least one bias branch, the corresponding candidate admittance control parameter is determined as the cancellation parameter.

5. The millimeter-wave power amplifier bias network design method as described in claim 4, characterized in that, The preset constraints include a preset upper limit for the real part and a preset upper limit for the imaginary part, which respectively determine the real and imaginary parts of the synthesized input admittance at each frequency point within the target millimeter-wave frequency band. The cancellation parameters whose absolute values ​​of the real part and imaginary part are not higher than the preset upper limit for the real part and the absolute values ​​of the imaginary part are not higher than the preset upper limit for the imaginary part are determined as the target bias network parameters.

6. The millimeter-wave power amplifier bias network design method as described in claim 5, characterized in that, The transmission parameters include the characteristic impedance and electrical length of the microstrip transmission line, which are changed by adjusting the line width and line length of the corresponding microstrip transmission line.

7. The millimeter-wave power amplifier bias network design method as described in claim 6, characterized in that, When determining the synthesized input admittance, the quality factor of the tuning capacitor is also obtained, the equivalent series resistance of the tuning capacitor is determined based on the quality factor, and the active power loss corresponding to the equivalent series resistance is included in the real part of the input admittance of the second bias branch.

8. The millimeter-wave power amplifier bias network design method as described in claim 7, characterized in that, The metal thickness of the microstrip transmission line is also obtained. The frequency domain input admittance of the first bias branch and the second bias branch is corrected based on the conductor resistance per unit length, effective characteristic impedance and electrical length change corresponding to the metal thickness. The preset constraint conditions are verified based on the corrected frequency domain input admittance.

9. The millimeter-wave power amplifier bias network design method according to any one of claims 1-8, characterized in that, The first bias branch and the second bias branch are connected in parallel between the RF / DC common bias node and the power supply decoupling node of the power transistor. In the DC state, the tuning capacitor is open, and the first bias branch and the second bias branch form DC conduction paths respectively, and the DC equivalent resistance of the two DC conduction paths are in parallel.

10. A millimeter-wave power amplifier bias network design system, characterized in that, include: The admittance acquisition module is used to acquire the target millimeter-wave frequency band of the amplifier, as well as the first bias branch and the second bias branch connected in parallel and their frequency domain input admittance; The admittance control module is used to adjust the admittance control parameters of the first bias branch and the second bias branch according to the frequency domain input admittance, so that the imaginary parts of the input admittance of the first bias branch and the second bias branch in the target millimeter wave frequency band are opposite in sign and at least partially canceled, and to generate a composite input admittance. The parameter output module is used to determine the admittance control parameters that make the synthesized input admittance meet the preset constraints as the target bias network parameters and output them.

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