A novel radio frequency front-end module circuit structure applied to a time division duplex system

Abstract

The application belongs to the technical field of radio frequency front-end module circuit, and particularly relates to a novel radio frequency front-end module circuit structure applied to a time division duplex system, which comprises a power amplifier PA connected to a transmitting channel TX, a low-noise amplifier LNA connected to a receiving channel RX, and capacitors C1, C2 and C3, introduction switches SW1, SW2 and SW3, windings L1, L2 and L3; wherein one end of the capacitor C1 is connected to the transmitting channel TX, the other end of the capacitor C1 is connected to one end of the winding L1 through the introduction switch SW1, the other end of the winding L1 is connected to the transmitting channel TX, the winding L2 and the capacitor C2 are connected in parallel on the transmitting channel TX, and the introduction switch SW1 and the capacitor C2 are grounded, and the winding L1 and the winding L2 constitute a balun. The performance of the radio frequency front-end module of the TDD system is greatly improved, the output power of the transmitting channel TX is not deteriorated, the sensitivity of the receiving channel RX is not deteriorated, and the ESD discharge capacity of the ANT port is improved.

Description

Technical Field

[0001] This invention relates to the field of radio frequency front-end module circuit technology, specifically a novel radio frequency front-end module circuit structure applied to time division duplex systems. Background Technology

[0002] In typical time-division duplex (TDD) systems, such as Bluetooth, Zigbee, and Wi-Fi, the RF front-end module needs to use a switch (SW) to switch between the receive channel (RX) and the transmit channel (TX) to achieve effective communication. Figure 1 As shown.

[0003] As can be seen, the switch SW, as one of the components, needs to maintain low loss characteristics to ensure that the power of the TX and RX branches is not significantly reduced, otherwise it will affect the radiated power of the antenna port and the noise figure of the receiving link. On the other hand, it also needs to have high isolation to avoid the transmission power of TX from degrading the sensitivity of RX. In more serious cases, it may even damage the RX input transistor.

[0004] Switches (SWs) are commonly designed using GaAs PHEMT or SOI processes. These two processes have low substrate losses, resulting in minimal losses introduced to the transmit (TX) or receive (RX) signals, but their extremely high cost limits their application in cost-critical Internet of Things (IoT) applications. If conventional silicon-based RFCMOS processes are used, the higher substrate losses lead to correspondingly higher SW losses in RFCMOS-designed switches. Using the same RF front-end topology, the switching losses in RFCMOS are 1-1.5 dB higher than in SOI. These switching losses directly result in a 1-1.5 dB reduction in transmit power (TX) and noise figure (RX). Therefore, designing low-loss switches in low-cost RFCMOS processes is a highly challenging task, facing insurmountable physical limitations.

[0005] Furthermore, the substrate of a typical RFCMOS transistor is a low-resistivity substrate, with a resistivity of approximately 10 Ω·cm, meaning that the Psub transistor is grounded through a low-resistivity path. Although this process supports deep N-wells (DNWs), allowing transistors to be fabricated within the DNW for better isolation, the parasitic diode between the DNW and the Psub transistor limits the power tolerance of the switching transistor. For example... Figure 2As shown, when a high-power input signal is applied to the source or drain node of the switching transistor SW, its voltage swing is high, superimposed on the DC level of DNW. Since Psub is grounded with low resistance, when the DNW voltage (node ​​2) swings negatively and is about 0.7V below ground, the parasitic diode between DNW and Psub will conduct, thus limiting the voltage swing of DNW node 2. This results in a deterioration of the floating characteristics of DNW, meaning it cannot guarantee AC floating, further limiting the swing and affecting the P1dB performance of the switching SW. This is also a physical limiting factor that restricts the maximum output power of the RFCMOS switching SW. Moving the Psub ground point away from the switching transistor can improve power performance, but it will increase the layout area of ​​the switching circuit, thereby increasing chip cost. Summary of the Invention

[0006] The purpose of this invention is to provide a novel radio frequency front-end module circuit structure for use in time-division duplex systems, so as to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a novel radio frequency front-end module circuit structure for use in a time-division duplex system, comprising: The power amplifier PA connected to the transmit channel TX, the low noise amplifier LNA connected to the receive channel RX, and also include capacitors C1, C2, and C3, input switches SW1, SW2, and SW3, windings L1, L2, and L3. Wherein, one end of capacitor C1 is connected to the transmission channel TX, the other end of capacitor C1 is connected to one end of winding L1 through the inlet switch SW1, the other end of winding L1 is connected to the transmission channel TX, winding L2 and capacitor C2 are connected in parallel on the transmission channel TX, and inlet switch SW1 and capacitor C2 are grounded, and winding L1 and winding L2 form a balun; The winding L3 and capacitor C3 are connected in parallel and connected to the receiving channel RX. The input switch SW2 is connected in series with capacitor C3 and grounded.

[0008] Preferably, it also includes an LNA bypass component, which includes a winding L4 and two capacitors connected in series. The two ends of the winding L4 and the two capacitors are connected in parallel with the winding L3 and the low noise amplifier LNA. A capacitor C4 and an input switch SW4 are connected in parallel on the winding L4, and the input switch SW4 is grounded.

[0009] Preferably, the capacitor C1 includes capacitors C1_1 and C1_2 connected in series, the input switch SW1 includes input switches SW1_1 and SW1_2 connected in series, and the input switches SW1_1 and SW1_2 are located between capacitors C1_1 and C1_2. The transmitting channels TX are respectively led out from both sides of capacitors C1_1 and C1_2, and the winding L1 includes windings L1_1 and L1_2 connected in series.

[0010] Preferably, there are two windings L2, which are connected in series and then in parallel with capacitor C. The windings L2 also include capacitors C2_1 and C2_2 connected in series. Switches SW2_1 and SW2_2 are connected in series between capacitors C2_1 and C2_2. Windings L2_1 and L2_2 are connected in parallel to capacitors C2_1 and C2_2, and windings L2_1 and L2_2 are connected in series with each other. Windings L2_1 and L2_2 also lead out to the transmission channel TX.

[0011] Compared with the prior art, the beneficial effects of the present invention are: By improving the circuit topology and avoiding the use of overpower switches, when the transmit channel TX is transmitting, the TX RF link is directly connected to the ANT port, and the receive channel RX section forms a parallel resonance, providing excellent isolation and preventing a reduction in the transmit power of the transmit channel TX. When the receive channel RX is receiving, the transmit channel TX section also forms an equivalent parallel resonance, and the equivalent inductance of the receive channel RX section is beneficial for matching the low-noise amplifier (LNA). The ground transistor of the receive channel RX can be used as an ESD bleeder, improving the ESD bleeder capability of the ANT port.

[0012] It greatly improves the performance of the RF front-end module of the TDD system, without degrading the TX output power of the transmit channel or the RX sensitivity of the receive channel, and can improve the ESD discharge capability of the ANT port. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of an existing RF front-end module circuit. Figure 2 State diagram when a high-power input signal is applied to the source or drain node of the switching transistor SW; Figure 3 This is the circuit schematic diagram of the present invention; Figure 4 This is a circuit diagram of the TX transmission channel of the present invention during operation; Figure 5 This is a circuit schematic diagram of the receiving channel RX of the present invention during operation; Figure 6 A circuit schematic diagram for adding an LNA bypass mode to this invention; Figure 7 This is a circuit schematic of the differential power amplifier PA of the present invention; Figure 8 for Figure 7 The schematic diagram of the extended circuit. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0016] Example 1: Please refer to Figure 3 , 4 5. This invention provides a technical solution: a novel radio frequency front-end module circuit structure applied to a time-division duplex system, comprising: The power amplifier PA connected to the transmit channel TX, the low noise amplifier LNA connected to the receive channel RX, and also include capacitors C1, C2, and C3, input switches SW1, SW2, and SW3, windings L1, L2, and L3. In this configuration, one end of capacitor C1 is connected to the transmitting channel TX, and the other end of capacitor C1 is connected to one end of winding L1 via a switch SW1. The other end of winding L1 is connected to the transmitting channel TX. Winding L2 and capacitor C2 are connected in parallel to the transmitting channel TX, and switch SW1 and capacitor C2 are grounded. Winding L1 and winding L2 form a balun. Winding L3 and capacitor C3 are connected in parallel and connected to the receiving channel RX. Switch SW2 is connected in series with capacitor C3 and is grounded.

[0017] Analysis of the above: Windings L1 (inductor) and L2 (inductor) form a balun, used to transform the output impedance of the power amplifier PA, converting the 50Ω impedance at the antenna port (ANT port) to the output impedance required by the power amplifier PA. By appropriately adjusting capacitor C2, winding L2 and capacitor C2 are made to resonate within the operating frequency band, thereby improving system efficiency. The working principle of this topology is as follows: When TX is working, switch SW1, switch SW2, and switch SW3 are closed. Figure 3 Equivalent to Figure 4 Capacitor C1, winding L1, capacitor C2, and winding L2 constitute the TX output matching circuit of the transmission channel, matched to the operating frequency band. Capacitor C3 and winding L3 form a parallel resonance, resonating within the operating frequency band. Assuming the operating frequency band is f0, the values ​​of capacitor C3 and winding L3 satisfy... This results in high impedance when viewed from the ANT port to the receiving channel RX, and also provides suppression of frequencies outside the operating band, thus suppressing harmonics. Since the RF power is not introduced through the switch SW, this circuit structure is particularly suitable for the high power and low insertion loss requirements of ordinary RFCMOS processes, thereby avoiding power tolerance limitations.

[0018] When RX is working, switches SW1, SW2, and SW3 are turned on. Figure 3 Equivalent to Figure 5 The power amplifier PA is not working, and the resonance of capacitor C1 and winding L1 fails due to the opening of switch SW1. The winding L1, capacitor C1, capacitor C2, and winding L2 constitute a balance mismatch. The impedance Z1 seen from the ANT port to the transmit channel TX branch is equivalent to the parallel connection of winding L2 and capacitor C2, which is equivalent to a high impedance in the receive channel RX operating frequency band, thus not affecting the receive channel RX link. Due to the opening of switches SW2 and SW3, the impedance of Z2 is equivalent to winding L3. In the noise matching of the RFCMOS low noise amplifier LNA, it is desirable to see an inductive source impedance. Therefore, winding L3 helps the noise matching of the low noise amplifier LNA.

[0019] In addition to winding L2 improving the ESD performance of ANT, winding L3 and inlet switch SW3 can also form another ESD discharge branch. The layout of inlet switch SW3 needs to be drawn as a GGNMOS (gate-ground NMOS) ESD structure.

[0020] Example 3: Please refer to Figure 6The present invention provides a technical solution: it further includes an LNA bypass component, the LNA bypass component includes a winding L4 connected in series and two capacitors, the two ends of the winding L4 and the two capacitors are connected in parallel with the winding L3 and the low noise amplifier LNA, and a capacitor C4 and an input switch SW4 are connected in parallel on the winding L4, and the input switch SW4 is grounded.

[0021] Analysis of the above content: Based on Figure 3 The single-pole double-throw switch (SPDT) is extended to SP3T or higher, such as SP3T, with an additional channel for LNA bypass mode, such as... Figure 6 As shown.

[0022] Example 3: Please refer to Figure 7 The present invention provides a technical solution: the capacitor C1 includes capacitors C1_1 and C1_2 connected in series, the input switch SW1 includes input switches SW1_1 and SW1_2 connected in series, and the input switches SW1_1 and SW1_2 are located between capacitors C1_1 and C1_2, the two sides of capacitors C1_1 and C1_2 respectively lead out the transmission channel TX, and the winding L1 includes windings L1_1 and L1_2 connected in series.

[0023] Analysis of the above content: such as Figure 7 As shown, in Embodiment 2, the circuit structure PA is a single-ended output. This structure can also be applied to a differential structure PA. Figure 7 ).

[0024] Example 4: Please refer to Figure 8 The present invention provides a technical solution based on embodiment three: there are two windings L2, and the two windings L2 are connected in series and then connected in parallel with capacitor C. It also includes capacitors C2_1 and C2_2 connected in series. Switches SW2_1 and SW2_2 are connected in series between capacitors C2_1 and C2_2. Windings L2_1 and L2_2 are connected in parallel to capacitors C2_1 and C2_2, and windings L2_1 and L2_2 are connected in series with each other. Windings L2_1 and L2_2 also lead out to the transmission channel TX.

[0025] Analysis of the above content: Figure 8 yes Figure 7 The circuit structure is expanded to achieve higher output power in RFCMOS technology through power combining.

[0026] In the above scheme, the circuit topology is improved to avoid the use of overpower switches. When the transmit channel TX transmits, the TX RF link is directly connected to the ANT port, and the receive channel RX section forms a parallel resonance, creating good isolation and preventing a reduction in the transmit power of the transmit channel TX. When the receive channel RX receives, the transmit channel TX section also effectively forms a parallel resonance, and the equivalent inductance of the receive channel RX section is beneficial for matching the low-noise amplifier (LNA). The ground transistor of the receive channel RX can be used as an ESD bleeder, improving the ESD bleeder capability of the ANT port.

[0027] It greatly improves the performance of the RF front-end module of the TDD system, without degrading the TX output power of the transmit channel or the RX sensitivity of the receive channel, and can improve the ESD discharge capability of the ANT port.

[0028] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or basic characteristics. Therefore, the embodiments should be considered exemplary and non-limiting in all respects. The scope of the invention is defined by the appended claims rather than the foregoing description. Therefore, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention, and no reference numerals in the claims should be construed as limiting the scope of the claims.

[0029] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A novel radio frequency front-end module circuit structure for use in time-division duplex systems, characterized in that, include: The power amplifier PA connected to the transmit channel TX, the low noise amplifier LNA connected to the receive channel RX, and also include capacitors C1, C2, and C3, input switches SW1, SW2, and SW3, windings L1, L2, and L3. Wherein, one end of capacitor C1 is connected to the transmission channel TX, the other end of capacitor C1 is connected to one end of winding L1 through the inlet switch SW1, the other end of winding L1 is connected to the transmission channel TX, winding L2 and capacitor C2 are connected in parallel on the transmission channel TX, and inlet switch SW1 and capacitor C2 are grounded, and winding L1 and winding L2 form a balun; The winding L3 and capacitor C3 are connected in parallel and connected to the receiving channel RX. The input switch SW2 is connected in series with capacitor C3 and grounded.

2. The novel RF front-end module circuit structure applied to a time division duplex system according to claim 1, characterized in that: It also includes an LNA bypass component, which includes a winding L4 and two capacitors connected in series. The two ends of the winding L4 and the two capacitors are connected in parallel with the winding L3 and the low noise amplifier LNA. A capacitor C4 and a lead-in switch SW4 are connected in parallel on the winding L4, and the lead-in switch SW4 is grounded.

3. The novel RF front-end module circuit structure applied to a time division duplex system according to claim 1, characterized in that: The capacitor C1 includes capacitors C1_1 and C1_2 connected in series. The input switch SW1 includes input switches SW1_1 and SW1_2 connected in series, and input switches SW1_1 and SW1_2 are located between capacitors C1_1 and C1_2. Transmission channels TX are respectively led out from both sides of capacitors C1_1 and C1_2. The winding L1 includes windings L1_1 and L1_2 connected in series.

4. The novel RF front-end module circuit structure applied to a time division duplex system according to claim 3, characterized in that: The winding L2 consists of two windings, which are connected in series and then in parallel with capacitor C. It also includes capacitors C2_1 and C2_2 connected in series. Switches SW2_1 and SW2_2 are connected in series between capacitors C2_1 and C2_2. Windings L2_1 and L2_2 are connected in parallel to capacitors C2_1 and C2_2, and windings L2_1 and L2_2 are connected in series with each other. Windings L2_1 and L2_2 also lead out to the transmission channel TX.

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