Common-mode compensation method and circuit for high-precision current detection amplifier and amplifier

Abstract

This application relates to the technical field of current detection circuits, and discloses a common-mode compensation method, circuit, and amplifier for a high-precision current detection amplifier. The method is based on a current detection sampling amplifier with a common-gate amplification structure in the input stage. Compensation data is calculated by calibrating the detection data and the actual detection data to complete the constant current source configuration. A bias constant current source is set at the input resistor R2 and the matching node to sample the positive input level and output an adaptive current positively correlated with it. An adaptive voltage is generated through R2 to compensate the amplifier amplification factor. The amplifier integrates a differential input sampling unit, a dual common-gate high-side / low-side input stage, a common-mode compensation circuit, and a subsequent amplification output stage. The compensation circuit consists of an operational amplifier, an NMOS transistor, and a resistor network. This application can offset the input resistance drift and amplification factor deviation caused by wide common-mode voltage fluctuations, improving the current detection accuracy, linearity, and operating condition adaptability.

Description

Technical Field

[0001] This application relates to the technical field of current detection circuits, and in particular to a common-mode compensation method, circuit, and amplifier for a high-precision current detection amplifier. Background Technology

[0002] In various electronic systems, current sensing is a core function for overcurrent protection, current limiting control, and load monitoring. High-side current sampling connects a sampling resistor in series between the power supply and the load to detect the current along the power supply path to the load. This avoids the need to connect a sampling resistor in the system ground wire, optimizes the system grounding layout, and improves anti-interference capabilities. It is widely used in integrated circuits for power management, motor drives, and battery protection.

[0003] The two input terminals of the high-side current sampling amplifier are directly connected to the two ends of the sampling resistor. Its input common-mode voltage varies widely with the fluctuation of the system power supply voltage. The input common-mode voltage range can extend from near ground potential to near the highest operating power supply voltage of the system.

[0004] When the input common-mode voltage varies over a wide range, parameters such as the operating point of the differential input, bias current, source-drain voltage, and substrate bias effect within the amplifier change accordingly. This causes a significant shift in the input offset voltage with the common-mode voltage, resulting in input offset voltage drift. The current-sensing output is proportional to the differential voltage across the sampling resistor, and the offset voltage is amplified along with the effective signal. The offset drift caused by common-mode variations is directly converted into current sensing error. In low-current and high-precision current sensing scenarios, the impact of this error is particularly pronounced, making it difficult to meet the requirements of high-precision applications. Summary of the Invention

[0005] To reduce the impact of input offset voltage drift and improve the accuracy of current sensing, this application provides a common-mode compensation method, circuit, and amplifier for a high-precision current sensing amplifier.

[0006] Firstly, this application provides a common-mode compensation method for a high-precision current sensing amplifier, employing the following technical solution: A common-mode compensation method for a high-precision current-sensing amplifier is disclosed, based on a current-sensing sampling amplifier with a common-gate amplification structure at its input stage. One input terminal of the common-gate amplification structure is equipped with an input resistor R1, one end of which is the positive input terminal, and the other end is connected to a preset bias node. The other input terminal of the common-gate amplification structure is connected to an input resistor R2, one end of which is the negative input terminal, and the other end is connected to a corresponding matching node. The method includes the following steps: Standard data is obtained by detecting the preset module under test based on the calibrated current detection module; The actual data is obtained by using a high-precision current sensing amplifier to detect the preset module under test. Compensation data is calculated based on standard data and actual data, and constant current source configuration is generated based on the compensation data and a preset compensation database. A bias constant current source is set at the connection between the input resistor R2 and the corresponding matching node. The bias constant current source has a sampling terminal, which is connected to the positive input terminal to sample the positive input level. The bias constant current source takes the positive input level as input and combines it with the constant current source configuration to output an adaptive current. The adaptive current is positively correlated with the positive input level. The adaptive current is passed through the input resistor R2 to generate an adaptive voltage. The adaptive voltage is used to compensate for the amplification factor of the high-precision current sensing amplifier.

[0007] By adopting the above technical solution, a precise constant current source configuration is generated by matching calibration data with actual detection data. The bias constant current source samples the positive input level and outputs an adaptive current, which is then used to generate an adaptive voltage via R2. This can accurately offset the resistance changes and amplification factor drift caused by substrate parasitic effects in the input resistors R1 and R2 under wide common-mode voltage fluctuations. This effectively reduces current detection errors and significantly improves the detection accuracy and working stability of the amplifier in the full common-mode input range. At the same time, it can adapt to different current detection conditions and ensure that the amplification factor remains stable and reliable.

[0008] Furthermore, the bias constant current source includes an operational amplifier and an NMOS transistor. The non-inverting input terminal of the operational amplifier is connected to a first resistor R11, and the other end of the first resistor R11 forms a sampling terminal and is electrically connected to the positive input terminal. The non-inverting input terminal of the operational amplifier is also grounded through a second resistor R10. The negative input terminal of the operational amplifier is grounded through a third resistor R9, and the negative input terminal of the operational amplifier is electrically connected to the source of the NMOS transistor. The output terminal of the operational amplifier is electrically connected to the gate of the NMOS transistor. The drain of the NMOS transistor is electrically connected to the connection node between the input resistor R2 and the second input terminal of the common-gate amplification structure. The voltage at the sampling terminal is sampled and divided using the first resistor R11 and the second resistor R10, and an adaptive current I is generated through a constant current NMOS transistor. OS , that is I OS =(V CSP ×R10 / (R10+R11)) / R9; Adaptive current I OS The corresponding adaptive voltage V is generated through the input resistor R2. os_CSN V OS_CSN =I OS ×R2; Adaptive voltage enables the output V of the high-precision current sense amplifier CSThe current sampling value is corrected, V CSP V is the voltage across the positive input terminal of the input resistor R1. CSN The voltage across the negative input terminal of input resistor R2 is the voltage. The output of the high-precision current sense amplifier is grounded through R7. V CS =(V CSP -(V) CSN -V OS_CSN ))×R7 / R1=(V CSP -V CSN +V OS_CSN ) × R7 / R1; When the resistance of the input resistor R1 increases, it causes V CS After becoming smaller, V is introduced. os_CSN Compensation V CS .

[0009] By adopting the above technical solution, the positive input level V is controlled through an operational amplifier, an NMOS transistor, and a voltage divider resistor network. CSP Perform sampling and voltage division to generate a voltage distribution with V CSP Positively correlated adaptive current I OS And it is converted into an adaptive voltage V through the input resistor R2. OS_CSN Introduced into the amplifier output formula, it can accurately offset the amplification factor deviation caused by substrate parasitic effects and resistance drift of input resistors R1 and R2 due to common-mode voltage fluctuations, realize adaptive correction of output current sampling values ​​across the entire common-mode input range, and effectively ensure the detection accuracy and linear stability of the high-precision current sensing amplifier.

[0010] Furthermore, the method also includes the following steps: The current level to be detected is obtained. The larger the current value, the larger the current level, and the smaller the current value, the smaller the current level. The corresponding resistance value is matched from the preset resistance database according to the current level. In the resistance database, the current level is divided into multiple continuous steps. Each step corresponds to a different range of current levels and each step corresponds to a different resistance value. The resistance value of the third resistor R9 is determined based on the matched resistance value. The difference between the matched resistance value and the resistance value of the third resistor R9 is less than the preset set difference. The lower the current level, the smaller the set difference; the higher the current level, the larger the set difference.

[0011] By adopting the above technical solution, the current level is divided into multiple continuous steps and corresponding resistance values ​​are preset. The resistance value of the third resistor R9 is matched according to the current level to be detected. The lower the current level, the smaller the setting difference, and the higher the current level, the larger the setting difference. This allows for precise adjustment of the adaptive compensation current for different current level scenarios, ensuring that the compensation intensity matches the current conditions. In low-current, high-precision scenarios, a smaller setting difference ensures compensation accuracy, while in high-current scenarios, a slightly larger setting difference balances cost and adaptability. This effectively optimizes the common-mode compensation effect across the entire current level range, reduces the difficulty of circuit debugging, and improves the versatility and mass production adaptability of the solution.

[0012] Furthermore, the method also includes the following steps: Before compensation, the detected current is obtained to generate the current value before compensation, and the resistance compensation coefficient is calculated based on the current value before compensation and the preset current compensation parameters. The target resistance value is calculated based on the resistance compensation coefficient and the base resistance value. If the target resistance value is within the adjustment range of the third resistor R9, the resistance value of the third resistor R9 is adjusted to the target resistance value during compensation; otherwise, the resistance value of the third resistor R9 is adjusted to the minimum value of the adjustment range during compensation.

[0013] By adopting the above technical solution, the resistance compensation coefficient is calculated from the current value before compensation, and then the target resistance value of the third resistor R9 is obtained, realizing stepless and precise adjustment of the compensation current. When the target resistance value is within the adjustment range, the adaptive compensation current can be precisely matched with the deviation of the actual amplification factor. When it exceeds the range, the minimum value of the adjustment range is taken to ensure that the basic compensation function of the circuit does not fail. This not only makes up for the lack of precision of the stepped resistor adjustment, but also takes into account the flexibility of the compensation scheme and the reliability of the circuit. It can dynamically optimize the compensation intensity according to the actual error.

[0014] Furthermore, the bias constant current source includes a voltage acquisition unit, a control unit, and a programmable current source unit; The voltage acquisition unit acquires the positive input level at the sampling terminal to generate voltage data, and sends the voltage data to the control unit. The control unit converts the voltage data into target current data according to a preset conversion algorithm, and generates a current source control command based on the target current data, and sends the current source control command to the current source unit. The current source unit generates the corresponding current in response to the current source control command and flows the current through the input resistor R2.

[0015] By adopting the above technical solution, a digital compensation architecture is constructed through a voltage acquisition unit, a control unit, and a programmable current source unit. The positive input level can be acquired in real time, and the control unit can dynamically generate the target compensation current command according to a preset algorithm. This drives the programmable current source unit to output a precise adaptive compensation current that flows through R2. Stepless and precise adjustment of the compensation current can be achieved without modifying the hardware. This not only greatly improves the flexibility and accuracy of common-mode compensation and can adapt to the compensation needs of different operating conditions and error scenarios, but also supports software configuration, online calibration, and parameter upgrades, reducing hardware debugging costs.

[0016] Furthermore, the conversion algorithm includes the following sub-steps: The voltage level is calculated based on the voltage data and the preset base value. The larger the voltage data, the larger the voltage level, and the smaller the voltage data, the smaller the voltage level. The corresponding current value is then matched from the preset current database based on the voltage level. In the current database, the voltage level is divided into multiple continuous steps, each step corresponding to a different voltage level range, and each step corresponding to a different current value; or, the current database is divided into multiple continuous segments according to the voltage level, each continuous segment corresponding to a different voltage level range, each continuous segment corresponding to a current continuous line, and a one-to-one correspondence between voltage data and current value is defined on the current continuous line. The target current data is determined based on the matched current value.

[0017] By adopting the above technical solution, the collected voltage data is divided into stepped segments or continuous segments according to voltage levels, supporting two modes: stepped current matching or stepless current matching based on continuous current lines. This can simplify the control logic, reduce computational complexity and hardware implementation costs by presetting the current value of the stepped segments, and efficiently complete the stepped compensation current adjustment. It can also achieve smooth and accurate output of the compensation current as the voltage changes through the continuous current lines, making the compensation current highly compatible with the changes in the positive input level.

[0018] Furthermore, the method also includes the following steps: The control unit acquires the output value of the high-precision current sensing amplifier, calculates the fluctuation value and average value of the output value within a preset time period, and calculates the fluctuation percentage based on the fluctuation value and average value. The coefficients corresponding to the voltage and current values ​​in the current continuous line are adjusted based on the negative correlation of the fluctuation percentage.

[0019] By adopting the above technical solution, closed-loop adaptive calibration of the compensation current amplitude is achieved. The compensation intensity can be dynamically corrected according to the actual output fluctuation state, effectively suppressing the output fluctuation caused by compensation deviation, device characteristic drift or operating condition changes.

[0020] Secondly, this application provides a common-mode compensation circuit for a high-precision current sensing amplifier, employing the following technical solution: A common-mode compensation circuit for a high-precision current sensing amplifier is provided, applied to a current sensing sampling amplifier, wherein the input stage of the current sensing sampling amplifier is a common-gate amplification structure; the common-gate amplification structure is configured with a positive input terminal and a negative input terminal, the positive input terminal is connected to the first input terminal of the common-gate amplification structure via an input resistor R1, and the negative input terminal is connected to the second input terminal of the common-gate amplification structure via an input resistor R2; The common-mode compensation circuit includes an operational amplifier and an NMOS transistor; The non-inverting input terminal of the operational amplifier is connected to a first resistor R11, and the other end of the first resistor R11 forms a sampling terminal and is electrically connected to the positive input terminal; the non-inverting input terminal of the operational amplifier is also grounded through a second resistor R10. The negative input terminal of the operational amplifier is grounded through the third resistor R9, and the negative input terminal of the operational amplifier is electrically connected to the source of the NMOS transistor; the output terminal of the operational amplifier is electrically connected to the gate of the NMOS transistor. The drain of the NMOS transistor is electrically connected to the connection node between the input resistor R2 and the second input terminal of the common-gate amplifier structure.

[0021] By adopting the above technical solution, the common-mode compensation circuit uses an operational amplifier, an NMOS transistor, and resistors R9, R10, and R11 to form a closed-loop bias constant current source structure. The voltage at the positive input terminal of the amplifier is sampled by R11, and a precise voltage feedback is formed by the voltage divider of R10. The operational amplifier drives the NMOS transistor to generate an adaptive compensation current that is positively correlated with the positive input level and injects it into the R2 connection node. This can dynamically offset the resistance drift and amplification factor deviation of the input resistors R1 and R2 caused by substrate parasitic effects under a wide common-mode voltage, significantly improving the current detection accuracy and linear stability.

[0022] Furthermore, the first resistor R11, the second resistor R10 and / or the third resistor R9 are rotary adjustable resistors or multi-position selector resistor arrays.

[0023] By adopting the above technical solution, using a knob-adjustable resistor or a multi-position selector resistor array, the resistance value of the compensation branch can be flexibly adjusted according to the actual common-mode voltage range, current detection accuracy requirements and application conditions, accurately adapting and optimizing the compensation current, and simplifying the circuit debugging and on-site calibration process.

[0024] Thirdly, this application provides a high-precision current sensing amplifier, which adopts the following technical solution: A high-precision current sensing amplifier includes a differential input sampling unit, a common-gate amplification input stage, a common-mode compensation circuit, and subsequent amplification and output stages; The differential input sampling unit includes an input resistor R1 and an input resistor R2. The positive terminal of the external current sampling CSP is connected to the common gate amplification input stage through the input resistor R1, and the negative terminal of the external current sampling CSN is connected to the common gate amplification input stage through the input resistor R2. The common-gate amplifier input stage includes a high-side input stage and a low-side input stage. The high-side input stage includes a first MOSFET, a second MOSFET, load resistors R3 and R4, and a first operational amplifier. The gate of the first MOSFET is connected to a fixed bias voltage Vb2, its source is connected to the output node of the input resistor R1, and its drain is connected to the power supply VDD via the load resistor R3. The drain of the second MOSFET is connected to the power supply VDD via the load resistor R4, and its source is connected to the signal node of the low-side input stage of the common-gate amplifier. The non-inverting input of the first operational amplifier is connected to the source of the first MOSFET. The inverting input terminal is connected to the source of the second MOS transistor, and the output terminal is connected to the gate of the second MOS transistor. The low-side input stage of the common-gate amplifier includes a third MOS transistor, a fourth MOS transistor, resistors R5 and R6, and a second operational amplifier. The gate of the third MOS transistor is connected to a fixed bias voltage Vb1, the source is grounded through resistor R5, and the drain is connected to the non-inverting input terminal of the second operational amplifier. The source of the fourth MOS transistor is grounded through resistor R6, the drain is connected to the inverting input terminal of the second operational amplifier, and the gate is connected to the output terminal of the second operational amplifier. The output node of the input resistor R2 is connected to the signal path of the low-side input stage of the common-gate amplifier. The common-mode compensation circuit includes a third operational amplifier, an NMOS transistor, a first resistor R11, a second resistor R10, and a third resistor R9. The non-inverting input of the third operational amplifier is connected to the positive terminal of the external current sampling CSP via the first resistor R11 and grounded via the second resistor R10. The inverting input of the third operational amplifier is grounded via the third resistor R9 and electrically connected to the source of the NMOS transistor. The output of the third operational amplifier is connected to the gate of the NMOS transistor. The drain of the NMOS transistor is connected to the connection node between the input resistor R2 and the low-side input stage of the common-gate amplifier. The subsequent amplification and output stage includes a fifth MOS transistor, a sixth MOS transistor, a current source, resistors R7 and R8; the fifth and sixth MOS transistors form a PMOS differential amplifier structure, with their gates connected to the output terminals of the high-side input stage and low-side input stage of the common-gate amplifier, respectively; the drain of the sixth MOS transistor is connected to the current source and leads out to the output node V. ledcsp The subsequent amplification and output stage is grounded via resistor R7 and outputs a current sampling voltage V. cs .

[0025] By adopting the above technical solution, a complete architecture is constructed using differential input sampling, dual common-gate high-side / low-side input stages, adaptive common-mode compensation circuit, and subsequent amplification output stage. Relying on the symmetrical common-gate amplification structure and closed-loop control, stable operation is achieved across the entire common-mode input range. The common-mode compensation circuit samples the positive input level in real time and generates a matching adaptive compensation current, accurately offsetting the parasitic resistance drift and amplification factor deviation caused by wide common-mode voltage fluctuations. At the same time, the subsequent differential amplification output ensures signal linearity and stability. The overall circuit has high integration and strong anti-interference capability, significantly improving the accuracy, linearity, and adaptability of current detection. Attached Figure Description

[0026] Figure 1 It is a high-precision current sensing amplifier with common-mode compensation circuit.

[0027] Figure 2 This is a comparison chart of the system output current before and after adding a common-mode compensation circuit. Detailed Implementation

[0028] The embodiments of this application are described in detail below, and examples of the embodiments are shown in the accompanying drawings.

[0029] This application discloses a common-mode compensation method for a high-precision current sensing amplifier, referring to... Figure 1 This embodiment utilizes a common-mode compensation circuit based on a current-sensing amplifier. The high-precision current-sensing amplifier employs a common-gate amplification structure in its input stage, enabling stable operation under wide common-mode voltage input conditions. It is suitable for high-precision current sampling requirements in power management, motor drive, and industrial control scenarios. The common-gate amplification structure features two differential inputs: one positive input, connected to the preset bias node of the common-gate amplification structure via input resistor R1 (the first input); and the other negative input, connected to the corresponding node of the common-gate amplification structure via input resistor R2 (the second input). The external current sampling signal is input as a differential voltage, with the positive input voltage being V. CSP The negative input voltage is V CSN The amplifier amplifies and processes this differential signal, outputting a sampling voltage V that is proportional to the sampling current. CS .

[0030] The common-mode compensation method in this embodiment includes the following steps: Based on the calibrated high-precision current detection module, multi-condition detection is performed on the preset detection module (such as sampling resistors of different specifications and current paths under different operating conditions) to obtain standard current sampling data under different current and common-mode voltage conditions, and to establish an ideal reference benchmark with error-free operating conditions.

[0031] Using a high-precision current sensing amplifier to be compensated, the same preset test module is repeatedly tested under the same operating conditions to obtain the corresponding actual current sampling data. Due to the wide common-mode voltage fluctuation, the input resistors R1 and R2 will have a substrate bias effect, causing resistance drift, and the actual test data will deviate from the standard data.

[0032] By comparing standard data with actual data, the error difference under different operating conditions is calculated to obtain compensation data. Based on the preset compensation database, the compensation data is mapped to the configuration parameters of the bias constant current source, such as the target compensation current value under different common mode voltages and the resistance level configuration, to form a constant current source configuration scheme that is compatible with the current amplifier.

[0033] A bias constant current source is set at the connection between the input resistor R2 and the corresponding matching node, and its sampling terminal is connected to the positive input terminal of the amplifier (V). CSP The node is electrically connected and samples the positive input level in real time. The bias constant current source is based on the sampled V. CSP Combined with the generated constant current source configuration, the output is related to V. CSP The adaptive compensation current I with positive correlation at the node OS The current flows through the input resistor R2, generating an adaptive voltage V. OS_CSN This is superimposed on the signal path at the negative input terminal to correct the amplifier's amplification factor and offset the error caused by the drift of the input resistor value.

[0034] In this embodiment, the bias constant current source adopts a closed-loop structure of operational amplifier + NMOS transistor, combined with a voltage divider resistor network to achieve adaptive current output. The circuit connection and working principle are as follows: The non-inverting input of the operational amplifier is connected to the first resistor R11. The other end of the first resistor R11 forms the sampling terminal, which is connected to the positive input terminal (V) of the amplifier. CSP The node is electrically connected to achieve positive input level sampling; simultaneously, the non-inverting input of the operational amplifier is grounded through the second resistor R10, and the first resistor R11 and the second resistor R10 form a voltage divider circuit for V. CSP Voltage division is performed. The inverting input of the operational amplifier is grounded through the third resistor R9, and is electrically connected to the source of the NMOS transistor; the output of the operational amplifier is electrically connected to the gate of the NMOS transistor, forming a voltage follower closed-loop control structure. The drain of the NMOS transistor is electrically connected to the connection node between the input resistor R2 and the second input of the common-gate amplifier structure, and the compensation current is injected into the negative input signal path from there.

[0035] Based on the "virtual short" characteristic of operational amplifiers, the voltages at their non-inverting and inverting inputs are equal. Therefore, the source voltage of the NMOS transistor is equal to the voltage after voltage division: V S =V CSP ×R10 / (R10+R11) The voltage applied across the third resistor R9 generates the source current of the NMOS transistor. When the NMOS transistor operates in the saturation region, the drain current and source current are approximately equal, therefore the adaptive compensation current I... OS The calculation formula is: I OS =(V CSP ×R10 / (R10+R11)) / R9; This formula shows that I OS With V CSP They show a positive correlation, and the slope of the compensation current can be adjusted by adjusting the resistance values ​​of the third resistors R9, R10, and R11 to adapt to different error compensation requirements.

[0036] Compensation current I OS After flowing through the input resistor R2, a corresponding adaptive voltage V is generated. OS_CSN The formula is: V OS_CSN =I OS ×R2; The amplifier output terminal achieves the voltage output of the current sampling signal through the grounding resistor R7. The formula for the output voltage before compensation is: V CS =(V CSP -V CSN ) × R7 / R1; After introducing the compensation voltage, the corrected output voltage formula is: V CS =(V CSP -(V) CSN -V OS_CSN ))×R7 / R1=(V CSP -V CSN +V OS_CSN ) × R7 / R1; When wide common-mode voltage fluctuations cause an increase in the input resistance R1, the uncompensated V CS It will decrease as R1 increases; at this time, the positively correlated V OS_CSN As a positive voltage, superimposed on the differential signal, it can affect V. CS Compensation is performed to counteract the output deviation caused by the drift of the R1 resistance, so that V CS It always maintains a linear correspondence with the detected current.

[0037] Based on the above-mentioned bias constant current source compensation scheme, this embodiment further proposes an adaptive configuration method for the third resistor R9 value based on the current level. By matching the resistor parameters in stages, the balance between compensation accuracy and debugging cost under different current conditions is optimized. The specific implementation method is as follows: In this embodiment, the magnitude of the current to be detected directly corresponds to different current levels. The classification logic is: the larger the current value, the higher the current level; the smaller the current value, the lower the current level. In practical applications, multiple current level ranges can be predefined according to the current range of the product application scenario, such as: micro-current level (0~1A), low current level (1~10A), medium current level (10~100A), and high current level (above 100A). Each level corresponds to a specific current value range, and the error characteristics of the amplifier and the requirements for compensation accuracy differ significantly within different ranges. During actual detection, the real-time value of the current to be detected is obtained through the front-end sampling circuit or controller to determine its current level range.

[0038] To achieve rapid and accurate matching of the third resistor R9 value under different current levels, this embodiment pre-constructs a resistor database. This database divides the current levels into multiple continuous stepped segments, each corresponding to a specific current level range. Each range has a pre-configured optimal reference resistance value for the third resistor R9. These reference values ​​are obtained through prior calibration tests: a comprehensive test of the amplifier error characteristics under different current levels is conducted, and combined with the compensation current formula and output voltage correction logic described earlier, the required third resistor R9 value to achieve the optimal compensation effect is calculated and stored in the database. For example, the reference value for the third resistor R9 is 100kΩ for the micro-current level range, 50kΩ for the low current level, 20kΩ for the medium current level, and 10kΩ for the high current level; different resistance values ​​correspond to different compensation current intensities. In practical applications, based on the current level range to which the current to be detected belongs, the corresponding reference resistance value is directly matched from the resistor database, achieving rapid positioning of the target resistance value for the third resistor R9.

[0039] After obtaining the reference resistance value, the actual resistance value of the third resistor R9 needs to be determined based on this reference value. The difference between the actual resistance value of the third resistor R9 and the reference value must be less than a preset difference. This preset difference is not a fixed value, but is directly related to the current rating. The lower the current level (such as microcurrent or low current scenarios), the smaller the setting difference should be. The higher the current level (such as medium and high current scenarios), the larger the setting difference should be.

[0040] For example, the set difference is ±1% for the micro-current level, ±3% for the low-current level, ±5% for the medium-current level, and ±10% for the high-current level; the logic behind these settings lies in the different compensation accuracy requirements at different current levels. In low-current scenarios, the amplifier's output signal amplitude is small, and the drift of the input resistors R1 and R2 has a greater impact on the amplification factor, requiring extremely high compensation accuracy. In this case, the value of the third resistor R9 should be as close as possible to the reference value, and the set difference should be smaller to ensure the accuracy of the compensation current and avoid amplifying low-current detection errors due to compensation current deviations.

[0041] In high-current scenarios, the output signal amplitude is large, and the error caused by resistor drift accounts for a relatively small proportion, so the requirements for compensation accuracy can be appropriately relaxed. In this case, the set difference can be appropriately increased, and resistors with lower accuracy and lower cost can be used, reducing circuit cost and debugging difficulty without affecting the overall detection accuracy.

[0042] Combined with the compensation current formula I OS =(V CSP The equation ×R10 / (R10+R11)) / R9 shows that the resistance value of the third resistor R9 directly determines the magnitude of the compensation current: the smaller the third resistor R9, the larger the compensation current, suitable for high-current scenarios with larger errors; the larger the third resistor R9, the smaller the compensation current, suitable for low-current scenarios with smaller errors. By configuring the resistance value of the third resistor R9 in stages, the compensation intensity can be precisely matched with the error level under different operating conditions, avoiding the problems of over-compensation or under-compensation.

[0043] To address the insufficient accuracy issue in stepped matching, this embodiment further introduces a pre-compensation current feedback calibration mechanism. Through real-time error quantization and target resistance calculation, it achieves fine-grained dynamic adjustment of the third resistor R9. The specific implementation method is as follows: Before the common-mode compensation function is officially activated, the control unit first collects the output signal of the amplifier to be compensated, and obtains the current value before compensation through the front-end sampling circuit or the built-in digital control module. This value is the actual measurement result of the amplifier on the current being detected in the state without common-mode compensation.

[0044] Due to factors such as wide common-mode voltage fluctuations, device manufacturing process variations, and temperature drift, there will be a deviation between the current value before compensation and the ideal standard current value. This deviation is the core basis for subsequent compensation. For example, at a certain low current level, the amplifier's output current value is 5% lower than the standard value because the input resistance R1 increases due to the common-mode voltage. This deviation will be directly reflected in the current value before compensation, providing an accurate error benchmark for calculating the compensation coefficient.

[0045] In this embodiment, the preset current compensation parameter is the standard reference current value or error correction benchmark parameter obtained from the previous calibration. This parameter is stored in the non-volatile memory of the control unit and corresponds to the ideal current level of different current levels. It can be obtained through factory calibration or on-site calibration.

[0046] The control unit calculates the resistance compensation coefficient through division based on the collected pre-compensation current value. The logic is to quantify the deviation ratio between the current actual current and the standard current, which can be expressed as: K=I comp_before / I ref Among them, I comp_before To compensate for the previous current value, I ref The preset current compensation parameter (standard reference current value) is K, which is the resistance compensation coefficient.

[0047] This coefficient directly reflects the direction and extent of the error: When K < 1, it means that the current value before compensation is lower than the standard value. The compensation current needs to be increased to improve the amplifier output. Correspondingly, the resistance value of the third resistor R9 needs to be reduced. When K > 1, it means that the current value before compensation is higher than the standard value. The compensation current needs to be reduced to reduce the amplifier output. Correspondingly, the resistance value of the third resistor R9 needs to be increased. When K=1, it means there is no obvious error at present, and the third resistor R9 can maintain the compensation balance by keeping the reference resistance value.

[0048] Based on the resistance compensation coefficient K and the preset base resistance value R of the third resistor R9 9_base Specifically, the target resistance value R of the third resistor R9 can be calculated using the reference resistance value obtained from the step matching in the aforementioned resistance database, or the factory-calibrated reference resistance value. 9_target Combining the compensation current formula I OS =(V CSP ×R10 / (R10+R11)) / R9, the resistance of the third resistor R9 is inversely proportional to the compensation current, therefore the formula for calculating the target resistance is: R 9_target =R 9_base ×K; This formula is designed to directly correspond to the adjustment logic of the compensation current: when the current value before compensation is too low (K<1), the target resistance is less than the base resistance, and the compensation current I is increased by reducing the resistance of the third resistor R9. OS Increase the amplifier output voltage; when the current value before compensation is too high (K>1), the target resistance value is greater than the basic resistance value. By increasing the resistance value of the third resistor R9, the compensation current IOS is reduced, the amplifier output voltage is reduced, and the reverse correction of the error is achieved.

[0049] The control unit will calculate the target resistance value R 9_target The preset adjustment range of the third resistor R9 [R] 9_min ,R 9_max Compare the results and implement different adjustment strategies accordingly: If R 9_min ≤R 9_target ≤R 9_maxThis indicates that the target resistance value is within the adjustable range. Therefore, directly adjust the resistance value of the third resistor R9 to R... 9_target To achieve precise compensation; If R 9_target <R 9_min This indicates that the calculated target resistance value exceeds the minimum adjustment limit of the third resistor R9. In this case, the resistance value of the third resistor R9 should be adjusted to the minimum value R within the adjustment range. 9_min Since the smaller the third resistor R9 is, the larger the compensation current is, adjusting it to the minimum value can provide the maximum compensation current allowed by the circuit, avoiding the inability to achieve compensation due to the target resistance value being too low, and preventing abnormal circuit operating point due to over-adjustment; If R 9_target >R 9_max The third resistor R9 can be adjusted to its maximum value R. 9_max This provides minimal compensation current and suppresses excessive output deviation.

[0050] To further enhance the flexibility, accuracy, and scenario adaptability of compensation, this embodiment also provides a digital architecture bias constant current source solution. Through the collaborative work of the voltage acquisition unit, control unit, and programmable current source unit, the software configuration and dynamic adjustment of the compensation current are realized. The specific implementation method is as follows: The bias constant current source in this embodiment adopts a three-level digital architecture of "front-end acquisition - digital control - back-end output", which is specifically divided into three units: Voltage acquisition unit: responsible for sampling the level signal at the positive input terminal of the amplifier, realizing the conversion of analog voltage to digital data; Control unit: As the core of digital control, it executes voltage-to-current conversion algorithms and generates current source control commands; Programmable current source unit: Receives control commands and outputs adaptive compensation current, completing the final execution of error correction. The three units communicate via an internal digital bus or dedicated interface, forming a closed-loop control link. This replaces the hardware compensation logic of fixed resistors and operational amplifiers in traditional analog circuits, enabling software-defined compensation strategies.

[0051] Specific implementation method and workflow of the voltage acquisition unit: The input terminal of the voltage acquisition unit and the sampling terminal (i.e., the positive input terminal V) of the amplifier. CSP The node is electrically connected and its function is to acquire the positive input level in real time and convert it into digital voltage data.

[0052] Hardware structure: It can be implemented using a high-precision analog-to-digital converter (ADC), such as a 12-bit / 16-bit successive approximation ADC; the front end can be configured with a low-noise buffer amplifier or voltage divider circuit to condition the input voltage to match the input range of the ADC, while suppressing common-mode noise interference.

[0053] Working process: The ADC samples V at a preset sampling rate (e.g., 1kHz~10kHz). CSP Periodic sampling converts the analog voltage signal into corresponding digital voltage data (such as a 16-bit binary value), and this data is sent to the control unit via an internal communication interface (such as SPI, I2C, or the chip's internal bus). This process achieves the digital quantization of the analog signal.

[0054] Specific implementation methods and workflow of the control unit: The control unit is the core of the digital bias constant current source. It can be implemented using a microcontroller (MCU), field-programmable gate array (FPGA), or dedicated digital signal processing (DSP) module. It internally stores preset conversion algorithms and compensation databases. The specific workflow is as follows: Voltage data reception and parsing: Receives digital voltage data sent by the voltage acquisition unit, filters and calibrates the data to eliminate sampling noise and temperature drift error, and obtains a stable positive input level quantization value; Target current data calculation: Based on a preset conversion algorithm, the voltage data is converted into target current data. This conversion algorithm can employ either the stepped segment matching mode or the current continuous line mapping mode described in the previous embodiments. Stepped mode: Maps voltage data to a preset voltage level range and matches the corresponding target current level; Continuous current mode: The target current value corresponding one-to-one with the voltage data is directly calculated through linear or nonlinear mapping relationships; Control command generation and transmission: Based on the target current data, corresponding current source control commands are generated. For example, for a DAC-type current source unit, a corresponding digital configuration word is generated; for a multi-stage current source array, a gating control signal for the current branch is generated; and for a PWM-controlled current source, a corresponding duty cycle control signal is generated. The control commands are sent to the programmable current source unit through a dedicated interface to drive it to output the target current.

[0055] Specific implementation methods and workflow of the programmable current source unit: The programmable current source unit is a configurable digitally controlled current output structure. After receiving control commands, it generates a compensation current corresponding to the target current data and injects it into the connection node of the input resistor R2. The specific implementation method is as follows: Hardware structure: Can be implemented in various forms: Current source based on digital-to-analog converter (DAC): The DAC receives control commands and generates an analog control voltage, which drives an NMOS transistor to form a constant current source structure. The current can be continuously adjusted by adjusting the DAC output voltage. Multi-stage current source array: It consists of multiple fixed current source branches with different current values ​​connected in parallel. The control command selects some branches and outputs a stepped compensation current through combination. PWM-controlled current source: By adjusting the duty cycle of the PWM signal, the conduction ratio of the switching transistor is controlled, thereby adjusting the average current. Working process: The current source unit responds to the control command, generates a compensation current IOS corresponding to the target current data, and injects this current into the connection node between the input resistor R2 and the second input terminal of the common-gate amplifier structure. The compensation current flowing through R2 generates an adaptive voltage V. OS_CSN =I OS ×R2 is superimposed on the low-side signal path to correct the amplifier gain. Its compensation logic is completely consistent with the aforementioned analog scheme.

[0056] In the above embodiment of the digital bias constant current source, the function of the control unit is to convert the acquired voltage data into target current data through a preset conversion algorithm to achieve dynamic matching of the compensation current. This embodiment provides a detailed explanation of the conversion algorithm, offering two switchable mapping modes that balance compensation efficiency and accuracy. The specific implementation method is as follows: The control unit first preprocesses the voltage data sent by the voltage acquisition unit, and calculates the corresponding voltage level based on the preset level base value through division.

[0057] The base value for the voltage level is a preset reference voltage value, which can be set through pre-calibration or design, for example, by setting it to 1V, 5V, etc., based on the typical step size of the common-mode voltage. The formula for calculating the voltage level is: N = V data / V base In the formula, V data V represents the digital voltage data corresponding to the acquired positive input level. base N is the base value for the voltage level, and N is the calculated voltage level.

[0058] Under this calculation logic, the larger the voltage data, the higher the corresponding voltage level N; the smaller the voltage data, the lower the voltage level N. Through this calculation, continuously changing positive input levels are mapped to quantifiable voltage levels, which facilitates segmented management of a wide range of common-mode voltages and provides a standardized index dimension for rapid matching of subsequent current databases.

[0059] The control unit matches the corresponding current value from a preset current database based on the calculated voltage level. The current database provides two selectable matching modes: stepped segment matching mode and continuous segment current continuous line matching mode. The two modes can be selected according to the accuracy and real-time requirements of the application scenario.

[0060] 1. Tiered segment matching mode In this mode, the current database divides the voltage level into multiple consecutive steps, each step corresponding to an independent voltage level range, and each range is pre-configured with a fixed current value.

[0061] For example, the voltage levels can be divided into multiple intervals such as [0,5), [5,10), and [10,20), with each interval corresponding to current values ​​of 10μA, 20μA, and 30μA, respectively. These current values ​​are obtained through preliminary calibration tests: the error characteristics of the amplifier under different voltage levels are comprehensively tested, and the correspondence between compensation current and error is combined to determine the current value that achieves the optimal compensation effect in each voltage interval, and stored in the current database.

[0062] During actual matching, the control unit determines the stepped segment range to which the calculated voltage level N belongs and directly reads the corresponding current value for that range. The advantage of this mode is that the matching logic is simple and the amount of calculation is small. It does not require complex real-time calculations and can quickly complete the current value matching. It is suitable for scenarios with high requirements for response speed and moderate requirements for compensation accuracy. At the same time, it is also easy to implement in hardware logic and reduces the computing power requirements of the control unit.

[0063] 2. Continuous current matching mode for continuous segments In this mode, the current database divides the voltage level into multiple continuous segments, each corresponding to an independent voltage level range, and each continuous segment corresponds to a current continuous line, which defines a one-to-one correspondence between voltage data and current values.

[0064] Specifically, the current continuity line within each continuous segment can be obtained by fitting previously calibrated data, and can be a linear or nonlinear relationship: Under linear relationships, the current continuous line can be expressed as I = a × V data +b, where a is the slope and b is the intercept. The slope and intercept of different continuous segments can be adjusted according to the error characteristics within the interval. For example, the slope is smaller in the low voltage level interval and larger in the high voltage level interval to adapt to the error change rate under different common mode voltages; Under nonlinear relationships, the current continuous line can be obtained through polynomial fitting, piecewise linear fitting, etc., which better matches the nonlinear error characteristics of the amplifier over a wide common-mode voltage range.

[0065] During actual matching, the control unit first determines the continuous segment interval to which voltage level N belongs, reads the corresponding current continuous line parameters for that interval, and then substitutes the collected voltage data into the current continuous line formula to calculate the corresponding current value. The advantage of this mode is that it achieves a one-to-one mapping between voltage data and current values. The compensation current can be continuously adjusted according to changes in voltage data, eliminating the interval boundary errors of the stepped segment mode, resulting in higher compensation accuracy. It is particularly suitable for scenarios with high-precision current detection and wide common-mode voltage input, accurately matching error levels under different voltages and achieving smooth compensation without step jumps.

[0066] Regardless of whether the stepped segment matching mode or the continuous segment current continuous line matching mode is used, the control unit uses the matched current value as the target current data. Subsequently, based on this data, a current source control command is generated and sent to the programmable current source unit to drive it to output the corresponding compensation current, thereby correcting the amplifier amplification factor.

[0067] This embodiment provides two flexible current value matching modes by refining the conversion algorithm. Users can choose or switch between them according to the needs of the application scenario: the stepped segment mode is simple to implement and has a fast response, making it suitable for low-power and real-time priority scenarios; the continuous segment current continuous line mode has higher accuracy and stronger adaptability, making it suitable for high-precision and wide-condition scenarios. This greatly improves the versatility and adaptability of the compensation scheme and can meet the compensation needs of different current sensing amplifiers.

[0068] Based on the above embodiment of the voltage-to-current conversion algorithm based on the current continuum line, this embodiment further introduces a closed-loop feedback calibration mechanism. By monitoring the output fluctuation state of the high-precision current sensing amplifier in real time, the correspondence coefficient between voltage data and current value in the current continuum line is dynamically corrected, thereby achieving adaptive optimization of the compensation strategy. The specific implementation method is as follows: To evaluate the effectiveness of the current common-mode compensation strategy, the control unit first periodically collects and analyzes the output value of the high-precision current sensing amplifier. The specific steps are as follows: Output value acquisition: The control unit acquires the current sampling voltage value V at the amplifier output terminal in real time through a built-in sampling circuit or a dedicated interface. CS The sampling frequency needs to be much higher than the amplifier's operating bandwidth, such as 1kHz to 10kHz, to ensure that subtle fluctuations in the output signal can be captured.

[0069] Statistical calculations within a set time period: Select a preset time period, such as 100ms to 1s, which can be adjusted according to the response requirements of the application scenario. Perform statistical analysis on multiple output value samples collected within this time period: Calculate the average of the output values CS, which is the arithmetic mean of all output values ​​within a set time period, reflects the center level of the output signal and is used to eliminate the impact of short-term noise on fluctuation assessment; Calculate the fluctuation value ΔV of the output value. CS Two definition methods can be used: ① Set the difference between the maximum and minimum values ​​of the output value within a set time period to directly quantify the peak-to-peak fluctuation amplitude of the signal; ② Set the standard deviation of the output value within a set time period to reflect the dispersion of the signal, which is more in line with the random fluctuation scenario caused by noise.

[0070] Fluctuation percentage calculation: Based on the fluctuation value and the average value, calculate the fluctuation percentage P of the output signal using the formula: P = ΔV CS / CS ×100%; This percentage quantifies the relative fluctuation of the output signal: the larger the fluctuation percentage, the worse the stability of the output signal under the current compensation strategy, the deviation in the matching relationship between the compensation current and voltage data, and the easy occurrence of signal oscillation or error amplification; the smaller the fluctuation percentage, the more stable the compensation effect, and the better the linearity and stability of the output signal.

[0071] The control unit adjusts the correlation coefficient between voltage data and current value in the current continuous line based on the calculated fluctuation percentage P. The larger the fluctuation percentage, the lower the response strength of the compensation current; the smaller the fluctuation percentage, the more the response strength of the compensation current can be appropriately increased, forming a negative feedback closed loop to suppress the fluctuation of the output signal.

[0072] Taking the aforementioned linear current continuous line as an example, the correspondence between voltage data and current values ​​can be expressed as: I = a × V data +b Where a is the slope coefficient (compensation strength coefficient), which directly determines the rate at which the compensation current changes with the voltage data; b is the intercept coefficient, corresponding to the base compensation current. In this embodiment, the dynamic optimization of the compensation strength is mainly achieved by adjusting the slope coefficient a.

[0073] The control unit gradually adjusts the slope coefficient a based on the magnitude of the fluctuation percentage P. When P > Pmax (Pmax is the preset upper limit threshold for the fluctuation percentage, such as 5%), it indicates that the current compensation intensity is too high, and the compensation current changes too quickly with the voltage data, causing the output signal to oscillate. In this case, the slope coefficient 'a' needs to be reduced, for example, by using formula a new =a old ×(1-k×(PP max )), where k is a preset adjustment step size coefficient (e.g., 0.1), which reduces the rate of change of the compensation current, decreases the response strength of the compensation, and suppresses output fluctuations; When P < P min (P) minWhen the percentage fluctuation reaches the preset lower limit (e.g., 1%), it indicates that the current compensation strength is insufficient and cannot effectively offset the influence of common-mode voltage fluctuations, but the output signal does not oscillate significantly. In this case, the slope coefficient 'a' can be appropriately increased, for example, by using formula a... new =a old ×(1+k×(P min -P)) improves the response sensitivity of the compensation current and enhances the error correction capability; When P min ≤P≤P max When the value is equal, it indicates that the current compensation state is stable and the coefficient remains unchanged, thus avoiding unnecessary adjustments that could introduce additional errors.

[0074] The adjustment process adopts a gradual strategy, with each adjustment step not exceeding 10% of the initial slope coefficient to prevent sudden changes in the coefficient that could lead to system instability. At the same time, after adjustment, the system re-enters the fluctuation monitoring process to form a closed-loop feedback, ensuring that the fluctuation percentage is always kept within a reasonable range.

[0075] This embodiment also provides a common-mode compensation circuit for a high-precision current sensing amplifier, which is applied to a current sensing sampling amplifier with a common-gate amplification structure in the input stage. It aims to solve the problem that the input resistance drifts due to the substrate bias effect in a wide common-mode voltage input scenario, which leads to the deviation of the amplifier amplification factor and the decrease in current sensing accuracy.

[0076] The input stage of the current-sensing sampling amplifier is a common-gate amplifier structure, which has a positive input terminal and a negative input terminal: the positive input terminal (connected to the positive terminal CSP of the external current sampling) is connected to the first input terminal of the common-gate amplifier structure via input resistor R1; the negative input terminal (connected to the negative terminal CSN of the external current sampling) is connected to the second input terminal of the common-gate amplifier structure via input resistor R2. The differential voltage signal (V) generated when the external current flows through the sampling resistor... CSP -V CSN The inputs (R1 and R2) are fed into the common-gate amplification structure to complete the initial amplification.

[0077] The common-mode compensation circuit is an independent bias constant current source structure. Its core function is to sample the common-mode voltage at the positive input terminal, generate an adaptive compensation current that is positively correlated with the common-mode voltage, and inject it into the connection node between R2 and the second input terminal. The compensation voltage generated on R2 is used to offset the resistance drift error of the input resistor R1.

[0078] The common-mode compensation circuit mainly includes an operational amplifier, an NMOS transistor, a first resistor R11, a second resistor R10, and a third resistor R9. The connection relationship of each component is as follows: Voltage sampling branch: The non-inverting input of the operational amplifier is connected to the first resistor R11. The other end of R11 forms the sampling terminal, which is connected to the positive input terminal (V) of the amplifier. CSPThe node is electrically connected to achieve sampling of the positive input level; simultaneously, the non-inverting input of the operational amplifier is grounded through the second resistor R10, and R11 and R10 form a voltage divider circuit for V. CSP Voltage is divided and conditioned to prevent excessively high common-mode voltage from exceeding the input range of the operational amplifier.

[0079] Constant current control closed loop: The inverting input of the operational amplifier is grounded through the third resistor R9, and is electrically connected to the source of the NMOS transistor; the output of the operational amplifier is electrically connected to the gate of the NMOS transistor, forming a voltage follower closed loop control structure. Based on the "virtual short" characteristic of the operational amplifier, the voltage at the inverting input will follow the voltage divider at the non-inverting input, thus forming a stable current across the third resistor R9.

[0080] Compensation current output branch: The drain of the NMOS transistor is electrically connected to the connection node between the input resistor R2 and the second input terminal of the common gate amplifier structure. The compensation current generated by the operational amplifier driving the NMOS transistor will be injected into the signal path of R2 through this node.

[0081] According to the "virtual short" characteristic of operational amplifiers, the voltage at their non-inverting input terminal is equal to the voltage at their inverting input terminal, that is: V - =V + =V CSP ×R10 / (R10+R11) This voltage is applied across the third resistor R9. Since the operational amplifier input current is approximately zero, all the current across the third resistor R9 will flow into the source of the NMOS transistor. When the NMOS transistor operates in the saturation region, the drain current and source current are approximately equal, thus generating an adaptive compensation current I. OS For: I OS =(V CSP ×R10 / (R10+R11)) / R9; The compensation current flows through the input resistor R2, generating a corresponding adaptive voltage V. OS_CSN V OS_CSN =I OS ×R2; The compensation voltage is superimposed on the signal path at the negative input terminal, which can offset the amplification factor deviation caused by the increased resistance of R1 due to the rise in common-mode voltage. The amplifier output voltage without compensation is V. CS =(V CSP -V CSN After introducing compensation, V × R7 / R1 is corrected to: CS =(V CSP -(V) CSN -V OS_CSN ))×R7 / R1; When the resistance of R1 increases with the increase of the common-mode voltage, the compensation voltage VOS_CSN The synchronous increase offsets the output attenuation caused by the drift of R1, maintaining the linear correspondence between the amplifier output and the detected current.

[0082] As an optional implementation, the first resistor R11, the second resistor R10, and / or the third resistor R9 can be implemented using a knob-adjustable resistor or a multi-position selector resistor array: The knob-adjustable resistor can be directly adjusted via an external knob to adapt to the common-mode voltage range and error characteristics of different application scenarios, simplifying the debugging process; The multi-level selectable resistor array can select resistor branches with different resistance values ​​through digital switches to realize multi-level configuration of compensation current, which is convenient to switch the compensation intensity through software control and adapt to the detection requirements of different current levels.

[0083] The adjustable resistor design allows for flexible adjustment of the voltage division ratio and compensation current, significantly improving the circuit's versatility and ease of debugging. It can adapt to various operating conditions without modifying the hardware.

[0084] This embodiment also provides a high-precision current sensing amplifier that integrates the above-mentioned common-mode compensation circuit. The overall architecture includes a differential input sampling unit, a common-gate amplification input stage, a common-mode compensation circuit, and subsequent amplification and output stages. It can achieve high-precision current sensing over a wide common-mode voltage input range and is suitable for power management, motor drive, industrial control and other scenarios.

[0085] The differential input sampling unit includes input resistors R1 and R2. The positive terminal of the external current sampling, CSP, is connected to the high-side input stage of the common-gate amplifier input stage via input resistor R1, and the negative terminal of the external current sampling, CSN, is connected to the low-side input stage of the common-gate amplifier input stage via input resistor R2. R1 and R2 serve as the input resistors of the amplifier, providing the input path for the differential signal. They are also key components of the common-mode compensation circuit, where the compensation voltage is injected into the signal path through R2.

[0086] The common-gate amplifier input stage includes a symmetrically arranged high-side input stage and a low-side input stage. It suppresses common-mode voltage fluctuations through the common-gate structure and maintains the stability of the differential signal through closed-loop control.

[0087] The high-side input stage includes a first MOSFET, a second MOSFET, load resistors R3 and R4, and a first operational amplifier. The gate of the first MOSFET is connected to a fixed bias voltage Vb2, the source is connected to the output node of the input resistor R1 (i.e., the node after CSP through R1), and the drain is connected to the power supply VDD through the load resistor R3. The drain of the second MOSFET is connected to the power supply VDD via the load resistor R4, and the source is connected to the signal node of the low-side input stage of the common-gate amplifier. The non-inverting input of the first operational amplifier is connected to the source of the first MOSFET, the inverting input is connected to the source of the second MOSFET, and the output is connected to the gate of the second MOSFET, forming a closed-loop control structure.

[0088] This closed-loop control enables the source voltages of the first and second MOSFETs to follow each other, maintaining the common-mode stability of the differential input, suppressing the impact of common-mode voltage fluctuations on the high-side signal path, and providing a stable single-ended output signal for subsequent differential amplification.

[0089] The low-side input stage includes a third MOSFET, a fourth MOSFET, resistor R5, resistor R6, and a second operational amplifier. The gate of the third MOS transistor is connected to a fixed bias voltage Vb1, the source is grounded through resistor R5, and the drain is connected to the non-inverting input of the second operational amplifier. The source of the fourth MOSFET is grounded through resistor R6, the drain is connected to the inverting input of the second operational amplifier, and the gate is connected to the output of the second operational amplifier. The output node of input resistor R2 is connected to the signal path of the low-side input stage, and it is also the access point of the common-mode compensation circuit.

[0090] The low-side input stage and the high-side input stage form a symmetrical differential signal path, providing a superposition node for the common-mode compensation voltage and realizing the correction of the error signal.

[0091] The common-mode compensation circuit is the bias constant current source structure in the aforementioned embodiments, including a third operational amplifier, an NMOS transistor, a first resistor R11, a second resistor R10, and a third resistor R9. The non-inverting input of the third operational amplifier is connected to the positive terminal of the external current sampling CSP through the first resistor R11, and grounded through the second resistor R10 to achieve sampling voltage division of the positive input level; The inverting input of the third operational amplifier is grounded via the third resistor R9 and is electrically connected to the source of the NMOS transistor. The output of the third operational amplifier is connected to the gate of the NMOS transistor, driving the NMOS transistor to generate compensation current; The drain of the NMOS transistor is connected to the connection node between the input resistor R2 and the low-side input stage of the common-gate amplifier, injecting compensation current into the signal path to generate a compensation voltage to offset the resistance drift error of R1.

[0092] The subsequent amplification and output stage includes a fifth MOSFET, a sixth MOSFET, a 0.5μA current source, resistors R7 and R8. The fifth and sixth MOS transistors form a PMOS differential amplifier structure, with their gates connected to the outputs of the high-side input stage and the low-side input stage of the common-gate amplifier, respectively, to amplify the corrected differential signal a second time. The drain of the sixth MOSFET is connected to a 0.5μA current source to form a current load, and the output node V is also brought out. ledcsp ; The subsequent amplification and output stages are grounded through resistor R7, and the final output is a current sampling voltage Vcs that is proportional to the detected current, thus realizing the voltage output of the current signal.

[0093] The amplifier operation in this embodiment is as follows: the differential voltage generated by the external current is input to the high-side / low-side common gate input stage through R1 and R2. The common-mode compensation circuit synchronously samples the CSP voltage and generates a compensation current that is injected into node R2. The corrected differential signal is then amplified by subsequent differential signal to output a stable Vcs signal.

[0094] Reference Figure 2 Without this improved circuit, the high-side current amplifier would cause linearity imbalance in the system output current. By adding a common-mode compensation circuit, the amplification factor of the high-side current amplifier remains unchanged even with a significant increase in the input common-mode voltage (X-axis), thus preventing fluctuations in the system output current. Although embodiments of this application have been shown and described above, it is understood that these embodiments are exemplary and should not be construed as limiting the application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A common-mode compensation method for a high-precision current sensing amplifier, characterized in that, Based on a current sensing sampling amplifier with a common-gate amplification structure as the input stage, one input terminal of the common-gate amplification structure is provided with an input resistor R1, one end of which is the positive input terminal and the other end is connected to a preset bias node. The other input terminal of the common-gate amplification structure is connected with an input resistor R2, one end of which is the negative input terminal and the other end is connected to a corresponding matching node. The process includes the following steps: Standard data is obtained by detecting the preset module under test based on the calibrated current detection module; The actual data is obtained by using a high-precision current sensing amplifier to detect the preset module under test. Compensation data is calculated based on standard data and actual data, and constant current source configuration is generated based on the compensation data and a preset compensation database. A bias constant current source is set at the connection between the input resistor R2 and the corresponding matching node. The bias constant current source has a sampling terminal, which is connected to the positive input terminal to sample the positive input level. The bias constant current source takes the positive input level as input and combines it with the constant current source configuration to output an adaptive current. The adaptive current is positively correlated with the positive input level. The adaptive current is passed through the input resistor R2 to generate an adaptive voltage, which is used to compensate for the amplification factor of the high-precision current sense amplifier.

2. The common-mode compensation method for a high-precision current sensing amplifier according to claim 1, characterized in that, The bias constant current source includes an operational amplifier and an NMOS transistor. The non-inverting input of the operational amplifier is connected to a first resistor R11, the other end of which forms a sampling terminal and is electrically connected to the positive input. The non-inverting input of the operational amplifier is also grounded through a second resistor R10. The negative input of the operational amplifier is grounded through a third resistor R9 and is electrically connected to the source of the NMOS transistor. The output of the operational amplifier is electrically connected to the gate of the NMOS transistor. The drain of the NMOS transistor is electrically connected to the connection node between the input resistor R2 and the second input terminal of the common-gate amplification structure. The voltage at the sampling terminal is sampled and divided using the first resistor R11 and the second resistor R10, and an adaptive current I is generated through a constant current NMOS transistor. OS , that is I OS = (V CSP ×R10 / (R10+R11)) / R9; Adaptive current I OS The corresponding adaptive voltage V is generated through the input resistor R2. os_CSN V OS_CSN =I OS ×R2; Adaptive voltage enables the output V of the high-precision current sense amplifier CS The current sampling value is corrected, V CSP V is the voltage across the positive input terminal of the input resistor R1. CSN The voltage across the negative input terminal of input resistor R2 is V. The output of the high-precision current sense amplifier is grounded through R7, i.e., V. CS = (V CSP -(V) CSN -V OS_CSN ))×R7 / R1=(V CSP -V CSN +V OS_CSN ) × R7 / R1; When the resistance of the input resistor R1 increases, it causes V CS After becoming smaller, V is introduced. os_CSN Compensation V CS .

3. The common-mode compensation method for a high-precision current sensing amplifier according to claim 2, characterized in that, The method also includes the following steps: The current level to be detected is obtained. The larger the current value, the larger the current level, and the smaller the current value, the smaller the current level. The corresponding resistance value is matched from the preset resistance database according to the current level. In the resistance database, the current level is divided into multiple continuous steps. Each step corresponds to a different range of current levels and each step corresponds to a different resistance value. The resistance value of the third resistor R9 is determined based on the matched resistance value. The difference between the matched resistance value and the resistance value of the third resistor R9 is less than the preset set difference. The lower the current level, the smaller the set difference; the higher the current level, the larger the set difference.

4. The common-mode compensation method for a high-precision current sensing amplifier according to claim 2, characterized in that, The method also includes the following steps: Before compensation, the detected current is obtained to generate the current value before compensation, and the resistance compensation coefficient is calculated based on the current value before compensation and the preset current compensation parameters. The target resistance value is calculated based on the resistance compensation coefficient and the base resistance value. If the target resistance value is within the adjustment range of the third resistor R9, the resistance value of the third resistor R9 is adjusted to the target resistance value during compensation; otherwise, the resistance value of the third resistor R9 is adjusted to the minimum value of the adjustment range during compensation.

5. The common-mode compensation method for a high-precision current sensing amplifier according to claim 1, characterized in that, The bias constant current source includes a voltage acquisition unit, a control unit, and a programmable current source unit; The voltage acquisition unit acquires the positive input level at the sampling terminal to generate voltage data, and sends the voltage data to the control unit. The control unit converts the voltage data into target current data according to a preset conversion algorithm, and generates a current source control command based on the target current data, and sends the current source control command to the current source unit. The current source unit generates the corresponding current in response to the current source control command and flows the current through the input resistor R2.

6. The common-mode compensation method for a high-precision current sensing amplifier according to claim 5, characterized in that, The conversion algorithm includes the following sub-steps: The voltage level is calculated based on the voltage data and the preset base value. The larger the voltage data, the larger the voltage level, and the smaller the voltage data, the smaller the voltage level. The corresponding current value is then matched from the preset current database based on the voltage level. In the current database, the voltage level is divided into multiple continuous steps, each step corresponding to a different voltage level range, and each step corresponding to a different current value; or, the current database is divided into multiple continuous segments according to the voltage level, each continuous segment corresponding to a different voltage level range, each continuous segment corresponding to a current continuous line, and a one-to-one correspondence between voltage data and current value is defined on the current continuous line. The target current data is determined based on the matched current value.

7. The common-mode compensation method for a high-precision current sensing amplifier according to claim 1, characterized in that, The method also includes the following steps: The control unit acquires the output value of the high-precision current sensing amplifier, calculates the fluctuation value and average value of the output value within a preset time period, and calculates the fluctuation percentage based on the fluctuation value and average value. The coefficients corresponding to the voltage and current values ​​in the current continuous line are adjusted based on the negative correlation of the fluctuation percentage.

8. A common-mode compensation circuit for a high-precision current detection amplifier, characterized in that, This is applied to a current sensing sampling amplifier, wherein the input stage of the current sensing sampling amplifier is a common-gate amplification structure; the common-gate amplification structure is configured with a positive input terminal and a negative input terminal, the positive input terminal is connected to the first input terminal of the common-gate amplification structure via an input resistor R1, and the negative input terminal is connected to the second input terminal of the common-gate amplification structure via an input resistor R2; The common-mode compensation circuit includes an operational amplifier and an NMOS transistor; The non-inverting input terminal of the operational amplifier is connected to a first resistor R11, and the other end of the first resistor R11 forms a sampling terminal and is electrically connected to the positive input terminal; the non-inverting input terminal of the operational amplifier is also grounded through a second resistor R10. The negative input terminal of the operational amplifier is grounded through the third resistor R9, and the negative input terminal of the operational amplifier is electrically connected to the source of the NMOS transistor; the output terminal of the operational amplifier is electrically connected to the gate of the NMOS transistor. The drain of the NMOS transistor is electrically connected to the connection node between the input resistor R2 and the second input terminal of the common-gate amplifier structure.

9. The common-mode compensation circuit of the high-precision current detection amplifier according to claim 8, characterized in that, The first resistor R11, the second resistor R10 and / or the third resistor R9 are rotary adjustable resistors or multi-position selector resistor arrays.

10. A high-precision current sensing amplifier, characterized in that, It includes a differential input sampling unit, a common-gate amplification input stage, a common-mode compensation circuit, and subsequent amplification and output stages; It includes a differential input sampling unit, a common-gate amplification input stage, a common-mode compensation circuit, and subsequent amplification and output stages; The differential input sampling unit includes an input resistor R1 and an input resistor R2. The positive terminal of the external current sampling CSP is connected to the common gate amplification input stage through the input resistor R1, and the negative terminal of the external current sampling CSN is connected to the common gate amplification input stage through the input resistor R2. The common-gate amplifier input stage includes a high-side input stage and a low-side input stage. The high-side input stage includes a first MOSFET, a second MOSFET, load resistors R3 and R4, and a first operational amplifier. The gate of the first MOSFET is connected to a fixed bias voltage Vb2, its source is connected to the output node of the input resistor R1, and its drain is connected to the power supply VDD via the load resistor R3. The drain of the second MOSFET is connected to the power supply VDD via the load resistor R4, and its source is connected to the signal node of the low-side input stage of the common-gate amplifier. The non-inverting input of the first operational amplifier is connected to the source of the first MOSFET. The inverting input terminal is connected to the source of the second MOS transistor, and the output terminal is connected to the gate of the second MOS transistor. The low-side input stage of the common-gate amplifier includes a third MOS transistor, a fourth MOS transistor, resistors R5 and R6, and a second operational amplifier. The gate of the third MOS transistor is connected to a fixed bias voltage Vb1, the source is grounded through resistor R5, and the drain is connected to the non-inverting input terminal of the second operational amplifier. The source of the fourth MOS transistor is grounded through resistor R6, the drain is connected to the inverting input terminal of the second operational amplifier, and the gate is connected to the output terminal of the second operational amplifier. The output node of the input resistor R2 is connected to the signal path of the low-side input stage of the common-gate amplifier. The common-mode compensation circuit includes a third operational amplifier, an NMOS transistor, a first resistor R11, a second resistor R10, and a third resistor R9. The non-inverting input of the third operational amplifier is connected to the positive terminal of the external current sampling CSP via the first resistor R11 and grounded via the second resistor R10. The inverting input of the third operational amplifier is grounded via the third resistor R9 and electrically connected to the source of the NMOS transistor. The output of the third operational amplifier is connected to the gate of the NMOS transistor. The drain of the NMOS transistor is connected to the connection node between the input resistor R2 and the low-side input stage of the common-gate amplifier. The subsequent amplification and output stage includes a fifth MOS transistor, a sixth MOS transistor, a current source, resistors R7 and R8; the fifth and sixth MOS transistors form a PMOS differential amplifier structure, with their gates connected to the output terminals of the high-side input stage and low-side input stage of the common-gate amplifier, respectively; the drain of the sixth MOS transistor is connected to the current source and leads out to the output node V. ledcsp The subsequent amplification and output stage is grounded via resistor R7 and outputs a current sampling voltage V. cs .

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