A differential amplification circuit

Abstract

This invention discloses a differential amplifier circuit. The differential amplifier circuit includes: an input circuit whose input terminal is connected to a first chopper switch; a first bias circuit, a second chopper switch, a dynamic matching circuit, and an output circuit connected sequentially; and a second bias circuit, a third chopper switch, a dynamic matching circuit, and an output circuit connected sequentially. The input circuit adjusts the bias current in the two branches of the second bias circuit according to the input differential signal. The output circuit's upper output transistor group includes two first terminals and two second terminals, and the lower output transistor group includes two first terminals and two second terminals. The dynamic matching circuit controls the selection of the first terminal of the upper output transistor group and the output terminal of the second chopper switch; controls the selection of the first terminal of the lower output transistor group and the output terminal of the output circuit; and controls the selection of the second terminal of the upper output transistor group and the output terminal of the output circuit. The technical solution of this invention improves the accuracy of the differential amplifier circuit.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and more particularly to a differential amplifier circuit. Background Technology

[0002] With the development of technologies such as sensing, biomedicine, industrial control, and precision measurement, more and more applications require accurate acquisition and processing of voltage or current signals with small amplitudes. Since the signals to be measured are usually quite weak, differential amplifier circuits not only need to have high gain, but also low input offset, noise, and nonlinear distortion to avoid errors generated by the differential amplifier circuit itself overwhelming the signal to be measured.

[0003] Chopper operational amplifiers shift input offset voltage and low-frequency flicker noise to a higher frequency band by periodically modulating the input signal, and then demodulate and filter it. They are widely used in the field of weak signal amplification.

[0004] However, existing chopper operational amplifiers still have errors and low accuracy. Summary of the Invention

[0005] This invention provides a differential amplifier circuit to improve the accuracy of differential amplifier circuits.

[0006] According to one aspect of the present invention, a differential amplifier circuit is provided, comprising: a first chopper switch, a second chopper switch, a third chopper switch, an input circuit, a first bias circuit, a second bias circuit, a dynamic matching circuit, and an output circuit; The input terminal of the input circuit is connected to the first chopper switch; The first bias circuit, the second chopper switch, the dynamic matching circuit, and the output circuit are connected in sequence, and the second bias circuit, the third chopper switch, the dynamic matching circuit, and the output circuit are connected in sequence; the first bias circuit and the second bias circuit are used to generate bias current; The input circuit is connected to the second bias circuit and is used to adjust the bias current on the two branches of the second bias circuit according to the input differential signal. The output circuit includes an upper output transistor group and a lower output transistor group; the upper output transistor group includes two first terminals and two second terminals, and the lower output transistor group includes two first terminals and two second terminals. The dynamic matching circuit is used to control the selection of the first terminal of the upper output transistor group and the output terminal of the second chopper switch; to control the selection of the first terminal of the lower output transistor group and the output terminal of the third chopper switch; to control the selection of the second terminal of the upper output transistor group and the output terminal of the output circuit; and to control the selection of the second terminal of the lower output transistor group and the output terminal of the output circuit.

[0007] Optionally, the output upper MOSFET group includes a first output upper MOSFET and a second output upper MOSFET, and the output lower MOSFET group includes a first output lower MOSFET and a second output lower MOSFET; The control terminal of the first output transistor is connected to the control terminal of the second output transistor, and a first bias voltage is applied; the first terminal of the first output transistor and the first terminal of the second output transistor serve as the first terminal of the output transistor group; the second terminal of the first output transistor and the second terminal of the second output transistor serve as the second terminal of the output transistor group. The control terminal of the first lower output transistor is connected to the control terminal of the second lower output transistor, and a second bias voltage is applied. The first terminal of the first lower output transistor and the first terminal of the second lower output transistor serve as the first terminal of the upper output transistor group. The second terminal of the first lower output transistor and the second terminal of the second lower output transistor serve as the second terminal of the upper output transistor group.

[0008] Optionally, the first output upper transistor includes at least two first transistors, the control terminal of each first transistor is connected to the control terminal of the first output upper transistor, the first terminal of each first transistor is connected to the first terminal of the first output upper transistor, and the second terminal of each first transistor is connected to the second terminal of the first output upper transistor. The second output upper transistor includes at least two second transistors, the control terminal of each second transistor is connected to the control terminal of the second output upper transistor, the first terminal of each second transistor is connected to the first terminal of the second output upper transistor, and the second terminal of each second transistor is connected to the second terminal of the second output upper transistor. The first output lower transistor includes at least two third transistors, the control terminal of each third transistor is connected to the control terminal of the first output lower transistor, the first terminal of each third transistor is connected to the first terminal of the first output lower transistor, and the second terminal of each third transistor is connected to the second terminal of the first output lower transistor. The second output lower transistor includes at least two fourth transistors, the control terminal of each fourth transistor is connected to the control terminal of the second output lower transistor, the first terminal of each fourth transistor is connected to the first terminal of the second output lower transistor, and the second terminal of each fourth transistor is connected to the second terminal of the second output lower transistor.

[0009] Optionally, the dynamic matching circuit includes a first switching unit, a second switching unit, and a third switching unit; The first switching unit includes two common terminals, which are respectively connected to the two first terminals of the output upper transistor group; the first gating terminal of the first switching unit is connected to the first output terminal of the second chopper switch, and the second gating terminal of the first switching unit is connected to the second output terminal of the second chopper switch. The second switching unit includes two common terminals, which are respectively connected to the two first terminals of the output lower transistor group; the first gating terminal of the second switching unit is connected to the first output terminal of the third chopper switch, and the second gating terminal of the second switching unit is connected to the second output terminal of the third chopper switch. The third switching unit includes four common terminals, which are respectively connected to the two second terminals of the upper output transistor group and the two second terminals of the lower output transistor group; the first selection terminal of the third switching unit is connected to the first output terminal of the output circuit, and the second selection terminal of the third switching unit is connected to the first output terminal of the output circuit.

[0010] Optionally, the differential amplifier circuit may also include a first bus, a second bus, a third bus, a fourth bus, a fifth bus, and a sixth bus; The first selection terminal of the first switching unit is connected to the first bus, and the second selection terminal of the first switching unit is connected to the second bus; the first bus is connected to the first output terminal of the second chopper switch, and the second bus is connected to the second output terminal of the second chopper switch. The first selection terminal of the second switching unit is connected to the third bus, and the second selection terminal of the second switching unit is connected to the fourth bus; the third bus is connected to the first output terminal of the third chopper switch, and the fourth bus is connected to the second output terminal of the third chopper switch. The first selection terminal of the third switching unit is connected to the fifth bus, and the second selection terminal of the third switching unit is connected to the sixth bus; the fifth bus is connected to the first output terminal of the output circuit, and the sixth bus is connected to the second output terminal of the output circuit.

[0011] Optionally, the first chopper switch includes a first group of switches, a second group of switches, a third group of switches, and a fourth group of switches; The first set of switches is connected between the first input terminal and the first output terminal of the first chopper switch; the second set of switches is connected between the first input terminal and the second output terminal of the first chopper switch; the third set of switches is connected between the second input terminal and the first output terminal of the first chopper switch; and the fourth set of switches is connected between the second input terminal and the second output terminal of the first chopper switch. The first group of switches, the second group of switches, the third group of switches, and the fourth group of switches each include at least two switches connected in parallel.

[0012] Optionally, the input circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The control terminal of the fifth transistor is connected to the third bias voltage, the first terminal of the fifth transistor is connected to the power supply voltage, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor; the control terminal of the sixth transistor is connected to the first bias voltage; the first terminals of the seventh transistor and the first terminals of the eighth transistor are both connected to the second terminal of the sixth transistor; the control terminal of the seventh transistor is connected to the first output terminal of the first chopper switch, and the control terminal of the eighth transistor is connected to the second output terminal of the first chopper switch; the second terminals of the seventh transistor and the second terminals of the eighth transistor are respectively connected to the two branches of the second bias circuit.

[0013] Optionally, the first bias circuit includes a ninth transistor and a tenth transistor; The first terminal of the ninth transistor and the first terminal of the tenth transistor are both connected to the power supply voltage. The control terminals of the ninth transistor and the tenth transistor are connected and connected to the third bias voltage. The second terminal of the ninth transistor is connected to the first input terminal of the second chopper switch, and the second terminal of the tenth transistor is connected to the second input terminal of the second chopper switch.

[0014] Optionally, the second bias circuit includes an eleventh transistor and a twelfth transistor; The first terminals of the eleventh transistor and the twelfth transistor are both grounded. The control terminals of the eleventh transistor and the twelfth transistor are connected and connected to the fourth bias voltage. The second terminal of the eleventh transistor is connected to the first input terminal of the third chopper switch, and the second terminal of the twelfth transistor is connected to the second input terminal of the third chopper switch.

[0015] Optionally, the differential amplifier circuit in this embodiment of the invention further includes a controller; The controller is connected to the first switch unit, the second switch unit, and the third switch unit respectively, and is used to control the common terminal of the first switch unit to be connected to the first or second selector terminal of the first switch unit; control the common terminal of the second switch unit to be connected to the first or second selector terminal of the second switch unit; and control the common terminal of the third switch unit to be connected to the first or second selector terminal of the third switch unit.

[0016] The technical solution of this invention, through a dynamic matching circuit, enables arbitrary selection between the two first terminals of the upper output transistor group and the output terminals of the second chopper switch, as well as arbitrary selection between the two second terminals of the upper output transistor group and the output terminals of the output circuit; it also enables arbitrary selection between the two first terminals of the lower output transistor group and the output terminals of the third chopper switch, and arbitrary selection between the two second terminals of the upper output transistor group and the output terminals of the output circuit. Furthermore, the nonlinear distortion contributed by the upper and lower output transistor groups to the output signal can be modulated to a high frequency, resulting in a higher-precision differential output signal after filtering. In summary, by using a dynamic matching circuit in conjunction with the first, second, and third chopper switches, the error of the differential amplifier circuit can be further reduced, thereby improving accuracy.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A circuit structure diagram of a differential amplifier circuit provided for existing related technologies; Figure 2 This is a schematic diagram of a differential amplifier circuit provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of another differential amplifier circuit provided in an embodiment of the present invention; Figure 4 A circuit structure diagram of a differential amplifier circuit provided in an embodiment of the present invention; Figure 5 A circuit diagram of a chopper switch provided for existing related technologies; Figure 6 The circuit structure diagram of a first chopper switch provided in an embodiment of the present invention is shown. Detailed Implementation

[0020] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0021] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0022] Figure 1 A circuit diagram of a differential amplifier circuit is provided to support existing related technologies. For example... Figure 1As shown, VIP represents a positive input signal, connected to port b1 of chopper switch CH1, and VIN represents a negative input signal, connected to port b3 of chopper switch CH1. Ports b2 and b4 of chopper switch CH2 are connected to the gates of input transistors M1 and M2, respectively. The sources of input transistors M1 and M2 are both connected to the drain of transistor M3. The gate of transistor M3 is biased by bias voltage VB1. The source of transistor M3 is connected to the drain of transistor M4. The gate of transistor M4 is biased by bias voltage VB3. The source of transistor M4 is connected to the power supply voltage VDD. Transistors M3 and M4 form a current source to provide the bias current for the operational amplifier. The drain of transistor M1 is connected to port b1 of chopper switch CH3 and the drain of transistor M11. The drain of transistor M2 is connected to port b3 of chopper switch CH3 and the drain of transistor M12. The sources of transistors M11 and M12 are connected to ground GND. The gates of transistors M11 and M12 are simultaneously biased by voltage VB4. Port 2 of chopper switch CH3 is connected to the source of transistor M9, and port b4 of chopper switch CH3 is connected to the source of transistor M10. The gates of transistors M9 and M10 are simultaneously biased by bias voltage VB2. The drain of transistor M9 is connected to the second output terminal VON and the drain of transistor M7, respectively. The drain of transistor M10 is connected to the first output terminal VOP and the drain of transistor M8, respectively. The gates of transistors M7 and M8 are simultaneously biased by bias voltage VB1. The source of transistor M7 is connected to port b2 of chopper switch CH2, and the source of transistor M8 is connected to port b4 of chopper switch CH2. Port b1 of chopper switch CH2 is connected to the drain of transistor M5, and port b3 of chopper switch CH2 is connected to the drain of transistor M6. The sources of transistors M5 and M6 are connected to the power supply voltage VDD. The gates of transistors M5 and M6 are both biased by the bias voltage VB3.

[0023] Figure 1 The differential amplifier circuit shown uses a chopper switch CH1 to modulate the offset voltage and 1 / f noise of the differential amplifier circuit to a high frequency, which are then filtered out by the subsequent filter circuit, thereby improving the accuracy. Figure 1 The differential amplifier circuit shown works as follows: the input signal Vin(t) is multiplied by a high-frequency square wave c(t), which is provided by chopper switch CH1. 1. Alternate. Amplify and then multiply by the same c(t) provided by chopper switches CH2 and CH3 to demodulate back. Because Therefore, the output of the rational differential amplifier is G is the amplification factor of the differential amplifier. The error Ve caused by offset and flicker noise will be modulated to... , It is a high-frequency signal, the frequency of which is determined by the switching frequency of the chopper switch. However, transistor M7 is fixedly connected to the first output terminal VOP, and the drain of transistor M8 is fixedly connected to the second output terminal VON. Transistors M7 and M8 do not participate in the chopping process. If a mismatch exists, it will contribute nonlinear distortion to the output signal Vout. Similarly, a mismatch between transistors M9 and M10 will also contribute nonlinear distortion to the output signal Vout. Assume that there is a nonlinear relationship between the output signal Vout and the input signal Vin of the differential amplifier circuit: .in It is a linear gain error; , This is nonlinear distortion, contributed by transistors M7, M8, M9, and M10. When the differential amplifier circuit begins chopping, i.e., the input signal Vin is first multiplied by c(t), and the output signal Vout is then multiplied by c(t): the output voltage after chopping is... , .but As can be seen, in existing differential amplifier circuits, even harmonics are multiplied by c(t), which means they are shifted to higher frequencies, but odd harmonics remain unchanged, so residual distortion still exists.

[0024] To address the shortcomings of existing differential amplifier circuits, Figure 2 This is a schematic diagram of a differential amplifier circuit provided in an embodiment of the present invention. The embodiment of the present invention is applicable to application scenarios where voltage or current signals with small amplitudes are accurately acquired and processed.

[0025] like Figure 2As shown, the differential amplifier circuit provided in this embodiment of the invention includes: a first chopper switch 1, a second chopper switch 2, a third chopper switch 3, an input circuit 4, a first bias circuit 5, a second bias circuit 6, a dynamic matching circuit 7, and an output circuit 8. The input terminal of the input circuit 4 is connected to the first chopper switch 1. The first bias circuit 5, the second chopper switch 2, the dynamic matching circuit 7, and the output circuit 8 are connected sequentially, as are the second bias circuit 6, the third chopper switch 3, the dynamic matching circuit 7, and the output circuit 8. The first bias circuit 5 and the second bias circuit 6 are used to generate bias current. The input circuit 4 is connected to the second bias circuit 6 and is used to adjust the bias current in the two branches of the second bias circuit 6 according to the input differential signal. The output circuit 8 includes an upper output transistor group 81 and a lower output transistor group 82. The upper output transistor group 81 includes two first terminals and two second terminals, and the lower output transistor group 82 includes two first terminals and two second terminals. The dynamic matching circuit 7 is used to control the first terminal of the upper output transistor group 81 and the output terminal of the second chopper switch 2 to be selected, to control the first terminal of the lower output transistor group 82 and the output terminal of the third chopper switch 3 to be selected, to control the second terminal of the upper output transistor group 81 and the first output terminal VOP of the output circuit 8 to be selected, and to control the second terminal of the lower output transistor group 82 and the second output terminal VON of the output circuit 8 to be selected.

[0026] In this embodiment of the invention, the first chopper switch 1 has two input terminals and two output terminals. The two input terminals are connected to the differential signal input terminals of the differential amplifier circuit, and the two output terminals are respectively connected to the two input terminals of the input circuit 4. Under the control of the chopping clock, the first chopper switch 1 can randomly exchange the connection relationship between the differential signal input to the differential amplifier circuit and the two input terminals of the input circuit 4. For example, the first input terminal a of the first chopper switch 1 is connected to the positive input terminal of the differential signal of the differential amplifier circuit and is connected to the positive input signal VIP. The second input terminal b of the first chopper switch 1 is connected to the negative input terminal of the differential signal of the differential amplifier circuit and is connected to the negative input signal VIN. The first output terminal c of the first chopper switch 1 is connected to the first input terminal e of the input circuit 4, and the second output terminal d of the first chopper switch 1 is connected to the second input terminal f of the input circuit 4. Under the control of the chopper clock, the first chopper switch 1 can output the positive input signal VIP at its first output terminal c and the negative input signal VIN at its second output terminal d; or, the first chopper switch 1 can output the positive input signal VIP at its second output terminal d and the negative input signal VIN at its first output terminal c; in this way, the first chopper switch 1 can modulate the differential signal input to the differential amplifier circuit.

[0027] The power supply terminal of input circuit 4 is connected to the power supply voltage VDD. Input circuit 4 includes two output terminals, which are respectively connected to the two output branches of the second bias circuit 6. Input circuit 4 can adjust the current in the branches containing the two output terminals according to the voltage difference between the positive input signal VIP and the negative input signal VIN. For example, the first input terminal e of input circuit 4 is connected to the positive input signal VIP, and the second input terminal f of input circuit 4 is connected to the negative input signal VIN; or, the first input terminal e of input circuit 4 is connected to the negative input signal VIN, and the second input terminal f of input circuit 4 is connected to the positive input signal VIP. The first output terminal g of input circuit 4 is connected to the first output terminal of the second bias circuit 6, and the second output terminal h of input circuit 4 is connected to the second output terminal of the second bias circuit 6. The first output terminal g of input circuit 4 outputs the current in the first branch, and the second output terminal h of input circuit 4 outputs the current in the second branch. Input circuit 4 adjusts the magnitude of the current in the first branch and the current in the second branch according to the voltage difference between the positive input signal VIP and the negative input signal VIN.

[0028] The power supply terminal of the first bias circuit 5 is connected to the power supply voltage VDD. The first bias circuit 5 may include two output terminals, which respectively provide a first bias current and a second bias current, providing a static operating point for the output upper transistor group 81 of the output circuit 8, so that the output upper transistor group 81 operates in the saturation region.

[0029] The first input terminal i and the second input terminal j of the second chopper switch 2 are respectively connected to the two output terminals of the first bias circuit 5. Under the control of the chopping clock, the second chopper switch 2 can randomly exchange the output paths of the first bias current and the second bias current. For example, the first input terminal i of the second chopper switch 2 receives the first bias current, and the second input terminal j receives the second bias current. The first output terminal k of the second chopper switch 2 outputs the first bias current, and the second output terminal m of the second chopper switch 2 outputs the second bias current; or the first output terminal k of the second chopper switch 2 outputs the second bias current, and the second output terminal m of the second chopper switch 2 outputs the first bias current.

[0030] The fixed potential terminal of the second bias circuit 6 is grounded. The second bias circuit 6 may include two output terminals, which respectively provide a third bias current and a fourth bias current to provide a static operating point for the output lower transistor group 82 of the output circuit 8, so that the output lower transistor group 82 operates in the saturation region.

[0031] The first input terminal r and the second input terminal x of the third chopper switch 3 are respectively connected to the two output terminals of the second bias circuit 6. A first node current is formed at the node where the first output terminal g of the input circuit 4, the first output terminal of the second bias circuit 6, and the first input terminal r of the third chopper switch 3 are connected. The first node current includes the superposition of the first branch current and the third bias current. A second node current is formed at the node where the second output terminal h of the input circuit 4, the second output terminal of the second bias circuit 6, and the second input terminal x of the third chopper switch 3 are connected. The second node current includes the superposition of the second branch current and the fourth bias current. Under the control of the chopper clock, the third chopper switch 3 can randomly exchange the output paths of the first node current and the second node current. For example, the first input terminal r of the third chopper switch 3 receives the first node current, and the second input terminal x of the third chopper switch 3 receives the second node current. The first output terminal y of the third chopper switch 3 outputs the first node current, and the second output terminal z of the third chopper switch 3 outputs the second node current; or the first output terminal y of the third chopper switch 2 outputs the second node current, and the second output terminal z of the third chopper switch 3 outputs the first node current. Furthermore, the third chopper switch 3 can demodulate the modulation of the first chopper switch 1.

[0032] The dynamic matching circuit 7 can control the arbitrary selection between the two first terminals of the upper output transistor group 81 and the two output terminals of the second chopper switch 2. For example, the dynamic matching circuit 7 controls the first terminal n1 of the upper output transistor group 81 to connect to the first output terminal k of the second chopper switch 2, and controls the other first terminal n2 of the upper output transistor group 81 to connect to the second output terminal m of the second chopper switch 2. Alternatively, the dynamic matching circuit 7 controls the first terminal n1 of the upper output transistor group 81 to connect to the second output terminal m of the second chopper switch 2, and controls the other first terminal n2 of the upper output transistor group 81 to connect to the first output terminal k of the second chopper switch 2. The dynamic matching circuit 7 can also control the arbitrary selection between the two first terminals of the lower output transistor group 82 and the two output terminals of the third chopper switch 3. For example, the dynamic matching circuit 7 controls the first terminal p1 of the lower output transistor group 82 to connect to the first output terminal y of the third chopper switch 3, and controls the other first terminal p2 of the lower output transistor group 82 to connect to the second output terminal z of the third chopper switch 3. Alternatively, the dynamic matching circuit 7 controls the first terminal p1 of the lower output transistor group 82 to connect to the second output terminal z of the third chopper switch 3, and controls the other first terminal p2 of the lower output transistor group 82 to connect to the first output terminal y of the third chopper switch 3. The dynamic matching circuit 7 can also control arbitrary selection between the two second terminals of the upper output transistor group 81 and the two output terminals of the output circuit 8; and control arbitrary selection between the two second terminals of the lower output transistor group 82 and the two output terminals of the output circuit 8. For example, the dynamic matching circuit 7 controls the second terminal o1 of the upper output transistor group 81 to connect to the first output terminal VOP of the output circuit 8, and controls the other second terminal o2 of the upper output transistor group 81 to connect to the second output terminal VON of the output circuit 8; or, the dynamic matching circuit 7 controls the second terminal o1 of the upper output transistor group 81 to connect to the second output terminal VON of the output circuit 8, and controls the other second terminal o2 of the upper output transistor group 81 to connect to the first output terminal VOP of the output circuit 8. The second terminal q1 of the lower control output transistor group 82 is connected to the first output terminal VOP of the output circuit 8, and the other second terminal q2 of the lower control output transistor group 82 is connected to the second output terminal VON of the output circuit 8; or, the second terminal q1 of the lower control output transistor group 82 is connected to the second output terminal VON of the output circuit 8, and the other second terminal q2 of the lower control output transistor group 82 is connected to the first output terminal VOP of the output circuit 8.

[0033] Specifically, input circuit 4 receives the positive input signal VIP and the negative input signal VIN, and converts the voltage difference between VIP and VIN into the first branch current and the second branch current. The first bias circuit 5 provides bias current to the upper output MOSFET group 81, and the second bias circuit 6 provides bias current to the lower output MOSFET group 82. The connection point of input circuit 4 and the second bias circuit 6 forms the first node current and the second node current. The two second terminals of the upper output MOSFET group 81 are randomly connected to the two second terminals of the lower output MOSFET group 82, and the connection point of the second terminals of the upper output MOSFET group 81 and the lower output MOSFET group 82 forms the output node. The upper output MOSFET group 81 can increase the impedance of the output circuit 8, thereby increasing the gain of the output circuit 8. The lower output MOSFET group 82 can also increase the impedance of the output circuit 8, thereby increasing the gain of the output circuit 8. The changes in the first branch current and the second branch current can be transmitted to the output node, resulting in an amplified differential voltage output at the output terminal of the output circuit 8. The first chopper switch 1 is connected between the differential input terminal of the differential amplifier circuit and the input circuit 4, modulating the input differential signal to the chopper frequency. The second chopper switch 2 is connected to the output terminal of the first bias circuit 5, randomly switching the output paths of the first bias current and the second bias current, thereby reducing the output offset caused by the first bias circuit 5. The third chopper switch 3 is connected to the output terminal of the second bias circuit 6, reducing the output offset caused by the second bias circuit 6 and demodulating the output signal. The dynamic matching circuit 7 can achieve arbitrary selection between the two first terminals of the upper output transistor group 81 and the output terminal of the second chopper switch 2, and arbitrary selection between the two second terminals of the upper output transistor group 81 and the output terminal of the output circuit 8; it can also achieve arbitrary selection between the two first terminals of the lower output transistor group 82 and the output terminal of the third chopper switch 3, and arbitrary selection between the two second terminals of the upper output transistor group 81 and the output terminal of the output circuit 8. In this way, the nonlinear distortion contributed by the upper output transistor group 81 and the lower output transistor group 82 to the output signal can also be modulated to a high frequency. After filtering, a more accurate differential output signal can be obtained.

[0034] For example, compared to the fixed nonlinear distortion coefficient a3 in the chopper-processed output voltage Vout_chopped of existing related technologies, the dynamic matching circuit 7 transforms the nonlinear distortion coefficient a3 into a randomly switching one. , Since it is a high-frequency signal, the energy of the residual odd harmonics is shifted to a higher frequency, resulting in the final chopper-processed output voltage: .

[0035] According to the technical solution of this invention, the dynamic matching circuit enables arbitrary selection between the two first terminals of the upper output transistor group and the output terminals of the second chopper switch, as well as arbitrary selection between the two second terminals of the upper output transistor group and the output terminals of the output circuit; it also enables arbitrary selection between the two first terminals of the lower output transistor group and the output terminals of the third chopper switch, and arbitrary selection between the two second terminals of the upper output transistor group and the output terminals of the output circuit. Furthermore, the nonlinear distortion contributed by the upper and lower output transistor groups to the output signal can be modulated to a high frequency, resulting in a higher-precision differential output signal after filtering. In summary, by using the dynamic matching circuit in conjunction with the first, second, and third chopper switches, the error of the differential amplifier circuit can be further reduced, thereby improving accuracy.

[0036] Figure 3 This is a schematic diagram of another differential amplifier circuit provided in an embodiment of the present invention. Figure 3 As shown, in some embodiments, the output upper transistor group 81 includes a first output upper transistor MP1 and a second output upper transistor MP2, and the output lower transistor group 82 includes a first output lower transistor MN1 and a second output lower transistor MN2. The control terminal of the first output upper transistor MP1 is connected to the control terminal of the second output upper transistor MP2 and is connected to a first bias voltage VB1. The first terminal of the first output upper transistor MP1 and the first terminal of the second output upper transistor MP2 serve as the first terminal of the output upper transistor group 81, and the second terminal of the first output upper transistor MP1 and the second terminal of the second output upper transistor MP2 serve as the second terminal of the output upper transistor group 81. The control terminal of the first output lower transistor MN1 is connected to the control terminal of the second output lower transistor MN2 and is connected to a second bias voltage VB2. The first terminal of the first output lower transistor MN1 and the first terminal of the second output lower transistor MN2 serve as the first terminal of the output upper transistor group 81, and the second terminal of the first output lower transistor MN1 and the second terminal of the second output lower transistor MN2 serve as the second terminal of the output upper transistor group 81.

[0037] In this configuration, the first high-output transistor MP1 and the second high-output transistor MP2 can be P-type MOSFETs with the same channel size. The first terminal of the first high-output transistor MP1 and the first terminal of the second high-output transistor MP2 can be the source of the P-type MOSFET, and the second terminal of the first high-output transistor MP1 and the second high-output transistor MP2 can be the drain of the P-type MOSFET. The control terminal of the first high-output transistor MP1 and the control terminal of the second high-output transistor MP2 can be the gate of the P-type MOSFET. Similarly, the first low-output transistor MN1 and the second low-output transistor MN2 can be N-type MOSFETs with the same channel size. The first terminal of the first low-output transistor MN1 and the first terminal of the second low-output transistor MN2 can be the source of the N-type MOSFET, and the second terminal of the first low-output transistor MN1 and the second low-output transistor MN2 can be the drain of the N-type MOSFET. The control terminal of the first low-output transistor MN1 and the control terminal of the second low-output transistor MN2 can be the gate of the N-type MOSFET.

[0038] For example, the first terminal of the first output transistor MP1 can be connected to the first output terminal k of the second chopper switch 2 through the dynamic matching circuit 7, and the first terminal of the second output transistor MP2 can be connected to the second output terminal m of the second chopper switch 2 through the dynamic matching circuit 7; or, the first terminal of the first output transistor MP1 can be connected to the second output terminal m of the second chopper switch 2 through the dynamic matching circuit 7, and the first terminal of the second output transistor MP2 can be connected to the first output terminal k of the second chopper switch 2 through the dynamic matching circuit 7. The control terminals of the first output transistor MP1 and the second output transistor MP2 are connected to the same first bias voltage VB1. The second terminal of the first output transistor MP1 can be connected to the first output terminal VOP of the output circuit 8 through the dynamic matching circuit 7, and the second terminal of the second output transistor MP2 can be connected to the second output terminal VON of the output circuit 8 through the dynamic matching circuit 7; or, the second terminal of the first output transistor MP1 can be connected to the second output terminal VON of the output circuit 8 through the dynamic matching circuit 7, and the second terminal of the second output transistor MP2 can be connected to the first output terminal VOP of the output circuit 8 through the dynamic matching circuit 7.

[0039] The first terminal of the first lower output transistor MN1 can be connected to the first output terminal y of the third chopper switch 3 through the dynamic matching circuit 7, and the first terminal of the second lower output transistor MN2 can be connected to the second output terminal z of the third chopper switch 3 through the dynamic matching circuit 7; or, the first terminal of the first lower output transistor MN1 can be connected to the second output terminal z of the third chopper switch 3 through the dynamic matching circuit 7, and the first terminal of the second lower output transistor MN2 can be connected to the first output terminal y of the third chopper switch 3 through the dynamic matching circuit 7. The control terminals of the first lower output transistor MN1 and the second lower output transistor MN2 are connected to the same second bias voltage VB2. The second terminal of the first lower output transistor MN1 can be connected to the first output terminal VOP of the output circuit 8 through the dynamic matching circuit 7, and the second terminal of the second lower output transistor MN2 can be connected to the second output terminal VON of the output circuit 8 through the dynamic matching circuit 7; or, the second terminal of the first lower output transistor MN1 can be connected to the second output terminal VON of the output circuit 8 through the dynamic matching circuit 7, and the second terminal of the second lower output transistor MN2 can be connected to the first output terminal VOP of the output circuit 8 through the dynamic matching circuit 7.

[0040] Continue to refer to Figure 3 In some embodiments, the dynamic matching circuit 7 includes a first switching unit 71, a second switching unit 72, and a third switching unit 73. The first switching unit 71 includes two common terminals, respectively connected to the two first terminals of the output upper transistor group 81. The first gating terminal of the first switching unit 71 is connected to the first output terminal k of the second chopper switch 2, and the second gating terminal of the first switching unit 71 is connected to the second output terminal m of the second chopper switch 2. The second switching unit 72 includes two common terminals, respectively connected to the two first terminals of the output lower transistor group 82. The first gating terminal of the second switching unit 72 is connected to the first output terminal y of the third chopper switch 3, and the second gating terminal of the second switching unit 72 is connected to the second output terminal z of the third chopper switch 3. The third switching unit 73 includes four common terminals, respectively connected to the two second terminals of the output upper transistor group 81 and the two second terminals of the output lower transistor group 82. The first gating terminal of the third switching unit 73 is connected to the first output terminal VOP of the output circuit 8, and the second gating terminal of the third switching unit 73 is connected to the first output terminal VOP of the output circuit 8.

[0041] The first switching unit 71 may include a first common terminal and a second common terminal. The first common terminal is connected to the first terminal of the first output upper transistor MP1, and the second common terminal is connected to the first terminal of the second output upper transistor MP2. The first common terminal may be connected to the first selection terminal of the first switching unit 71, and the second common terminal may be connected to the second selection terminal of the first switching unit 71; or, the first common terminal may be connected to the second selection terminal of the first switching unit 71, and the second common terminal may be connected to the first selection terminal of the first switching unit 71.

[0042] The second switching unit 72 may include a third common terminal and a fourth common terminal. The third common terminal is connected to the first terminal of the first output lower transistor MN1, and the fourth common terminal is connected to the first terminal of the second output lower transistor MN2. The third common terminal may be connected to the first selection terminal of the second switching unit 72, and the fourth common terminal may be connected to the second selection terminal of the second switching unit 72; or, the third common terminal may be connected to the second selection terminal of the second switching unit 72, and the fourth common terminal may be connected to the first selection terminal of the second switching unit 72.

[0043] The third switching unit 73 may include a fifth common terminal, a sixth common terminal, a seventh common terminal, and an eighth common terminal. The fifth common terminal is connected to the second terminal of the first upper output transistor MP1, and the sixth common terminal is connected to the second terminal of the second upper output transistor MP2. The seventh common terminal is connected to the second terminal of the first lower output transistor MN1, and the eighth common terminal is connected to the second terminal of the second lower output transistor MN2. The fifth common terminal may be connected to the first selection terminal of the third switching unit 73, and the sixth common terminal may be connected to the second selection terminal of the third switching unit 73; or, the fifth common terminal may be connected to the second selection terminal of the third switching unit 73, and the sixth common terminal may be connected to the first selection terminal of the third switching unit 73. The seventh common terminal may be connected to the first selection terminal of the third switching unit 73, and the eighth common terminal may be connected to the second selection terminal of the third switching unit 73; or, the seventh common terminal may be connected to the second selection terminal of the third switching unit 73, and the eighth common terminal may be connected to the first selection terminal of the third switching unit 73.

[0044] Figure 4 This is a circuit structure diagram of a differential amplifier circuit provided in an embodiment of the present invention. (Combined with...) Figure 3 and Figure 4In some embodiments, the first output upper transistor MP1 includes at least two first transistors, the control terminal of each first transistor being connected to the control terminal of the first output upper transistor MP1, the first end of each first transistor being connected to the first end of the first output upper transistor MP1, and the second end of each first transistor being connected to the second end of the first output upper transistor MP1. The second output upper transistor MP2 includes at least two second transistors, the control terminal of each second transistor being connected to the control terminal of the second output upper transistor MP2, the first end of each second transistor being connected to the first end of the second output upper transistor MP2, and the second end of each second transistor being connected to the second end of the second output upper transistor MP2. The first output lower transistor MN1 includes at least two third transistors, the control terminal of each third transistor being connected to the control terminal of the first output lower transistor MN1, the first end of each third transistor being connected to the first end of the first output lower transistor MN1, and the second end of each third transistor being connected to the second end of the first output lower transistor MN1. The second output lower transistor MN2 includes at least two fourth transistors, the control terminal of each fourth transistor being connected to the control terminal of the second output lower transistor MN2, the first end of each fourth transistor being connected to the first end of the second output lower transistor MN2, and the second end of each fourth transistor being connected to the second end of the second output lower transistor MN2.

[0045] For example, consider a first output upper transistor MP1 comprising four first transistors, a second output upper transistor MP2 comprising four second transistors, a first output lower transistor MN1 comprising four third transistors, and a second output lower transistor MN2 comprising four fourth transistors. The four first transistors can be represented as MP11, MP12, MP13, and MP14, respectively. The type of the four first transistors is the same as that of the first output upper transistor MP1, and the total channel size of the four first transistors is the same as that of the first output upper transistor MP1. The first terminals of all four first transistors are connected to a first common terminal, and the second terminals of all four first transistors are connected to a fifth common terminal. The four second transistors can be represented as MP21, MP22, MP23, and MP24, respectively. The type of the four second transistors is the same as that of the second output upper transistor MP2, and the total channel size of the four second transistors is the same as that of the second output upper transistor MP2. The first terminals of all four second transistors are connected to a second common terminal, and the second terminals of all four second transistors are connected to a sixth common terminal. The control terminals of the four first transistors are connected to the control terminals of the four second transistors and are connected to the same first bias voltage VB1. The four third transistors can be represented by MN11, MN12, MN13, and MN14, respectively. The four third transistors are of the same type as the first lower output transistor MN1, and their total channel size is the same as that of MN1. The first terminals of all four third transistors are connected to a third common terminal, and their second terminals are all connected to a seventh common terminal. The four fourth transistors can be represented by MN21, MN22, MN23, and MN24, respectively. The four fourth transistors are of the same type as the second lower output transistor MN2, and their total channel size is the same as that of MN2. The first terminals of all four fourth transistors are connected to a fourth common terminal, and their second terminals are all connected to an eighth common terminal. The control terminals of the four third transistors are connected to the control terminals of the four fourth transistors and are connected to the same second bias voltage VB2.

[0046] Continue to refer to Figure 3 and Figure 4In some embodiments, the differential amplifier circuit further includes a first bus, a second bus, a third bus, a fourth bus, a fifth bus, and a sixth bus. The first selection terminal of the first switching unit 71 is connected to the first bus, and the second selection terminal of the first switching unit 71 is connected to the second bus. The first bus is connected to the first output terminal k of the second chopper switch 2, and the second bus is connected to the second output terminal m of the second chopper switch 2. The first selection terminal of the second switching unit 72 is connected to the third bus, and the second selection terminal of the second switching unit 72 is connected to the fourth bus. The third bus is connected to the first output terminal y of the third chopper switch 3, and the fourth bus is connected to the second output terminal z of the third chopper switch 3. The first selection terminal of the third switching unit 73 is connected to the fifth bus, and the second selection terminal of the third switching unit 73 is connected to the sixth bus. The fifth bus is connected to the first output terminal VOP of the output circuit 8, and the sixth bus is connected to the second output terminal VON of the output circuit 8.

[0047] The first switching unit 71, the second switching unit 72, and the third switching unit 73 can each include a plurality of single-pole double-throw (SPD) switches. For example, taking a first output transistor MP1 comprising four first transistors, a second output transistor MP2 comprising four second transistors, and the first switching unit 71 comprising eight SPD switches as an example. Four of these SPD switches can be represented as S1P, S2P, S3P, and S4P. The common terminal of each SPD switch (S1P-S4P) is connected to the first terminal of the first transistor, the first selector terminal of each SPD switch (S1P-S4P) is connected to the first bus, and the second selector terminal of each SPD switch (S1P-S4P) is connected to the second bus. The other four SPD switches can be represented as S5P, S6P, S7P, and S8P. The common terminal of each S5P-S8P single-pole double-throw switch is connected to the first terminal of the second transistor. The first strobe terminal of each S5P-S8P single-pole double-throw switch is connected to the first bus. The second strobe terminal of each S5P-S8P single-pole double-throw switch is connected to the second bus.

[0048] Taking an example where the first output lower transistor MN1 includes four third transistors, the second output lower transistor MN2 includes four fourth transistors, and the second switching unit 72 includes eight single-pole double-throw (SPD) switches, four of which can be represented as S9P, S10P, S11P, and S12P. The common terminal of each SPD switch (S9P-S12P) is connected to the first terminal of the third transistor, the first selector terminal of each SPD switch (S9P-S12P) is connected to the third bus, and the second selector terminal of each SPD switch (S9P-S12P) is connected to the fourth bus. The other four SPD switches can be represented as S13P, S14P, S15P, and S16P. The common terminal of each single-pole double-throw switch from S13P to S16P is connected to the first terminal of the fourth transistor. The first strobe terminal of each single-pole double-throw switch from S13P to S16P is connected to the third bus. The second strobe terminal of each single-pole double-throw switch from S13P to S16P is connected to the fourth bus.

[0049] Taking the third switching unit 73, which includes 16 single-pole double-throw (SPDT) switches, as an example, four of these SPDT switches can be represented as S1N, S2N, S3N, and S4N. The common terminal of each SPDT switch from S1N to S4N is connected to the second terminal of the first transistor. The first selector terminal of each SPDT switch from S1N to S4N is connected to the fifth bus, and the second selector terminal of each SPDT switch from S1N to S4N is connected to the sixth bus. Four more SPDT switches can be represented as S5N, S6N, S7N, and S8N. The common terminal of each SPDT switch from S5N to S8N is connected to the second terminal of the second transistor. The first selector terminal of each SPDT switch from S5N to S8N is connected to the fifth bus, and the second selector terminal of each SPDT switch from S5N to S8N is connected to the sixth bus. Four more SPDT switches can be represented as S9N, S10N, S11N, and S12N. The common terminal of each single-pole double-throw (SPD) switch from S9N to S12N is connected to the second terminal of the third transistor. The first select terminal of each SPD switch from S9N to S12N is connected to the fifth bus, and the second select terminal of each SPD switch from S9N to S12N is connected to the sixth bus. Four SPD switches can be represented as S13N, S14N, S15N, and S16N. The common terminal of each SPD switch from S13N to S16N is connected to the second terminal of the fourth transistor. The first select terminal of each SPD switch from S13N to S16N is connected to the fifth bus, and the second select terminal of each SPD switch from S13N to S16N is connected to the sixth bus.

[0050] Continue to refer to Figure 4In some embodiments, the differential amplifier circuit further includes a controller 9. The controller 9 is connected to the first switching unit 71, the second switching unit 72, and the third switching unit 73, respectively, and is used to control the common terminal of the first switching unit 71 to be connected to either the first or second selection terminal of the first switching unit 71, control the common terminal of the second switching unit 72 to be connected to either the first or second selection terminal of the second switching unit 72, and control the common terminal of the third switching unit 73 to be connected to either the first or second selection terminal of the third switching unit 73.

[0051] The controller 9 can be connected to the single-pole double-throw switch in the first switch unit 71, the second switch unit 72, and the third switch unit 73. Controller 9 controls the single-pole double-throw switch to randomly select and ensure that the total channel size of the transistor connected to the first output terminal k of the second chopper switch 2 is the same as the channel size of the first upper output transistor MP1 (or the second upper output transistor MP2) each time, and ensures that the total channel size of the transistor connected to the second output terminal m of the second chopper switch 2 is the same as the channel size of the first upper output transistor MP1 (or the second upper output transistor MP2) each time, that is, ensures that the total channel size of the transistors connected to the first output terminal k and the second output terminal m of the second chopper switch 2 is the same; ensures that the total channel size of the transistor connected to the first output terminal y of the third chopper switch 3 is the same as the channel size of the first lower output transistor MN1 (or the second lower output transistor MN2) each time, and ensures that the total channel size of the transistor connected to the second output terminal z of the third chopper switch 3 is the same as the channel size of the first lower output transistor MN1 (or the second lower output transistor MN2) each time, that is, ensures that the total channel size of the transistors connected to the first output terminal y and the second output terminal z of the third chopper switch 3 is the same. The controller 9 can also control half of the transistors in the first upper output transistor MP1 and the second upper output transistor MP2 to be connected to the first output terminal VOP of the output circuit 8, and control the other half of the transistors in the first upper output transistor MP1 and the second upper output transistor MP2 to be connected to the second output terminal VON of the output circuit 8. It can also control half of the transistors in the first lower output transistor MN1 and the second lower output transistor MN2 to be connected to the first output terminal VOP of the output circuit 8, and control the other half of the transistors in the first lower output transistor MN1 and the second lower output transistor MN2 to be connected to the second output terminal VON of the output circuit 8.

[0052] For example, consider a first output upper transistor MP1 comprising four first transistors, a second output upper transistor MP2 comprising four second transistors, a first output lower transistor MN1 comprising four third transistors, and a second output lower transistor MN2 comprising four fourth transistors. The controller 9 randomly selects four transistors to be connected to the first output terminal k of the second chopper switch 2. These four transistors can include any four of the four first transistors and four of the four second transistors. The controller 9 controls another four of the four first transistors and four of the four second transistors to be connected to the second output terminal m of the second chopper switch 2. The controller 9 randomly selects four transistors to be connected to the first output terminal VOP of the output circuit 8. These four transistors can include any four of the four first transistors and four of the four second transistors. The controller 9 controls another four of the four first transistors and four of the four second transistors to be connected to the second output terminal VON of the output circuit 8. The four transistors connected to the first output terminal VOP of the output circuit 8 can be the same as or different from the four transistors connected to the first output terminal k of the second chopper switch 2. The controller 9 randomly selects four transistors to be switched to the first output terminal y of the third chopper switch 3. These four transistors can include any four of the four third transistors and four fourth transistors. The controller 9 then controls another four of the four third and four fourth transistors to be switched to the second output terminal z of the third chopper switch 3. The four transistors switched to the first output terminal VOP of the output circuit 8 can be the same as or different from the four transistors switched to the first output terminal y of the third chopper switch.

[0053] Continue to refer to Figure 3 and Figure 4 In some embodiments, the input circuit 4 includes a fifth transistor MP5, a sixth transistor MP6, a seventh transistor MP7, and an eighth transistor MP8. The control terminal of the fifth transistor MP5 is connected to a third bias voltage VB3, the first terminal of the fifth transistor MP5 is connected to the power supply voltage VDD, the second terminal of the fifth transistor MP5 is connected to the first terminal of the sixth transistor MP6, and the control terminal of the sixth transistor MP6 is connected to a first bias voltage VB1. The first terminals of both the seventh transistor MP7 and the eighth transistor MP8 are connected to the second terminals of the sixth transistor MP6. The control terminal of the seventh transistor MP7 is connected to the first output terminal c of the first chopper switch 1, and the control terminal of the eighth transistor MP8 is connected to the second output terminal d of the first chopper switch 1. The second terminals of the seventh transistor MP7 and the eighth transistor MP8 are respectively connected to two branches of the second bias circuit 6.

[0054] Among them, the fifth transistor MP5, the sixth transistor MP6, the seventh transistor MP7, and the eighth transistor MP8 can be P-type MOS transistors. The first terminal of the fifth transistor MP5, the first terminal of the sixth transistor MP6, the first terminal of the seventh transistor MP7, and the first terminal of the eighth transistor MP8 can be the source of the P-type MOS transistors. The second terminal of the fifth transistor MP5, the second terminal of the sixth transistor MP6, the second terminal of the seventh transistor MP7, and the second terminal of the eighth transistor MP8 can be the drain of the P-type MOS transistors. The control terminal of the fifth transistor MP5, the control terminal of the sixth transistor MP6, the control terminal of the seventh transistor MP7, and the control terminal of the eighth transistor MP8 can be the gate of the P-type MOS transistors.

[0055] The fifth transistor MP5 and the sixth transistor MP6 can form a third bias circuit. The fifth transistor MP5 generates a bias current based on the power supply voltage VDD and the third bias voltage, while the sixth transistor MP6 generates a bias current based on the voltage at the second terminal of the fifth transistor MP5 and the first bias voltage VB1. This third bias circuit can then generate a stable bias current, providing a quiescent operating point for the seventh transistor MP7 and the eighth transistor MP8.

[0056] The seventh transistor MP7 and the eighth transistor MP8 have the same channel size. The control terminal of the seventh transistor MP7 can be the first input terminal e of the input circuit 4, and the control terminal of the eighth transistor MP8 can be the second input terminal f of the input circuit 4. The second terminal of the seventh transistor MP7 can be the first output terminal g of the input circuit 4, and the second terminal of the eighth transistor MP8 can be the second output terminal h of the input circuit 4. When the voltages at the control terminals of the seventh transistor MP7 and the eighth transistor MP8 are different, the opening degrees of the seventh transistor MP7 and the eighth transistor MP8 are different, thereby adjusting the first branch current of the branch containing the second terminal of the seventh transistor MP7 and the second branch current of the branch containing the second terminal of the eighth transistor MP8.

[0057] Continue to refer to Figure 3 and Figure 4 In some embodiments, the first bias circuit 5 includes a ninth transistor MP9 and a tenth transistor MP10. The first terminals of both the ninth transistor MP9 and the tenth transistor MP10 are connected to the power supply voltage VDD. The control terminals of the ninth transistor MP9 and the tenth transistor MP10 are connected and connected to a third bias voltage. The second terminal of the ninth transistor MP9 is connected to the first input terminal i of the second chopper switch 2, and the second terminal of the tenth transistor MP10 is connected to the second input terminal of the second chopper switch 2.

[0058] In this circuit, the ninth transistor MP9 and the tenth transistor MP10 can be P-type MOSFETs. The first terminal of the ninth transistor MP9 and the first terminal of the tenth transistor MP10 can be the source of the P-type MOSFET, and the second terminal of the ninth transistor MP9 and the second terminal of the tenth transistor MP10 can be the drain of the P-type MOSFET. The control terminal of the ninth transistor MP9 and the control terminal of the tenth transistor MP10 can be the gate of the P-type MOSFET. The second terminal of the ninth transistor MP9 can be the first output terminal of the first bias circuit 5, and the second terminal of the tenth transistor MP10 can be the second output terminal of the first bias circuit 5.

[0059] Continue to refer to Figure 3 and Figure 4 In some embodiments, the second bias circuit 6 includes an eleventh transistor MN3 and a twelfth transistor MN4. The first terminals of the eleventh transistor MN3 and the twelfth transistor MN4 are both grounded. The control terminals of the eleventh transistor MN3 and the twelfth transistor MN4 are connected and connected to a fourth bias voltage. The second terminal of the eleventh transistor MN3 is connected to the first input terminal r of the third chopper switch 3, and the second terminal of the twelfth transistor MN4 is connected to the second input terminal x of the third chopper switch 3.

[0060] In this circuit, the eleventh transistor MN3 and the twelfth transistor MN4 can be N-type MOSFETs. The first terminal of the eleventh transistor MN3 and the first terminal of the twelfth transistor MN4 can be the source of the N-type MOSFETs, and the second terminal of the eleventh transistor MN3 and the second terminal of the twelfth transistor MN4 can be the drain of the N-type MOSFETs. The control terminal of the eleventh transistor MN3 and the control terminal of the twelfth transistor MN4 can be the gate of the N-type MOSFETs. The second terminal of the eleventh transistor MN3 can be the first output terminal of the second bias circuit 6, and the second terminal of the twelfth transistor MN4 can be the second output terminal of the second bias circuit 6.

[0061] Figure 5 A circuit diagram of a chopper switch is provided for existing related technologies. Figure 1 The chopper switches in the differential amplifier circuit shown can all be derived from... Figure 5 The circuit structure shown is composed of... Figure 5 As shown, the first switch S1 can select the first input terminal b1 and the first output terminal b2 of the chopper switch, the second switch S2 can select the first input terminal b1 and the second output terminal b4 of the chopper switch, the third switch S3 can select the second input terminal b3 and the first output terminal b2 of the chopper switch, and the fourth switch S4 can select the second input terminal b3 and the second output terminal b4 of the chopper switch.

[0062] In this circuit, switches S1 through S4 can all be controlled by MOSFETs. During the turn-on or turn-off of the MOSFETs, clock feedthrough and charge injection can easily generate differential-mode errors when the input positive signal VIP and the input negative signal VIN are asymmetrical. The chopper switch, under the control of the chopper clock, closes either switches S1 and S4, or switches S2 and S3. When switches S1, S2, S3, and S4 switch in a fixed sequence, the differential-mode error can be approximated as a DC value and cannot be filtered out in subsequent filtering processes, thus reducing the accuracy of the differential amplifier circuit.

[0063] Based on the shortcomings of existing chopper switches in related technologies Figure 6 This is a circuit diagram of a first chopper switch provided in an embodiment of the present invention. Figure 6 As shown, in some embodiments, the first chopper switch includes a first group of switches, a second group of switches, a third group of switches, and a fourth group of switches. The first group of switches is connected between the first input terminal a and the first output terminal c of the first chopper switch; the second group of switches is connected between the first input terminal a and the second output terminal d of the first chopper switch; the third group of switches is connected between the second input terminal b and the first output terminal c of the first chopper switch; and the fourth group of switches is connected between the second input terminal b and the second output terminal d of the first chopper switch. Each of the first, second, third, and fourth groups of switches includes at least two switches connected in parallel.

[0064] In this setup, a fifth switch S11 connected in parallel to the first switch S1 forms the first group of switches; a sixth switch S21 connected in parallel to the second switch S2 forms the second group of switches; a seventh switch S31 connected in parallel to the third switch S3 forms the third group of switches; and an eighth switch S41 connected in parallel to the fourth switch S4 forms the fourth group of switches. Any switch from the first group, the second group, the third group, or the fourth group can be randomly selected. For example, under the control of the chopper clock, the chopper switch can close the first switch S1 and the fourth switch S4, or close the fifth switch S11 and the eighth switch S41, or close the second switch S2 and the third switch S3, or close the sixth switch S21 and the seventh switch S31, or other combinations thereof. In this way, the differential-mode error caused by the first chopper switch is effectively modulated to a high frequency, and can thus be eliminated in subsequent filtering processes.

[0065] Understandably, the first and third chopper switches could also adopt the same structure as the first chopper switch to further improve the accuracy of the differential amplifier circuit.

[0066] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0067] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A differential amplifier circuit, characterized in that, include: First chopper switch, second chopper switch, third chopper switch, input circuit, first bias circuit, second bias circuit, dynamic matching circuit and output circuit; The input terminal of the input circuit is connected to the first chopper switch; The first bias circuit, the second chopper switch, the dynamic matching circuit, and the output circuit are connected in sequence; the second bias circuit, the third chopper switch, the dynamic matching circuit, and the output circuit are also connected in sequence; the first bias circuit and the second bias circuit are used to generate bias current. The input circuit is connected to the second bias circuit and is used to adjust the bias current on the two branches of the second bias circuit according to the input differential signal. The output circuit includes an upper output transistor group and a lower output transistor group; the upper output transistor group includes two first terminals and two second terminals, and the lower output transistor group includes two first terminals and two second terminals. The dynamic matching circuit is used to control the selection of the first terminal of the upper output transistor group and the output terminal of the second chopper switch; control the selection of the first terminal of the lower output transistor group and the output terminal of the third chopper switch; control the selection of the second terminal of the upper output transistor group and the output terminal of the output circuit; and control the selection of the second terminal of the lower output transistor group and the output terminal of the output circuit.

2. The differential amplifier circuit according to claim 1, characterized in that, The output upper transistor group includes a first output upper transistor and a second output upper transistor, and the output lower transistor group includes a first output lower transistor and a second output lower transistor. The control terminal of the first output transistor is connected to the control terminal of the second output transistor, and a first bias voltage is applied; the first terminal of the first output transistor and the first terminal of the second output transistor serve as the first terminal of the output transistor group; the second terminal of the first output transistor and the second terminal of the second output transistor serve as the second terminal of the output transistor group. The control terminal of the first lower output transistor is connected to the control terminal of the second lower output transistor, and a second bias voltage is applied; the first end of the first lower output transistor and the first end of the second lower output transistor serve as the first end of the upper output transistor group; the second end of the first lower output transistor and the second end of the second lower output transistor serve as the second end of the upper output transistor group.

3. The differential amplifier circuit according to claim 2, characterized in that, The first output upper transistor includes at least two first transistors, the control terminal of each first transistor is connected to the control terminal of the first output upper transistor, the first terminal of each first transistor is connected to the first terminal of the first output upper transistor, and the second terminal of each first transistor is connected to the second terminal of the first output upper transistor. The second output upper transistor includes at least two second transistors, the control terminal of each second transistor is connected to the control terminal of the second output upper transistor, the first terminal of each second transistor is connected to the first terminal of the second output upper transistor, and the second terminal of each second transistor is connected to the second terminal of the second output upper transistor; The first output lower transistor includes at least two third transistors, the control terminal of each third transistor is connected to the control terminal of the first output lower transistor, the first terminal of each third transistor is connected to the first terminal of the first output lower transistor, and the second terminal of each third transistor is connected to the second terminal of the first output lower transistor. The second output lower transistor includes at least two fourth transistors, the control terminal of each fourth transistor is connected to the control terminal of the second output lower transistor, the first terminal of each fourth transistor is connected to the first terminal of the second output lower transistor, and the second terminal of each fourth transistor is connected to the second terminal of the second output lower transistor.

4. The differential amplifier circuit according to claim 2, characterized in that, The dynamic matching circuit includes a first switching unit, a second switching unit, and a third switching unit; The first switching unit includes two common terminals, which are respectively connected to the two first terminals of the output upper transistor group; the first gating terminal of the first switching unit is connected to the first output terminal of the second chopper switch, and the second gating terminal of the first switching unit is connected to the second output terminal of the second chopper switch. The second switching unit includes two common terminals, which are respectively connected to the two first terminals of the output lower transistor group; the first gating terminal of the second switching unit is connected to the first output terminal of the third chopper switch, and the second gating terminal of the second switching unit is connected to the second output terminal of the third chopper switch. The third switching unit includes four common terminals, which are respectively connected to the two second terminals of the upper output transistor group and the two second terminals of the lower output transistor group; the first selection terminal of the third switching unit is connected to the first output terminal of the output circuit, and the second selection terminal of the third switching unit is connected to the first output terminal of the output circuit.

5. The differential amplifier circuit according to claim 4, characterized in that, The differential amplifier circuit further includes a first bus, a second bus, a third bus, a fourth bus, a fifth bus, and a sixth bus; The first selection terminal of the first switch unit is connected to the first bus, and the second selection terminal of the first switch unit is connected to the second bus; The first bus is connected to the first output terminal of the second chopper switch, and the second bus is connected to the second output terminal of the second chopper switch; The first selection terminal of the second switching unit is connected to the third bus, and the second selection terminal of the second switching unit is connected to the fourth bus; The third bus is connected to the first output terminal of the third chopper switch, and the fourth bus is connected to the second output terminal of the third chopper switch; The first selection terminal of the third switch unit is connected to the fifth bus, and the second selection terminal of the third switch unit is connected to the sixth bus; the fifth bus is connected to the first output terminal of the output circuit, and the sixth bus is connected to the second output terminal of the output circuit.

6. The differential amplifier circuit according to claim 1, characterized in that, The first chopper switch includes a first group of switches, a second group of switches, a third group of switches, and a fourth group of switches; The first set of switches is connected between the first input terminal and the first output terminal of the first chopper switch; the second set of switches is connected between the first input terminal and the second output terminal of the first chopper switch; the third set of switches is connected between the second input terminal and the first output terminal of the first chopper switch; and the fourth set of switches is connected between the second input terminal and the second output terminal of the first chopper switch. The first group of switches, the second group of switches, the third group of switches, and the fourth group of switches each include at least two switches connected in parallel.

7. The differential amplifier circuit according to claim 1, characterized in that, The input circuit includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; The control terminal of the fifth transistor is connected to a third bias voltage, the first terminal of the fifth transistor is connected to a power supply voltage, and the second terminal of the fifth transistor is connected to the first terminal of the sixth transistor; the control terminal of the sixth transistor is connected to a first bias voltage; the first terminals of the seventh transistor and the eighth transistor are both connected to the second terminal of the sixth transistor; the control terminal of the seventh transistor is connected to the first output terminal of the first chopper switch, and the control terminal of the eighth transistor is connected to the second output terminal of the first chopper switch; the second terminals of the seventh transistor and the second terminals of the eighth transistor are respectively connected to two branches of the second bias circuit.

8. The differential amplifier circuit according to claim 1, characterized in that, The first bias circuit includes a ninth transistor and a tenth transistor; The first terminal of the ninth transistor and the first terminal of the tenth transistor are both connected to the power supply voltage. The control terminals of the ninth transistor and the tenth transistor are connected and connected to the third bias voltage. The second terminal of the ninth transistor is connected to the first input terminal of the second chopper switch, and the second terminal of the tenth transistor is connected to the second input terminal of the second chopper switch.

9. The differential amplifier circuit according to claim 1, characterized in that, The second bias circuit includes an eleventh transistor and a twelfth transistor; The first terminal of the eleventh transistor and the first terminal of the twelfth transistor are both grounded. The control terminals of the eleventh transistor and the twelfth transistor are connected and connected to a fourth bias voltage. The second terminal of the eleventh transistor is connected to the first input terminal of the third chopper switch, and the second terminal of the twelfth transistor is connected to the second input terminal of the third chopper switch.

10. The differential amplifier circuit according to claim 4, characterized in that, It also includes the controller; The controller is connected to the first switch unit, the second switch unit, and the third switch unit respectively, and is used to control the common terminal of the first switch unit to be connected to the first selector terminal or the second selector terminal of the first switch unit; control the common terminal of the second switch unit to be connected to the first selector terminal or the second selector terminal of the second switch unit; and control the common terminal of the third switch unit to be connected to the first selector terminal or the second selector terminal of the third switch unit.

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