Analog front-end circuit and circuitry and electronic device

Abstract

The present invention provides an analog front-end circuit, circuit system, and electronic device, including a first integrator and a signal readout module. The first integrator includes a transconductance amplification module, a mode switching module, and an integrating output capacitor. The mode switching module is connected between the sources of the first input MOSFET and the second input MOSFET in the transconductance amplification module. Since the signal types of the first differential input signal and the second differential input signal match the mode switching signal, the mode switching module can switch to the corresponding mode according to the mode switching signal. This allows for the detection of different signal types of the first differential input signal and the second differential input signal under the same transconductance amplification module and integrating output capacitor architecture, thereby reducing the detection cost of different signal types, greatly improving the flexibility and application scenarios of the chip in which the analog front-end circuit is located, and improving the linearity of the transconductance amplification module by acting as an equivalent resistor when the mode switching module is in voltage mode.

Description

Technical Field

[0001] This invention relates to the field of signal acquisition technology, and more particularly to an analog front-end circuit, circuit system, and electronic device. Background Technology

[0002] Reconfigurable multimodal analog front-end (AFE) circuits have become a research hotspot in physiological signal acquisition, wearable devices, and intelligent sensing systems in recent years. These circuits aim to achieve high-efficiency, high-precision, and highly integrated acquisition of various physiological signals, such as electrocardiogram (ECG), bioimpedance (BioZ), Galvanic skin response (GSR), photoplethysmographic (PPG), and electrochemical (E-Chem) signals. This supports multimodal health monitoring and environmental sensing in miniaturized and portable devices.

[0003] However, integrators in existing analog front-end circuits struggle to detect different signal types using the same transconductance amplification module, thus limiting the flexibility of the chip housing the transconductance amplification module. Furthermore, existing transconductance amplification modules exhibit nonlinearity, affecting the linearity of the analog front-end circuit. Summary of the Invention

[0004] To solve the above-mentioned technical problems, the present invention provides an analog front-end circuit, circuit system, and electronic device, which realizes the detection of different signal types of integrator through the same transconductance amplification module and improves the linearity of the transconductance amplification module.

[0005] The technical solution of the present invention provides an analog front-end circuit, comprising: A first integrator includes a transconductance amplification module, a mode switching module, and an integrating output capacitor. The transconductance amplification module includes a first input MOSFET and a second input MOSFET. The gate of the first input MOSFET receives a first differential input signal, and the gate of the second input MOSFET receives a second differential input signal. The mode switching module is connected between the sources of the first and second input MOSFETs. The mode switching module switches to voltage mode, current mode, or conductance mode according to a mode switching signal. When the mode switching module switches to voltage mode, it is equivalent to a resistor. The signal types of the first and second differential input signals match the mode switching signal. A first terminal of the integrating output capacitor is connected to the drain of the first input MOSFET, and the other terminal of the integrating output capacitor is connected to the drain of the second input MOSFET. The integrating output capacitor outputs a first-stage integrated signal of the first and second differential input signals. The signal reading module is used to digitally quantize the first-level integral signal, output a digital output signal, perform digital-to-analog conversion on the digital output signal, output a first feedback differential signal to the source of the first input MOS transistor, and output a second feedback differential signal to the source of the second input MOS transistor.

[0006] Optionally, the transconductance amplification module further includes: A first input amplifier, wherein the non-inverting input terminal of the first input amplifier is connected to the first differential input signal, the inverting input terminal of the first input amplifier is connected to the source of the first input MOSFET, and the output terminal of the first input amplifier is connected to the gate of the first input MOSFET; The second input amplifier has the non-inverting input terminal connected to the second differential input signal, the inverting input terminal connected to the source of the second input MOSFET, and the output terminal connected to the gate of the second input MOSFET.

[0007] Optionally, the mode switching module includes a source degradation resistive unit, a photoelectric conversion unit, a conductivity unit, a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit; The two ends of the source degradation resistive unit are connected to or disconnected from the source of the first input MOS transistor and the source of the second input MOS transistor through the first switching unit and the second switching unit, respectively. One end of the third switching unit is connected to the source of the first input MOS transistor, one end of the fourth switching unit is connected to the source of the second input MOS transistor, and the other ends of the third switching unit and the other ends of the fourth switching unit are connected to the photoelectric conversion unit or the conductivity unit. When the two ends of the source degradation resistive unit are connected to the source of the first input MOS transistor and the source of the second input MOS transistor, the mode switching module is in voltage mode; When the two ends of the photoelectric conversion unit are connected to the source of the first input MOS transistor and the source of the second input MOS transistor, the mode switching module is in current mode; When the two ends of the conductivity unit are connected to the source of the first input MOS transistor and the source of the second input MOS transistor, the mode switching module is in conductivity mode.

[0008] Optionally, the source degradation resistive unit includes a resistor; The photoelectric conversion unit includes an external photodiode. The positive terminal of the photodiode is coupled to the source of the first input MOS transistor through the third switching unit, and the negative terminal of the photodiode is coupled to the source of the second input MOS transistor through the fourth switching unit. The conductivity unit includes human skin.

[0009] Optionally, the first switching unit, the second switching unit, the third switching unit, and the fourth switching unit each include a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a fifth NMOS transistor; The drain of the seventh PMOS transistor serves as the first connection terminal of the switching subunit. The source of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor and the substrate of the ninth PMOS transistor. The gate of the seventh PMOS transistor is connected to the second enable signal. The gate of the eighth PMOS transistor is connected to a first enable signal, and the source of the eighth PMOS transistor is connected to a power supply voltage. The first enable signal and the second enable signal are out of phase. The source of the ninth PMOS transistor is connected to the drain of the seventh PMOS transistor, the gate of the ninth PMOS transistor is connected to the second enable signal, and the drain of the ninth PMOS transistor serves as the second connection terminal of the switching subunit. The gate of the fifth NMOS transistor is connected to the first enable signal, the source of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the fifth NMOS transistor is connected to the drain of the ninth PMOS transistor.

[0010] Optionally, it may also include a first current switch, a second current switch, and a voltage-current multiplexing module; One end of the first current switch is connected to the source of the first input MOSFET, and the other end of the first current switch is connected to the second current terminal of the voltage-current multiplexing module. One end of the second current switch is connected to the source of the second input MOSFET, and the other end of the second current switch is connected to the first current terminal of the voltage-current multiplexing module. Both the first current switch and the second current switch are turned on when the mode switching module switches to current mode or conductance mode. The voltage-current multiplexing module is used for: When the mode switching module switches to the current mode or the conductance mode, it outputs the corresponding high current from its first current terminal according to the high current control signal, and extracts the corresponding low current from its second current terminal according to the low current control signal. The flow direction from the high current to the low current is opposite to the flow direction of the current from the source of the first input MOS transistor to the source of the second input MOS transistor. When the mode switching module switches to the current mode, it outputs a corresponding low bias voltage to the gate of the first input MOSFET according to the low voltage control signal, and outputs a corresponding high bias voltage to the gate of the second input MOSFET according to the high voltage control signal. When the mode switching module switches to the conductivity mode, it outputs a corresponding high-level excitation voltage to the gate of the first input MOS transistor according to the high-level voltage control signal, and outputs a corresponding low-level excitation voltage to the gate of the second input MOS transistor according to the low-level voltage control signal.

[0011] Optionally, the voltage-current multiplexing module includes: A reference current unit is used to generate a reference current based on a reference voltage. The first current mirror unit is used to mirror the reference current proportionally and output the first mirror current. The reference voltage unit is used to output a high-level bias voltage or a high-level excitation voltage under the control of the high-level voltage control signal based on the first mirror current and the reference voltage, and to output a low-level bias voltage or a low-level excitation voltage under the control of the low-level voltage control signal. Several high-level current mirror units are used to mirror the reference current proportionally and output several high-level sub-currents. The magnitudes of the high-level sub-currents are arranged sequentially according to binary weights. Several low-level current mirror units are used to mirror the reference current proportionally and extract several low-level sub-currents. The magnitude relationship of the several low-level sub-currents is also arranged in order according to binary weights. The current output unit is configured to control the output of several high-level sub-currents according to the high-level current control signal, so as to output the high-level current from the first current terminal; and is also configured to control the output of several low-level sub-currents according to the low-level current control signal, so as to draw the low-level current from the second current terminal.

[0012] Optionally, the reference current unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a reference amplifier, and an array resistor; the sources of the first PMOS transistor and the third PMOS transistor are both connected to the power supply voltage; the gate of the first PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the second PMOS transistor, the gate of the fourth PMOS transistor, and the output terminal of the reference amplifier; the drain of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to one end of the array current; the other end of the array resistor is connected to ground; the drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor; the drain of the fourth PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor; the source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to ground; The first current mirror unit includes several high-level current sub-units and several low-level current sub-units; each of the high-level current sub-units includes a fifth PMOS transistor and a sixth PMOS transistor, the source of each fifth PMOS transistor is connected to the power supply voltage, the drain of each fifth PMOS transistor is connected to the source of the corresponding sixth PMOS transistor, and the gate of each fifth PMOS transistor is connected to the gate of the third PMOS transistor; the gate of each sixth PMOS transistor is connected to the gate of the fourth PMOS transistor; each of the low-level current sub-units includes a third NMOS transistor and a fourth NMOS transistor, the gate of each third NMOS transistor is connected to the gate of the first NMOS transistor, the source of each third NMOS transistor is connected to the drain of the corresponding fourth NMOS transistor; the gate of each fourth NMOS transistor is connected to the gate of the second NMOS transistor, and the drain of each fourth NMOS transistor is connected to the ground terminal; The reference voltage unit includes several first high-level switches, first voltage-dividing resistors, second voltage-dividing resistors, and several first low-level switches. One end of each first high-level switch is connected to the drain of the corresponding sixth PMOS transistor, and the other end of each first high-level switch is connected to one end of the first voltage-dividing resistor. Each of the several first high-level switches outputs the high-level bias voltage or the high-level excitation voltage from one end of the first voltage-dividing resistor according to the high-level voltage control signal. The other end of each first voltage-dividing resistor is connected to one end of the second voltage-dividing resistor and to the reference voltage. The other end of each second voltage-dividing resistor is connected to one end of each of the first low-level switches. Each of the several first low-level switches outputs the low-level bias voltage or the low-level excitation voltage from the other end of the second voltage-dividing resistor according to the low-level voltage control signal. The other end of each first low-level switch is connected to the drain of the corresponding third NMOS transistor. The current output unit includes a plurality of second high-level switches and a plurality of second low-level switches; one end of each second high-level switch is connected to the current output terminal of the corresponding high-level current mirror unit, and the other end of each second high-level switch is connected to the first current terminal; the plurality of second high-level switches cause the first current terminal to output the high-level current according to the high-level current control signal; one end of each second low-level switch is connected to the current extraction terminal of the corresponding low-level current mirror unit, and the other end of each second low-level switch is connected to the second current terminal; the plurality of second low-level switches cause the second current terminal to extract the high-level current according to the low-level current control signal.

[0013] Optionally, it also includes a current excitation module, which, when the mode switching module is in voltage mode, outputs a first differential excitation voltage to the gate of the first input MOSFET based on the initial excitation current flowing through the resistor under test, and outputs a second differential excitation voltage to the gate of the second input MOSFET. The current excitation module is also used to migrate the flicker noise in the initial excitation current to a preset frequency and its harmonics by matching the switch with several dynamic elements according to the switch switching signal. The preset frequency is tens of kHz, and the maximum frequency of the resistor signal under test is hundreds of Hz.

[0014] Optionally, the current excitation module includes: An initial excitation current source is used to output the initial excitation current; The second current mirror unit is used to mirror the initial excitation current proportionally and output the excitation current. An excitation resistor is provided, one end of which is connected to the output terminal of the second current mirror unit, and the other end of which is coupled to the power supply voltage. One end of the excitation resistor outputs the second differential excitation voltage, and the other end of the excitation resistor outputs the first differential excitation voltage. A common-mode control unit is used to detect the common-mode voltage of the first differential excitation voltage and the second differential excitation voltage, compare the common-mode voltage with the reference voltage, and stabilize the common-mode voltage to the reference voltage based on the comparison result; The plurality of dynamic matching switches are respectively disposed in the corresponding common source and common gate current source structure in the second current mirror unit. The plurality of dynamic matching switches are used to transfer the flicker noise in the excitation current to the preset frequency and its harmonics according to the switch switching signal.

[0015] The present invention also provides a circuit system, including the analog front-end circuit.

[0016] The present invention also provides an electronic device, including the aforementioned circuit system.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: In the analog front-end circuit provided by the technical solution of this invention, the mode switching module is connected between the sources of the first input MOSFET and the second input MOSFET in the transconductance amplification module. Since the signal types of the first differential input signal and the second differential input signal match the mode switching signal, the mode switching module can match the signal types of the first differential input signal and the second differential input signal according to the mode switching signal and switch to the corresponding mode, thereby detecting the first differential input signal and the second differential input signal of different signal types. If the transconductance amplification module detects a voltage signal, such as an electrocardiogram signal or a bioimpedance signal, the mode switching module switches to the voltage mode. If the transconductance amplification module detects a current signal, such as a blood volumetric signal, the mode switching module switches to the current mode. If the transconductance amplification module detects a conductance signal, such as a skin conductance response signal, the mode switching module switches to the conductance mode.

[0018] Therefore, under the same transconductance amplification module and integrating output capacitor architecture, different signal types can be detected simply by switching the mode of the mode switching module, thereby reducing the detection cost of different signal types and greatly improving the flexibility and application scenarios of the chip where the analog front-end circuit is located. Simultaneously, since the mode switching module is equivalent to a resistor in voltage mode, it is equivalent to introducing a resistor between the sources of the first and second input MOSFETs. This makes the equivalent transconductance of the differential input pair formed by the first and second input MOSFETs approximately the reciprocal of the aforementioned resistance, thus greatly improving the linearity of the transconductance amplification module, i.e., the linearity of the analog front-end circuit.

[0019] Furthermore, by setting a first input amplifier between the first differential input signal and the first input MOS transistor, and setting a second input amplifier between the second differential input signal and the second input MOS transistor, a nested negative feedback is formed. This utilizes the huge gain of the first / second input amplifier to make the equivalent transconductance of the transconductance amplification module more approximate the reciprocal of the equivalent resistance of the mode switching module in voltage mode, thereby relaxing the design constraints on the equivalent resistance and equivalent transconductance.

[0020] Furthermore, the technical solution of the present invention provides a voltage-current multiplexing module, which, when the mode switching module switches to the current mode or the conductance mode, outputs a corresponding high-level current from its first current terminal according to the high-level current control signal, and extracts a corresponding low-level current from its second current terminal according to the low-level current control signal. The flow direction from the high-level current to the low-level current is opposite to the flow direction of the current from the source of the first input MOS transistor to the source of the second input MOS transistor, thereby canceling the DC component in the integrated current and improving the detection accuracy of the AC component in the integrated current. When the mode switching module switches to the current mode, the voltage-current multiplexing module outputs a corresponding low-level bias voltage to the gate of the first input MOS transistor according to the low-level voltage control signal, and outputs a corresponding high-level bias voltage to the gate of the second input MOS transistor according to the high-level voltage control signal, thereby applying a reverse bias voltage across the two ends of the photoelectric conversion unit, which effectively reduces the parasitic capacitance of the photoelectric conversion unit and improves the stability of the overall circuit.

[0021] Finally, when the mode switching module switches to the conductance mode, the voltage-current multiplexing module outputs a corresponding high-level excitation voltage to the gate of the first input MOS transistor according to the high-level voltage control signal, and outputs a corresponding low-level excitation voltage to the gate of the second input MOS transistor according to the low-level voltage control signal, so as to form a positive excitation voltage at both ends of the conductance unit.

[0022] In summary, the technical solution of this invention fully realizes the output of DC canceling current through the voltage and current multiplexing module, applies reverse bias voltage to both ends of the photoelectric conversion unit, and forms positive excitation voltage at both ends of the conductance unit. Thus, while reducing costs through circuit multiplexing, it also assists in the acquisition and detection of various signals.

[0023] Furthermore, in the current excitation module, the common-mode control unit is used to detect the common-mode voltage of the first differential excitation voltage and the second differential excitation voltage, compare the common-mode voltage with the reference voltage, and stabilize the common-mode voltage to the reference voltage based on the comparison result, thereby achieving automatic stabilization of the common-mode voltage. This eliminates the need for an additional bias voltage generation circuit and reduces circuit costs. In addition, each of the dynamic matching switches is respectively disposed within the corresponding common-source cascode current source structure in the second current mirror unit. The plurality of dynamic matching switches are used to migrate the flicker noise in the initial excitation current to the preset frequency and its harmonics according to the switch switching signal, thereby greatly reducing the noise of the excitation current and improving the accuracy of the first differential excitation voltage and the second differential excitation voltage. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A schematic diagram of the circuit structure of the analog front-end circuit provided for an embodiment of the present invention; Figure 2 A schematic diagram of the circuit structure of the current excitation module provided for an embodiment of the present invention; Figure 3 A schematic diagram of the circuit structure of the first integrator acquiring ECG or BioZ signals, provided for an embodiment of the present invention; Figure 4 A schematic diagram of the circuit structure of the first integrator acquiring PPG or GSR signals, provided for an embodiment of the present invention; Figure 5 A schematic diagram of the circuit structure of a voltage-current multiplexing module provided for an embodiment of the present invention; Figure 6 A circuit structure diagram of the first switching unit, the second switching unit, the third switching unit, and the fourth switching unit provided for embodiments of the present invention; Figure 7 A schematic diagram of a signal reading module provided in an embodiment of the present invention.

[0026] Explanation of reference numerals in the attached figures: 1-First integrator; 11-Transconductance amplification module; 12-Mode switching module; 2-Signal reading module; 21-Second integrator; 22-bit successive approximation quantizer; 23-Data weighted average unit; 24-Feedback Resistor Digital-to-Analog Converter Array; 3-Current excitation module; 311 - First common-source cascode current source structure; 312 - Second common-source cascode current source structure; 313 - Third common-source cascode current source structure; 32-Dynamic element matching switch; 33-Common mode control unit; 331-Common Mode Feedback Subunit; 4-Voltage and current multiplexing module; 41-Reference Current Unit; 42 - First current mirror unit; 421 - High-level current subunit; 422 - Low-level current subunit; 43 - Reference Voltage Unit; 44-High-position current mirror unit; 45 - Low-position current mirror unit; 46 - Current output unit; M1 - First input MOSFET; M2 - Second input MOSFET; M3 - Common-mode controlled PMOS transistor; M4 - First PMOS transistor; M5 - Second PMOS transistor; M6 - Third PMOS transistor; M7 - Fourth PMOS transistor; M8 - First NMOS transistor; M9 - Second NMOS transistor; M10 - Fifth PMOS transistor; M11 - The sixth PMOS transistor; M12 - Third NMOS transistor; M13 - Fourth NMOS transistor; M14 - Seventh PMOS transistor; M15 - Eighth PMOS transistor; M16 - Ninth PMOS transistor; M17 - Fifth NMOS transistor; CINT - Integrating output capacitor; EN1 - First enable signal; EN2 - Second enable signal; Vinp1 - First differential input signal; Vinn1 - Second differential input signal; Vinp2 - First differential feedback signal; Vinn2 - Second differential feedback signal; VCM - Reference voltage; VBIOZP - First differential excitation voltage; VBIOZN - Second differential excitation voltage; VREFP1 - High bias voltage; VREFP2 - High-level excitation voltage; VREFN1 - Low bias voltage; VREFN2 - Low-level excitation voltage; Vout - Digital output signal; RBIOZ - Excitation resistor; Rs - source degenerates resistive unit; Va - First-order integral signal; OP1 - First Input Amplifier; OP2 - Second Input Amplifier; SW1 - First switching unit; SW2 - Second Switching Unit; SW3 - Third Switching Unit; SW4 - Fourth Switching Unit; SW5 - First current switch; SW6 - Second current switch; SW7 - First high-position switch; SW8 - First low-position switch; SW9 - Second high-position switch; SW10 - Second low-position switch; SW11 - Third high-position switch; SW12 - Third low-position switch; SW13 - Fourth high-position switch; SW14 - Fourth low-position switch; D GSRP <0:15> - High-level voltage control signal; D GSRN <0:15> - Low-level voltage control signal; ICPP<0:7> - High-level current control signal; ICPN<0:7> - Low-level current control signal; IP - High Current; IN - Low-level current; r1 - First voltage divider resistor; r2 - Second voltage divider resistor; r3 - Third voltage divider resistor; r4 - Fourth voltage divider resistor; PD-photoelectric conversion unit; GSKIN - Conductivity Unit; IREF - Initial Excitation Current Source. Detailed Implementation

[0027] As described in the background section, the reconfigurable multimodal simulation front end aims to achieve high-efficiency, high-precision, and high-integration acquisition of various physiological signals, such as electrocardiogram (ECG), bio-impedance (BioZ), Galvanic Skin Response (GSR), photoplethysmographic (PPG), and electrochemical (E-Chem) signals.

[0028] Existing technologies typically adopt the following approach when implementing the functionality of the aforementioned reconfigurable multimodal simulation front-end: (1) Parallelized multimodal analog front-end circuit: The specific structure of this scheme is generally to correspond multiple physiological signals to be acquired to multiple channels, and each channel has a corresponding different circuit structure. Therefore, this scheme can perform targeted optimization for the signals to be acquired for each channel. However, due to the parallel architecture of this scheme, it is not advantageous in terms of area and power consumption. For example, the area of ​​the overall circuit architecture will be greater than 10 mm². 2 Furthermore, the power consumption of the overall circuit architecture can reach the milliwatt level, which is not conducive to the integration of miniaturized devices on the edge.

[0029] (2) Reconfigurable instrumentation amplifier combined with a shareable analog-to-digital converter: This scheme mainly focuses on reconfiguring the front-end amplifier to avoid the waste of resources on the shareable analog-to-digital converter in the parallel multi-channel structure, and realizes the measurement of different types of physiological signals through the reconfigurable front-end amplifier. However, this scheme designs the amplifier and the analog-to-digital converter separately, which sacrifices some power consumption compared with the direct digital structure. Moreover, existing chip designs often face the problem of low resolution of the analog-to-digital converter (12-bit to 14-bit), which is not conducive to the reading of weak physiological signals.

[0030] (3) Reconfigurable direct digital analog front-end circuit: This scheme combines the advantages of reconfigurable instrumentation amplifiers combined with shared analog-to-digital converters and high-precision analog-to-digital converters. It often uses a high-resolution Δ-Σ analog-to-digital converter and optimizes physiological signal acquisition at the first-stage integrator, such as input impedance, noise, and common-mode rejection ratio. However, this scheme often suffers from problems such as high noise, low linearity, and low input impedance, which have an adverse effect on the high-precision acquisition of human physiological signals.

[0031] In view of this, the technical solution of the present invention provides a novel analog front-end circuit, a circuit system, and an electronic device, including a first integrator and a signal readout module. The first integrator includes a transconductance amplification module, a mode switching module, and an integrating output capacitor. The mode switching module is connected between the source of the first input MOSFET and the source of the second input MOSFET in the transconductance amplification module. Since the signal types of the first differential input signal and the second differential input signal match the mode switching signal, the mode switching module can switch to the corresponding mode according to the mode switching signal, thereby detecting the first differential input signal and the second differential input signal of different signal types under the same transconductance amplification module and integrating output capacitor architecture. This reduces the detection cost of different signal types, greatly improves the flexibility and application scenarios of the chip in which the analog front-end circuit is located, and improves the linearity of the transconductance amplification module by acting as an equivalent resistor when the mode switching module is in voltage mode.

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] The technical solution of the present invention will be described in detail below with reference to the embodiments in this example. These embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0034] Please refer to Figure 1 This embodiment provides an analog front-end circuit, which includes a first integrator 1 and a signal reading module 2.

[0035] Please continue to refer to this. Figure 1 In this embodiment, the first integrator 1 includes a transconductance amplification module 11, a mode switching module 12, and an integral output capacitor CINT.

[0036] The transconductance amplification module 11 includes a first input MOSFET M1 and a second input MOSFET M2. The gate of the first input MOSFET M1 receives a first differential input signal Vinp1, and the gate of the second input MOSFET M2 receives a second differential input signal Vinn1.

[0037] The mode switching module 12 is connected between the source of the first input MOSFET M1 and the source of the second input MOSFET M2. The mode switching module 12 switches to voltage mode, current mode or conductance mode according to the mode switching signal. When the mode switching module 12 switches to voltage mode, it is equivalent to a resistor.

[0038] The first end of the integral output capacitor CINT is connected to the drain of the first input MOSFET M1, and the other end of the integral output capacitor CINT is connected to the drain of the second input MOSFET M2. The integral output capacitor CINT outputs the first-stage integral signal Va of the first differential input signal Vinp1 and the second differential input signal Vinn1.

[0039] Since the signal types of the first differential input signal Vinp1 and the second differential input signal Vinn1 match the mode switching signal, the mode switching module 12 can match the signal types of the first differential input signal Vinp1 and the second differential input signal Vinn1 according to the mode switching signal and switch to the corresponding mode.

[0040] If the transconductance amplification module 11 detects a voltage signal, such as an electrocardiogram signal or a bioimpedance signal, the mode switching module 12 switches to the voltage mode. If the transconductance amplification module 11 detects a current signal, such as a blood volumetric signal, the mode switching module 12 switches to the current mode. If the transconductance amplification module 11 detects a conductance signal, such as a skin conductance response signal, the mode switching module 12 switches to the conductance mode.

[0041] Therefore, this embodiment can achieve the detection of different signal types by simply switching the mode of the mode switching module 12 under the same transconductance amplification module 11 and integral output capacitor CINT architecture, thereby reducing the detection cost of different types of signals and greatly improving the flexibility and application scenarios of the chip where the analog front-end circuit is located.

[0042] Furthermore, since the mode switching module 12 is equivalent to a resistor when in voltage mode, it is equivalent to introducing a resistance between the sources of the first input MOSFET M1 and the second input MOSFET M2. Therefore, the equivalent transconductance of the differential input pair formed by the first input MOSFET M1 and the second input MOSFET M2 is approximately the reciprocal of the aforementioned resistance. That is, the formula for the equivalent transconductance of the differential input pair is as follows: Formula (1) In formula (1), Gm represents the equivalent transconductance of the differential input pair. gm represents the transconductance of the first input MOSFET M1 or the second input MOSFET M2. RS represents the equivalent resistance of the mode switching module 12 when it switches to voltage mode.

[0043] As can be seen from formula (1), the transconductance value of the equivalent transconductance is expressed by the transconductance of the first input MOS transistor M1 or the second input MOS transistor M2 and the equivalent resistance. When it is assumed that gm*RS is much greater than 1, the equivalent transconductance of the differential input pair formed by the first input MOS transistor M1 and the second input MOS transistor M2 can be approximated by the reciprocal of the equivalent resistance, thereby greatly improving the linearity of the transconductance amplification module 11 and thus improving the linearity of the analog front-end circuit.

[0044] Please continue to refer to this. Figure 1 However, gm*RS is much greater than 1 and cannot meet all designs. Therefore, the transconductance amplification module 11 in this embodiment also includes a first input amplifier OP1 and a second input amplifier OP2.

[0045] The non-inverting input terminal of the first input amplifier OP1 is connected to the first differential input signal Vinp1, the inverting input terminal of the first input amplifier OP1 is connected to the source of the first input MOS transistor M1, and the output terminal of the first input amplifier OP1 is connected to the gate of the first input MOS transistor M1.

[0046] The non-inverting input terminal of the second input amplifier OP2 is connected to the second differential input signal Vinn1, the inverting input terminal of the second input amplifier OP2 is connected to the source of the second input MOS transistor M2, and the output terminal of the second input amplifier OP2 is connected to the gate of the second input MOS transistor M2.

[0047] After adding the first input amplifier OP1 and the second input amplifier OP2, formula (1) is adjusted to: Formula (2) In formula (2), Av represents the gain of the first input amplifier OP1 or the second input amplifier OP2, thereby ensuring that gm*RS*Av is much greater than 1, greatly reducing the requirement to satisfy the condition that gm*RS*Av is much greater than 1, and thus making the equivalent transconductance of the differential input pair almost entirely dependent on the reciprocal of the equivalent resistance and almost unaffected by the overall architecture of the first integrator 1, thereby further improving the linearity of the transconductance amplification module 11.

[0048] Please continue to refer to this. Figure 1The mode switching module 12 includes a source degradation resistive unit Rs, a photoelectric conversion unit PD, a conductivity unit GSKIN, a first switching unit sw1, a second switching unit sw2, a third switching unit sw3, and a fourth switching unit sw4.

[0049] The two ends of the source degradation resistive unit Rs are connected to or disconnected from the source of the first input MOSFET M1 and the source of the second input MOSFET M2 through the first switching unit sw1 and the second switching unit sw2, respectively. Specifically, the equivalent resistance of the source degradation resistive unit Rs is equal to the equivalent resistance of the mode switching module 12 when it switches to voltage mode.

[0050] Furthermore, the source degradation resistive unit Rs can be a resistor. Of course, in other embodiments, the source degradation resistive unit Rs can be other resistive devices, and this is not limited here. The resistance value of the resistor can be 50kΩ.

[0051] One end of the third switching unit sw3 is connected to the source of the first input MOS transistor M1, one end of the fourth switching unit sw4 is connected to the source of the second input MOS transistor M2, and the other ends of the third switching unit sw3 and the fourth switching unit sw4 are connected to the photoelectric conversion unit PD or the conductivity unit GSKIN.

[0052] Furthermore, the photoelectric conversion unit PD can be a photodiode. The conductivity unit GSKIN can be human skin.

[0053] When the mode switching signal controls both the first switching unit sw1 and the second switching unit sw2 to be turned on, and controls both the third switching unit sw3 and the fourth switching unit sw4 to be turned off, the two ends of the source degradation resistive unit Rs are connected to the source of the first input MOSFET M1 and the source of the second input MOSFET M2, and the mode switching module 12 is in voltage mode. In voltage mode, the first integrator 1 can detect voltage signals such as electrocardiogram (ECG) signals and bio-impedance (BioZ) signals.

[0054] When the mode switching signal controls the first switching unit sw1 and the second switching unit sw2 to be turned off, and controls the third switching unit sw3 and the fourth switching unit sw4 to be turned on, and the other end of the third switching unit sw3 and the other end of the fourth switching unit sw4 are connected to the photoelectric conversion unit PD, the mode switching module 12 is in current mode. In current mode, the first integrator 1 can detect current signals such as photoplethysmographic (PPG) signals.

[0055] When the other end of the third switching unit sw3 and the other end of the fourth switching unit sw4 are connected to the human skin, the mode switching module 12 is in conductivity mode. In conductivity mode, the first integrator 1 can detect conductivity signals such as Galvanic Skin Response (GSR).

[0056] The following description uses the first integrator 1 provided in this embodiment to detect ECG, BioZ, PPG, and GSR signals respectively as an example to illustrate the auxiliary circuit additionally provided in the analog front-end circuit: For detecting ECG signals: ECG signals are acquired via surface electrodes, where the contact impedance between the dry electrodes and the skin can reach several MΩ or even hundreds of MΩ. If the input impedance of the first integrator 1 is not high enough, the signal will experience voltage division and attenuation between the electrode contact impedance and the input impedance of the first integrator 1, resulting in a smaller amplitude of the acquired signal than the actual value. For weak ECG signals, this attenuation can severely affect diagnostic accuracy. Furthermore, insufficient input impedance also reduces the common-mode rejection ratio, making it easier for 50Hz power line interference to couple into the signal path.

[0057] Furthermore, the main energy of the ECG signal is concentrated in the extremely low frequency range, for example, 0.5Hz to 150Hz. The energy of the inherent 1 / f noise (flicker noise) of the first input MOSFET M1, the second input MOSFET M2, and the MOSFETs in the amplifier is also concentrated in the low-frequency region, and the power spectral density of flicker noise is inversely proportional to frequency. Therefore, within the signal bandwidth of the ECG, flicker noise is the primary noise source, significantly reducing the signal-to-noise ratio.

[0058] To address the aforementioned problems with the ECG signal, this embodiment incorporates chopper switches at the input terminals of both the first input amplifier OP1 and the second input amplifier OP2. These switches modulate the first differential input signal Vinp1 input to the first input amplifier OP1 and the second differential input signal Vinn1 input to the second input amplifier OP2 using the chopper frequency. This shifts the first differential input signal Vinp1 and the second differential input signal Vinn1, which serve as the ECG signal, to the chopper frequency. The signal is then amplified by the first input amplifier OP1 and the second input amplifier OP2, and demodulated to restore it to baseband.

[0059] Since the first differential input signal Vinp1 and the second differential input signal Vinn1 are modulated to near the chopping frequency, the flicker noise of the MOSFET and the offset voltage in the amplifier are mainly concentrated in the DC and low-frequency range and are not affected by the modulation of the front-end chopper switch. After demodulating the outputs of the first input amplifier OP1 and the second input amplifier OP2, the useful signal will be restored to the baseband, while the flicker noise and the offset voltage will be modulated to near the chopping frequency. The flicker noise and the offset voltage near the chopping frequency will be filtered out by the low-pass filter in the signal readout module 2.

[0060] For BioZ signals: Bioimpedance measurement involves injecting a known excitation current into the human body, typically on the order of tens of μA and with a frequency in the tens of kHz range. The impedance value is then calculated by measuring the voltage response generated between the electrodes. Therefore, flicker noise present in the excitation current directly affects the accuracy of the impedance measurement, ultimately manifesting as an error in the measurement.

[0061] Furthermore, when the excitation current flows through the human body impedance, the non-ideal characteristics of the current source of the excitation current may cause the common-mode voltage of the differential voltage generated at the electrode terminals to deviate from the expected value, resulting in a limited input common-mode range of the equivalent transconductance of the differential input structure composed of the first input MOSFET M1 and the second input MOSFET M2, or even causing circuit saturation.

[0062] Please refer to Figure 2 To address the aforementioned issues with the BioZ signal, the analog front-end circuit provided in this embodiment additionally includes a current excitation module 3. The current excitation module 3, when the mode switching module 12 is in voltage mode, outputs a first differential excitation voltage VBIOZP to the gate of the first input MOS transistor M1 based on the initial excitation current flowing through the resistor under test, and outputs a second differential excitation voltage VBIOZN to the gate of the second input MOS transistor M2.

[0063] The current excitation module 3 is also used to migrate the flicker noise in the initial excitation current to a preset frequency and its harmonics by matching the switch 32 with several dynamic elements according to the switch switching signal. The preset frequency is tens of kHz, and the maximum frequency of the resistor signal under test is hundreds of Hz.

[0064] Please continue to refer to this. Figure 2 The current excitation module 3 includes an initial excitation current source IREF, a second current mirror unit, an excitation resistor RBIOZ, several dynamic element matching switches 32, and a common mode control unit 33.

[0065] The initial excitation current source IREF is used to output the initial excitation current. Further, the initial excitation current can be 1 μA.

[0066] The second current mirror unit is used to mirror the initial excitation current proportionally and output the excitation current.

[0067] Furthermore, the second current mirror unit includes a first cascode current source structure 311, a second cascode current source structure 312, and a third cascode current source structure 313. The first cascode current source structure 311 is used to mirror the initial excitation current source IREF by a factor of five to output a current of 5μA. The second cascode current source structure 312 is used to mirror the 5μA current by a factor of five to output a current of 25μA. The third cascode current source structure 313 is used to control the 25μA current according to a current mirroring control signal, performing any one of the following mirroring methods: equal mirroring to five-fold mirroring, to output an excitation current of 25μA, 50μA, 75μA, 100μA, or 125μA. The magnitude of the current output by the third cascode current source structure 313 can be selected according to actual needs and is not limited here.

[0068] One end of the excitation resistor RBIOZ is connected to the output terminal of the second current mirror unit, and the other end of the excitation resistor RBIOZ is coupled to the power supply voltage. The excitation current output by the second current mirror unit flows through the excitation resistor RBIOZ, so that one end of the excitation resistor RBIOZ outputs the second differential excitation voltage VBIOZN, and the other end of the excitation resistor RBIOZ outputs the first differential excitation voltage VBIOZP.

[0069] The common-mode control unit 33 is used to detect the common-mode voltage of the first differential excitation voltage VBIOZP and the second differential excitation voltage VBIOZN, to compare the common-mode voltage with the reference voltage VCM, and to stabilize the common-mode voltage to the reference voltage VCM based on the comparison result.

[0070] Furthermore, the common-mode control unit 33 includes a common-mode control PMOS transistor M3 and a common-mode feedback subunit 331. The common-mode feedback subunit 331 samples the first differential excitation voltage VBIOZP and the second differential excitation voltage VBIOZN, compares the common-mode voltages of the first differential excitation voltage VBIOZP and the second differential excitation voltage VBIOZN with the reference voltage VCM, and outputs a common-mode control signal to the gate of the common-mode control PMOS transistor M3. The source of the common-mode control PMOS transistor M3 is connected to the power supply voltage, and the drain of the common-mode control PMOS transistor M3 is connected to the other end of the excitation resistor RBIOZ. The common-mode control signal is used to control the conduction state of the common-mode control PMOS transistor M3, thereby stabilizing the common-mode voltages of the first differential excitation voltage VBIOZP and the second differential excitation voltage VBIOZN to the reference voltage VCM, achieving automatic stabilization of the common-mode voltage, thus eliminating the need for an additional bias voltage generation circuit and reducing circuit cost.

[0071] Each of the aforementioned dynamic matching switches is respectively disposed within the corresponding common-source cascode current source structure in the second current mirror unit. These dynamic matching switches are used to switch the connection mode of the current mirror transistors corresponding to the common-source cascode current source structure according to the switch switching signal and at a preset frequency. Since the flicker noise of the initial excitation current is related to the bias state and conduction path of the current mirror transistor itself, by continuously switching the connection mode of each current mirror transistor, the flicker noise originally concentrated at low frequencies is shifted to the preset frequency and its harmonics. Because the preset frequency is much higher than the excitation frequencies of the first differential excitation voltage VBIOZP and the second differential excitation voltage VBIOZN, the shifted flicker noise will not fall within the signal bandwidth, thereby greatly reducing the noise of the excitation current and improving the accuracy of the first differential excitation voltage VBIOZP and the second differential excitation voltage VBIOZN.

[0072] For PPG and GSR signals: First, when the mode switching module 12 is in current mode to detect the PPG signal, a photodiode is connected between the sources of the first input MOSFET M1 and the second input MOSFET M2 to detect changes in light intensity in human tissue. The current generated by the photodiode contains a large DC component and a very small AC component. The DC component corresponds to the diffuse reflection of light through tissue and non-pulsating blood layers, while the AC component corresponds to the periodic changes in blood volume in arterial blood.

[0073] If the first integrator 1 directly integrates the DC component, it will occupy most of the input dynamic range of the first integrator 1, resulting in a serious lack of accuracy for the extremely small AC component.

[0074] When the mode switching module 12 is in conductance mode to detect the GSR signal, human skin is connected between the sources of the first input MOS transistor M1 and the second input MOS transistor M2 to measure the conductance of human skin.

[0075] Since skin conductance can vary from sub-μS to several μS, the range of variation of the DC current flowing through the skin under a fixed bias voltage is very large, resulting in the first integrator 1 having the same problem as the PPG signal detection.

[0076] It can be understood that when the mode switching module 12 switches to the current mode or the conductance mode, there is a large DC component in the integrated current flowing from the source of the first input MOS transistor M1 to the source of the second input MOS transistor M2, which will affect the input dynamic range of the first integrator 1 and reduce the detection accuracy of the effective AC component.

[0077] Please continue to refer to this. Figure 1 Therefore, the analog front-end circuit of this embodiment additionally provides a voltage and current multiplexing module 4, a first current switch sw5, and a second current switch sw6.

[0078] One end of the first current switch sw5 is connected to the source of the first input MOSFET M1, and the other end of the first current switch sw5 is connected to the second current terminal of the voltage-current multiplexing module 4. One end of the second current switch sw6 is connected to the source of the second input MOSFET M2, and the other end of the second current switch sw6 is connected to the first current terminal of the voltage-current multiplexing module 4.

[0079] When the analog front-end circuit acquires ECG or BioZ signals, the first switching unit sw1 and the second switch are both turned on by mode switching signals, the third switching unit sw3 and the fourth switch are both turned off by mode switching signals, and the first current switch sw5 and the second current switch sw6 are both turned off. Figure 3 As shown.

[0080] When the analog front-end circuit acquires the PPG or GSR signal, the first switching unit sw1 and the second switch are both turned off by the mode switching signal, the third switching unit sw3 and the fourth switch are both turned on by the mode switching signal, and the first current switch sw5 and the second current switch sw6 are both turned on. Figure 4 As shown.

[0081] The voltage-current multiplexing module 4 is used to: when the mode switching module 12 switches to the current mode or the conductance mode, output the corresponding high current IP from its first current terminal according to the high current control signal ICPP<0:7>, and extract the corresponding low current IN from its second current terminal according to the low current control signal ICPN<0:7>. The current flow from the high current IP to the low current IN is opposite to the current flow from the source of the first input MOSFET M1 to the source of the second input MOSFET M2, thereby canceling the DC component in the integrated current and improving the detection accuracy of the AC component in the integrated current.

[0082] Secondly, since the photoelectric conversion unit PD, especially the photodiode, has a large parasitic capacitance, it is easy to generate low-frequency poles at the source of the first input MOSFET M1 and the source of the second input MOSFET M2, which affects the stability of the overall circuit. Therefore, when the mode switching module 12 switches to the current mode, the voltage and current multiplexing module 4 is also used to output the corresponding low-level bias voltage VREFN1 to the gate of the first input MOSFET M1 according to the low-level voltage control signal DGSRN<0:15>, and to output the corresponding high-level bias voltage VREFP1 to the gate of the second input MOSFET M2 according to the high-level voltage control signal DGSRP<0:15>, thereby applying a reverse bias voltage across the two ends of the photoelectric conversion unit PD, which effectively reduces the parasitic capacitance of the photoelectric conversion unit PD and improves the stability of the overall circuit.

[0083] Finally, when the mode switching module 12 switches to the conductance mode, the voltage-current multiplexing module 4 outputs the corresponding high-level excitation voltage VREFP2 to the gate of the first input MOS transistor M1 according to the high-level voltage control signal DGSRP<0:15>, and outputs the corresponding low-level excitation voltage VREFN2 to the gate of the second input MOS transistor M2 according to the low-level voltage control signal DGSRN<0:15>, so as to form a positive excitation voltage across the conductance unit GSKIN.

[0084] Please refer to Figure 5 The voltage and current multiplexing module 4 includes a reference current unit 41, a first current mirror unit 42, a reference voltage unit 43, several high-level current mirror units 44, several low-level current mirror units 45, and a current output unit 46.

[0085] The reference current unit 41 is used to generate a reference current based on the reference voltage VCM.

[0086] Further, the reference current unit 41 includes a first PMOS transistor M4, a second PMOS transistor M5, a third PMOS transistor M6, a fourth PMOS transistor M7, a first NMOS transistor M8, a second NMOS transistor M9, a reference amplifier, and an array resistor; the source of the first PMOS transistor M4 and the source of the third PMOS transistor M6 are both connected to the power supply voltage, and the gate of the first PMOS transistor M4 is connected to the gate of the third PMOS transistor M6, the gate of the second PMOS transistor M5, the gate of the fourth PMOS transistor M7, and the output terminal of the reference amplifier. The drain of transistor M4 is connected to the source of the second PMOS transistor M5; the drain of the second PMOS transistor M5 is connected to one end of the array current; the other end of the array resistor is connected to ground; the drain of the third PMOS transistor M6 is connected to the source of the fourth PMOS transistor M7; the drain of the fourth PMOS transistor M7 is connected to the drain of the first NMOS transistor M8, the gate of the first NMOS transistor M8, and the gate of the second NMOS transistor M9; the source of the first NMOS transistor M8 is connected to the drain of the second NMOS transistor M9, and the source of the second NMOS transistor M9 is connected to ground.

[0087] The first current mirror unit 42 is used to mirror the reference current proportionally and output the first mirror current.

[0088] Further, the first current mirror unit 42 includes a plurality of high-level current sub-units 421 and a plurality of low-level current sub-units 422; each of the high-level current sub-units 421 includes a fifth PMOS transistor M10 and a sixth PMOS transistor M11, the source of each fifth PMOS transistor M10 is connected to the power supply voltage, the drain of each fifth PMOS transistor M10 is connected to the source of the corresponding sixth PMOS transistor M11, and the gate of each fifth PMOS transistor M10 is connected to the gate of the third PMOS transistor M6; each of the sixth PMOS transistors M11... The gates of all 11 are connected to the gate of the fourth PMOS transistor M7; each of the low-level current sub-units 422 includes a third NMOS transistor M12 and a fourth NMOS transistor M13, the gate of each third NMOS transistor M12 is connected to the gate of the first NMOS transistor M8, and the source of each third NMOS transistor M12 is connected to the drain of the corresponding fourth NMOS transistor M13; the gate of each fourth NMOS transistor M13 is connected to the gate of the second NMOS transistor M9, and the drain of each fourth NMOS transistor M13 is connected to the ground terminal. Specifically, in this embodiment, the first current mirror unit 42 includes 15 high-level current sub-units 421 and 15 low-level current sub-units 422.

[0089] The reference voltage unit 43 is used to output a high-level bias voltage VREFP1 or a high-level excitation voltage VREFP2 under the control of the high-level voltage control signal DGSRP<0:15> based on the first mirror current and the reference voltage VCM, and to output a low-level bias voltage VREFN1 or a low-level excitation voltage VREFN2 under the control of the low-level voltage control signal DGSRN<0:15>.

[0090] Furthermore, the reference voltage unit 43 includes several first high-level switches sw7, first voltage divider resistors r1, second voltage divider resistors r2, and several first low-level switches sw8. One end of each of the first high-level switches sw7 is connected to the drain of the corresponding sixth PMOS transistor M11, and the other end of each of the first high-level switches sw7 is connected to one end of the first voltage divider resistor r1. Each of the first high-level switches sw7 outputs the high-level bias voltage VREFP1 or the high-level excitation voltage VREFP2 from one end of the first voltage divider resistor r1 according to the high-level voltage control signal DGSRP<0:15>. The other end of the first voltage divider resistor r1 is connected to one end of the second voltage divider resistor r2 and to the reference voltage VCM. The other end of the second voltage divider resistor r2 is connected to one end of each of the first low-level switches sw8. Each of the first low-level switches sw8 outputs the low-level bias voltage VREFN1 or the low-level excitation voltage VREFN2 from the other end of the second voltage divider resistor r2 according to the low-level voltage control signal DGSRN<0:15>. The other end of each of the first low-level switches sw8 is connected to the drain of the corresponding third NMOS transistor M12. Specifically, in this embodiment, the number of first high-level switches sw7 is the same as and corresponds one-to-one with the number of high-level current subunits 421, and the number of first low-level switches sw8 is the same as and corresponds one-to-one with the number of low-level current subunits 422. Each first high-level switch sw7 is composed of a PMOS switch, and each first low-level switch sw8 is composed of an NMOS switch. The high-level voltage control signal DGSRP<0:15> and the low-level voltage control signal DGSRN<0:15> are inverse signals. Therefore, each first high-level switch sw7 and the corresponding first low-level switch sw8 are synchronously turned on or off.

[0091] Several high-level current mirror units 44 are used to mirror the reference current proportionally and output several high-level sub-currents. The magnitude relationship of the several high-level sub-currents is arranged in order according to binary weights.

[0092] Several low-position current mirror units 45 are used to mirror the reference current proportionally and extract several low-position sub-currents. The magnitude relationship of the several low-position sub-currents is also arranged in sequence according to binary weights.

[0093] Furthermore, in this embodiment, there are seven high-level current mirror units 44 and seven low-level current mirror units 45. The high-level current mirror unit 44 is composed of two PMOS transistors connected in series, and the low-level current mirror unit 45 is composed of two NMOS transistors connected in series.

[0094] The current output unit 46 is used to control the output of several high-level sub-currents according to the high-level current control signal ICPP<0:7>, so as to output the high-level current IP from the first current terminal; and is also used to control the output of several low-level sub-currents according to the low-level current control signal ICPN<0:7>, so as to extract the low-level current IN from the second current terminal.

[0095] Further, the current output unit 46 includes a plurality of second high-level switches sw9 and a plurality of second low-level switches sw10; one end of each second high-level switch sw9 is connected to the current output terminal of the corresponding high-level current mirror unit 44, and the other end of each second high-level switch sw9 is connected to the first current terminal. The plurality of second high-level switches sw9 cause the first current terminal to output the high-level current IP according to the high-level current control signal ICPP<0:7>; one end of each second low-level switch sw10 is connected to the current extraction terminal of the corresponding low-level current mirror unit 45, and the other end of each second low-level switch sw10 is connected to the second current terminal. The plurality of second low-level switches sw10 cause the second current terminal to extract the high-level current IP according to the low-level current control signal ICPN<0:7>. Specifically, in this embodiment, the second high-level switch sw9 can be a PMOS transistor, and the second low-level switch sw10 can be an NMOS transistor. The high-level current control signal ICPP<0:7> and the low-level current control signal ICPN<0:7> are also inverted signals.

[0096] Please continue to refer to this. Figure 5 The reference voltage unit 43 also includes several third high-level switches sw11, third voltage divider resistors r3, fourth voltage divider resistors r4, and several third low-level switches sw12.

[0097] One end of each of the third high-level switches sw11 is connected to the drain of the corresponding sixth PMOS transistor M11, and the other end of each of the third high-level switches sw11 is connected to one end of the second voltage divider resistor r2. Each of the third high-level switches sw11 is controlled to turn on and off by the low-level voltage control signal DGSRN<0:15>, and the third high-level switches sw11 are composed of PMOS transistors.

[0098] The other end of the third voltage divider resistor r3 is connected to one end of the fourth voltage divider resistor r4, and the other end of the fourth voltage divider resistor r4 is connected to one end of each of the third low-position switches sw12. The other end of each of the third low-position switches sw12 is connected to the drain of the corresponding third NMOS transistor M12. Each of the third low-position switches sw12 is controlled to turn on and off by the high-position voltage control signal DGSRP<0:15>, and the third low-position switches sw12 are composed of NMOS transistors.

[0099] This can be understood as follows: when the first high-level switch SW7 and the first low-level switch SW8 are simultaneously turned on, the third high-level switch SW11 and the third low-level switch SW12 are simultaneously turned off, and vice versa.

[0100] The reference voltage unit 43 further includes a plurality of fourth high-level switches sw13 and a plurality of fourth low-level switches sw14. Each of the fourth high-level switches sw13 corresponds one-to-one with a plurality of high-level current mirror units 44; therefore, one end of each fourth high-level switch sw13 is connected to the current output terminal of the corresponding high-level current mirror unit 44. Each of the fourth high-level switches sw13 corresponds one-to-one with a plurality of fourth low-level switches sw14; therefore, the other end of each fourth high-level switch sw13 is connected to one end of the corresponding fourth low-level switch sw14. Each of the fourth low-level switches sw14 corresponds one-to-one with a plurality of low-level current mirror units 45; therefore, the other end of each fourth low-level switch sw14 is connected to the current extraction terminal of the corresponding low-level current mirror unit 45.

[0101] Several fourth high-level switches sw13 are controlled to turn on and off by the low-level current control signal ICPN<0:7>, and several fourth low-level switches sw14 are controlled to turn on and off by the high-level current control signal ICPP<0:7>. Furthermore, the fourth high-level switches sw13 and the second high-level switch sw9 are both composed of PMOS transistors, and the fourth low-level switches sw14 and the second low-level switch sw10 are both composed of NMOS transistors. Therefore, when the second high-level switches sw9 and the second low-level switches sw10 are simultaneously turned on, the fourth high-level switches sw13 and the fourth low-level switches sw14 are simultaneously turned off, and vice versa.

[0102] Please refer to Figure 6 The first switching unit sw1, the second switching unit sw2, the third switching unit sw3, and the fourth switching unit sw4 may each include a seventh PMOS transistor M14, an eighth PMOS transistor M15, a ninth PMOS transistor M16, and a fifth NMOS transistor M17.

[0103] The drain of the seventh PMOS transistor M14 serves as the first connection terminal of the switching subunit. The source of the seventh PMOS transistor M14 is connected to the drain of the eighth PMOS transistor M15 and the substrate of the ninth PMOS transistor M16. The gate of the seventh PMOS transistor M14 is connected to the second enable signal EN2.

[0104] The gate of the eighth PMOS transistor M15 is connected to the first enable signal EN1, and the source of the eighth PMOS transistor M15 is connected to the power supply voltage. The first enable signal EN1 and the second enable signal EN2 are out of phase.

[0105] The source of the ninth PMOS transistor M16 is connected to the drain of the seventh PMOS transistor M14, the gate of the ninth PMOS transistor M16 is connected to the second enable signal EN2, and the drain of the ninth PMOS transistor M16 serves as the second connection terminal of the switching subunit.

[0106] The gate of the fifth NMOS transistor M17 is connected to the first enable signal EN1, the source of the fifth NMOS transistor M17 is connected to the drain of the seventh PMOS transistor M14, and the drain of the fifth NMOS transistor M17 is connected to the drain of the ninth PMOS transistor M16.

[0107] Please continue to refer to this. Figure 7 The signal reading module 2 includes a second integrator 21, a four-bit successive approximation quantizer 22, a data weighted averaging unit 23, and a feedback resistor digital-to-analog converter array 24.

[0108] The second integrator 21 is used to perform a second integration on the first-level integral signal Va and output the second-level integral signal to the four-bit successive approximation quantizer 22.

[0109] The four-bit successive approximation quantizer 22 is used to quantize the second-level integral signal and output a digital output signal Vout.

[0110] The data weighted averaging unit 23 is used to perform mismatch shaping on the digital output signal Vout and output the shaped digital output signal Vout to reduce the harmonic energy of the digital output signal Vout.

[0111] The feedback resistor digital-to-analog converter array 24 is used to perform digital-to-analog conversion on the shaped digital output signal Vout, and output a first differential feedback signal Vinp2 to the inverting input terminal of the first input amplifier OP1, and output a second differential feedback signal Vinn2 to the inverting input terminal of the second input amplifier OP2.

[0112] In other embodiments, a circuit system is also provided, including the analog front-end circuit provided in any of the above embodiments.

[0113] In other embodiments, an electronic device is also provided, including the circuit system provided in the above embodiments.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An analog front-end circuit, characterized in that, include: A first integrator includes a transconductance amplification module, a mode switching module, and an integrating output capacitor. The transconductance amplification module includes a first input MOSFET and a second input MOSFET. The gate of the first input MOSFET receives a first differential input signal, and the gate of the second input MOSFET receives a second differential input signal. The mode switching module is connected between the sources of the first and second input MOSFETs. The mode switching module switches to voltage mode, current mode, or conductance mode according to a mode switching signal. When the mode switching module switches to voltage mode, it is equivalent to a resistor. The signal types of the first and second differential input signals match the mode switching signal. A first terminal of the integrating output capacitor is connected to the drain of the first input MOSFET, and the other terminal of the integrating output capacitor is connected to the drain of the second input MOSFET. The integrating output capacitor outputs a first-stage integrated signal of the first and second differential input signals. The signal reading module is used to digitally quantize the first-level integral signal, output a digital output signal, perform digital-to-analog conversion on the digital output signal, output a first feedback differential signal to the source of the first input MOS transistor, and output a second feedback differential signal to the source of the second input MOS transistor.

2. The analog front-end circuit according to claim 1, characterized in that, The transconductance amplification module also includes: A first input amplifier, wherein the non-inverting input terminal of the first input amplifier is connected to the first differential input signal, the inverting input terminal of the first input amplifier is connected to the source of the first input MOSFET, and the output terminal of the first input amplifier is connected to the gate of the first input MOSFET; The second input amplifier has the non-inverting input terminal connected to the second differential input signal, the inverting input terminal connected to the source of the second input MOSFET, and the output terminal connected to the gate of the second input MOSFET.

3. The analog front-end circuit according to claim 1 or 2, characterized in that, The mode switching module includes a source degradation resistive unit, a photoelectric conversion unit, a conductivity unit, a first switching unit, a second switching unit, a third switching unit, and a fourth switching unit; The two ends of the source degradation resistive unit are connected to or disconnected from the source of the first input MOS transistor and the source of the second input MOS transistor respectively through the first switching unit and the second switching unit; One end of the third switching unit is connected to the source of the first input MOS transistor, one end of the fourth switching unit is connected to the source of the second input MOS transistor, and the other ends of the third switching unit and the other ends of the fourth switching unit are connected to the photoelectric conversion unit or the conductivity unit. When the two ends of the source degradation resistive unit are connected to the source of the first input MOS transistor and the source of the second input MOS transistor, the mode switching module is in voltage mode; When the two ends of the photoelectric conversion unit are connected to the source of the first input MOS transistor and the source of the second input MOS transistor, the mode switching module is in current mode; When the two ends of the conductivity unit are connected to the source of the first input MOS transistor and the source of the second input MOS transistor, the mode switching module is in conductivity mode.

4. The analog front-end circuit according to claim 3, characterized in that, The source degradation resistive unit includes a resistor; The photoelectric conversion unit includes an external photodiode. The positive terminal of the photodiode is coupled to the source of the first input MOS transistor through the third switching unit, and the negative terminal of the photodiode is coupled to the source of the second input MOS transistor through the fourth switching unit. The conductivity unit includes human skin.

5. The analog front-end circuit according to claim 3, characterized in that, The first switching unit, the second switching unit, the third switching unit, and the fourth switching unit all include a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, and a fifth NMOS transistor; The drain of the seventh PMOS transistor serves as the first connection terminal of the switching subunit. The source of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor and the substrate of the ninth PMOS transistor. The gate of the seventh PMOS transistor is connected to the second enable signal. The gate of the eighth PMOS transistor is connected to a first enable signal, and the source of the eighth PMOS transistor is connected to a power supply voltage. The first enable signal and the second enable signal are out of phase. The source of the ninth PMOS transistor is connected to the drain of the seventh PMOS transistor, the gate of the ninth PMOS transistor is connected to the second enable signal, and the drain of the ninth PMOS transistor serves as the second connection terminal of the switching subunit. The gate of the fifth NMOS transistor is connected to the first enable signal, the source of the fifth NMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the fifth NMOS transistor is connected to the drain of the ninth PMOS transistor.

6. The analog front-end circuit according to claim 3, characterized in that, It also includes a first current switch, a second current switch, and a voltage-current multiplexing module; One end of the first current switch is connected to the source of the first input MOSFET, and the other end of the first current switch is connected to the second current terminal of the voltage-current multiplexing module. One end of the second current switch is connected to the source of the second input MOSFET, and the other end of the second current switch is connected to the first current terminal of the voltage-current multiplexing module. Both the first current switch and the second current switch are turned on when the mode switching module switches to current mode or conductance mode. The voltage-current multiplexing module is used for: When the mode switching module switches to the current mode or the conductance mode, it outputs the corresponding high current from its first current terminal according to the high current control signal, and extracts the corresponding low current from its second current terminal according to the low current control signal. The flow direction from the high current to the low current is opposite to the flow direction of the current from the source of the first input MOS transistor to the source of the second input MOS transistor. When the mode switching module switches to the current mode, it outputs a corresponding low-level bias voltage to the gate of the first input MOSFET according to the low-level voltage control signal, and outputs a corresponding high-level bias voltage to the gate of the second input MOSFET according to the high-level voltage control signal. When the mode switching module switches to the conductivity mode, it outputs a corresponding high-level excitation voltage to the gate of the first input MOS transistor according to the high-level voltage control signal, and outputs a corresponding low-level excitation voltage to the gate of the second input MOS transistor according to the low-level voltage control signal.

7. The analog front-end circuit according to claim 6, characterized in that, The voltage-current multiplexing module includes: A reference current unit is used to generate a reference current based on a reference voltage. The first current mirror unit is used to mirror the reference current proportionally and output the first mirror current. The reference voltage unit is used to output a high-level bias voltage or a high-level excitation voltage under the control of the high-level voltage control signal based on the first mirror current and the reference voltage, and to output a low-level bias voltage or a low-level excitation voltage under the control of the low-level voltage control signal. Several high-level current mirror units are used to mirror the reference current proportionally and output several high-level sub-currents. The magnitudes of the high-level sub-currents are arranged sequentially according to binary weights. Several low-level current mirror units are used to mirror the reference current proportionally and extract several low-level sub-currents. The magnitude relationship of the several low-level sub-currents is also arranged in order according to binary weights. The current output unit is configured to control the output of several high-level sub-currents according to the high-level current control signal, so as to output the high-level current from the first current terminal; and is also configured to control the output of several low-level sub-currents according to the low-level current control signal, so as to draw the low-level current from the second current terminal.

8. The analog front-end circuit according to claim 7, characterized in that, The reference current unit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a reference amplifier, and an array resistor. The sources of the first PMOS transistor and the third PMOS transistor are both connected to the power supply voltage. The gate of the first PMOS transistor is connected to the gate of the third PMOS transistor, the gate of the second PMOS transistor, the gate of the fourth PMOS transistor, and the output terminal of the reference amplifier. The drain of the first PMOS transistor is connected to the source of the second PMOS transistor. The drain of the second PMOS transistor is connected to one end of the array current unit. The other end of the array resistor is connected to ground. The drain of the third PMOS transistor is connected to the source of the fourth PMOS transistor. The drain of the fourth PMOS transistor is connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor, and the source of the second NMOS transistor is connected to ground. The first current mirror unit includes several high-level current sub-units and several low-level current sub-units; each of the high-level current sub-units includes a fifth PMOS transistor and a sixth PMOS transistor, the source of each fifth PMOS transistor is connected to the power supply voltage, the drain of each fifth PMOS transistor is connected to the source of the corresponding sixth PMOS transistor, and the gate of each fifth PMOS transistor is connected to the gate of the third PMOS transistor; the gate of each sixth PMOS transistor is connected to the gate of the fourth PMOS transistor; each of the low-level current sub-units includes a third NMOS transistor and a fourth NMOS transistor, the gate of each third NMOS transistor is connected to the gate of the first NMOS transistor, the source of each third NMOS transistor is connected to the drain of the corresponding fourth NMOS transistor; the gate of each fourth NMOS transistor is connected to the gate of the second NMOS transistor, and the drain of each fourth NMOS transistor is connected to the ground terminal; The reference voltage unit includes several first high-level switches, first voltage-dividing resistors, second voltage-dividing resistors, and several first low-level switches. One end of each first high-level switch is connected to the drain of the corresponding sixth PMOS transistor, and the other end of each first high-level switch is connected to one end of the first voltage-dividing resistor. Each of the several first high-level switches outputs the high-level bias voltage or the high-level excitation voltage from one end of the first voltage-dividing resistor according to the high-level voltage control signal. The other end of the first voltage-dividing resistor is connected to one end of the second voltage-dividing resistor and to the reference voltage. The other end of the second voltage divider resistor is connected to one end of each of the first low-position switches. Each of the first low-position switches outputs the low-position bias voltage or the low-position excitation voltage from the other end of the second voltage divider resistor according to the low-position voltage control signal. The other end of each of the first low-position switches is connected to the drain of the corresponding third NMOS transistor. The current output unit includes a plurality of second high-level switches and a plurality of second low-level switches; one end of each second high-level switch is connected to the current output terminal of the corresponding high-level current mirror unit, and the other end of each second high-level switch is connected to the first current terminal; the plurality of second high-level switches cause the first current terminal to output the high-level current according to the high-level current control signal; one end of each second low-level switch is connected to the current extraction terminal of the corresponding low-level current mirror unit, and the other end of each second low-level switch is connected to the second current terminal; the plurality of second low-level switches cause the second current terminal to extract the high-level current according to the low-level current control signal.

9. The analog front-end circuit according to claim 3, characterized in that, It also includes a current excitation module, which, when the mode switching module is in voltage mode, outputs a first differential excitation voltage to the gate of the first input MOSFET based on the initial excitation current flowing through the resistor under test, and outputs a second differential excitation voltage to the gate of the second input MOSFET. The current excitation module is also used to migrate the flicker noise in the initial excitation current to a preset frequency and its harmonics by matching the switch with several dynamic elements according to the switch switching signal. The preset frequency is tens of kHz, and the maximum frequency of the resistor signal under test is hundreds of Hz.

10. The analog front-end circuit according to claim 9, characterized in that, The current excitation module includes: An initial excitation current source is used to output the initial excitation current; The second current mirror unit is used to mirror the initial excitation current proportionally and output the excitation current. An excitation resistor is provided, one end of which is connected to the output terminal of the second current mirror unit, and the other end of which is coupled to the power supply voltage. One end of the excitation resistor outputs the second differential excitation voltage, and the other end of the excitation resistor outputs the first differential excitation voltage. A common-mode control unit is used to detect the common-mode voltage of the first differential excitation voltage and the second differential excitation voltage, compare the common-mode voltage with the reference voltage, and stabilize the common-mode voltage to the reference voltage based on the comparison result; The plurality of dynamic matching switches are respectively disposed in the corresponding common source and common gate current source structure in the second current mirror unit. The plurality of dynamic matching switches are used to transfer the flicker noise in the excitation current to the preset frequency and its harmonics according to the switch switching signal.

11. A circuit system, characterized in that, Includes the analog front-end circuit as described in any one of claims 1 to 10.

12. An electronic device, characterized in that, Includes the circuit system described in claim 11.

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