Flip-flop adaptive metastability time optimization circuit
By using an adaptive metastable time optimization circuit for triggers to dynamically adjust the pull-up and pull-down drive strength, the performance degradation of traditional triggers under PVT conditions is solved, achieving timing stability and frequency improvement over a wide voltage and temperature range.
Patent Information
- Application Number
- CN202611147329.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-30
- Publication Date
- 2026-11-06
AI Technical Summary
The metastable time of traditional flip-flops cannot be adaptively adjusted, resulting in a decrease in circuit performance under different PVT conditions, which cannot meet the timing stability requirements of high-speed communication and high-performance computing.
An adaptive metastable time optimization circuit for a flip-flop is designed. Closed-loop control of the metastable time is achieved through a deserialization circuit and a detection and calibration circuit. The pull-up and pull-down drive strengths are dynamically adjusted using a digitally adjustable D flip-flop and a duty cycle detection module to optimize the metastable time.
Significantly reduces timing violation risk under different PVT conditions, ensures timing margin, and improves the operating frequency and reliability of high-speed mixed-signal integrated circuits.
Smart Images
Figure CN123055041A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit design technology, specifically relating to a trigger adaptive metastable time optimization circuit. Background Technology
[0002] The ever-increasing demand for high-speed communication and high-performance computing is driving data links toward higher transmission rates and lower timing margins. As the core unit of sequential circuits, the setup time and hold time of flip-flops directly determine the system's maximum operating frequency and timing stability. The metastable time, which is the sum of the two, is a key bottleneck limiting the performance of high-speed circuits.
[0003] Traditional flip-flops have their metastable times fixed during the design phase and cannot adaptively adjust to fluctuations in process, voltage, and temperature (PVT). Under extreme process angles such as FS (Fast PMOS / Slow NMOS) and SF (Slow PMOS / Fast NMOS), the circuit's drive capability and propagation delay will significantly shift, leading to a substantial increase in metastable time. This can cause setup or hold time violations, resulting in circuit malfunction or decreased reliability. Furthermore, as the operating voltage decreases and the operating temperature varies over a wide range, the impact of PVT fluctuations on device performance is further amplified. Traditional D flip-flops with fixed metastable times struggle to maintain stable timing margins across wide voltage and temperature ranges, failing to meet the stringent timing stability requirements of high-speed mixed-signal integrated circuits.
[0004] Therefore, how to realize a trigger that can dynamically adjust the metastable time and ensure stable timing margin under different PVT conditions has become a key technical problem that urgently needs to be solved in this field. Summary of the Invention
[0005] To address the aforementioned problems in the prior art, this invention provides a trigger adaptive metastable time optimization circuit.
[0006] The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a trigger adaptive metastable time optimization circuit, including a deserialization circuit and a detection and calibration circuit; the deserialization circuit includes at least two parallel first digitally adjustable D flip-flops; the detection and calibration circuit includes a second digitally adjustable D flip-flop, a duty cycle detection module, and an up / down counter; The deserialization circuit is used to control the pull-up and pull-down drive strength according to the Trim_Code signal of the first digitally adjustable D flip-flop in order to adjust the metastable time. The detection and calibration circuit is used to detect the duty cycle of the output signal of the DZ_Sense node of the second digitally adjustable D flip-flop using the duty cycle detection module, and obtain the corresponding adjustment signal; it is also used to output the adjustment signal to the control code of the Trim_Code signal of the up / down counter to control the pull-up and pull-down drive strength, and realize closed-loop control of metastable time.
[0007] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects: In the above technical solution, the present invention maintains the metastable time at a small value by dynamically adjusting the pull-up and pull-down drive strength, which significantly reduces the risk of timing violations under extreme process angles such as FS and SF, while ensuring timing margin under wide voltage and wide temperature range scenarios. It effectively improves the operating frequency and reliability of high-speed mixed-signal integrated circuits and can be widely used in timing circuit design in fields such as high-speed communication and high-performance computing.
[0008] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description
[0009] Figure 1 This is a schematic diagram of a trigger adaptive metastable time optimization circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a first digitally adjustable D flip-flop provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a master clock-controlled inverter provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of a metastable time provided in an embodiment of the present invention; Figure 5a This is a simulation waveform diagram of the output signal duty cycle provided in an embodiment of the present invention; Figure 5b This is a transient response simulation waveform diagram provided in an embodiment of the present invention. Detailed Implementation
[0010] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.
[0011] Figure 1 This is a schematic diagram of a trigger adaptive metastable time optimization circuit provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the circuit includes: a deserialization circuit and a detection and calibration circuit; the deserialization circuit includes at least two parallel first digitally adjustable D flip-flops; the detection and calibration circuit includes a second digitally adjustable D flip-flop, a duty cycle detection module, and an up / down counter; The deserialization circuit is used to control the pull-up and pull-down drive strength according to the Trim_Code signal of the first digitally adjustable D flip-flop in order to adjust the metastable time.
[0012] It is understandable that the Trim_Code signal includes the PU_Trim<1:0> signal and the PD_Trim<1:0> signal. The PU_Trim<1:0> and PD_Trim<1:0> signals of the first digitally adjustable D flip-flop control the pull-up and pull-down drive strength of its internal circuitry. This allows for adjustment of the circuit response speed based on different PVT conditions, ultimately achieving dynamic adjustment of the outputs D0 and D1 for the metastable time. The DZ_Sense detection node of the second digitally adjustable D flip-flop provides a key detection signal for closed-loop detection of the metastable time. The duty cycle detection module, composed of a low-pass filter and a comparator, detects the duty cycle of the output signal from the DZ_Sense node of the second digitally adjustable D flip-flop. By comparing the detection result with a reference duty cycle, it outputs a corresponding adjustment signal to an up / down counter, enabling real-time monitoring of the metastable time. The up / down counter dynamically adjusts the PU_Trim<1:0> and PD_Trim<1:0> control codes based on the output signal from the duty cycle detection module. By changing the pull-up and pull-down strength of the internal circuitry of the digitally adjustable D flip-flop, its drive strength is adjusted, ultimately achieving closed-loop optimization control of the metastable time.
[0013] Optionally, Figure 2 This is a schematic diagram of the structure of a first digitally adjustable D flip-flop provided in an embodiment of the present invention, as shown below. Figure 2 As shown, at least two parallel first digitally adjustable D flip-flops have the same structure, each including: a master latch and a slave latch; the master latch includes a master clock-controlled inverter, a master inverter, and a first feedback clock-controlled inverter. The master clock-controlled inverter receives the input signal DIN and the complementary clock signal CK. The output terminal node M outputs to node N through the master inverter. Node N is connected to the first feedback clock-controlled inverter controlled by the complementary clock signal CK; node N is also led out as a DZ_Sense detection node and connected to the input terminal of the slave clock-controlled inverter in the slave latch. The slave latch also includes a second feedback clock-controlled inverter controlled by the complementary clock signal CK, a logic AND gate, and an output inverter; the output terminal of the slave latch is connected to the input terminals of the second feedback clock-controlled inverter and the output inverter, respectively. The output terminal of the second feedback clock-controlled inverter is connected to the input terminal of the logic AND gate, the output terminal of the logic AND gate is connected to the input terminal of the output inverter, and the output terminal of the output inverter outputs the output signal Q. The overall structure of the first digitally adjustable D flip-flop enables data sampling, latching, and output, and provides a key signal detection node for closed-loop detection and regulation of metastable time.
[0014] It is worth mentioning that the structure of the second digitally adjustable D flip-flop is exactly the same as that of the first digitally adjustable D flip-flop, and will not be described in detail hereafter.
[0015] Optionally, Figure 3 This is a schematic diagram of the structure of a master clock-controlled inverter provided in an embodiment of the present invention, as shown below. Figure 3 As shown, the master clock inverter includes transistors MP1, MP2, MP5, MP6, MP9, MP10, MN3, MN4, MN7, MN8, MN11, and MN12. The sources of transistors MP1, MP5, and MP9 are connected to the power supply VDD, and their gates are connected to the clock signal CK. The drains of transistors MP2, MP6, and MP10 are connected to the output node DOUT. The drains of transistors MN3, MN7, and MN11 are connected to the output node DOUT. The sources of transistors MN4, MN8, and MN12 are connected to ground GND, and their gates are connected to the complementary clock signal CK. The gate of transistor MP2 and the gate of transistor MN3 are connected to the input signal DIN. The gate of transistor MP6 is connected to the input signal DIN via PU_Trim. <0> The signal is the output of the NOR gate connected to the input signal DIN. The gate of transistor MN7 is connected to PD_Trim. <0> The AND gate output of the DIN input signal is connected to the gate of transistor MP10 via PU_Trim. <1> The signal is the output of the NOR gate connected to the input signal DIN. The gate of transistor MN11 is connected to PD_Trim. <1> The AND gate output of the DIN input signal is connected to the source of transistors MP2, MP6, and MP10, respectively. The source of transistors MN3, MN7, and MN11 is connected to the drain of transistors MN4, MN8, and MN12, respectively. The conduction state of the corresponding branches is controlled by the PU_Trim<1:0> and PD_Trim<1:0> signals, enabling digitally adjustable control of the clock-controlled inverter's output drive strength and providing a basis for closed-loop dynamic adjustment of the metastable time.
[0016] It is understandable that metastable time includes setup time and hold time; setup time includes high-level setup time and low-level setup time; hold time includes high-level hold time and low-level hold time.
[0017] Figure 4 This is a schematic diagram of a metastable time provided in an embodiment of the present invention, showing the high-level setup time ( )like Figure 4In the diagram, ① (the black line represents the input data D of the D flip-flop, and the red line represents the clock) indicates the minimum time that D must remain high before the effective clock edge (the rising edge of CK) arrives. For example... Figure 2 and 3 As shown, at this time, the NMOS (MN4) pull-down branch of the master clock inverter in the master latch is turned on, and the PMOS (MP1) pull-up branch is turned off. Data is transmitted to node M through the pull-down path, and then to node N through the inverter. To ensure that node N stably establishes a high level (corresponding to D being high) on the effective clock edge, the establishment time is determined by the transmission delay of the pull-down branch, that is, the high-level establishment time is expressed as follows: ; in, Indicates the high-level setup time. The propagation delay of the pull-down path of transistor MN4 in the master clock inverter. The buffer delay from node M to node N, This is due to clock propagation delay. Under SF6 process conditions, NMOS drive is weak. Enlargement, leading to Significant increase.
[0018] Low-level setup time ( )like Figure 4 In section ③ (black line represents D, blue line represents the clock), it refers to the minimum time that D must remain low and stable before the effective clock edge arrives. At this time, the PMOS (MP1) pull-up branch of the master clock inverter is turned on, and the NMOS (MN4) pull-down branch is turned off. Data is transmitted through the pull-up path, and the setup time is determined by the pull-up branch transmission delay. The low-level setup time is expressed as follows: ; in, Low-level setup time, The propagation delay of the pull-up path of transistor MP1 in the main inverter. The PMOS (MP1) drive is weak at the FS process corner. Enlargement, leading to Significant increase.
[0019] Establish time asymmetric interpolation ( ): Defined as the difference between the maximum and minimum values during the setup time of the high and low levels, i.e.: ; This difference directly reflects the degree of imbalance in the pull-up / pull-down path driving capabilities. PVT fluctuations exacerbate this imbalance, making... Increase.
[0020] High level hold time ( )like Figure 4In section ④ (black line represents data D, blue line represents clock), it refers to the minimum time that data D must remain stable at a high level after the effective clock edge arrives. At this time, node N is low, and the NMOS pull-down branch of the main latch feedback clock inverter needs to quickly latch this level, or the main clock inverter needs to be turned off to prevent data transitions from overwriting it. The holding time is determined by the turn-off time of the PMOS controlled by CK in the main clock inverter. The high-level holding time is expressed as follows: ; in, The time when the PMOS transistor of the main clock-controlled inverter is turned off.
[0021] Low level hold time ( )like Figure 4 In step ② (black line represents data D, red line represents clock), it refers to the minimum time that data D must remain stable at a low level after the effective clock edge arrives. At this time, node N is high, and the PMOS pull-up branch of the feedback clock inverter needs to quickly latch this level, or the main clock inverter needs to be turned off to prevent data transitions from overwriting the signal. The hold time is determined by the turn-off time of the NMOS controlled by CK in the main clock inverter. The low-level hold time is expressed as follows: ; in, The time when the NMOS transistor of the main clock-controlled inverter is turned off.
[0022] Duration asymmetry difference ( ): Defined as the difference between the maximum and minimum values during the high and low level holding times, i.e.: ; Its physical essence is the imbalance between the turn-off capabilities of the PMOS and NMOS controlled by CK in the first-stage clocked inverter, which is also significantly affected by PVT fluctuations.
[0023] In the timing mechanism of a trigger, there is a strict mutual exclusion relationship between setup time and hold time. Based on the high and low levels of the input data, timing parameters can be divided into four categories, including high-level setup time. Low-level setup time High-level hold time Low level hold time The four types of parameters have fixed timing mutual exclusion logic: the circuit satisfies the high-level setup timing. Under certain conditions, the low-level holding time It certainly does not exist; its equivalent expression is: The value is 0; the circuit satisfies the low-level setup timing condition. High-level hold time It certainly does not exist; its equivalent expression is: The value is 0, and this mutual exclusion relationship is determined by the flip-flop clock sampling timing and the internal latch circuit operating logic. Based on the above definition, the metastable time in this invention ( To establish the sum of the time asymmetry difference and the hold time asymmetry difference, it is expressed as follows:
[0024] ; in, This indicates the metastable time.
[0025] The detection and calibration circuit is used to detect the duty cycle of the output signal of the DZ_Sense node of the second digitally adjustable D flip-flop using the duty cycle detection module, and obtain the corresponding adjustment signal; it is also used to output the adjustment signal to the control code of the Trim_Code signal for dynamic adjustment of the up / down counter, so as to control the pull-up and pull-down drive strength and realize closed-loop control of metastable time.
[0026] Figure 5a This is a simulation waveform diagram of the output signal duty cycle provided in an embodiment of the present invention. Figure 5b This is a transient response simulation waveform diagram provided in an embodiment of the present invention. See also... Figure 5a and Figure 5b In one embodiment of the present invention, a partial simulation result of a trigger adaptive metastable time optimization method and circuit is provided, wherein... Figure 5a This is a simulation waveform of the duty cycle of the output signal of the DZ_Sense node under different Trim control code configurations for the D trigger of this invention. The horizontal axis represents the simulation time (in ns), and the vertical axis represents the duty cycle (in %). Each plateau in the waveform corresponds to a fixed set of PU_Trim<1:0> and PD_Trim<1:0> control codes, intuitively demonstrating the effect of drive strength on the duty cycle adjustment. Figure 5b The transient response simulation waveform of the D flip-flop of the present invention in the deserialization circuit operation mode is shown from top to bottom as follows: high-speed serial data input signal DIN, complementary sampling clock signals CK and CKB, and two parallel data signals Q0 and Q1 output after being deserialized by the D flip-flop of the present invention.
[0027] Please refer to Table 1 for the simulation results comparing the metastable time of the D flip-flop before and after implementation of the embodiments of the present invention. Table 1 records the changes in key timing parameters before and after closed-loop regulation under different PVT conditions, including the PU / PDTrim control code, high and low level setup time, hold time, and final metastable time.
[0028] Table 1
[0029] As can be seen from the data in Table 1, before calibration, the metastable time of traditional fixed-structure triggers is significantly affected by PVT fluctuations, exhibiting large differences under different process angles, voltages, and temperatures: under TTNVNT (typical process, ambient voltage, ambient temperature) conditions, the metastable time is 0.6 ps; under SSLVHT (slow process, low voltage, high temperature) conditions, the metastable time is as high as 7 ps; under FFHVH (fast process, high voltage, high temperature) conditions, the metastable time is 2.5 ps; under SFLVHT (slow NMOS, fast PMOS, low voltage, high temperature) conditions, the metastable time reaches a maximum of 9.8 ps; and under FSHVLT (fast NMOS, slow PMOS, high voltage, low temperature) conditions, the metastable time is 7.8 ps.
[0030] These data indicate that, under extreme process angles, the traditional structure suffers from a significant increase in the difference between high / low level setup and hold times due to the imbalance between NMOS and PMOS driving capabilities, resulting in a sharp increase in metastable time and a serious risk of insufficient timing margin.
[0031] After closed-loop calibration according to this invention, under different PVT conditions, the metastable time was effectively suppressed by dynamically adjusting the PU_Trim<1:0> and PD_Trim<1:0> control codes: under TTNVNT condition, the metastable time decreased from 0.6ps to 0.1ps; under SSLVHT condition, the metastable time decreased from 7ps to 4.5ps; under FFHVH condition, the metastable time decreased from 2.5ps to 0.6ps; under SFLVHT condition, the metastable time decreased from 9.8ps to 4.4ps; and under FSHVLT condition, the metastable time decreased from 7.8ps to 4.4ps.
[0032] Throughout the entire PVT range, the maximum metastable time decreased from 9.8 ps to 4.6 ps, with an average reduction of approximately 50%, and the metastable time remained stable within a small range under all conditions. Simultaneously, the difference between the setup and hold times of the high / low levels was significantly reduced after adjustment. This result verifies the core principle of this invention: reducing the timing asymmetry difference by adjusting the balanced pull-up / pull-down drive strength in a closed-loop manner, thereby reducing the metastable time.
[0033] In summary, this invention realizes a method and circuit for adaptive metastable time optimization of triggers. By introducing digitally adjustable pull-up and pull-down branches in the first-stage clocked inverter of the main latch, programmable control of the output drive strength is achieved. By introducing a closed-loop feedback loop composed of a duty cycle detection module and an up / down counter, dynamic monitoring and adaptive adjustment of the metastable time are achieved. This invention can stably maintain the metastable time at a small value under different PVT conditions, especially in extreme process angles such as FS and SF, effectively combating the timing degradation caused by PVT fluctuations, and ensuring sufficient timing margin in wide voltage and wide temperature range scenarios. It can be widely used in timing circuit units in high-speed mixed-signal integrated circuits, significantly improving the operating frequency and timing stability of the system.
[0034] It should be noted that the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention.
[0035] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0036] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings and the disclosure in carrying out the claimed invention. In the description of the invention, the word "comprising" does not exclude other components or steps, "a" or "an" does not exclude a plurality, and "a plurality" means two or more, unless otherwise explicitly specified. Furthermore, while different embodiments may describe certain measures, this does not mean that these measures cannot be combined to produce good results.
[0037] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A trigger-adaptive metastable time optimization circuit, characterized in that, It includes a deserialization circuit and a detection and calibration circuit; the deserialization circuit includes at least two parallel first digitally adjustable D flip-flops; the detection and calibration circuit includes a second digitally adjustable D flip-flop, a duty cycle detection module, and an up / down counter; The deserialization circuit is used to control the pull-up and pull-down drive strength according to the Trim_Code signal of the first digitally adjustable D flip-flop in order to adjust the metastable time. The detection and calibration circuit is used to detect the duty cycle of the output signal of the DZ_Sense node of the second digitally adjustable D flip-flop using the duty cycle detection module, and obtain the corresponding adjustment signal; it is also used to output the adjustment signal to the control code of the Trim_Code signal of the up / down counter to control the pull-up and pull-down drive strength, and realize closed-loop control of metastable time.
2. The trigger adaptive metastable time optimization circuit according to claim 1, characterized in that, The at least two parallel first digitally adjustable D flip-flops have the same structure, each including a master latch and a slave latch. The master latch includes a master clock-controlled inverter, a master inverter, and a first feedback clock-controlled inverter. The master clock-controlled inverter receives the input signal DIN and the complementary clock signal CK. The output node M outputs to node N through the master inverter. Node N is connected to the first feedback clock-controlled inverter controlled by the complementary clock signal CK. Node N is also led out as a DZ_Sense detection node and connected to the input of the slave clock-controlled inverter in the slave latch. The slave latch also includes a second feedback clock-controlled inverter controlled by the complementary clock signal CK, a logic AND gate, and an output inverter. The output of the slave latch is connected to the input of the second feedback clock-controlled inverter and the output inverter, respectively. The output of the second feedback clock-controlled inverter is connected to the input of the logic AND gate. The output of the logic AND gate is connected to the input of the output inverter. The output of the output inverter outputs the output signal Q.
3. The trigger adaptive metastable time optimization circuit according to claim 2, characterized in that, The master clock inverter includes transistors MP1, MP2, MP5, MP6, MP9, MP10, MN3, MN4, MN7, MN8, MN11, and MN12. The sources of transistors MP1, MP5, and MP9 are all connected to the power supply VDD, and their gates are all connected to the clock signal CK. The drains of transistors MP2, MP6, and MP10 are all connected to the output node DOUT. The drains of transistors MN3, MN7, and MN11 are connected to the output node DOUT; the sources of transistors MN4, MN8, and MN12 are connected to ground GND; and the gates of transistors MN4, MN8, and MN12 are connected to the complementary clock signal CK. The gate of transistor MP2 and the gate of transistor MN3 are connected to the input signal DIN; and the gate of transistor MP6 is connected to PU_Trim. <0> The signal is the output of the NOR gate connected to the input signal DIN. The gate of transistor MN7 is connected to PD_Trim. <0> The AND gate output of the DIN input signal is connected to the gate of transistor MP10 via PU_Trim. <1> The signal is the output of the NOR gate connected to the input signal DIN. The gate of transistor MN11 is connected to PD_Trim. <1> The AND gate output of the DIN input signal is connected to the source of transistors MP2, MP6 and MP10, respectively. The source of transistors MN3, MN7 and MN11 is connected to the drain of transistors MN4, MN8 and MN12, respectively.
4. The trigger adaptive metastable time optimization circuit according to claim 3, characterized in that, The metastable time includes setup time and hold time; the setup time includes high-level setup time and low-level setup time; the hold time includes high-level hold time and low-level hold time.
5. The trigger adaptive metastable time optimization circuit according to claim 4, characterized in that, The high-level setup time is represented as follows: ； in, This indicates the high-level setup time. The propagation delay of the pull-down path of transistor MN4 in the master clock inverter. The buffer delay from node M to node N, This is the clock transmission delay.
6. The trigger adaptive metastable time optimization circuit according to claim 5, characterized in that, The low-level setup time is represented as follows: ； in, The low-level setup time The propagation delay of the pull-up path of transistor MP1 in the main inverter.
7. The trigger adaptive metastable time optimization circuit according to claim 6, characterized in that, The high-level hold time is expressed as follows: ； in, The time when the PMOS transistor of the main clock-controlled inverter is turned off.
8. The trigger adaptive metastable time optimization circuit according to claim 7, characterized in that, The low-level hold time is expressed as follows: in, The time when the NMOS transistor of the main clock-controlled inverter is turned off.
9. The trigger adaptive metastable time optimization circuit according to claim 8, characterized in that, The metastable time is represented as follows: ； in, This represents the metastable time.