Circuit, chip and test equipment for single event transient anomaly voltage induced failure

Abstract

This application discloses a circuit for single-event transient voltage-induced faults, belonging to the field of semiconductor detection technology. The circuit includes transistor PMOS1, transistor NMOS1, inverters INV1 and INV2, resistors R1 and R2, and MOS devices. The source and gate of PMOS1 are connected to the power supply, and the drain is connected to N2 via NMOS1. INV1 and INV2 are cross-coupled to form a latch structure. The gate of NMOS2 or PMOS2 is controlled by the latch output N3. Under no external irradiation, N1 and N2 remain low, and N3 remains high. When a single-event transient strikes PMOS1, generating a transient conduction pulse, N1, N2, and N3 flip, turning off NMOS2 or short-circuiting PMOS2. Chips and detection equipment are based on this circuit. This application provides a quantitative assessment method for verifying the radiation reliability of aerospace chips, accurately locating sensitive weak points, identifying hidden threats, and thus comprehensively eliminating detection blind spots in the supply chain security and space radiation protection of chips in key areas, improving the on-orbit safety and protection of chips under space radiation environments.

Description

Technical Field

[0001] This application belongs to the field of semiconductor testing technology, and in particular relates to circuits, chips and testing equipment for single-event transient abnormal voltage-induced faults. Background Technology

[0002] In the space environment, high-energy particles such as protons, neutrons, and heavy ions bombarding semiconductor reverse-biased PN junctions can generate single-event transient effects (SETs). The ionization of these high-energy particles produces a large number of electron-hole pairs, which, under the influence of an electric field, form instantaneous current pulses, triggering abnormal voltage disturbances at circuit nodes. When this voltage disturbance occurs in an on-orbit chip, it can easily trigger the state flipping of the internal latch circuit, thereby cutting off the power supply to downstream functional modules, causing short-term system interruption or even permanent damage. The complete physical chain of this effect is: high-energy particle bombardment → transistor transient conduction → abnormal node voltage → cross-latch state flipping → functional module power failure and temporary system shutdown. However, currently, there are no publicly available circuit solutions in China that can completely simulate the complete fault process described above: "single-event transient bombardment generates abnormal node voltage and fluctuations → triggers latch flipping → cuts off power supply to functional modules → system interruption." This makes it impossible to reproduce system-level intermittent shutdowns and irreversible damage scenarios. Furthermore, hardware safety testing datasets lack single-event voltage disturbance-triggered failure samples, making it difficult to address the risks of intermittent equipment failure and damage under space radiation conditions.

[0003] Currently, the industry faces two major technical shortcomings in this field. First, there is a lack of reliable irradiation verification methods: existing single-event irradiation tests can only observe device-level characteristics such as transient voltage and single-event pulses in MOS devices, lacking standardized dedicated circuits to fully reproduce the complete failure chain from high-energy particle bombardment to temporary system shutdown. This makes it impossible to quantitatively verify the suppression effects of protection circuits such as power redundancy, single-event voltage filtering, and transient hardening, and also makes it difficult to locate single-event voltage-sensitive weak points within the chip. Consequently, aerospace chip reliability assessment tests lack controllable fault excitation sources. Second, there is a shortage of chip supply chain safety testing samples: untrusted links exist in the global chip supply chain, and some hidden defective circuits utilize single-event transient voltage anomalies as low-probability triggering conditions, intermittently causing equipment shutdowns in on-orbit environments. Existing hardware risk circuit feature libraries lack single-event voltage disturbance-triggered functional interruption samples, and various hardware defect detection algorithms cannot identify such hidden threats, resulting in significant blind spots in radiation safety protection for chips in key areas.

[0004] In response to the problem that aerospace integrated circuits are prone to abnormal node voltages, intermittent functional interruptions, power supply short circuits to ground, and permanent chip burnout when exposed to single-particle radiation, existing test circuits cannot fully reproduce the recoverable soft faults and irreversible hard faults. Chip radiation safety testing also lacks corresponding failure samples. The above-mentioned industry pain points urgently need to be addressed. Summary of the Invention

[0005] This application aims to address the technical problem that existing circuits cannot reproduce system-level failure links caused by single-event events. To this end, this application provides a circuit, chip, and testing equipment for single-event transient abnormal voltage-induced faults, which can reproduce recoverable soft faults and irreversible hard faults caused by high-energy particle bombardment, realistically recreate the intermittent shutdown and damage scenarios of on-orbit equipment, provide a quantitative assessment method for verifying the radiation reliability of aerospace chips, accurately locate sensitive weak nodes, identify hidden threats, and thus comprehensively eliminate the detection blind spots of chips in key areas in supply chain security and space radiation protection, and improve the on-orbit operation safety and protection of chips in the space radiation environment.

[0006] In a first aspect, this application provides a circuit for single-event transient voltage-induced faults, comprising: Power supply terminal and ground terminal; Inverters INV1 and INV2 are connected together to form node N2, and the output of inverter INV1 is connected to form node N3. Transistor PMOS1 and transistor NMOS1 are connected. The drain of transistor PMOS1 and the source and gate of transistor NMOS1 are connected to form node N1. The source and gate of transistor PMOS1 are connected to the power supply terminal. The drain of transistor NMOS1 is connected to the input terminal of inverter INV1 at node N2. Resistors R1 and R2 are connected together. One end of resistor R1 is connected to node N1 and the other end is connected to ground. One end of resistor R2 is connected to node N2 and the other end is connected to ground. The MOS device has its source connected to the power supply terminal, its drain connected to the ground terminal, and its gate connected to node N3.

[0007] In some implementations, the output drive current of inverter INV1 is greater than the output drive current of inverter INV2, and the pull-down current of resistor R2 is less than the output drive current of inverter INV2.

[0008] In some implementations, the MOS device is an NMOS transistor, denoted as transistor NMOS2; or a PMOS transistor, denoted as transistor PMOS2.

[0009] In some implementations, a functional module as a load is also included, which is connected in series between transistor NMOS2 and ground; or the functional module is connected in parallel with transistor PMOS2.

[0010] In some implementations, when the MOS device is an NMOS transistor: Under conditions of no external irradiation, node N3 remains at the first level, nodes N1 and N2 remain at the second level, transistor NMOS2 is turned on, and transistors PMOS1 and NMOS1 are turned off; wherein the first level is higher than the second level. When a single-event bombardment causes the PMOS1 crystal to turn on momentarily, an abnormal voltage is generated at node N1 and transmitted to node N2 via transistor NMOS1, triggering inverters INV1 and INV2 to flip their levels. Node N3 switches to the second level, and transistor NMOS2 turns off.

[0011] In some implementations, when the MOS device is a PMOS transistor: Under conditions of no external irradiation, node N3 remains at the first level, nodes N1 and N2 remain at the second level, and transistors PMOS2, PMOS1 and NMOS1 are turned off. When a single-event bombardment causes the PMOS1 crystal to turn on momentarily, an abnormal voltage is generated at node N1 and transmitted to node N2 via transistor NMOS1, triggering inverters INV1 and INV2 to flip their levels. Node N3 switches to the second level, and transistor PMOS2 turns on.

[0012] In some implementations, the functional module is an electronic device, a sensor interface, or a system circuit.

[0013] In some implementations, inverters INV1 and INV2 are cross-coupled to form a cross-coupled latch structure.

[0014] Secondly, this application provides a chip for simulating single-event transient induced chip faults, comprising: The main functional circuit is configured to perform data processing operations; The embedded test unit integrates the aforementioned simulation circuit for single-event transient-induced chip failure, which is used to apply test excitation under single-event transient bombardment and acquire test response; the embedded test unit is coupled to the main functional circuit.

[0015] Thirdly, this application provides a detection device for simulating single-event transient induced chip faults, comprising: The above-mentioned single-event transient induced chip fault simulation circuit; The sensor, connected to nodes N1 and N2 of the circuit, is used to acquire signals at the first and second levels. The output module receives signals collected by the sensor and outputs the processed detection result signal.

[0016] As can be seen from the above technical solution, the beneficial effects of this application are as follows: 1. The circuit of this application comprises a power supply terminal, a ground terminal, inverters INV1 and INV2, transistors PMOS1 and NMOS1, resistors R1 and R2, and a MOS device whose gate is controlled by N3. The source and gate of transistor PMOS1 are both connected to the power supply terminal, and its drain is pulled down via R1 to form node N1, constituting a normally open sensitive cell. During a single-particle bombardment, it is momentarily overdriven, pulling N1 high. Transistor NMOS1 uses a diode with its source and gate connected to N1 and its drain pulled down via R2 to connect to N2, transmitting abnormal node voltages to subsequent stages. Inverters INV1 and INV2 are cross-coupled to form a bistable latch. Nodes N2 and N3 flip states, latching nanosecond-level transient pulses into a persistent state. The gate of the MOS device is connected to N3, its source to the power supply terminal, and its drain to the ground terminal, switching its power supply state according to the level of N3. Therefore... This application can reproduce recoverable soft faults and irreversible hard faults caused by high-energy particle bombardment, realistically recreate the intermittent shutdown and damage scenarios of on-orbit equipment, provide a quantitative assessment method for the radiation reliability verification of aerospace chips, accurately locate sensitive and weak nodes, identify hidden threats, and thus comprehensively eliminate the detection blind spots of chips in key areas in supply chain security and space radiation protection, and improve the on-orbit operation safety and protection of chips in the space radiation environment.

[0017] 2. The chip described in this application integrates a simulation circuit for single-event transient (SET) induced chip failure within an embedded test unit. This allows the chip to apply test stimuli to the main functional circuit under actual SET bombardment and acquire test responses in real time. This enables rapid and clear indication of the critical failure point of the main functional circuit under SET interference, providing a high-precision on-chip test benchmark for evaluating the SET sensitivity threshold of the chip in harsh space environments. This design not only achieves in-situ monitoring of the chip's SET resistance capability but also significantly enhances the reliability verification capability of semiconductor devices under extreme radiation environments. It effectively supports the optimization and iteration of radiation-hardened designs, the improvement of on-orbit fault diagnosis and fault-tolerance mechanisms for chips, and the quality inspection and standardization of radiation-hardened chips in the aerospace electronic systems supply chain.

[0018] 3. The testing equipment of this application integrates the aforementioned circuitry with the sensor and output module into a single unit. Utilizing an in-situ acquisition mechanism where the sensor is directly coupled to nodes N1 and N2, it accurately captures the subtle level fluctuation signal caused by the negative drift of the NMOS3 threshold voltage. The output module processes this signal and outputs a high signal-to-noise ratio test result, avoiding the contact noise and signal attenuation introduced by traditional probe station testing. This significantly improves the accuracy of radiation failure feature extraction compared to discrete testing methods. Thus, this application can stably identify the failure threshold of SRAM cells in complex electromagnetic environments, facilitating the analysis of failure thresholds and latch failure mechanisms under long-term irradiation conditions. This improves the efficiency and confidence level of reliability assessment for electronic equipment in aerospace, space, and nuclear radiation environments. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced one by one below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other embodiments and drawings can be obtained based on these drawings without creative effort. The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be decomposed, while some operations / steps can be combined or partially combined. Therefore, the actual execution order may change according to the actual situation.

[0020] Figure 1 A schematic diagram of an embodiment of the circuit for single-event transient abnormal voltage-induced faults of the present invention is shown; Figure 2 A schematic diagram of another embodiment of the circuit for single-event transient abnormal voltage-induced faults of the present invention is shown; Figure label: VDD, power supply terminal; GND, ground terminal. Detailed Implementation

[0021] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application. The described embodiments are only a part of the embodiments of this application, not all of them. Based on the embodiments in this application, they can be arranged and designed in various different configurations. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] This application is described below with reference to the accompanying drawings and specific embodiments: Please refer to Figure 1According to a first aspect of this application, a circuit for single-event transient voltage-induced faults is provided, comprising a power supply terminal VDD, a ground terminal GND, transistors PMOS1 and NMOS1, inverters INV1 and INV2, MOS devices, resistors R1 and R2. The power supply terminal VDD is used to connect to an external DC power supply, providing operating voltage to the sources of each MOS transistor in the circuit; the ground terminal GND is used to connect to a reference ground potential (i.e., 0V reference level), providing a grounding loop to the drains of each NMOS transistor in the circuit. The input terminal of inverter INV1 is connected to node N2, and the output terminal is connected to node N3. The input terminal of inverter INV2 is connected to node N3, and the output terminal is connected to node N2. Inverters INV1 and INV2 are cross-coupled to form a cross-coupled latch structure, which maintains a stable voltage level at nodes N2 and N3 under conditions without external single-event transient irradiation. The drain of transistor PMOS1 and the source and gate of transistor NMOS1 are connected to form node N1. The source and gate of transistor PMOS1 are connected to the power supply terminal VDD. The drain of transistor NMOS1 and the input terminal of inverter INV1 are connected to node N2. One end of resistor R1 is connected to node N1 and the other end is connected to ground terminal GND. One end of resistor R2 is connected to node N2 and the other end is connected to ground terminal GND. The source of the MOS device is connected to the power supply terminal VDD, the drain is connected to the ground terminal GND, and the gate is connected to node N3.

[0023] The circuit described in this application can be integrated into chip test pads and test samples, and can: 1) Support the verification of single-event hardening and overcurrent protection of aerospace chips: standardize the reproduction of single-event-induced temporary shutdown and permanent chip burn-out faults, and use it to compare and test the protection capabilities and suppression effects of various power protection, single-event hardening, redundant power supply, radiation-resistant latching, and overcurrent fuse solutions; 2) Improve the hardware security testing system: generate standard samples of single-event-triggered hidden failure and permanent damage hidden circuits, extract circuit layout, timing, and triggering characteristics, expand the hardware risk circuit feature database, train and optimize hardware defect detection algorithms, and investigate hidden damage circuits implanted in the supply chain; 3) Promote the iterative improvement of industry standards: provide a controllable and reproducible single-event failure test carrier, rely on conducting multiple sets of irradiation comparison tests, quantify the single-event-sensitive node mining and single-event permanent burn-out threshold under different processes, circuit topologies, locate chip irradiation vulnerable nodes, and help improve national standards and industry specifications related to the irradiation reliability and supply chain security of aerospace integrated circuits.

[0024] In some implementations, transistor PMOS1 serves as a single-event sensitive unit to withstand single-event transient bombardment. Both the source and gate of transistor PMOS1 are connected to the power supply terminal VDD. Under normal operating conditions, transistor PMOS1 is in the off state. Simultaneously, node N1 is pulled down to the ground terminal GND via resistor R1. Together, these two factors maintain node N1 at a low level (second level) under no-irradiation conditions. When a single particle (such as a proton, neutron, or heavy ion) bombards the drain or channel region of transistor PMOS1, the resulting electron-hole pairs cause transistor PMOS1 to momentarily overdrive and conduct, causing a sharp increase in drain current. Node N1 is rapidly pulled high, generating an abnormal voltage pulse in the circuit corresponding to the single-event transient effect. Because a single particle acts on transistor PMOS1, the drain region of transistor PMOS1 constitutes a single-event voltage-sensitive node. By changing the device parameters or irradiation of transistor PMOS1, voltage-sensitive weak nodes under different process conditions can be located.

[0025] In some implementations, inverters INV1 and INV2 are cross-coupled to form a cross-coupled latch structure, and nodes N2 and N3 constitute a pair of interlocked latch nodes with opposite voltage levels, serving as inputs and outputs to each other, thus forming a bistable state. Through the fixed connection relationship between the above devices, a three-stage cascaded fault excitation circuit is constructed, consisting of "single-event sensitive unit - transient level transmission - cross-coupled latch flip-flop - power supply state switching," which can controllably reproduce the functional interruption or permanent burnout process induced by single-event transient abnormal voltage.

[0026] In some implementations, the output drive current of inverter INV1 is greater than the output drive current of inverter INV2, and the pull-down current of resistor R2 is less than the output drive current of inverter INV2. A larger drive current (capability) indicates a stronger charging and discharging effect of the inverter on its output node, and a larger pull-down current (capability) indicates a stronger pull-down effect of the resistor on that node. The sum of the charging current provided by transistor NMOS1 through node N2 and the drive current provided by inverter INV2 through node N2 is greater than the pull-down current of R2 on N2. During single-event triggering, the output node N3 of inverter INV1 flips from high to low. The drop in node N3 further pulls node N2 high via inverter INV2, forming positive feedback, causing the latch state to irreversibly flip from (N2 low, N3 high) to (N2 high, N3 low). This configuration ensures that the circuit does not erroneously flip due to the pull-down of R2 under normal conditions, and reliably completes the latch flip during irradiation triggering.

[0027] like Figure 1In some implementations, the MOS device is an NMOS transistor, denoted as transistor NMOS2. The circuit also includes a functional module as a load, connected in series between transistor NMOS2 and ground GND. Specifically, the connection relationships of transistor PMOS1, transistor NMOS1, inverter INV1, inverter INV2, resistor R1, and resistor R2 are consistent with the overall technical solution described above. The gate of transistor NMOS2 is connected to node N3, the source is connected to the power supply terminal VDD, and the drain is connected to the functional module, which is then connected to ground GND. When a high-energy particle bombardment generates a single-particle transient current, it can accurately simulate the instantaneous jump in node level triggering the cross-latch state to flip, cutting off the power supply to the functional module, causing a temporary system shutdown. After power failure and restart, the circuit resumes normal operation. This circuit is used to simulate power interruption faults. Under conditions without external irradiation, due to the presence of cross-coupled inverters INV1 and INV2, node N3 remains at the first level. Due to the presence of pull-down resistors R1 and R2, nodes N1 and N2 remain at the second level (low level). Transistor NMOS2 is turned on, while transistors PMOS1 and NMOS1 are turned off. At this time, the source of transistor NMOS2 is connected to VDD, and the gate is connected to the high level N3. Transistor NMOS2 is in the on state, and the power supply terminal VDD supplies power to the functional module through the on-state transistor NMOS2, allowing the functional module to power on and operate normally. Since transistor PMOS1 is not triggered, transistor NMOS1 is turned off, and the latch remains unchanged (N2 low, N3 high), while transistor NMOS2 remains on, the circuit does not affect the power supply to the functional module. The circuit as a whole is in a silent state, without changing the original power supply timing, logic function, and power consumption characteristics of the chip.

[0028] When a single-event bombardment causes the PMOS transistor to momentarily turn on, an abnormal voltage is generated at node N1 and transmitted to node N2 via transistor NMOS1. Node N1 is momentarily pulled high to the first level (high level), and transistor NMOS1 turns on, pulling node N2 from the second level (low level) to the first level (high level). This triggers a level flip in inverters INV1 and INV2. The positive feedback of inverter INV2 further locks the high level of node N2, and the latch state flips from (N2 low, N3 high) to (N2 high, N3 low). Node N3 switches to the second level (low level), the gate voltage of transistor NMOS2 decreases, and transistor NMOS2 turns off. The functional module loses power, and the system experiences a temporary shutdown, thus realistically reproducing the complete functional interruption failure chain of "high-energy particle bombardment → instantaneous turn-on of PMOS transistor → abnormal voltage generation at node → cross-latch level flip → functional module power failure and temporary system shutdown".

[0029] When a power-off restart operation is performed on the circuit, the levels of each node are reset. Transistor PMOS1 turns on again and establishes a low level for N1, transistor NMOS1 turns off, N2 falls back to low, the latch returns to (N2 low, N3 high), transistor NMOS2 turns on again, the functional modules are powered on again, and the circuit automatically resets to the normal operating state. This achieves the bistable controllable characteristics of "stable power supply without irradiation, latching to maintain the power-off state after a single-particle bombardment, and automatic reset to the normal operating state after a power-off restart".

[0030] like Figure 2 In some implementations, the MOS device is a PMOS transistor, denoted as transistor PMOS2; the circuit also includes a functional module as a load, which is connected in parallel to transistor PMOS2. Specifically, the connection relationships of transistor PMOS1, transistor NMOS1, inverter INV1, inverter INV2, resistor R1, and resistor R2 are consistent with the overall technical solution described above. The gate of transistor PMOS2 is connected to node N3, the source is connected to the power supply terminal VDD, and the drain is connected to the ground terminal GND. When a high-energy particle bombardment generates a single-event transient current pulse, it can accurately simulate the instantaneous jump in node level triggering the cross-latch state flip, conducting the ground short-circuit transistor to cause VDD and GND to be directly connected, and the large current causes the chip to be permanently burned out. After power failure and restart, the circuit failure state cannot be recovered. This circuit is used to simulate the permanent short circuit and irreversible burn-out fault of the chip power supply induced by a single-event transient. Under conditions without external radiation, node N3 remains at the first level. Similarly, due to the presence of pull-down resistors R1 and R2, nodes N1 and N2 remain at the second level, and transistors PMOS2, PMOS1, and NMOS1 are turned off. Due to the presence of inverters INV1 and INV2, node N3 is at the first level (high level), and transistor PMOS2 is turned off because its gate is high. At this time, the source of transistor PMOS2 is connected to VDD, and its gate is connected to the high level N3. Transistor PMOS2 is in the off state, and there is no conduction path between the power supply terminal VDD and the ground terminal GND via transistor PMOS2. The circuit has no short circuit, the functional module powers on normally, and the chip works normally. Under no-irradiation conditions, transistor PMOS1 is not triggered, transistor NMOS1 is turned off, latching is maintained (N2 low, N3 high), and transistor PMOS2 remains off. The circuit is also in a silent state, without changing the chip's original power supply timing, logic function, and power consumption characteristics.

[0031] When a single-event bombardment causes the PMOS1 crystal to momentarily turn on, an abnormal voltage is generated at node N1 and transmitted to node N2 via transistor NMOS1. This triggers a level flip in inverters INV1 and INV2, causing node N3 to switch to the second level, and transistor PMOS2 to turn on. The abnormal voltage generated at node N1 is transmitted to node N2 via transistor NMOS1, causing node N1 to be momentarily pulled high to the first level (high level). Transistor NMOS1 then turns on, pulling node N2 from the second level (low level) to the first level (high level), triggering a level flip in inverters INV1 and INV2. The positive feedback of inverter INV2 further locks the high level of node N2, and the latch state flips from (N2 low, N3 high) to (N2 high, N3 low). Node N3 switches to the second level (low level), the gate voltage of transistor PMOS2 decreases, and transistor PMOS2 switches from off to on. The power supply VDD is directly connected to the ground GND via the conducting transistor PMOS2, forming a permanent short circuit path from VDD to GND. The power supply VDD is continuously pulled low, causing irreversible burnout of the chip. This truly replicates the complete permanent burnout failure chain of "high-energy particle bombardment → instantaneous conduction of transistor PMOS → abnormal voltage generated at the node → cross latch level flipping → power supply to ground short circuit → irreversible burnout and permanent restart failure of the chip".

[0032] In some implementations, the functional module is an electronic device, a sensor interface, or a system circuit. In the power interruption fault simulation, the functional module is connected in series between PMOS4 and ground. PMOS4 acts as a power supply path switch controlled by N2, normally conducting to supply power to the functional module, and turning off after a single-event irradiation trigger to cut off the power supply to the functional module. In the power short-circuit fault simulation mode, the functional module is connected in parallel to NMOS3. NMOS3 acts as a short-circuit path switch controlled by N2, normally turning off and not forming a short circuit, and turning on after a single-event irradiation trigger to form a power-to-ground short-circuit path. Those skilled in the art can select the appropriate functional module and MOS device type according to the actual load type of the chip under test and the fault simulation requirements.

[0033] A second aspect of this application provides a chip for simulating single-event transient (SET) induced chip failure. The chip includes a main functional circuit and an embedded test unit. The main functional circuit is configured to perform data processing operations. The embedded test unit integrates the aforementioned SET induced chip failure simulation circuit, used to apply test stimuli under SET bombardment and acquire test responses. The embedded test unit is coupled to the main functional circuit. This chip integrates the originally discrete SET induced chip failure simulation circuit and main functional circuit into a single hardware entity, solidifying the abstract SET fault simulation and monitoring logic into an industrial product with a physical carrier. When this chip is implanted into a single-event effect detection device (such as a heavy-ion accelerator or pulsed laser test platform) and subjected to SET bombardment, the embedded test unit applies test stimuli and acquires test responses, directly outputting deterministic test response signals. The specific generation mechanism and technical effects of each signal are the same as in the circuit embodiment described above, enabling the chip to perform specific in-situ fault simulation and testing actions, achieving high-precision SET reliability verification. For the sake of brevity, any parts not mentioned in this embodiment can be referred to the corresponding content in the foregoing circuit embodiments.

[0034] In some implementations, the specific type of the main functional circuit is not limited, and it can be configured to perform various data processing operations, such as digital signal processing, data storage and retrieval, and logic control instruction execution. Its specific circuit architecture may include a central processing unit (CPU) core, a graphics processing unit (GPU) core, a memory array, a digital signal processor (DSP) module, or an application-specific integrated circuit (ASIC) functional module, etc. Those skilled in the art can select the appropriate module based on the actual application requirements of the chip, such as aerospace-specific integrated circuits, satellite payload chips, or deep space exploration chips. The method of coupling the embedded test unit to the main functional circuit is not limited. The main functional circuit and the embedded test unit can be integrated onto a semiconductor substrate using the same CMOS process, compatible with existing commercial CMOS and aerospace-specific radiation-resistant fabrication processes. No special processes or special layout hardening structures are required, resulting in low integration costs. It can be used in batches for chip single-event transient effect evaluation experiments, quickly locating single-event transient sensitive design nodes. Those skilled in the art will understand that the above description does not constitute a limitation on the chip. In practical applications, the chip can also integrate more functional units according to the needs of the application scenario, such as a built-in test stimulus generation unit, response acquisition and processing unit, and clock management unit. These units work together with embedded test units and main functional circuits on the substrate through metal interconnects to complete the simulation and monitoring process of single-event transient induced chip failures, significantly improving the testing efficiency and reliability of semiconductor devices under extreme radiation environments.

[0035] A third aspect of this application provides a detection device for state reversal based on the total dose irradiation effect, comprising the aforementioned single-event transient induced chip fault simulation circuit, a sensor, and an output module. The sensor is connected to nodes N1 and N2 of the circuit to acquire signals at first and second levels. The output module receives the signals acquired by the sensor and outputs the processed detection result signal. This detection device integrates the irradiation-sensitive circuit and the signal acquisition and processing unit into the same hardware system, solidifying the abstract irradiation failure monitoring logic into an industrial device with on-site testing capabilities. The sensor is directly coupled to the core nodes N1 and N2 of the circuit, enabling in-situ capture of minute level changes caused by the negative drift of the NMOS3 threshold voltage, avoiding contact noise and signal attenuation introduced by traditional probe station testing. The output module filters, amplifies, and digitizes the acquired signal, converting the state reversal process within the circuit into a standardized detection result signal with a high signal-to-noise ratio. For brevity, any aspects not mentioned in this embodiment can be referred to the corresponding content of the foregoing embodiments.

[0036] In some embodiments, the specific types of the aforementioned sensors include, but are not limited to: high-impedance differential voltage probes, current sensors, or on-chip integrated sensing circuits (such as comparators, analog-to-digital converters, or ADCs), used for real-time monitoring of the level difference or switching timing between nodes N1 and N2. The specific forms of the aforementioned output modules may include, but are not limited to: signal conditioning circuits (such as instrumentation amplifiers, low-pass filters), microcontroller units (MCUs) or field-programmable gate arrays (FPGAs), and interface units for communication with external terminals (such as universal asynchronous receiver / transmitter (UART), serial peripheral interface (SPI), Ethernet ports, or wireless communication modules). Those skilled in the art will understand that the above description does not constitute a limitation on the detection device. In practical applications, the device may also include a power supply module (such as a regulated power supply, battery management unit), a calibration module (for eliminating sensor zero drift), etc.

[0037] Regarding the specific implementation methods of this application, it should be noted that: In the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, procedure, apparatus, device, or readable storage medium that comprises a list of elements includes not only those elements but also other elements not expressly listed that are consistent with the concept of this application, or elements inherent to such process, method, procedure, apparatus, device, or readable storage medium. Without further limitation, elements defined by phrases such as "a…," "two…," "at least," etc., do not exclude the presence of additional elements.

[0038] In the description of this application, the use of terms such as "some embodiments," "optional embodiments," "example," "specific example," "optional example," or "optional embodiment," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application, but does not imply that these embodiments illustrate and describe all possible forms of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0039] The present invention has been described in detail above with reference to specific embodiments and exemplary examples. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments; the above description should not be construed as a limitation of the present invention. Technical solutions between various embodiments can be combined with each other, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application. Although embodiments of the present application have been shown and described, various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. Those skilled in the art will understand that various other specific changes and combinations of embodiments based on the technical teachings disclosed in this application, without departing from the essence of the present application, are still within the scope of protection defined by the claims of the present invention and their equivalent technical solutions.

Claims

1. A circuit for single-event transient voltage-induced faults, characterized in that, include: Power supply terminal and ground terminal; Inverters INV1 and INV2 are connected, with the input terminal of inverter INV1 and the output terminal of inverter INV2 connected to form node N2, and the output terminal of inverter INV1 and the input terminal of inverter INV2 connected to form node N3. Transistor PMOS1 and transistor NMOS1 are connected, with the drain of transistor PMOS1 and the source and gate of transistor NMOS1 connected to form node N1. The source and gate of transistor PMOS1 are connected to the power supply terminal. The drain of transistor NMOS1 is connected to the input terminal of inverter INV1 and to node N2. Resistors R1 and R2 are provided, with one end of resistor R1 connected to node N1 and the other end connected to the ground terminal, and one end of resistor R2 connected to node N2 and the other end connected to the ground terminal. A MOS device, wherein the source is connected to the power supply terminal, the drain is connected to the ground terminal, and the gate is connected to the node N3.

2. The circuit for single-event transient abnormal voltage-induced faults according to claim 1, characterized in that, The output drive current of inverter INV1 is greater than the output drive current of inverter INV2, and the pull-down current of resistor R2 is less than the output drive current of inverter INV2.

3. The circuit for single-event transient abnormal voltage-induced faults according to claim 2, characterized in that, The MOS device is an NMOS transistor, denoted as transistor NMOS2; or a PMOS transistor, denoted as transistor PMOS2.

4. The circuit for single-event transient abnormal voltage-induced faults according to claim 3, characterized in that, It also includes a functional module as a load, which is connected in series between the transistor NMOS2 and the ground terminal; or the functional module is connected in parallel with the transistor PMOS2.

5. The circuit for single-event transient abnormal voltage-induced faults according to claim 4, characterized in that, When the MOS device is an NMOS transistor: Under conditions of no external irradiation, node N3 is maintained at a first level, nodes N1 and N2 are maintained at a second level, transistor NMOS2 is turned on, and transistors PMOS1 and NMOS1 are turned off; wherein the first level is higher than the second level; When a single particle bombards the crystal PMOS1 and causes it to turn on momentarily, an abnormal voltage is generated at node N1 and transmitted to node N2 via transistor NMOS1, triggering a level flip of inverters INV1 and INV2. Node N3 switches to the second level, and transistor NMOS2 turns off.

6. The circuit for single-event transient abnormal voltage-induced faults according to claim 4, characterized in that, When the MOS device is a PMOS transistor: Under conditions of no external irradiation, node N3 is maintained at the first level, node N1 and node N2 are maintained at the second level, and transistors PMOS2, PMOS1 and NMOS1 are turned off; When a single particle bombards the crystal PMOS1 and causes it to turn on momentarily, an abnormal voltage is generated at node N1 and transmitted to node N2 via transistor NMOS1, triggering a level flip of inverters INV1 and INV2. Node N3 switches to the second level, and transistor PMOS2 turns on.

7. The circuit for single-event transient abnormal voltage-induced faults according to claim 4, characterized in that, The functional modules are electronic devices, sensor interfaces, or system circuits.

8. The circuit for single-event transient abnormal voltage-induced faults according to claim 1, characterized in that, The inverters INV1 and INV2 are cross-coupled to form a cross-coupled latch structure.

9. A chip for simulating single-event transient induced chip faults, characterized in that, include: The main functional circuit is configured to perform data processing operations; An embedded test unit integrates a simulation circuit for single-event transient-induced chip failure as described in any one of claims 1-8, used to apply test excitation under single-event transient bombardment and acquire test response; the embedded test unit is coupled to the main functional circuit.

10. A detection device for simulating single-event transient induced chip faults, characterized in that, include: The single-particle transient induced chip fault simulation circuit according to any one of claims 1-8; A sensor, connected to nodes N1 and N2 of the circuit, is used to acquire signals at the first and second levels; The output module receives the signals collected by the sensor and outputs the processed detection result signal.

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