All-digital phase-locked loop, method, apparatus, device, storage medium and program product

Abstract

This disclosure relates to a fully digital phase-locked loop (PLL), method, apparatus, device, storage medium, and program product, falling under the field of PLL technology. The fully digital PLL includes an oscillation circuit, a frequency-locked circuit, and a phase-locked circuit. Both the frequency-locked circuit and the phase-locked circuit are connected to the oscillation circuit. The frequency-locked circuit receives the frequency-locked clock signal output by the oscillation circuit, generates a frequency control code corresponding to the frequency-locked clock signal, and outputs the frequency control code to the oscillation circuit to lock the frequency of the clock signal output by the oscillation circuit. The phase-locked circuit receives the phase-locked clock signal output by the oscillation circuit, generates a phase control code corresponding to the phase-locked clock signal, and outputs the phase control code to the oscillation circuit to lock the phase of the clock signal output by the oscillation circuit. By using different circuits for frequency locking and phase locking, rapid frequency and phase locking is achieved, simplifying the locking process and reducing locking time.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a fully digital phase-locked loop, a clock signal locking method, a locking device, an electronic device, a computer-readable storage medium, a chip, and a computer program product. Background Technology

[0002] An all-digital phase-locked loop (ADPLL) is a feedback control system composed of digital circuits that achieves phase / frequency locking in the digital domain. Its core is to replace the phase detector, filter, and voltage-controlled oscillator of a traditional analog phase-locked loop with digital modules to achieve signal synchronization and frequency synthesis.

[0003] Currently, all-digital phase-locked loops use the same circuit architecture to achieve frequency and phase locking, making it difficult to achieve fast locking of both frequency and phase simultaneously. In other words, the clock signal locking process is relatively cumbersome, increasing the locking time. Summary of the Invention

[0004] This disclosure provides a fully digital phase-locked loop, a method for locking a clock signal, a locking device, an electronic device, a computer-readable storage medium, and a computer program product.

[0005] According to a first aspect of the present disclosure, a fully digital phase-locked loop (PLL) is provided, comprising: an oscillation circuit; a frequency-locking circuit connected to the oscillation circuit, configured to receive a frequency-locked clock signal output by the oscillation circuit, generate a frequency control code corresponding to the frequency-locked clock signal, and output the frequency control code to the oscillation circuit to frequency-lock the clock signal output by the oscillation circuit; and a phase-locking circuit connected to the oscillation circuit, configured to receive the phase-locked clock signal output by the oscillation circuit, generate a phase control code corresponding to the phase-locked clock signal, and output the phase control code to the oscillation circuit to phase-lock the clock signal output by the oscillation circuit.

[0006] A fully digital phase-locked loop (PLL) comprises an oscillation circuit, a frequency-locked circuit, and a phase-locked circuit. The oscillation circuit generates a clock signal, which is frequency-locked by the frequency-locked circuit, and the phase-locked circuit is phase-locked by the phase-locked clock signal generated by the oscillation circuit. In other words, frequency locking and phase locking are implemented using different circuits; the frequency-locked circuit meets the requirements for frequency locking, and the phase-locked circuit meets the requirements for phase locking. This allows for rapid frequency and phase locking, simplifies the locking process, and reduces locking time.

[0007] In some embodiments of this disclosure, the frequency locking circuit includes a first frequency calibration circuit and a second frequency calibration circuit; wherein, the first frequency calibration circuit is connected to the oscillation circuit, and is used to receive a first frequency-locked clock signal output by the oscillation circuit, perform frequency calibration on the first frequency-locked clock signal to generate a first frequency control code corresponding to the first frequency-locked clock signal, and output the first frequency control code to the oscillation circuit; the second frequency calibration circuit is connected to the oscillation circuit, and is used to receive a second frequency-locked clock signal output by the oscillation circuit, perform frequency calibration on the second frequency-locked clock signal to generate a second frequency control code corresponding to the second frequency-locked clock signal, and output the second frequency control code to the oscillation circuit.

[0008] A first frequency calibration circuit and a second frequency calibration circuit are used to process different frequency-locked clock signals, respectively. Specifically, the first frequency calibration circuit is adapted to process the first frequency-locked clock signal, and the second frequency calibration circuit is adapted to process the second frequency-locked clock signal. By dividing the frequency-locked clock signal to be processed into two types and then using two different frequency calibration circuits to process the two types of frequency-locked clock signals respectively, the locking process speed is accelerated.

[0009] In some embodiments of this disclosure, the all-digital phase-locked loop further includes a control circuit; wherein the control circuit is connected to the first frequency calibration circuit, the second frequency calibration circuit and the oscillation circuit respectively, and is used to enable the first frequency calibration circuit and the second frequency calibration circuit according to the frequency difference between the clock signal output by the oscillation circuit and the reference clock signal.

[0010] The enable function is implemented by the control circuit. The control circuit determines the frequency difference between the clock signal output by the oscillator circuit and the reference clock signal. If the frequency difference is large, it controls the first frequency calibration circuit to work. If the frequency difference is small, that is, the frequency of the clock signal output by the oscillator circuit is already close to the frequency of the reference clock signal, but still has a small frequency difference, it controls the second frequency calibration circuit to work.

[0011] In some embodiments of this disclosure, the first frequency calibration circuit is used to generate a first frequency control code corresponding to the first frequency-locked clock signal based on a first difference between the count value and the target count value, and output the first frequency control code to the oscillation circuit, wherein the count value is the count value of the first frequency-locked clock signal within a preset time period.

[0012] The first frequency control code is adjusted based on the first difference between the count value and the target count value. The first frequency control code is output to the oscillation circuit, and then the oscillation circuit outputs the corresponding first frequency-locked clock signal. Through multiple iterations, the first difference is made to meet the requirements, thereby controlling the frequency of the frequency-locked clock signal output by the oscillation circuit within a preset frequency range.

[0013] In some embodiments of this disclosure, the first frequency calibration circuit is used to generate a first frequency control code corresponding to the first frequency-locked clock signal by applying a binary search method based on a first difference between the count value and the target count value, and output the first frequency control code to the oscillation circuit.

[0014] The binary search method is used to achieve fast frequency locking of the first frequency-locked clock signal by the first frequency calibration circuit.

[0015] In some embodiments of this disclosure, the second frequency calibration circuit is used to generate a second control code corresponding to the second frequency-locked clock signal based on a second difference between the frequency division ratio and the first target frequency division ratio, and output the second control code to the oscillation circuit, wherein the frequency division ratio is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal.

[0016] The second frequency control code is monotonically accumulated based on the second difference. When the second frequency calibration circuit finishes calibration, the frequency of the clock signal output by the oscillation circuit is within the neighborhood of the frequency of the reference clock signal. That is, the frequency of the clock signal is equal to the frequency of the reference clock signal, or the error between the frequency of the clock signal and the frequency of the reference clock signal is negligible, which is sufficient to meet the operating requirements of other circuits driven by the clock signal output by the fully digital phase-locked loop.

[0017] In some embodiments of this disclosure, the first frequency calibration circuit includes: a first conversion sub-circuit for converting the first frequency-locked clock signal into a first frequency-related signal; and a second conversion sub-circuit connected to the first conversion sub-circuit for converting the first frequency-related signal into the first frequency control code and outputting the first frequency control code to the oscillation circuit.

[0018] The first conversion sub-circuit converts the first frequency-locked clock signal into a frequency-related signal, and the second conversion sub-circuit converts the first frequency-related signal into a first frequency control code. In other words, the two sub-circuits included in the first frequency calibration circuit are used to calibrate the frequency of the first frequency-locked clock signal.

[0019] In some embodiments of this disclosure, the first frequency-related signal is a first difference between a count value and a target count value, the count value being the count value of the first frequency-locked clock signal within a preset time period, the first conversion sub-circuit being used to convert the first frequency-locked clock signal into the first difference; the second conversion sub-circuit being used to convert the first difference into the first frequency control code and output the first frequency control code to the oscillation circuit.

[0020] The first frequency control code is adjusted based on the first difference between the count value and the target count value. The first frequency control code is output to the oscillation circuit, and then the oscillation circuit outputs the corresponding first frequency-locked clock signal. Through multiple iterations, the first difference is made to meet the requirements, thereby controlling the frequency of the frequency-locked clock signal output by the oscillation circuit within a preset frequency range.

[0021] In some embodiments of this disclosure, the second frequency calibration circuit includes: a third conversion sub-circuit for converting the second frequency-locked clock signal into a second frequency-related signal; and a fourth conversion sub-circuit connected to the third conversion sub-circuit for converting the second frequency-related signal into the second frequency control code and outputting the second frequency control code to the oscillation circuit.

[0022] The third conversion sub-circuit converts the second frequency-locked clock signal into a frequency-related signal, and the fourth conversion sub-circuit converts the second frequency-related signal into a second frequency control code. In other words, the two sub-circuits included in the second frequency calibration circuit are used to calibrate the frequency of the second frequency-locked clock signal.

[0023] In some embodiments of this disclosure, the second frequency-related signal is a second difference between the frequency division ratio and the first target frequency division ratio, wherein the frequency division ratio is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal; a third conversion sub-circuit is used to convert the second frequency-locked clock signal into the second difference; and a fourth conversion sub-circuit, connected to the third conversion sub-circuit, is used to convert the second difference into the second frequency control code and output the second frequency control code to the oscillation circuit.

[0024] The first target frequency division ratio is the pre-set frequency division ratio. When the second frequency calibration circuit finishes calibration, the frequency division ratio between the second frequency-locked clock signal and the reference clock signal is obtained. At the end of the second frequency calibration circuit calibration, the frequency of the clock signal output by the oscillation circuit is within the neighborhood of the reference clock signal frequency. That is, the frequency of the clock signal is equal to the frequency of the reference clock signal, or the error between the frequencies of the clock signal and the reference clock signal is negligible.

[0025] In some embodiments of this disclosure, the phase-locked circuit includes a phase comparison circuit, a digital loop filter circuit, a frequency divider circuit, and a time phase shifter circuit; wherein, the output terminal of the phase comparison circuit is connected to the input terminal of the digital loop filter circuit, the output terminal of the digital loop filter circuit is connected to the input terminal of the oscillation circuit, and the output terminal of the oscillation circuit is sequentially fed back to the feedback input terminal of the phase comparison circuit via the frequency divider circuit and the time phase shifter circuit.

[0026] A phase-locked circuit, comprising a phase comparison circuit, a digital loop filter circuit, a frequency divider circuit, and a time phase shifter circuit, enables rapid phase locking.

[0027] In some embodiments of this disclosure, the digital loop filter circuit is used to receive the phase difference signal output by the phase comparison circuit, filter the phase difference signal, and adjust the filtering parameters of the digital loop filter circuit according to the magnitude of the phase difference signal.

[0028] Filtering parameters include integral coefficients, proportional coefficients, and so on. By adjusting the filtering parameters of the digital loop filter circuit to adapt to different phase difference signals, the filtering effect is improved, thereby achieving precise phase locking.

[0029] In some embodiments of this disclosure, different filtering parameters of the digital loop filter circuit correspond to different operating modes. The digital loop filter circuit is also used to switch the operating mode from a first operating mode to a second operating mode in response to an operating mode switching command, and to collect the phase difference signal in the first operating mode and use the phase difference signal in the first operating mode for phase compensation in the second operating mode.

[0030] By sampling the phase difference signal output by the phase comparison circuit during mode switching and compensating for the phase difference carried by this signal to the switched operating mode, fast phase locking is achieved in the second operating mode. Furthermore, the mode switching achieves overshoot-free phase alignment.

[0031] According to a second aspect of the present disclosure, an electronic device is provided, comprising: a fully digital phase-locked loop circuit and a main control circuit, wherein the fully digital phase-locked loop circuit is any of the fully digital phase-locked loop circuits described in the first aspect above, and the fully digital phase-locked loop circuit is connected to the main control circuit; the fully digital phase-locked loop circuit is used to output a target clock signal with frequency and phase locked; the main control circuit receives the target clock signal output by the fully digital phase-locked loop circuit and performs a predetermined function under the drive of the target clock signal.

[0032] Electronic devices that include fully digital phase-locked loop circuits and main control circuits have improved overall operational stability because the fully digital phase-locked loop circuits generate clock signals with precisely locked frequency and phase.

[0033] According to a third aspect of the present disclosure, a clock signal locking method is provided, comprising: processing a frequency-locked clock signal output by an oscillating circuit through a frequency-locking circuit to obtain a frequency control code corresponding to the frequency-locked clock signal, wherein the frequency control code is used to frequency-lock the clock signal output by the oscillating circuit; and processing a phase-locked clock signal output by the oscillating circuit through a phase-locking circuit to generate a phase control code corresponding to the phase-locked clock signal, wherein the phase control code is used to phase-lock the clock signal output by the oscillating circuit.

[0034] The frequency-locked clock signal output from the oscillator circuit is processed by a frequency-locked circuit, while the phase-locked clock signal output from the oscillator circuit is processed by a phase-locked circuit. In other words, frequency locking and phase locking are implemented using different circuits; the frequency-locked circuit meets the requirements for frequency locking, and the phase-locked circuit meets the requirements for phase locking. This allows for rapid locking of both frequency and phase, simplifying the locking process and reducing locking time.

[0035] In some embodiments of this disclosure, the frequency-locked clock signal output by the oscillation circuit is processed by a frequency-locked circuit to obtain a frequency control code corresponding to the frequency-locked clock signal, including: frequency calibration of the first frequency-locked clock signal to generate a first frequency control code corresponding to the first frequency-locked clock signal; and frequency calibration of the second frequency-locked clock signal to generate a second frequency control code corresponding to the second frequency-locked clock signal.

[0036] By performing targeted frequency calibration on different frequency-locked clock signals, the locking process speed can be accelerated.

[0037] In some embodiments of this disclosure, frequency calibration is performed on a first frequency-locked clock signal to generate a first frequency control code corresponding to the first frequency-locked clock signal, including: obtaining a first difference between a count value and a target count value, wherein the count value is the count value of the first frequency-locked clock signal within a preset time period; and generating a first frequency control code corresponding to the first frequency-locked clock signal based on the first difference.

[0038] The first frequency control code is adjusted based on the first difference between the count value and the target count value. The first frequency control code is output to the oscillation circuit, and then the oscillation circuit outputs the corresponding first frequency-locked clock signal. Through multiple iterations, the first difference is made to meet the requirements, thereby controlling the frequency of the frequency-locked clock signal output by the oscillation circuit within a preset frequency range.

[0039] In some embodiments of this disclosure, frequency calibration is performed on the second frequency-locked clock signal to generate a second frequency control code corresponding to the second frequency-locked clock signal, including: obtaining a second difference between the division ratio and a first target division ratio, wherein the division ratio is the division ratio between the second frequency-locked clock signal and a reference clock signal; and generating a second frequency control code corresponding to the second frequency-locked clock signal based on the second difference.

[0040] The first target frequency division ratio is a pre-set ratio between the second frequency-locked clock signal and the reference clock signal, obtained at the end of the calibration of the second frequency-locked clock signal. Based on the second difference, the second frequency control code is monotonically accumulated to achieve precise frequency locking.

[0041] In some embodiments of this disclosure, the method further includes: if frequency hopping occurs, obtaining a second target division ratio, and adjusting the frequency control code to an approximate value of the target control code to adjust the division ratio to be equal to the second target division ratio. By adjusting the frequency control code to an approximate value of the target control code to adjust the division ratio to be equal to the second target division ratio, rapid cancellation of frequency hopping is achieved. Furthermore, the operation of comparing the count value with the target count value is no longer performed when frequency hopping occurs, greatly saving the time required to cancel frequency modulation.

[0042] According to a fourth aspect of the present disclosure, a clock signal locking device is provided, comprising: a frequency locking module, configured to process a frequency-locked clock signal output by an oscillating circuit through a frequency locking circuit to obtain a frequency control code corresponding to the frequency-locked clock signal, wherein the frequency control code is used to frequency-lock the clock signal output by the oscillating circuit; and a phase locking module, configured to process a phase-locked clock signal output by the oscillating circuit through a phase locking circuit to generate a phase control code corresponding to the phase-locked clock signal, wherein the phase control code is used to phase-lock the clock signal output by the oscillating circuit.

[0043] According to a fifth aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform any of the methods described in the third aspect above.

[0044] According to a sixth aspect of the present disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform any of the methods described in the third aspect above.

[0045] According to a seventh aspect of the present disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements any of the methods in the third aspect described above.

[0046] This disclosure provides an eighth aspect of a chip, including the phase-locked loop (PLL) proposed in the first aspect. In embodiments of this disclosure, the chip may include a baseband chip.

[0047] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects: This disclosure presents a fully digital phase-locked loop (PLL) comprising an oscillator circuit, a frequency-locked circuit, and a phase-locked circuit. The oscillator circuit generates a clock signal, the frequency-locked circuit locks the frequency of the clock signal generated by the oscillator circuit, and the phase-locked circuit locks the phase of the clock signal generated by the oscillator circuit. That is, frequency locking and phase locking are implemented using different circuits; the frequency-locked circuit meets the requirements for frequency locking, and the phase-locked circuit meets the requirements for phase locking. This enables rapid locking of both frequency and phase, simplifies the locking process, and reduces locking time.

[0048] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0049] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0050] Figure 1 This is a schematic diagram of a fully digital phase-locked loop in related technologies; Figure 2 This is a schematic diagram of a fully digital phase-locked loop according to some embodiments of the present disclosure. Figure 1 .

[0051] Figure 3 This is a schematic diagram of a fully digital phase-locked loop according to some embodiments of the present disclosure. Figure 2 .

[0052] Figure 4 This is a schematic diagram of a fully digital phase-locked loop according to some embodiments of the present disclosure. Figure 3 .

[0053] Figure 5 This is a schematic diagram of a fully digital phase-locked loop according to some embodiments of the present disclosure. Figure 4 .

[0054] Figure 6 This is a schematic diagram of a fully digital phase-locked loop according to some embodiments of the present disclosure. Figure 5 .

[0055] Figure 7 This is a schematic diagram of a fully digital phase-locked loop according to some embodiments of the present disclosure. Figure 6 .

[0056] Figure 8 This is a block diagram illustrating an electronic device according to some embodiments of the present disclosure; Figure 9 This is a flowchart illustrating a clock signal locking method according to some embodiments of the present disclosure; Figure 10 This is a flowchart illustrating a fully digital phase-locked loop (PLL) locking process according to some embodiments of the present disclosure; Figure 11 This is a schematic diagram of the counting results of an asynchronous counting circuit according to some embodiments of the present disclosure; Figure 12 This is a schematic diagram of a digital loop filter circuit according to some embodiments of the present disclosure; Figure 13 This is a diagram illustrating the all-digital phase-locked loop locking process according to some embodiments of this disclosure; Figure 14 This is a schematic diagram of overshoot locking in the related art according to an exemplary embodiment of the present disclosure; Figure 15 This is a block diagram illustrating another electronic device according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0057] Some embodiments of this disclosure will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. Various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but can be changed as will become apparent upon understanding this disclosure, except for operations that must be performed in a particular order. Furthermore, for clarity and brevity, descriptions of features known in the art may be omitted.

[0058] The embodiments described in the following examples of this disclosure are not representative of all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0059] It should be noted that, in the description of this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this disclosure are used to distinguish similar objects and are not used to describe a particular order or sequence.

[0060] All-digital phase-locked loops in related technologies, such as Figure 1 As shown, application Figure 1 The same circuit is used for frequency and phase locking in conventional all-digital phase-locked loops, making it difficult to achieve fast locking of both frequency and phase simultaneously. This results in a cumbersome locking process and increased locking time. To overcome these technical shortcomings, this disclosure provides an all-digital phase-locked loop, a clock signal locking method, a locking device, an electronic device, a computer-readable storage medium, and a computer program product.

[0061] The specific implementation methods of the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0062] Figure 2 This is a schematic diagram of the structure of a fully digital phase-locked loop according to an embodiment of the first aspect of this disclosure. Figure 1 ,like Figure 2 As shown, the all-digital phase-locked loop includes: Oscillating circuit; A frequency locking circuit, connected to the oscillation circuit, is used to receive the frequency-locked clock signal output by the oscillation circuit, generate a frequency control code corresponding to the frequency-locked clock signal, and output the frequency control code to the oscillation circuit to lock the frequency of the clock signal output by the oscillation circuit. See Figure 2 The frequency lock circuit is connected to the oscillator circuit to form a negative feedback loop. In the specific implementation, the frequency lock circuit uses the negative feedback principle to perform multiple iterations on the frequency-locked clock signal output by the oscillator circuit to obtain multiple frequency control codes until the frequency of the clock signal output by the oscillator circuit is locked.

[0063] A phase-locked circuit, connected to the oscillation circuit, is used to receive the phase-locked clock signal output by the oscillation circuit, generate a phase control code corresponding to the phase-locked clock signal, and output the phase control code to the oscillation circuit to phase-lock the clock signal output by the oscillation circuit.

[0064] See Figure 2The phase-locked circuit is connected to the oscillator circuit to form a negative feedback loop. In the specific implementation, the phase-locked circuit uses the negative feedback principle to perform multiple iterations on the phase-locked clock signal output by the oscillator circuit to obtain multiple phase control codes until the phase of the clock signal output by the oscillator circuit is locked.

[0065] The iterative processing applied to the all-digital phase-locked loop is a discrete iterative negative feedback.

[0066] Both the frequency-locked clock signal and the phase-locked clock signal are clock signals output by the oscillator circuit. The difference lies in their application: the clock signal used for frequency locking is the frequency-locked clock signal, while the clock signal used for phase locking is the phase-locked clock signal. In other words, the frequency-locked clock signal and the phase-locked clock signal are clock signals output by the oscillator circuit at different time intervals.

[0067] The all-digital phase-locked loop of this disclosure includes an oscillation circuit, a frequency-locked circuit, and a phase-locked circuit. The oscillation circuit generates a clock signal, the frequency-locked clock signal generated by the oscillation circuit is frequency-locked by the frequency-locked circuit, and the phase-locked clock signal generated by the oscillation circuit is phase-locked by the phase-locked circuit. That is, frequency locking and phase locking are implemented using different circuits; the frequency-locked circuit meets the requirements for frequency locking, and the phase-locked circuit meets the requirements for phase locking. This enables rapid locking of both frequency and phase, simplifies the locking process, and reduces locking time.

[0068] In exemplary embodiments of this disclosure, such as Figure 3 As shown, the frequency locking circuit includes a first frequency calibration circuit and a second frequency calibration circuit; wherein, The first frequency calibration circuit is connected to the oscillation circuit and is used to receive the first frequency-locked clock signal output by the oscillation circuit, perform frequency calibration on the first frequency-locked clock signal to generate a first frequency control code corresponding to the first frequency-locked clock signal, and output the first frequency control code to the oscillation circuit. The second frequency calibration circuit is connected to the oscillation circuit and is used to receive the second frequency-locked clock signal output by the oscillation circuit, perform frequency calibration on the second frequency-locked clock signal to generate a second frequency control code corresponding to the second frequency-locked clock signal, and output the second frequency control code to the oscillation circuit.

[0069] To satisfy the wide frequency tuning range of the oscillation circuit, this embodiment employs a first frequency calibration circuit and a second frequency calibration circuit to process different frequency-locked clock signals, respectively. Specifically, the first frequency calibration circuit is adapted to process the first frequency-locked clock signal, and the second frequency calibration circuit is adapted to process the second frequency-locked clock signal. By dividing the frequency-locked clock signal to be processed into two types and then using two different frequency calibration circuits to process the two types of frequency-locked clock signals respectively, the locking process speed is accelerated.

[0070] Specifically, the frequency-locked clock signal to be processed can be divided into a first frequency-locked clock signal and a second frequency-locked clock signal based on its frequency. For example, the first frequency-locked clock signal is a signal with a higher frequency; the second frequency-locked clock signal is a signal with a lower frequency.

[0071] The frequency-locked clock signal to be processed can also be divided into a first frequency-locked clock signal and a second frequency-locked clock signal based on the frequency difference between the frequency-locked clock signal and the reference clock signal. For example, the signal corresponding to a larger frequency difference can be regarded as the first frequency-locked clock signal, and the signal corresponding to a smaller frequency difference can be regarded as the second frequency-locked clock signal.

[0072] In this embodiment of the disclosure, the first frequency calibration circuit and the second frequency calibration circuit use different frequency calibration methods when performing frequency calibration. For example, the first frequency calibration circuit uses a coarse frequency adjustment method to perform frequency calibration, while the second frequency calibration circuit uses a fine frequency adjustment method to perform frequency calibration, in order to adapt to the rapid calibration of frequency-locked clock signals of different frequencies.

[0073] In coarse frequency tuning, the adjustment range or step size of the frequency control code is greater than that in fine frequency tuning. In some cases, the adjustment range or step size of the frequency control code in coarse frequency tuning is much larger than that in fine frequency tuning.

[0074] In this embodiment of the disclosure, the frequency calibration accuracy of the first frequency calibration circuit and the second frequency calibration circuit differs. For example, the frequency calibration accuracy of the first frequency calibration circuit is lower than that of the second frequency calibration circuit. In this case, the first frequency calibration circuit is suitable for processing higher frequency locked clock signals, and the second frequency calibration circuit is suitable for processing lower frequency locked clock signals.

[0075] In some embodiments of this disclosure, the first frequency-locked clock signal is obtained in an earlier time period, has a higher frequency, and is more suitable for coarse frequency adjustment. The second frequency-locked clock signal is obtained in a later time period, has a lower frequency, and is more suitable for fine frequency adjustment.

[0076] In a more specific embodiment, the first frequency calibration circuit first performs frequency calibration on the first frequency-locked clock signal with a higher frequency to obtain the first frequency control code corresponding to the last processing. Then, the first frequency control code is input to the oscillation circuit, the oscillation circuit outputs the corresponding second frequency-locked clock signal, and the second frequency calibration circuit is used to calibrate the second frequency-locked clock signal. That is, the calibration of the first frequency calibration circuit comes first, and the calibration of the second frequency calibration circuit comes later, and the calibration processes of the two frequency calibration circuits are continuous.

[0077] In some embodiments of this disclosure, see again Figure 3 The first frequency calibration circuit not only performs frequency calibration on the first frequency-locked clock signal to generate a first frequency control code corresponding to the first frequency-locked clock signal, but also determines whether to perform frequency calibration. That is, the first frequency calibration circuit has both frequency calibration and enable / determine functions. Specifically, the first frequency calibration circuit detects whether the frequency of the frequency-locked clock signal output by the oscillation circuit corresponds to its frequency calibration frequency; if so, the first frequency calibration circuit begins frequency calibration. The second frequency calibration circuit has a similar function to the first frequency calibration circuit, performing both frequency calibration and enable / determine functions.

[0078] In some embodiments of this disclosure, the all-digital phase-locked loop further includes a control circuit; wherein... The control circuit is connected to the first frequency calibration circuit, the second frequency calibration circuit, and the oscillation circuit respectively, and is used to enable the first frequency calibration circuit and the second frequency calibration circuit according to the frequency difference between the clock signal output by the oscillation circuit and the reference clock signal.

[0079] Unlike the first frequency calibration circuit, the second frequency calibration circuit not only has a frequency calibration function but also an enable judgment function. In this embodiment, the enable judgment function is implemented by the control circuit. The control circuit judges the frequency difference between the clock signal output by the oscillation circuit and the reference clock signal. If the frequency difference is large, the first frequency calibration circuit is controlled to work. If the frequency difference is small, that is, the frequency of the clock signal output by the oscillation circuit is already close to the frequency of the reference clock signal, but there is still a small frequency difference, the second frequency calibration circuit is controlled to work.

[0080] In some embodiments of this disclosure, the first frequency calibration circuit is used to generate a first frequency control code corresponding to the first frequency-locked clock signal based on a first difference between the count value and the target count value, and output the first frequency control code to the oscillation circuit, wherein the count value is the count value of the first frequency-locked clock signal within a preset time period.

[0081] The first frequency control code is adjusted based on the first difference between the count value and the target count value. The first frequency control code is output to the oscillation circuit, and then the oscillation circuit outputs the corresponding first frequency-locked clock signal. Through multiple iterations, the first difference is made to meet the requirements, thereby controlling the frequency of the frequency-locked clock signal output by the oscillation circuit within a preset frequency range.

[0082] The target count value is the count value of the first frequency-locked clock signal obtained at the end of the calibration of the first frequency calibration circuit within a preset time period. The frequency difference between the first frequency-locked clock signal obtained at the end of the calibration of the first frequency calibration circuit and the reference clock signal is less than a preset frequency. Correspondingly, the first difference between the count value and the target count value is less than a preset difference, meaning the frequency value of the first frequency-locked clock signal is close to the frequency value of the reference clock signal. In other words, the first frequency calibration circuit brings the frequency of the first frequency-locked clock signal to near the target frequency.

[0083] The preset time period in this embodiment can be selected from various options, such as the period of the reference clock signal, a fixed timing period (e.g., 1ms, 5ms, 10ms, etc.), or an integer multiple of the period of the reference clock signal.

[0084] In this embodiment, in addition to generating a first frequency control code corresponding to the first frequency-locked clock signal based on the first difference between the count value and the target count value, a first frequency control code corresponding to the first frequency-locked clock signal can also be generated based on other frequency-related parameters, such as high-level width, low-level width, clock period, and total time consumption of a fixed number of pulses. Of course, when using these parameters, the corresponding target value also needs to be obtained, and then the actual measured value and the target value are compared before generating the corresponding first frequency control code based on the difference between the two.

[0085] To achieve rapid frequency locking of the first frequency-locked clock signal by the first frequency calibration circuit, the first frequency calibration circuit generates a first frequency control code corresponding to the first frequency-locked clock signal based on a first difference between the count value and the target count value using a binary search method, and outputs the first frequency control code to the oscillation circuit. Specifically, if the first difference between the count value and the target count value is less than a preset difference, the updated first frequency control code is searched in the right half of the interval; if the first difference between the count value and the target count value is greater than the preset difference, the updated first frequency control code is searched in the left half of the interval, until the first difference between the count value and the target count value equals the preset difference, thus locking the frequency of the clock signal output by the oscillation circuit to near the frequency of the reference clock signal. The binary search method is used to quickly lock the frequency of the clock signal output by the oscillation circuit to near the frequency of the reference clock signal.

[0086] In this embodiment of the present disclosure, the second frequency calibration circuit is used to generate a second control code corresponding to the second frequency-locked clock signal based on the second difference between the frequency division ratio and the first target frequency division ratio, and output the second control code to the oscillation circuit, wherein the frequency division ratio is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal.

[0087] The frequency division ratio is specifically the frequency division ratio between the real-time second frequency-locked clock signal and the reference clock signal during the operation of the second frequency calibration circuit.

[0088] The first target frequency division ratio is the pre-set frequency division ratio obtained when the second frequency calibration circuit finishes calibration, which is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal. Based on the second difference, the second frequency control code is monotonically accumulated. When the second frequency calibration circuit finishes calibration, the frequency of the clock signal output by the oscillation circuit is within the neighborhood of the reference clock signal's frequency. That is, the frequency of the clock signal is equal to the frequency of the reference clock signal, or the error between the clock signal's frequency and the reference clock signal's frequency is negligible, sufficient to meet the operating requirements of other circuits driven by the clock signal output by the fully digital phase-locked loop.

[0089] In this embodiment, in addition to generating a second control code corresponding to the second frequency-locked clock signal based on the second difference between the frequency division ratio and the first target frequency division ratio, a second control code corresponding to the second frequency-locked clock signal can also be generated based on other frequency-related parameters, such as the frequency multiplication ratio. Of course, when using these parameters, the corresponding target value also needs to be obtained, and then the actual measured value and the target value are compared, and the corresponding first frequency control code is generated based on the difference between the two.

[0090] See Figure 5 The first frequency calibration circuit includes a first conversion sub-circuit and a second conversion sub-circuit. The first conversion sub-circuit converts the first frequency-locked clock signal into a first frequency-related signal. The second conversion sub-circuit is connected to the first conversion sub-circuit and converts the first frequency-related signal into the first frequency control code, outputting the first frequency control code to the oscillation circuit. In other words, the first conversion sub-circuit converts the first frequency-locked clock signal into a frequency-related signal, and the second conversion sub-circuit converts the first frequency-related signal into the first frequency control code. Thus, the two sub-circuits included in the first frequency calibration circuit are used to calibrate the frequency of the first frequency-locked clock signal.

[0091] The first frequency-related signal is a signal that reflects the frequency of the first frequency-locked clock signal. The first frequency-related signal can have various options, such as high-level width, low-level width, clock period, number of pulses within a fixed gate time, and total time consumption of a fixed number of pulses.

[0092] In a specific embodiment of this disclosure, the first frequency-related signal is a first difference between a count value and a target count value, the count value being the count value of the first frequency-locked clock signal within a preset time period, the first conversion sub-circuit being used to convert the first frequency-locked clock signal into the first difference; the second conversion sub-circuit being used to convert the first difference into the first frequency control code and output the first frequency control code to the oscillation circuit.

[0093] The first frequency control code is adjusted based on the first difference between the count value and the target count value. The first frequency control code is output to the oscillation circuit, and then the oscillation circuit outputs the corresponding first frequency-locked clock signal. Through multiple iterations, the first difference is made to meet the requirements, thereby controlling the frequency of the frequency-locked clock signal output by the oscillation circuit within a preset frequency range.

[0094] See Figure 5 The second frequency calibration circuit includes: a third conversion sub-circuit for converting the second frequency-locked clock signal into a second frequency-related signal; and a fourth conversion sub-circuit connected to the third conversion sub-circuit for converting the second frequency-related signal into the second frequency control code and outputting the second frequency control code to the oscillation circuit.

[0095] The second frequency-related signal is a signal that reflects the frequency of the second frequency-locked clock signal. There are several options for the second frequency-related signal, such as the division ratio and multiplication ratio.

[0096] The third conversion sub-circuit converts the second frequency-locked clock signal into a frequency-related signal, and the fourth conversion sub-circuit converts the second frequency-related signal into a second frequency control code. In other words, the two sub-circuits included in the second frequency calibration circuit are used to calibrate the frequency of the second frequency-locked clock signal.

[0097] In a specific embodiment of this disclosure, the second frequency-related signal is a second difference between the frequency division ratio and the first target frequency division ratio, wherein the frequency division ratio is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal, and the third conversion sub-circuit is used to convert the second frequency-locked clock signal into the second difference; the fourth conversion sub-circuit is connected to the third conversion sub-circuit and is used to convert the second difference into the second frequency control code and output the second frequency control code to the oscillation circuit.

[0098] The first target frequency division ratio is the pre-set frequency division ratio. When the second frequency calibration circuit finishes calibration, the frequency division ratio between the second frequency-locked clock signal and the reference clock signal is obtained. At the end of the second frequency calibration circuit calibration, the frequency of the clock signal output by the oscillation circuit is within the neighborhood of the reference clock signal frequency. That is, the frequency of the clock signal is equal to the frequency of the reference clock signal, or the error between the frequencies of the clock signal and the reference clock signal is negligible.

[0099] In this embodiment of the disclosure, frequency calibration using a division ratio can be implemented using an asynchronous counting circuit, which is based on the asynchronous counting principle.

[0100] In this embodiment of the present disclosure, the second conversion circuit, in addition to converting the first frequency-related signal into the first frequency control code and outputting the first frequency control code to the oscillation circuit, also enables the first conversion circuit. In this case, the second conversion circuit receives the clock signal output by the oscillation circuit and enables the first conversion circuit according to the magnitude of the frequency of the clock signal.

[0101] In this embodiment of the disclosure, the second conversion circuit converts the first frequency-related signal into the first frequency control code and outputs the first frequency control code to the oscillation circuit. Enabling the second conversion circuit is achieved by other control circuits, for example... Figure 4 The control circuit in it.

[0102] Similarly, the fourth conversion circuit converts the second frequency-related signal into the second frequency control code and outputs the second frequency control code to the oscillation circuit. Enabling the fourth conversion circuit is achieved by other control circuits, for example... Figure 4 The control circuit in it.

[0103] In this embodiment of the present disclosure, the fourth conversion circuit, in addition to converting the second frequency-related signal into the second frequency control code and outputting the second frequency control code to the oscillation circuit, also enables the third conversion circuit. In this case, the fourth conversion circuit receives the clock signal output by the oscillation circuit and enables the third conversion circuit according to the magnitude of the frequency of the clock signal.

[0104] In this embodiment of the disclosure, see Figure 6 The second and third conversion circuits are integrated and merged into a single fifth conversion sub-circuit, which has the functions of both the second and third conversion circuits. In other words, the functions of the second and third conversion circuits are achieved using a single fifth conversion sub-circuit.

[0105] In this embodiment of the disclosure, see Figure 7The phase-locked circuit includes a phase comparator circuit, a digital loop filter circuit, a frequency divider circuit, and a time phase shifter circuit. The output of the phase comparator circuit is connected to the input of the digital loop filter circuit, and the output of the digital loop filter circuit is connected to the input of the oscillation circuit. The output of the oscillation circuit is fed back to the feedback input of the phase comparator circuit via the frequency divider circuit and the time phase shifter circuit. The phase comparator circuit receives a reference clock signal and a feedback signal from the time phase shifter circuit, compares the phases of the two signals, and outputs an error signal characterizing the phase difference and phase lead / lag relationship, providing the initial error control quantity for subsequent loop adjustment. The digital loop filter circuit receives the error signal output by the phase comparator circuit and performs smoothing filtering, noise suppression, loop gain adjustment, and integral shaping on the error signal. It filters out high-frequency interference and comparison glitches, converting the discrete phase error into a stable digital control voltage / control code, stabilizing the loop adjustment characteristics, and preventing loop lock-up and oscillation. The oscillation circuit, as the core frequency generation unit of the loop, receives the control signal (control code) output from the digital loop filter circuit. Based on the control quantity, it adjusts the phase of its output clock signal in real time to achieve controlled oscillation, providing a reference oscillation source for the entire phase-locked loop. The frequency divider circuit performs integer / fractional frequency division and frequency reduction on the high-frequency oscillation signal output from the oscillation circuit, dividing the VCO high-frequency signal to a frequency level close to the reference signal. This matches the input frequency range of the phase comparator circuit, achieving closed-loop frequency matching. The time-shifting circuit performs controllable time delay and phase fine-tuning on the frequency-divided signal, precisely adjusting the phase offset of the feedback signal; compensating for link transmission delay and achieving accurate phase calibration, ensuring the feedback signal phase accurately tracks the reference signal phase and improving phase-locking accuracy.

[0106] In this embodiment, the digital loop filter circuit receives the phase difference signal output by the phase comparison circuit, filters the phase difference signal, and adjusts the filtering parameters of the digital loop filter circuit according to the magnitude of the phase difference signal. The filtering parameters include integral coefficients, proportional coefficients, etc. By adjusting the filtering parameters of the digital loop filter circuit to adapt to different phase difference signals, the filtering effect is improved, thereby achieving precise phase locking.

[0107] In this embodiment, different filtering parameters of the digital loop filter circuit correspond to different operating modes. The digital loop filter circuit is further configured to switch the operating mode from a first operating mode to a second operating mode in response to an operating mode switching command, and to acquire the phase difference signal in the first operating mode, using the phase difference signal in the first operating mode for phase compensation in the second operating mode. By sampling the phase difference signal output by the phase comparison circuit during operating mode switching, and compensating the phase difference carried by this phase difference signal to the switched operating mode, rapid phase locking in the second operating mode is achieved. Furthermore, the operating mode switching achieves overshoot-free phase alignment.

[0108] See Figure 7 A frequency-locked loop is formed by a first frequency calibration circuit, a second frequency calibration circuit, and an oscillation circuit; a phase-locked loop is formed by a phase comparison circuit, a digital loop filter circuit, an oscillation circuit, a frequency divider circuit, and a time phase shifter circuit. The first frequency calibration circuit generates a first frequency control code corresponding to the first frequency-locked clock signal based on the first difference between the count value and the target count value using a binary division method, and outputs the first frequency control code to the oscillation circuit. The second frequency calibration circuit generates a second control code corresponding to the second frequency-locked clock signal based on the second difference between the frequency division ratio and the first target frequency division ratio, and outputs the second control code to the oscillation circuit, achieving fast and accurate frequency locking. The digital loop filter circuit adjusts the filter parameters according to filtering requirements to achieve fast and accurate phase locking. It can balance the wide frequency tuning range and low quantization noise performance of the oscillation circuit. No additional correction is required; it utilizes asynchronous counting and adaptive loop filtering technology to achieve fast frequency and phase locking and frequency hopping functions. Compared to… Figure 1 The all-digital phase-locked loop in the system significantly reduces the locking time at a reference frequency of 38.4MHz.

[0109] In this embodiment, the digital loop filter circuit, based on filtering requirements, first uses proportional adjustment to achieve coarse phase adjustment, and then uses proportional-derivative adjustment to achieve fine phase adjustment. Using proportional adjustment for coarse phase adjustment provides excellent phase capture performance, but after locking, a certain phase difference still exists between the output signal and the reference signal. Proportional-derivative adjustment, with its integral gain and loop bandwidth, allows for good convergence of the locking mechanism. Compared to proportional adjustment, it offers better noise performance, locking the phase difference between the clock signal output by the oscillation circuit and the reference clock signal near zero, while simultaneously completing loop locking.

[0110] A second aspect of this disclosure also provides an electronic device, such as... Figure 8As shown, it includes: a fully digital phase-locked loop circuit and a main control circuit, wherein the fully digital phase-locked loop circuit is the fully digital phase-locked loop circuit in the first aspect embodiment; the fully digital phase-locked loop circuit is connected to the main control circuit; the fully digital phase-locked loop circuit is used to output a target clock signal with frequency and phase locked; the main control circuit receives the target clock signal output by the fully digital phase-locked loop circuit and performs a predetermined function under the drive of the target clock signal.

[0111] The electronic device of this disclosure includes a fully digital phase-locked loop circuit and a main control circuit. Since the fully digital phase-locked loop circuit generates a clock signal with both frequency and phase precisely locked, the operating timing of the main control circuit is more stable, thereby improving the overall operating stability of the electronic device.

[0112] A third aspect of this disclosure also provides a method for locking a clock signal, see [link to relevant documentation]. Figure 9 ,include: Step S901: The frequency-locked clock signal output by the oscillation circuit is processed by the frequency-locked circuit to obtain the frequency control code corresponding to the frequency-locked clock signal. The frequency control code is used to lock the frequency of the clock signal output by the oscillation circuit. Step S902: The phase-locked clock signal output by the oscillator circuit is processed by the phase-locked circuit to generate a phase control code corresponding to the phase-locked clock signal. The phase control code is used to phase-lock the clock signal output by the oscillator circuit.

[0113] The clock signal locking method of this disclosure processes the frequency-locked clock signal output by the oscillation circuit through a frequency-locking circuit and the phase-locked clock signal output by the oscillation circuit through a phase-locking circuit. That is, frequency locking and phase locking are implemented using different circuits; the frequency-locking circuit meets the requirements of frequency locking, and the phase-locking circuit meets the requirements of phase locking. This allows for rapid locking of both frequency and phase, simplifies the locking process, and reduces locking time.

[0114] In this embodiment of the disclosure, the frequency-locked clock signal output by the oscillation circuit is processed by a frequency-locked circuit to obtain a frequency control code corresponding to the frequency-locked clock signal, including: The first frequency-locked clock signal is calibrated to generate a first frequency control code corresponding to the first frequency-locked clock signal. The second frequency-locked clock signal is calibrated to generate a second frequency control code corresponding to the second frequency-locked clock signal.

[0115] By performing targeted frequency calibration on different frequency-locked clock signals, the locking process speed can be accelerated.

[0116] In this embodiment of the disclosure, frequency calibration is performed on the first frequency-locked clock signal to generate a first frequency control code corresponding to the first frequency-locked clock signal, including: Obtain the first difference between the count value and the target count value, wherein the count value is the count value of the first frequency-locked clock signal within a preset time period; A first frequency control code corresponding to the first frequency-locked clock signal is generated based on the first difference.

[0117] The first frequency control code is adjusted based on the first difference between the count value and the target count value. The first frequency control code is output to the oscillation circuit, and then the oscillation circuit outputs the corresponding first frequency-locked clock signal. Through multiple iterations, the first difference is made to meet the requirements, thereby controlling the frequency of the frequency-locked clock signal output by the oscillation circuit within a preset frequency range.

[0118] In this embodiment of the disclosure, frequency calibration is performed on the second frequency-locked clock signal to generate a second frequency control code corresponding to the second frequency-locked clock signal, including: Obtain a second difference between the frequency division ratio and the first target frequency division ratio, wherein the frequency division ratio is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal; A second frequency control code corresponding to the second frequency-locked clock signal is generated based on the second difference.

[0119] The first target frequency division ratio is a pre-set ratio between the second frequency-locked clock signal and the reference clock signal, obtained at the end of the calibration of the second frequency-locked clock signal. Based on the second difference, the second frequency control code is monotonically accumulated to achieve precise frequency locking.

[0120] In this embodiment of the disclosure, the method further includes: if frequency hopping occurs, obtaining a second target division ratio, and adjusting the frequency control code to an approximate value of the target control code to adjust the division ratio to be equal to the second target division ratio. The second target division ratio is a pre-set division ratio corresponding to frequency hopping cancellation, and the target control code is the control code corresponding to the clock signal output by the oscillation circuit when frequency hopping is cancelled. By adjusting the frequency control code to an approximate value of the target control code to adjust the division ratio to be equal to the second target division ratio, rapid cancellation of frequency hopping is achieved. Furthermore, the operation of comparing the count value with the target count value is no longer performed when frequency hopping occurs, greatly saving the time for frequency cancellation.

[0121] In related technologies, to balance the wide frequency tuning range and low quantization noise performance of numerically controlled oscillators (equivalent to the oscillation circuit described in this paper), a multi-stage tuning method is adopted. This involves dividing the tuning gain of the numerically controlled oscillator into multiple levels and switching between different tuning modes to achieve a wider tuning range and higher tuning resolution, effectively reducing quantization noise. However, multi-stage tuning of the numerically controlled oscillator is detrimental to the locking behavior of the ADPLL, requiring the ADPLL to undergo multiple locking processes to complete the locking, significantly increasing the loop locking time.

[0122] For a traditional, stable loop filter phase-locked loop (PLL), it eventually converges to a damped oscillation process. At its gain crossover frequency, its closed-loop frequency step response is underdamped, and the system is close to oscillation, generating overshoot spikes. Increasing damping can alleviate overshoot to some extent, but it will worsen the locking speed. Therefore, eliminating overshoot is crucial for the PLL's performance under fast locking conditions.

[0123] To at least address overshoot, this disclosure provides a specific solution, see [link to relevant documentation]. Figure 10 ,include: After loop reset, it checks whether automatic frequency calibration is enabled. If enabled, the loop enters the binary automatic frequency calibration state. Automatic frequency calibration and frequency locking are implemented using a first frequency calibration circuit. This first frequency calibration circuit uses the first difference between the count value and the target count value, applying a binary division method to generate a first frequency control code corresponding to the first frequency-locked clock signal, and outputs this code to the oscillation circuit. The coarse adjustment setting of the calibration oscillation circuit (DCO) is set to the control code, ensuring the frequency output is near the target frequency. Otherwise, it enters the asynchronous counting state based on the manually given DCO coarse adjustment control code. Because the accuracy of the binary division method is limited by the number of quantization bits, and the first frequency calibration circuit has low locking accuracy and lacks phase information, the loop does not enter the locked state but instead enters the asynchronous counting state to continue frequency locking. The asynchronous counter (second frequency calibration circuit) estimates the current division ratio by counting the high-frequency clock of each reference cycle.

[0124] The control circuit determines the difference between the current division ratio and the target division ratio, integrates and accumulates this difference, and then achieves rapid frequency locking. At this point, the frequency is locked at ±αK of the target frequency. TDC K DCO Within the range, α represents K TDC or K DCO The relative error or fluctuation coefficient, K TDC This indicates that the time-to-digital converter (TDC) is equivalent to a phase comparator circuit and a time phase shifter circuit, K DCO This represents the gain of the numerically controlled oscillator, ±αK. TDC KDCO Describes the deviation of the actual total gain from the nominal value.

[0125] After employing different counting frequency locking methods, the loop enters the phase-locked state of a Type I loop filter. Considering that there was no phase information within the loop before, the phase difference between the current frequency and the target frequency of the clock signal output by the numerically controlled oscillator is uncontrollable. For a Type I loop filter, the output frequency is the result of multiplying the output of the loop phase comparator circuit by a proportional coefficient α. The phase is monotonically captured within a certain range, and at this time, the output frequency phase is locked within the capture range of the loop phase comparator circuit.

[0126] Considering that the current output clock frequency and phase are already close to the target frequency, switch the loop to Type II loop filter phase-locked state. At this point, loop parameters with a larger loop bandwidth can be quickly locked.

[0127] If frequency hopping occurs, after loop locking, the frequency division control and loop filtering are modulated at two points, connected to the second target frequency division ratio and the target control code respectively. Considering that the target control code cannot be obtained accurately and the phase is inaccurate, the locking loop is re-entered because the loop re-enters asynchronous counting frequency locking.

[0128] Automatic frequency calibration uses a binary search method for frequency tracking. First, the count value of the target frequency within a certain reference period is calculated as a reference value. Using the binary search method, the coarse adjustment DCO frequency control code is pre-calculated. At this point, the number of currently output high-frequency clocks within a certain reference period is counted. Considering the low accuracy of single-cycle counting and the impact of multi-cycle counting on the lock-in time, a trade-off needs to be made. After obtaining the result, the difference between the current count value and the reference value is used to adjust the direction of the binary search approximation, quickly approaching the target frequency, and finally locking the frequency near the target frequency. The lock-in time is fixed and affected by the coarse adjustment quantization accuracy and the counting period.

[0129] The counting effect of asynchronous counting circuit is as follows Figure 11As shown. In the asynchronous counting circuit, the current high-frequency clock and the low-frequency reference clock are input. During the counting process, the remaining high-frequency clock phase residual in the current reference clock cycle is accumulated into the next reference clock cycle, which is equivalent to division. The average is then used to obtain a stable fractional division ratio. In practical applications, the current high-frequency clock is first counted down. Then, a synchronous clock is constructed between the reference clock and the current high-frequency clock to sample the counting result, obtaining an asynchronous counting result. In the asynchronous counting circuit, the reference clock is used to sample and decode the counting result to obtain the final current division ratio. The average is then used to obtain the fractional division ratio. In the asynchronous counting circuit, the difference between the current division ratio and the target division ratio is multiplied by the gain value and integrated. Finally, this is added to the control code of the automatic frequency correction module to obtain the final DCO control code. The current division result is updated in the next cycle. After iteration, the target frequency can be approximated, and frequency locking is finally achieved. The locking time is affected by the gain value, but the locking accuracy must also be considered; otherwise, it will be difficult to capture the phase in a type I loop filter phase-locked loop.

[0130] Figure 11 middle, , , ; ;

[0131] The adaptive loop filter (equivalent to the digital loop filter circuit described in the text) is as follows: Figure 12 As shown in the diagram, this module allows for adaptive switching of the loop filter mode. In a Type I loop filter, the integrator branch gain is reduced to 0, so only the proportional gain is effective. This locking behavior enables rapid, overshoot-free phase / frequency capture. However, even after loop locking, the phase difference between the output and reference signals cannot converge to near zero, and a certain phase difference still exists. To quickly eliminate this phase difference, the output value of the phase comparator circuit is sampled during locking and used as the current phase difference input to the time-shifting circuit for phase compensation. When switching to a Type II loop filter, unlike the Type I filter, the Type II loop filter has an integral gain and a suitable loop bandwidth. Therefore, the locking mechanism converges well, exhibiting better noise performance than the Type I loop filter. It can lock the phase difference between the output and reference signals to near zero, and loop locking is completed simultaneously.

[0132] When frequency hopping is enabled, the loop filter and frequency division control are modulated at two points. During the frequency hopping process, the loop receives the external target frequency division ratio and an approximate value of the target control code. The loop then re-enters the locking process, except for the automatic frequency calibration module using the binary division method, achieving rapid frequency hopping. This process does not require high accuracy of the target DCO control code, and the frequency modulation process is monotonically implemented, mitigating frequency overshoot. Furthermore, due to the characteristics of the asynchronous counting module and the Type I loop filter, the frequency hopping process is guaranteed to be monotonically implemented without frequency overshoot.

[0133] After the loop is locked, the loop filter configuration value can be switched to select a smaller and more suitable loop parameter, which has an advantage in terms of loop noise performance after locking.

[0134] This disclosure relates to a fully digital phase-locked loop (PLL) locking process that utilizes asynchronous counting technology and adaptive loop filtering technology to achieve fast locking and frequency hopping, as follows: Figure 13 As shown. Comparison Figure 1 The all-digital phase-locked loop architecture shown in this scheme significantly reduces the locking time. The binary automatic frequency correction module, the asynchronous counting module, and the adaptive loop filter all effectively optimize the loop locking speed, resulting in a flat-band spectrum. The asynchronous counting module of this disclosure adjusts the control code without requiring the involvement of a high-frequency clock, saving system hardware resources and time overhead. Simultaneously, the adaptive loop filter proposed in this disclosure significantly improves upon the slow locking of traditional Type II loop filters, achieving fast phase locking. (Comparison) Figure 14 The method shown is adopted Figure 1 The fully digital phase-locked loop architecture in this disclosure performs multi-pulse locking, and the locking time is significantly shortened.

[0135] This disclosure utilizes a binary search method for automatic frequency calibration to achieve rapid coarse frequency adjustment, outputting the frequency to the coarse adjustment level corresponding to the target frequency. It employs asynchronous counting for rapid monotonic frequency locking and an adaptive loop filter for rapid phase alignment. This significantly reduces the locking time without the need for calibration or a high-speed digital clock, greatly reducing system design complexity and cost.

[0136] A fourth aspect embodiment of this disclosure also provides a clock signal locking device, comprising: A frequency locking module is used to process the frequency-locked clock signal output by the oscillation circuit through a frequency locking circuit to obtain a frequency control code corresponding to the frequency-locked clock signal, wherein the frequency control code is used to lock the frequency of the clock signal output by the oscillation circuit. A phase-locked module is used to process the phase-locked clock signal output by the oscillation circuit through a phase-locked circuit to generate a phase control code corresponding to the phase-locked clock signal, wherein the phase control code is used to phase-lock the clock signal output by the oscillation circuit.

[0137] The clock signal locking device of this disclosure includes a frequency locking module that processes the frequency-locked clock signal output by the oscillation circuit through a frequency locking circuit, and a phase locking module that processes the phase-locked clock signal output by the oscillation circuit through a phase locking circuit. That is, frequency locking and phase locking are implemented using different circuits; the frequency locking circuit meets the requirements of frequency locking, and the phase locking circuit meets the requirements of phase locking. This allows for rapid locking of both frequency and phase, simplifies the locking process, and reduces locking time.

[0138] Locking devices can be implemented through software, hardware, or a combination of both, and can be all or part of a device.

[0139] It should be noted that the locking device provided in the above embodiments is only illustrated by the division of the above functional modules when executing the method. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the clock signal locking device and the clock signal locking method embodiments provided in the above embodiments belong to the same concept, and the implementation process is detailed in the method embodiments, which will not be repeated here.

[0140] In this embodiment of the disclosure, the locking device is used to perform all steps in the clock signal locking method of the third aspect embodiment.

[0141] In this embodiment, the frequency locking module includes a first generation submodule and a second generation submodule. The first generation submodule is used to perform frequency calibration on a first frequency-locked clock signal and generate a first frequency control code corresponding to the first frequency-locked clock signal. The second generation submodule is used to perform frequency calibration on a second frequency-locked clock signal and generate a second frequency control code corresponding to the second frequency-locked clock signal. By performing targeted frequency calibration on different frequency-locked clock signals, the locking process speed is accelerated.

[0142] In this embodiment, the first generation submodule is further configured to obtain a first difference between a count value and a target count value, wherein the count value is the count value of the first frequency-locked clock signal within a preset time period; and to generate a first frequency control code corresponding to the first frequency-locked clock signal based on the first difference. By adjusting the first frequency control code according to the first difference between the count value and the target count value, the first frequency control code is output to the oscillation circuit, and the oscillation circuit outputs the corresponding first frequency-locked clock signal. Through multiple iterations, the first difference is made to meet the requirements, thereby controlling the frequency of the frequency-locked clock signal output by the oscillation circuit within a preset frequency range.

[0143] In this embodiment, the second generation submodule is further configured to obtain a second difference between the frequency division ratio and the first target frequency division ratio, wherein the frequency division ratio is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal; and to generate a second frequency control code corresponding to the second frequency-locked clock signal based on the second difference. The first target frequency division ratio is a pre-set frequency division ratio between the second frequency-locked clock signal and the reference clock signal obtained at the end of calibration of the second frequency-locked clock signal. The second frequency control code is monotonically accumulated based on the second difference to achieve precise frequency locking.

[0144] In this embodiment, the device further includes an adjustment module. The adjustment module is used to, if frequency hopping occurs, obtain a second target division ratio and adjust the frequency control code to an approximate value of the target control code to adjust the division ratio to be equal to the second target division ratio. The second target division ratio is a pre-set division ratio corresponding to frequency hopping cancellation, and the target control code is the control code corresponding to the clock signal output by the oscillation circuit when frequency hopping is cancelled. By controlling the frequency control code to an approximate value of the target control code to adjust the division ratio to be equal to the second target division ratio, rapid cancellation of frequency hopping is achieved. Furthermore, the operation of comparing the count value with the target count value is no longer performed when frequency hopping occurs, greatly saving the time for frequency cancellation.

[0145] A fifth aspect embodiment of this disclosure also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to perform all steps in the clock signal locking method of the at least one processor in the third aspect embodiment.

[0146] A sixth aspect embodiment of this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions, characterized in that the computer instructions are used to cause the computer to perform all steps in the clock signal locking method of the third aspect embodiment.

[0147] A seventh aspect embodiment of this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the clock signal locking method of the third aspect embodiment.

[0148] An eighth aspect of this disclosure provides a chip including the phase-locked loop (PLL) proposed in the first aspect of this disclosure. In this embodiment, the chip may include a baseband chip.

[0149] Figure 15 This is a block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure. The electronic device includes a fully digital phase-locked loop (PLL). For example, the electronic device 1500 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness device, personal digital assistant, etc.

[0150] Reference Figure 15 The electronic device 1500 may include one or more of the following components: a processing component 1502, a memory 1504, a power supply component 1506, a multimedia component 1508, an audio component 1510, an input / output (I / O) interface 1512, a sensor component 1514, and a communication component 1516.

[0151] Processing component 1502 typically controls the overall operation of electronic device 1500, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 1502 may include one or more processors 1520 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 1502 may include one or more modules to facilitate interaction between processing component 1502 and other components. For example, processing component 1502 may include a multimedia module to facilitate interaction between multimedia component 1508 and processing component 1502.

[0152] Memory 1504 is configured to store various types of data to support the operation of electronic device 1500. Examples of this data include instructions for any application or method operating on electronic device 1500, contact data, phonebook data, messages, pictures, videos, etc. Memory 1504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0153] Power supply component 1506 provides power to various components of electronic device 1500. Power supply component 1506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 1500.

[0154] Multimedia component 1508 includes a screen that provides an output interface between the electronic device 1500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 1508 includes a front-facing camera and / or a rear-facing camera. When the electronic device 1500 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0155] Audio component 1510 is configured to output and / or input audio signals. For example, audio component 1510 includes a microphone (MIC) configured to receive external audio signals when electronic device 1500 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 1504 or transmitted via communication component 1516. In some embodiments, audio component 1510 also includes a speaker for outputting audio signals.

[0156] I / O interface 1512 provides an interface between processing component 1502 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0157] Sensor assembly 1514 includes one or more sensors for providing state assessments of various aspects of electronic device 1500. For example, sensor assembly 1514 may detect the on / off state of electronic device 1500, the relative positioning of components such as the display and keypad of electronic device 1500, changes in position of electronic device 1500 or a component of electronic device 1500, the presence or absence of user contact with electronic device 1500, the orientation or acceleration / deceleration of electronic device 1500, and temperature changes of electronic device 1500. Sensor assembly 1514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 1514 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 1514 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0158] Communication component 1516 is configured to facilitate wired or wireless communication between electronic device 1500 and other devices. Electronic device 1500 can access wireless networks based on communication standards, such as WiFi, 3G, 4G, 5G, other communication standards, or combinations thereof. In some embodiments of this disclosure, communication component 1516 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In some embodiments of this disclosure, communication component 1516 further includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0159] In some embodiments of this disclosure, the electronic device 1500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0160] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0161] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A fully digital phase-locked loop, characterized in that, include: Oscillating circuit; A frequency locking circuit, connected to the oscillation circuit, is used to receive the frequency-locked clock signal output by the oscillation circuit, generate a frequency control code corresponding to the frequency-locked clock signal, and output the frequency control code to the oscillation circuit to lock the frequency of the clock signal output by the oscillation circuit. A phase-locked circuit, connected to the oscillation circuit, is used to receive the phase-locked clock signal output by the oscillation circuit, generate a phase control code corresponding to the phase-locked clock signal, and output the phase control code to the oscillation circuit to phase-lock the clock signal output by the oscillation circuit.

2. The all-digital phase-locked loop according to claim 1, characterized in that, The frequency locking circuit includes a first frequency calibration circuit and a second frequency calibration circuit; wherein... The first frequency calibration circuit is connected to the oscillation circuit and is used to receive the first frequency-locked clock signal output by the oscillation circuit, perform frequency calibration on the first frequency-locked clock signal to generate a first frequency control code corresponding to the first frequency-locked clock signal, and output the first frequency control code to the oscillation circuit. The second frequency calibration circuit is connected to the oscillation circuit and is used to receive the second frequency-locked clock signal output by the oscillation circuit, perform frequency calibration on the second frequency-locked clock signal to generate a second frequency control code corresponding to the second frequency-locked clock signal, and output the second frequency control code to the oscillation circuit.

3. The all-digital phase-locked loop according to claim 2, characterized in that, The all-digital phase-locked loop also includes a control circuit; wherein... The control circuit is connected to the first frequency calibration circuit, the second frequency calibration circuit, and the oscillation circuit respectively, and is used to enable the first frequency calibration circuit and the second frequency calibration circuit according to the frequency difference between the clock signal output by the oscillation circuit and the reference clock signal.

4. The all-digital phase-locked loop according to claim 2, characterized in that, The first frequency calibration circuit is used to generate a first frequency control code corresponding to the first frequency-locked clock signal based on the first difference between the count value and the target count value, and output the first frequency control code to the oscillation circuit, wherein the count value is the count value of the first frequency-locked clock signal within a preset time period.

5. The all-digital phase-locked loop according to claim 4, characterized in that, The first frequency calibration circuit is used to generate a first frequency control code corresponding to the first frequency-locked clock signal by applying a binary division method based on the first difference between the count value and the target count value, and output the first frequency control code to the oscillation circuit.

6. The all-digital phase-locked loop according to claim 2, characterized in that, The second frequency calibration circuit is used to generate a second control code corresponding to the second frequency-locked clock signal based on the second difference between the frequency division ratio and the first target frequency division ratio, and output the second control code to the oscillation circuit, wherein the frequency division ratio is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal.

7. The all-digital phase-locked loop according to claim 2, characterized in that, The first frequency calibration circuit includes: The first conversion sub-circuit is used to convert the first frequency-locked clock signal into a first frequency-related signal; The second conversion sub-circuit, connected to the first conversion sub-circuit, is used to convert the first frequency-related signal into the first frequency control code and output the first frequency control code to the oscillation circuit.

8. The all-digital phase-locked loop according to claim 7, characterized in that, The first frequency-related signal is the first difference between the count value and the target count value, where the count value is the count value of the first frequency-locked clock signal within a preset time period. The first conversion sub-circuit is used to convert the first frequency-locked clock signal into the first difference value; The second conversion sub-circuit is used to convert the first difference into the first frequency control code and output the first frequency control code to the oscillation circuit.

9. The all-digital phase-locked loop according to claim 2, characterized in that, The second frequency calibration circuit includes: The third conversion sub-circuit is used to convert the second frequency-locked clock signal into a second frequency-related signal; The fourth conversion sub-circuit, connected to the third conversion sub-circuit, is used to convert the second frequency-related signal into the second frequency control code and output the second frequency control code to the oscillation circuit.

10. The all-digital phase-locked loop according to claim 9, characterized in that, The second frequency-related signal is the second difference between the division ratio and the first target division ratio, wherein the division ratio is the division ratio between the second frequency-locked clock signal and the reference clock signal. The third conversion sub-circuit is used to convert the second frequency-locked clock signal into the second difference value; The fourth conversion sub-circuit, connected to the third conversion sub-circuit, is used to convert the second difference into the second frequency control code and output the second frequency control code to the oscillation circuit.

11. The all-digital phase-locked loop according to claim 1, characterized in that, The phase-locked circuit includes a phase comparison circuit, a digital loop filter circuit, a frequency divider circuit, and a time phase-shifting circuit; wherein... The output of the phase comparison circuit is connected to the input of the digital loop filter circuit, the output of the digital loop filter circuit is connected to the input of the oscillation circuit, and the output of the oscillation circuit is sequentially fed back to the feedback input of the phase comparison circuit via the frequency divider circuit and the time phase shifter circuit.

12. The all-digital phase-locked loop according to claim 11, characterized in that, The digital loop filter circuit is used to receive the phase difference signal output by the phase comparison circuit, filter the phase difference signal, and adjust the filtering parameters of the digital loop filter circuit according to the magnitude of the phase difference signal.

13. The all-digital phase-locked loop according to claim 12, characterized in that, Different filtering parameters of the digital loop filter circuit correspond to different operating modes. The digital loop filter circuit is also used to switch the operating mode from the first operating mode to the second operating mode in response to the operating mode switching command, and to collect the phase difference signal in the first operating mode and use the phase difference signal in the first operating mode for phase compensation in the second operating mode.

14. An electronic device comprising: The fully digital phase-locked loop circuit and main control circuit, among which, The fully digital phase-locked loop circuit is the fully digital phase-locked loop circuit according to any one of claims 1-13, and the fully digital phase-locked loop circuit is connected to the main control circuit; The all-digital phase-locked loop circuit is used to output a target clock signal with frequency and phase locked. The main control circuit receives the target clock signal output by the all-digital phase-locked loop circuit and executes a predetermined function under the drive of the target clock signal.

15. A method for locking a clock signal, characterized in that, include: The frequency-locked clock signal output by the oscillation circuit is processed by the frequency-locked circuit to obtain the frequency control code corresponding to the frequency-locked clock signal. The frequency control code is used to lock the frequency of the clock signal output by the oscillation circuit. The phase-locked clock signal output by the oscillation circuit is processed by a phase-locked circuit to generate a phase control code corresponding to the phase-locked clock signal. The phase control code is used to phase-lock the clock signal output by the oscillation circuit.

16. The locking method according to claim 15, characterized in that, The frequency-locked clock signal output from the oscillation circuit is processed by a frequency-locked circuit to obtain a frequency control code corresponding to the frequency-locked clock signal, including: The first frequency-locked clock signal is calibrated to generate a first frequency control code corresponding to the first frequency-locked clock signal. The second frequency-locked clock signal is calibrated to generate a second frequency control code corresponding to the second frequency-locked clock signal.

17. The locking method according to claim 16, characterized in that, Frequency calibration is performed on the first frequency-locked clock signal to generate a first frequency control code corresponding to the first frequency-locked clock signal, including: Obtain the first difference between the count value and the target count value, wherein the count value is the count value of the first frequency-locked clock signal within a preset time period; A first frequency control code corresponding to the first frequency-locked clock signal is generated based on the first difference.

18. The locking method according to claim 16, characterized in that, The second frequency-locked clock signal is frequency-calibrated to generate a second frequency control code corresponding to the second frequency-locked clock signal, including: Obtain a second difference between the frequency division ratio and the first target frequency division ratio, wherein the frequency division ratio is the frequency division ratio between the second frequency-locked clock signal and the reference clock signal; A second frequency control code corresponding to the second frequency-locked clock signal is generated based on the second difference.

19. The locking method according to claim 15, characterized in that, The method further includes: If frequency hopping occurs, the second target division ratio is obtained, and the division ratio is adjusted to be equal to the second target division ratio by adjusting the frequency control code to an approximate value of the target control code.

20. A clock signal locking device, characterized in that, include: A frequency locking module is used to process the frequency-locked clock signal output by the oscillation circuit through a frequency locking circuit to obtain a frequency control code corresponding to the frequency-locked clock signal, wherein the frequency control code is used to lock the frequency of the clock signal output by the oscillation circuit. A phase-locked module is used to process the phase-locked clock signal output by the oscillation circuit through a phase-locked circuit to generate a phase control code corresponding to the phase-locked clock signal, wherein the phase control code is used to phase-lock the clock signal output by the oscillation circuit.

21. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of claims 15-19.

22. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 15-19.

23. A chip comprising the phase-locked loop according to any one of claims 1-14.

24. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method according to any one of claims 15-19.

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