Clock frequency correction method and apparatus, communication device, medium and program product

Abstract

This application relates to a clock frequency correction method, apparatus, communication device, medium, and program product. The method includes: the communication device comprising a first chip and a second chip, wherein the first chip and the second chip share the same crystal oscillator to provide a reference frequency; at a current trigger moment, in response to detecting a trigger signal for a counter synchronization latch unit in the first chip, acquiring a first current count value of the first counter in the first chip at the current trigger moment and a second current count value of the second counter in the second chip at the current trigger moment; determining a frequency adjustment amount for a first phase-locked loop (PLL) in the first chip based on the first current count value, the second current count value, a first previous count value of the first counter at the previous trigger moment, and a second previous count value of the second counter at the previous trigger moment; and correcting the clock frequency of the PLL based on the frequency adjustment amount. This method can eliminate inter-chip clock asynchronous deviations.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a clock frequency correction method, apparatus, communication equipment, medium, and program product. Background Technology

[0002] In multi-chip communication hardware architectures, a dual-chip collaborative working mode is often used to realize functions such as communication transmission and reception, baseband processing, and radio frequency control. To ensure timing matching between the two chips, a single crystal oscillator is commonly used to provide a unified reference clock. The first and second chips each have independent counters and phase-locked loops (PLLs), relying on the same crystal oscillator to achieve clock synchronization. The counter continuously accumulates counts with the clock pulses output by the PLL, and the change in the count value can represent the actual operating frequency of the clock. This is often used in scenarios such as inter-chip timing alignment, data packet timing verification, and communication frame time slot synchronization.

[0003] The normal operating logic is as follows: the two chips generate their own working clocks based on the same crystal oscillator frequency division, the counters count with the local clock, and the system triggers the latching of the two counters at a preset fixed period. Relying on the natural consistency of the same clock, the count increments of the two chips are basically equal, and there is no need to dynamically adjust the PLL.

[0004] However, crystal oscillators have initial tolerance, temperature drift, and aging drift. Even if the first and second chips share a single crystal oscillator, inconsistencies exist in the frequency divider circuit, buffer path, trace delay, and gate circuit propagation delay within the chip's internal PLL. After the crystal oscillator's output reference frequency is multiplied and divided by the internal circuits of the two chips, the actual clock frequency supplied to the counter will have a slight deviation. Under long-term operation, the difference in the count increment per cycle between the two counters accumulates continuously, and the timing offset between the chips continues to increase, causing communication frame time slot misalignment, baseband and RF timing mismatch, and increased bit errors in high-speed interfaces (MIPI, SerDes). Summary of the Invention

[0005] Therefore, it is necessary to provide a clock frequency correction method, apparatus, communication equipment, medium, and program product to address the aforementioned technical problems.

[0006] In a first aspect, this application provides a clock frequency correction method applied to a communication device; the communication device includes a first chip and a second chip, and the first chip and the second chip share the same crystal oscillator to provide a reference frequency; including:

[0007] At the current triggering moment, in response to detecting a trigger signal for the counter synchronization latching unit in the first chip, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current triggering moment are obtained; wherein, the trigger signal is used to instruct the counter synchronization latching unit to synchronously latch the first counter and the second counter;

[0008] Based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip;

[0009] The clock frequency of the phase-locked loop is corrected according to the frequency adjustment amount.

[0010] In one embodiment, determining the frequency adjustment amount for the first phase-locked loop in the first chip based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time includes:

[0011] The first count change amount is determined based on the difference between the first current count value and the first previous count value of the first counter at the previous trigger time;

[0012] The second count change is determined based on the difference between the second current count value and the second previous count value of the second counter at the previous trigger time;

[0013] Based on the first count change, the second count change, the first current count value, and the second current count value, determine the frequency adjustment amount for the first phase-locked loop in the first chip.

[0014] In one embodiment, determining the frequency adjustment amount for the first phase-locked loop in the first chip based on the first count change, the second count change, the first current count value, and the second current count value includes:

[0015] Determine a first numerical relationship between the first count change and the second count change, and a second numerical relationship between the first current count value and the second current count value;

[0016] Based on the first numerical relationship and the second numerical relationship, the frequency adjustment amount for the first phase-locked loop in the first chip is determined.

[0017] In one embodiment, determining the frequency adjustment amount for the first phase-locked loop in the first chip based on the first numerical relationship and the second numerical relationship includes:

[0018] In response to the first numerical relationship indicating that the first count change is greater than the second count change, and the second numerical relationship indicating that the first current count value is greater than the second current count value, or in response to the first numerical relationship indicating that the first count change is less than the second count change, and the second numerical relationship indicating that the first current count value is less than the second current count value, the frequency adjustment amount for the first phase-locked loop in the first chip is determined as the target difference.

[0019] The target difference is the difference between the first count change and the second count change.

[0020] In one embodiment, correcting the clock frequency of the first phase-locked loop in the first chip according to the frequency adjustment amount includes:

[0021] In response to the first numerical relationship indicating that the first count change is greater than the second count change, the clock frequency of the first phase-locked loop is increased according to the frequency adjustment amount;

[0022] In response to the first numerical relationship indicating that the first count change is less than the second count change, the clock frequency of the first phase-locked loop is reduced according to the frequency adjustment amount.

[0023] In one embodiment, the time interval between two adjacent different trigger times is determined in the following way:

[0024] Obtain the first digital quantization error of the first phase-locked loop and the second digital quantization error of the second phase-locked loop in the second chip;

[0025] The total quantization error is determined based on the sum of the first digital quantization error and the second digital quantization error;

[0026] Based on the totalized error, the time interval between two adjacent different trigger times is determined.

[0027] Secondly, this application also provides a clock frequency correction device configured in a communication device, the communication device including a first chip and a second chip, wherein the first chip and the second chip share the same crystal oscillator to provide a reference frequency; including:

[0028] The value acquisition module is configured to, at the current trigger moment, in response to detecting a trigger signal for the counter synchronization latch unit in the first chip, acquire a first current count value of the first counter in the first chip and a second current count value of the second counter in the second chip at the current trigger moment; wherein, the trigger signal is used to instruct the counter synchronization latch unit to synchronously latch the first counter and the second counter;

[0029] The adjustment determination module is used to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time.

[0030] The frequency correction module is used to correct the clock frequency of the phase-locked loop according to the frequency adjustment amount.

[0031] Thirdly, this application also provides a communication device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0032] At the current triggering moment, in response to detecting a trigger signal for the counter synchronization latching unit in the first chip, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current triggering moment are obtained; wherein, the trigger signal is used to instruct the counter synchronization latching unit to synchronously latch the first counter and the second counter;

[0033] Based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip;

[0034] The clock frequency of the phase-locked loop is corrected according to the frequency adjustment amount.

[0035] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0036] At the current triggering moment, in response to detecting a trigger signal for the counter synchronization latching unit in the first chip, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current triggering moment are obtained; wherein, the trigger signal is used to instruct the counter synchronization latching unit to synchronously latch the first counter and the second counter;

[0037] Based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip;

[0038] The clock frequency of the phase-locked loop is corrected according to the frequency adjustment amount.

[0039] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, performs the following steps:

[0040] At the current triggering moment, in response to detecting a trigger signal for the counter synchronization latching unit in the first chip, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current triggering moment are obtained; wherein, the trigger signal is used to instruct the counter synchronization latching unit to synchronously latch the first counter and the second counter;

[0041] Based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip;

[0042] The clock frequency of the phase-locked loop is corrected according to the frequency adjustment amount.

[0043] The aforementioned clock frequency correction method, device, communication equipment, medium, and program products, based on a hardware synchronous latching mechanism, ensure that the count values ​​of the first counter and the second counter are collected within the exact same real time interval, eliminating sampling time difference errors caused by cross-chip transmission delays. They rely on the four sets of count values ​​from the current and previous rounds to obtain accurate clock pulse count differences. Based on the consistent counting relationship, they accurately calculate the real frequency offset of the first phase-locked loop, precisely quantifying the clock operating rate difference between the two chips. This allows for the calculation of the frequency adjustment amount adapted to the first phase-locked loop and the completion of clock frequency correction. This avoids counting errors caused by inconsistent reading times of the counters from different chips, eliminates asynchronous clock deviations between chips, and achieves high-precision clock synchronization between the two chips based on the actual measured operating time of the counters. Simultaneously, the entire process relies on a hardware counter latching mechanism to achieve timing acquisition, providing strong real-time performance without requiring complex software calculations. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a diagram illustrating the application environment of a clock frequency correction method in one embodiment.

[0046] Figure 2 This is a flowchart illustrating a clock frequency correction method in one embodiment;

[0047] Figure 3 This is a flowchart illustrating the process of determining the frequency adjustment amount of the first phase-locked loop in one embodiment.

[0048] Figure 4 A flowchart illustrating the frequency adjustment amount of the first phase-locked loop in another embodiment;

[0049] Figure 5 This is a flowchart illustrating the process of correcting the clock frequency of the first phase-locked loop in one embodiment.

[0050] Figure 6 This is a flowchart illustrating the process of determining the time interval between two adjacent different triggering times in one embodiment;

[0051] Figure 7 This is a flowchart illustrating a clock frequency correction method in another embodiment;

[0052] Figure 8 This is a structural block diagram of a clock frequency correction device in one embodiment;

[0053] Figure 9 This is an internal structure diagram of a communication device in one embodiment. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0055] The clock frequency correction method provided in this application embodiment can be applied to, for example, Figure 1 In the application environment shown, the first chip (Chip A) and the second chip (Chip B) together form a dual-chip communication hardware architecture. XO is a crystal oscillator that provides a reference frequency for both the first and second chips. PLL_A is the first phase-locked loop in the first chip, and PLL_B is the second phase-locked loop in the second chip. Both PLL_A and PLL_B receive the reference frequency of XO, perform frequency multiplication and division, and output the chip's original clock.

[0056] CG_A is the first clock gating unit in the first chip, used to receive the raw clock output from PLL_A, perform clock buffering, path selection, noise suppression, and output a stable counting clock to drive the first counter in the first chip. Correspondingly, CG_B is the second clock gating unit in the second chip, used to receive the raw clock output from PLL_B, perform clock buffering, path selection, noise suppression, and output a stable counting clock to drive the second counter in the second chip.

[0057] SW is the synchronization control unit. The SW in the first chip generates a global trigger signal, which is sent out in two ways: one is sent locally to CNT_latch, and the other is sent to the SW of the second chip via the uplink FIFO, so as to realize the synchronization of latching instructions between the two chips. CNT_latch is the counter synchronization latch unit, which is specifically used to latch the instantaneous count value of the first chip at the trigger moment to ensure that the count value does not continue to jump with the clock.

[0058] CNT_A is the first counter of the first chip, and CNT_B is the second counter of the second chip. The SW synchronous trigger signal of the first chip is simultaneously sent to CNT_latch and across chips to the second chip, so that the first chip and the second chip latch the readings at the same time, eliminating the sampling time difference error.

[0059] In one exemplary embodiment, such as Figure 2 As shown, a clock frequency correction method is provided. Taking the application of this method in a communication device as an example, the method includes the following steps:

[0060] S201, at the current trigger moment, in response to detecting a trigger signal for the counter synchronization latch unit in the first chip, the first current count value of the first counter in the first chip at the current trigger moment and the second current count value of the second counter in the second chip at the current trigger moment are obtained.

[0061] Among them, the current trigger time is the effective edge time of the global synchronization trigger signal, the precise time point of the first counter and the second counter with the same latch degree, and the time interval between the two trigger times is the unified real duration.

[0062] The trigger signal is a synchronization pulse command output by the synchronization control unit of the first chip. The trigger signal is used to instruct the counter synchronization latch unit to synchronously latch the first counter and the second counter. The first current count value is the count of the first counter latched at the current trigger time; the second current count value is the count of the second counter latched at the current trigger time.

[0063] Optionally, when the valid edge of the trigger signal arrives, the first chip's counter synchronization latch unit hardware latches the first counter, and simultaneously, across chips, the second chip hardware latches the second counter; furthermore, the two sets of latch registers are read to obtain the first current count value and the second current count value corresponding to the current trigger time.

[0064] It should be noted that the latching action is driven by hardware edges, rather than software sampling, to avoid timing deviations caused by software read latency.

[0065] For example, the rising edge of the trigger signal is used as latch enable, and the first and second counters are immediately latched at the hardware level. After latching, the first and second counters continue to run normally in the background, and the register readings no longer change. The two latch registers are read in parallel at one time through the bus to obtain two sets of current count values.

[0066] In this embodiment, when the triggering small signal is transmitted across chips via FIFO, it can be synchronized across clock domains to ensure that the latching edges of the second chip are aligned and there will be no time difference between the first chip latching first and the second chip latching later.

[0067] S202, based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip.

[0068] The first previous count value is the count of the first counter latched at the previous trigger moment; the second previous count value is the count of the second counter latched at the previous trigger moment. The frequency adjustment amount is quantized data obtained through numerical difference calculation, including the offset direction and offset magnitude, and is the basis for modifying the frequency configuration register of the first latch.

[0069] Optionally, the pulse increments of the first and second counters within the two trigger intervals can be used to calculate the ratio of the actual operating rates of the first and second chip clocks, compare it with the standard rate to obtain the clock deviation, and convert it into a frequency adjustment amount that the first phase-locked loop can recognize.

[0070] In this embodiment, the increment calculation formula is general: the first counter increment ΔN1 = the first current count value - the first previous count value; the second counter increment ΔN2 = the second current count value - the second previous count value; ΔN1 represents the total number of first chip clock pulses within the interval; ΔN2 represents the total number of second chip clock pulses within the same period.

[0071] For example, the clock rate ratio, i.e., the ratio between ΔN1 and ΔN2, can be calculated. The synchronization state is defined as a clock rate ratio of 1. A clock rate ratio > 1 indicates that the first chip clock is too fast, and a clock rate ratio < 1 indicates that the first chip clock is too slow. Further, the frequency deviation rate is calculated based on the difference between the clock rate ratio and the standard value of 1, and the frequency deviation rate is mapped to the frequency multiplication factor adjustment step size according to the first phase-locked loop register, thus generating the frequency adjustment amount.

[0072] S203 corrects the clock frequency of the phase-locked loop based on the frequency adjustment amount.

[0073] Optionally, the frequency adjustment amount can be written into the first phase-locked loop configuration register to modify the first phase-locked loop multiplication, division, and loop parameters, thereby completing the clock frequency pullback calibration.

[0074] In the aforementioned clock frequency correction method, the hardware synchronous latch mechanism ensures that the count values ​​of the first counter and the second counter are collected within the same real time interval, eliminating sampling time difference errors caused by cross-chip transmission delay. It obtains accurate clock pulse count differences based on the four sets of count values ​​from the current and previous rounds, and accurately calculates the real frequency offset of the first phase-locked loop based on the consistent counting relationship. This precisely quantifies the difference in clock operating rates between the two chips, thereby calculating the frequency adjustment amount suitable for the first phase-locked loop and completing the clock frequency correction. This avoids counting errors caused by inconsistent counter reading times from different chips, eliminates asynchronous clock deviations between chips, and achieves high-precision clock synchronization between the two chips based on the actual measured operating time of the counters. Simultaneously, the entire process relies on the hardware counter latch mechanism for timing acquisition, resulting in strong real-time performance without the need for complex software calculations.

[0075] Optionally, in an exemplary embodiment, such as Figure 3 As shown, a method for determining the frequency adjustment amount of a first phase-locked loop is provided, specifically including the following steps:

[0076] S301, determine the first count change amount based on the difference between the first current count value and the first previous count value of the first counter at the previous trigger time.

[0077] Among them, the first count change is the pulse increment accumulated by the first counter within the two trigger intervals, which represents the total number of clock pulses of the first chip during that time period.

[0078] Optionally, the time window of the two synchronous triggers can be used as a uniform duration, and the difference between the values ​​of the first counter latched in the current and previous rounds can be calculated to obtain the total number of clock pulses generated by the first chip within the window, i.e., the first count change; additionally, the overflow scenario can be adapted based on the bit width of the first counter to avoid the error in the difference calculation caused by the count returning to zero.

[0079] In an exemplary embodiment, a dedicated hardware hair-cutting logic circuit can be built inside the first chip to connect the first current count value and the second previous count value in parallel to the input of the subtractor. After the calculation is completed, the first technical change amount is directly latched into the hardware register.

[0080] In another exemplary embodiment, the CPU of the terminal can also read the first current count value and the first previous count value stored in the storage area, calculate the difference between the first current count value and the first previous count value of the first counter at the previous trigger time through the program, and output the first count change amount.

[0081] S302, determine the second count change amount based on the difference between the second current count value and the second previous count value of the second counter at the previous trigger time.

[0082] The second count change is the cumulative pulse increment of the second counter within the two trigger intervals, representing the total number of reference clock pulses during that time period.

[0083] Correspondingly, the same method as S301 can be used to determine the second count change.

[0084] S303, determine the frequency adjustment amount for the first phase-locked loop in the first chip based on the first count change amount, the second count change amount, the first current count value, and the second current count value.

[0085] Optionally, the first and second count changes can be used to characterize the total number of pulses in the two clock segments under the same duration to preliminarily determine the frequency deviation; additionally, the first and second current count values ​​are introduced for auxiliary verification to correct the errors caused by instantaneous count jitter, single trigger micro-hour timing deviation, and cumulative count drift, and to calculate the accurate frequency adjustment amount by comprehensively considering multi-dimensional parameters.

[0086] In this embodiment, the independent count changes of the two counters are obtained by performing difference calculations on the count values ​​at the trigger times before and after the trigger times. This accurately represents the actual cumulative number of clock pulses of the two chips within the same time interval. Not only can the difference in the clock running rates of the two sides be calculated based on the two sets of changes, but the two count values ​​at the current time are also introduced to help correct the calculation deviation caused by count overflow and instantaneous jitter. This makes the clock deviation judgment dimension more comprehensive, and the accuracy of the first phase-locked loop frequency adjustment calculated accordingly is higher.

[0087] Optionally, in an exemplary embodiment, such as Figure 4 As shown, a method for determining the frequency adjustment amount of a first phase-locked loop is provided, which specifically includes the following steps:

[0088] S401, determine a first numerical relationship between a first count change and a second count change, and a second numerical relationship between a first current count value and a second current count value.

[0089] The first numerical relationship is a quantitative mathematical relationship constructed from the first and second count changes, used to characterize the magnitude relationship between the first and second count changes. The second numerical relationship is a quantitative mathematical relationship constructed from the two absolute count values ​​at the current trigger moment, used to characterize the magnitude relationship between the two absolute count values.

[0090] Optionally, a first numerical relationship reflecting the dynamic difference between clock speed and slowness can be established based on the calculated two-way count increments; a second numerical relationship reflecting the static count offset can be established based on the instantaneous absolute count value of the synchronous latch.

[0091] In an optional embodiment, the first numerical relationship can be defined as a ratio-type numerical relationship, for example, the first numerical relationship First count change / Second count change This indicates that the change in the first count is greater than the change in the second count; This indicates that the change in the first count is less than the change in the second count; This indicates that the first change in count is equal to the second change in count.

[0092] In another alternative embodiment, the first numerical relationship can be defined as a difference-type numerical relationship, for example, the first numerical relationship First count change - Second count change This indicates that the change in the first count is greater than the change in the second count; This indicates that the change in the first count is less than the change in the second count; This indicates that the first change in count is equal to the second change in count.

[0093] Accordingly, the first numerical relationship can be determined using the method described above for determining the first numerical relationship.

[0094] S402, determine the frequency adjustment amount for the first phase-locked loop in the first chip based on the first numerical relationship and the second numerical relationship.

[0095] Optionally, the first numerical relationship can be used to determine the frequency deviation of the clock itself as the main calibration basis, and the second numerical relationship can be used as an auxiliary constraint and anomaly check to correct misjudgments caused by count overflow, single sampling jitter, and cumulative count offset, and output a precise and safe frequency adjustment amount.

[0096] In this embodiment, a first numerical relationship corresponding to the change in count and a second numerical relationship corresponding to the absolute count value at the current moment are constructed respectively. This can be combined with the rate difference of the clock pulse increment of the two chips within the same duration and the static offset of the absolute readings of the two counters at the moment of triggering to complete a dual-dimensional judgment. It can accurately characterize the dynamic frequency drift of the two chip clocks by relying on the first numerical relationship, and can also identify the cumulative count deviation of the counter, instantaneous sampling jitter, and count overflow critical anomaly by using the second numerical relationship, so as to realize the joint verification of dynamic frequency deviation and static count deviation.

[0097] Optionally, based on the above embodiments, in one optional embodiment, determining the frequency adjustment amount for the first phase-locked loop in the first chip according to the first numerical relationship and the second numerical relationship can be: in response to the first numerical relationship indicating that the first count change is greater than the second count change, and the second numerical relationship indicating that the first current count value is greater than the second current count value; or in response to the first numerical relationship indicating that the first count change is less than the second count change, and the second numerical relationship indicating that the first current count value is less than the second current count value, the frequency adjustment amount for the first phase-locked loop in the first chip is determined as a target difference; wherein, the target difference is the difference between the first count change and the second count change.

[0098] Specifically, the first numerical relationship (incremental magnitude trend) and the second numerical relationship (absolute count value trend) are judged separately. Only when the two trends are in the same direction are the deviations determined to be from the real clock frequency drift, and the difference between the first count change and the second count change is set as the frequency adjustment amount. If the two trends are opposite, the deviations are determined to be most likely caused by count overflow, random jitter, or instantaneous sampling error, and the calibration is abandoned and the phase-locked loop parameters are not updated.

[0099] Furthermore, if the first numerical relationship indicates that the change in the first count is greater than the change in the second count, and the second numerical relationship indicates that the first current count value is less than or equal to the second current count value, it means that the deviation is not caused by stable clock frequency drift, but is most likely caused by occasional factors such as count overflow, single sampling disturbance, and short-time pulse jitter. In this case, the frequency parameters of the first phase-locked loop are not adjusted, and the accumulated readings of the first counter and the second counter gradually converge over time.

[0100] Similarly, if the first numerical relationship indicates that the change in the first count is less than the change in the second count, and the second numerical relationship indicates that the first current count value is greater than or equal to the second current count value, then it proves that the deviation is not caused by stable clock frequency drift. It is more likely caused by occasional anomalies such as counter overflow, instantaneous count jitter caused by electromagnetic interference, metastability of single sampling, and bus transmission glitches. It does not belong to a real continuous clock offset. In this case, the frequency parameters of the first phase-locked loop are not adjusted, and the accumulated readings of the first and second counters gradually converge over time.

[0101] It is understandable that if the first numerical relationship indicates that the first count change is equal to the second count change, it means that there is no deviation between the first counter and the second counter, and in this case, it is also not necessary to adjust the frequency parameter of the first phase-locked loop.

[0102] In this embodiment, the difference between the two count changes is determined as the frequency adjustment amount of the phase-locked loop only when the trends of the first and second numerical relationships are in the same direction. When the relationship between the count increments is consistent with the relationship between the instantaneous absolute count values, it can be confirmed that the dual-chip counting deviation is dominated by the real clock frequency drift, eliminating the errors caused by count overflow, instantaneous random sampling jitter, and accidental count jumps, and avoiding incorrect frequency adjustment of the phase-locked loop caused by non-clock drift factors. Using the difference in count changes as the target difference to directly serve as the adjustment amount is simple and intuitive, without the need for complex floating-point operations. It can accurately complete the phase-locked loop frequency correction based on the real clock speed deviation, avoiding invalid calibration and reverse frequency adjustment problems under abnormal operating conditions, and reducing unnecessary frequent clock fluctuations.

[0103] Optionally, based on the above embodiments, in an exemplary embodiment, such as Figure 5 As shown, a clock frequency correction process for a first phase-locked loop is provided, which specifically includes the following steps:

[0104] S501, in response to the first numerical relationship indicating that the first count change is greater than the second count change, increases the clock frequency of the first phase-locked loop according to the frequency adjustment amount.

[0105] Optionally, a larger change in the first count indicates that the first chip outputs more clock pulses within the same duration, resulting in a faster clock speed. According to the preset closed-loop control logic, the first phase-locked loop is positively frequency-modulated based on the quantized frequency adjustment, thereby increasing the clock output frequency and reducing the rate deviation from the reference clock.

[0106] For example, the terminal CPU determines the value through software. After determining that the first numerical relationship indicates that the first count change is greater than the second count change, it reads the stored frequency adjustment amount. The frequency adjustment amount is added to the frequency multiplication parameter of the first phase-locked loop configuration register and written to the register through memory mapping. The phase-locked loop then increases the output clock frequency. A stepped frequency adjustment logic is added. If the adjustment amount is too large, it is split into multiple rounds of small upward adjustment to prevent instantaneous frequency changes from causing peripheral malfunctions.

[0107] S502, in response to the first numerical relationship indicating that the first count change is less than the second count change, reduces the clock frequency of the first phase-locked loop according to the frequency adjustment amount.

[0108] Optionally, a smaller change in the first count indicates fewer clock pulses from the first chip within the same duration, resulting in a slower clock speed. Based on the closed-loop reverse adjustment approach, the frequency adjustment is used to negatively modulate the phase-locked loop, reducing the clock operating frequency and narrowing the speed difference with the reference clock.

[0109] For example, the terminal CPU determines the value through software. After determining that the first numerical relationship indicates that the first count change is less than the second count change, it reads the stored frequency adjustment amount. The frequency adjustment amount is subtracted from the multiplication parameter of the first phase-locked loop configuration register and written to the register through memory mapping. The phase-locked loop then increases the output clock frequency. A stepped frequency adjustment logic is added. If the adjustment amount is too large, it is split into multiple rounds of small upward adjustment to prevent instantaneous frequency changes from causing peripheral malfunctions.

[0110] In this embodiment, the speed of the first chip clock is distinguished based on the relationship between the first count change and the second count change. When the first count change is larger and the clock runs faster, the phase-locked loop clock frequency is increased based on the frequency adjustment amount. When the first count change is smaller and the clock runs slower, the phase-locked loop clock frequency is decreased. This achieves a precise correspondence between the clock deviation direction and the frequency adjustment action, forming a closed-loop reverse adjustment logic.

[0111] Optionally, in an exemplary embodiment, to ensure the reasonableness of the time interval setting between two adjacent different trigger times, such as... Figure 6 As shown, a method for determining the time interval between two adjacent different trigger times is provided, specifically including the following steps:

[0112] S601, obtain the first digital quantization error of the first phase-locked loop and the second digital quantization error of the second phase-locked loop in the second chip.

[0113] The first digital quantization error is the quantized value of the digital phase / frequency deviation generated in the first phase-locked loop due to digital frequency division, fractional frequency division, ADC quantization, and discrete register configuration. It is a readable digital quantity and represents the inherent quantization jitter error of the first chip clock itself. The second digital quantization error is the quantized value of the digital phase / frequency deviation generated in the second phase-locked loop due to digital frequency division, fractional frequency division, ADC quantization, and discrete register configuration. It is a readable digital quantity and represents the inherent quantization jitter error of the second chip clock itself.

[0114] Optionally, the digital quantization error values ​​of the first phase-locked loop and the second phase-locked loop outputs can be read separately. The quantization error is the standardized digital deviation of the outputs of the phase-locked loop loop filter and the fractional divider, representing the degree of frequency and phase jitter caused by digital discretization of their respective clocks.

[0115] S602, determine the total quantization error based on the sum of the first digital quantization error and the second digital quantization error.

[0116] Among them, the total quantization error is the sum of the first digital quantization error and the second digital quantization error. It represents the total quantization deviation level after the clock system of the first chip and the second chip is superimposed, and is the core basis for trigger interval adjustment.

[0117] Optionally, the first digital quantization error and the second digital quantization error can be added together to superimpose the quantization deviation of the dual-end clock, thus characterizing the total quantization disturbance level of the entire dual-chip clock system.

[0118] For example, the terminal CPU reads the first digital quantization error and the second digital quantization error, performs an addition operation, and stores the total quantization error into the memory cache.

[0119] S603, based on the total quantification error, determines the time interval between two adjacent different trigger times.

[0120] The adjacent trigger time interval is the time length of the synchronous latch trigger signal issued by the counter twice, which is the sampling period of the clock calibration, and is adaptively adjusted according to the magnitude of the total quantitative error.

[0121] Optionally, the larger the total quantization error, the more severe the overall quantization jitter of the dual clocks, requiring a shorter trigger interval and increased calibration frequency to correct the jitter in a timely manner; the smaller the total quantization error, the more stable the clock quantization noise, allowing for a longer trigger interval and reducing the hardware overhead caused by frequent calibration.

[0122] For example, floating-point division can be used to calculate the time interval between two adjacent different trigger times. For instance:

[0123]

[0124] in, , This is the total quantification error; For time intervals.

[0125] In this embodiment, the digital quantization errors of the two phase-locked loops are collected simultaneously and superimposed to obtain a total quantization error that can characterize the overall discrete jitter level of the entire dual-chip clock. This allows for dynamic adaptive adjustment of the time interval between adjacent triggering moments. The judgment is based on the native quantization parameters of the phase-locked loops, ensuring that the source of the error closely matches the actual cause of clock jitter. The interval adjustment logic precisely matches the clock noise conditions, balancing the timeliness of calibration during periods of severe clock jitter with the low hardware load during periods of stable clock operation.

[0126] Figure 7 This is a flowchart illustrating a clock frequency correction method in another embodiment. Based on the above embodiments, this embodiment provides an optional example of a clock frequency correction method. (Combined with...) Figure 7 The specific implementation process is as follows:

[0127] S701, at the current trigger moment, in response to detecting a trigger signal for the counter synchronization latch unit in the first chip, the first current count value of the first counter in the first chip at the current trigger moment and the second current count value of the second counter in the second chip at the current trigger moment are obtained.

[0128] The trigger signal is used to instruct the counter synchronization latch unit to synchronously latch the first counter and the second counter.

[0129] S702, determine the first count change amount based on the difference between the first current count value and the first previous count value of the first counter at the previous trigger time.

[0130] S703, determine the second count change amount based on the difference between the second current count value and the second previous count value of the second counter at the previous trigger time.

[0131] S704, determine a first numerical relationship between a first count change and a second count change, and a second numerical relationship between a first current count value and a second current count value.

[0132] S705, in response to a first numerical relationship indicating that the first count change is greater than the second count change and the second numerical relationship indicating that the first current count value is greater than the second current count value, or in response to a first numerical relationship indicating that the first count change is less than the second count change and the second numerical relationship indicating that the first current count value is less than the second current count value, the frequency adjustment amount for the first phase-locked loop in the first chip is determined as the target difference.

[0133] The target difference is the difference between the first count change and the second count change.

[0134] S706, in response to the first numerical relationship indicating that the first count change is greater than the second count change, increases the clock frequency of the first phase-locked loop according to the frequency adjustment amount.

[0135] S707, in response to the first numerical relationship indicating that the first count change is less than the second count change, reduces the clock frequency of the first phase-locked loop according to the frequency adjustment amount.

[0136] The specific processes of S701-S707 described above can be found in the description of the above method embodiments. Their implementation principles and technical effects are similar, and will not be repeated here.

[0137] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0138] Based on the same inventive concept, this application also provides a clock frequency correction device for implementing the clock frequency correction method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more clock frequency correction device embodiments provided below can be found in the limitations of the clock frequency correction method described above, and will not be repeated here.

[0139] In one exemplary embodiment, such as Figure 8As shown, a clock frequency correction device 800 is provided, configured in a communication device. The communication device includes a first chip and a second chip, and the first chip and the second chip share the same crystal oscillator to provide a reference frequency. The device includes: a value acquisition module 810, an adjustment determination module 820, and a frequency correction module 830, wherein:

[0140] The value acquisition module 810 is used to acquire, at the current trigger time, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current trigger time in response to the detection of a trigger signal for the counter synchronization latch unit in the first chip; wherein the trigger signal is used to instruct the counter synchronization latch unit to synchronously latch the first counter and the second counter.

[0141] The adjustment determination module 820 is used to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time.

[0142] The frequency correction module 830 is used to correct the clock frequency of the phase-locked loop according to the frequency adjustment amount.

[0143] In one embodiment, the adjustment determination module 820 includes:

[0144] The first determining unit is used to determine the first count change amount based on the difference between the first current count value and the first previous count value of the first counter at the previous trigger time;

[0145] The second determining unit is used to determine the second count change amount based on the difference between the second current count value and the second previous count value of the second counter at the previous trigger time;

[0146] The third determining unit is used to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on the first count change amount, the second count change amount, the first current count value, and the second current count value.

[0147] In one embodiment, the third determining unit includes:

[0148] The first determining unit is used to determine a first numerical relationship between a first count change and a second count change, and a second numerical relationship between a first current count value and a second current count value;

[0149] The second determining unit is used to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on the first numerical relationship and the second numerical relationship.

[0150] In one embodiment, the second determination from the unit is specifically used for:

[0151] In response to a first numerical relationship indicating that the first count change is greater than the second count change, and a second numerical relationship indicating that the first current count value is greater than the second current count value, or in response to a first numerical relationship indicating that the first count change is less than the second count change, and a second numerical relationship indicating that the first current count value is less than the second current count value, the frequency adjustment amount for the first phase-locked loop in the first chip is determined as a target difference; wherein the target difference is the difference between the first count change and the second count change.

[0152] In one embodiment, the frequency correction module 830 is further configured to:

[0153] In response to a first numerical relationship indicating that the first count change is greater than the second count change, the clock frequency of the first phase-locked loop is increased according to the frequency adjustment amount; in response to a first numerical relationship indicating that the first count change is less than the second count change, the clock frequency of the first phase-locked loop is decreased according to the frequency adjustment amount.

[0154] In one embodiment, the clock frequency correction device 800 further includes an interval determination module, used for:

[0155] Obtain the first digital quantization error of the first phase-locked loop and the second digital quantization error of the second phase-locked loop in the second chip; determine the total quantization error based on the sum of the first and second digital quantization errors; determine the time interval between two adjacent different trigger times based on the total quantization error.

[0156] Each module in the aforementioned clock frequency correction device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of the communication device in hardware form or independent of it, or stored in the memory of the communication device in software form, so that the processor can call and execute the corresponding operations of each module.

[0157] In one embodiment, a communication device is provided, the internal structure of which can be shown as follows: Figure 9As shown, the communication device includes a processor, memory, communication interface, display screen, and input device connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a clock frequency correction method.

[0158] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the communication device to which the present application is applied. Specific communication devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0159] In one exemplary embodiment, a communication device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to perform the following steps:

[0160] At the current triggering moment, in response to detecting a trigger signal for the counter synchronization latching unit in the first chip, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current triggering moment are obtained; wherein, the trigger signal is used to instruct the counter synchronization latching unit to synchronously latch the first counter and the second counter;

[0161] Based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip;

[0162] The clock frequency of the phase-locked loop is corrected based on the frequency adjustment amount.

[0163] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first current count value, a second current count value, a first previous count value of the first counter at the previous trigger time, and a second previous count value of the second counter at the previous trigger time, the processor further performs the following steps:

[0164] A first count change is determined based on the difference between the first current count value and the first previous count value of the first counter at the previous trigger moment; a second count change is determined based on the difference between the second current count value and the second previous count value of the second counter at the previous trigger moment; and a frequency adjustment amount for the first phase-locked loop in the first chip is determined based on the first count change, the second count change, the first current count value, and the second current count value.

[0165] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first count change, a second count change, a first current count value, and a second current count value, it further performs the following steps:

[0166] Determine a first numerical relationship between a first count change and a second count change, and a second numerical relationship between a first current count value and a second current count value; based on the first and second numerical relationships, determine the frequency adjustment amount for the first phase-locked loop in the first chip.

[0167] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first numerical relationship and a second numerical relationship, it also performs the following steps:

[0168] In response to a first numerical relationship indicating that the first count change is greater than the second count change, and a second numerical relationship indicating that the first current count value is greater than the second current count value, or in response to a first numerical relationship indicating that the first count change is less than the second count change, and a second numerical relationship indicating that the first current count value is less than the second current count value, the frequency adjustment amount for the first phase-locked loop in the first chip is determined as a target difference; wherein the target difference is the difference between the first count change and the second count change.

[0169] In one embodiment, when the processor executes a computer program to correct the clock frequency of the first phase-locked loop in the first chip according to the frequency adjustment amount, it also performs the following steps:

[0170] In response to a first numerical relationship indicating that the first count change is greater than the second count change, the clock frequency of the first phase-locked loop is increased according to the frequency adjustment amount; in response to a first numerical relationship indicating that the first count change is less than the second count change, the clock frequency of the first phase-locked loop is decreased according to the frequency adjustment amount.

[0171] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0172] Obtain the first digital quantization error of the first phase-locked loop and the second digital quantization error of the second phase-locked loop in the second chip; determine the total quantization error based on the sum of the first and second digital quantization errors; determine the time interval between two adjacent different trigger times based on the total quantization error.

[0173] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0174] At the current triggering moment, in response to detecting a trigger signal for the counter synchronization latching unit in the first chip, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current triggering moment are obtained; wherein, the trigger signal is used to instruct the counter synchronization latching unit to synchronously latch the first counter and the second counter;

[0175] Based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip;

[0176] The clock frequency of the phase-locked loop is corrected based on the frequency adjustment amount.

[0177] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first current count value, a second current count value, a first previous count value of the first counter at the previous trigger time, and a second previous count value of the second counter at the previous trigger time, the processor further performs the following steps:

[0178] A first count change is determined based on the difference between the first current count value and the first previous count value of the first counter at the previous trigger moment; a second count change is determined based on the difference between the second current count value and the second previous count value of the second counter at the previous trigger moment; and a frequency adjustment amount for the first phase-locked loop in the first chip is determined based on the first count change, the second count change, the first current count value, and the second current count value.

[0179] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first count change, a second count change, a first current count value, and a second current count value, it further performs the following steps:

[0180] Determine a first numerical relationship between a first count change and a second count change, and a second numerical relationship between a first current count value and a second current count value; based on the first and second numerical relationships, determine the frequency adjustment amount for the first phase-locked loop in the first chip.

[0181] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first numerical relationship and a second numerical relationship, it also performs the following steps:

[0182] In response to a first numerical relationship indicating that the first count change is greater than the second count change, and a second numerical relationship indicating that the first current count value is greater than the second current count value, or in response to a first numerical relationship indicating that the first count change is less than the second count change, and a second numerical relationship indicating that the first current count value is less than the second current count value, the frequency adjustment amount for the first phase-locked loop in the first chip is determined as a target difference; wherein the target difference is the difference between the first count change and the second count change.

[0183] In one embodiment, when the processor executes a computer program to correct the clock frequency of the first phase-locked loop in the first chip according to the frequency adjustment amount, it also performs the following steps:

[0184] In response to a first numerical relationship indicating that the first count change is greater than the second count change, the clock frequency of the first phase-locked loop is increased according to the frequency adjustment amount; in response to a first numerical relationship indicating that the first count change is less than the second count change, the clock frequency of the first phase-locked loop is decreased according to the frequency adjustment amount.

[0185] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0186] Obtain the first digital quantization error of the first phase-locked loop and the second digital quantization error of the second phase-locked loop in the second chip; determine the total quantization error based on the sum of the first and second digital quantization errors; determine the time interval between two adjacent different trigger times based on the total quantization error.

[0187] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps:

[0188] At the current triggering moment, in response to detecting a trigger signal for the counter synchronization latching unit in the first chip, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current triggering moment are obtained; wherein, the trigger signal is used to instruct the counter synchronization latching unit to synchronously latch the first counter and the second counter;

[0189] Based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip;

[0190] The clock frequency of the phase-locked loop is corrected based on the frequency adjustment amount.

[0191] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first current count value, a second current count value, a first previous count value of the first counter at the previous trigger time, and a second previous count value of the second counter at the previous trigger time, the processor further performs the following steps:

[0192] A first count change is determined based on the difference between the first current count value and the first previous count value of the first counter at the previous trigger moment; a second count change is determined based on the difference between the second current count value and the second previous count value of the second counter at the previous trigger moment; and a frequency adjustment amount for the first phase-locked loop in the first chip is determined based on the first count change, the second count change, the first current count value, and the second current count value.

[0193] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first count change, a second count change, a first current count value, and a second current count value, it further performs the following steps:

[0194] Determine a first numerical relationship between a first count change and a second count change, and a second numerical relationship between a first current count value and a second current count value; based on the first and second numerical relationships, determine the frequency adjustment amount for the first phase-locked loop in the first chip.

[0195] In one embodiment, when the processor executes a computer program to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on a first numerical relationship and a second numerical relationship, it also performs the following steps:

[0196] In response to a first numerical relationship indicating that the first count change is greater than the second count change, and a second numerical relationship indicating that the first current count value is greater than the second current count value, or in response to a first numerical relationship indicating that the first count change is less than the second count change, and a second numerical relationship indicating that the first current count value is less than the second current count value, the frequency adjustment amount for the first phase-locked loop in the first chip is determined as a target difference; wherein the target difference is the difference between the first count change and the second count change.

[0197] In one embodiment, when the processor executes a computer program to correct the clock frequency of the first phase-locked loop in the first chip according to the frequency adjustment amount, it also performs the following steps:

[0198] In response to a first numerical relationship indicating that the first count change is greater than the second count change, the clock frequency of the first phase-locked loop is increased according to the frequency adjustment amount; in response to a first numerical relationship indicating that the first count change is less than the second count change, the clock frequency of the first phase-locked loop is decreased according to the frequency adjustment amount.

[0199] In one embodiment, the processor, when executing a computer program, also performs the following steps:

[0200] Obtain the first digital quantization error of the first phase-locked loop and the second digital quantization error of the second phase-locked loop in the second chip; determine the total quantization error based on the sum of the first and second digital quantization errors; determine the time interval between two adjacent different trigger times based on the total quantization error.

[0201] It should be noted that the data involved in this application (including but not limited to data used for analysis, data stored, data displayed, etc.) are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0202] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0203] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0204] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A clock frequency correction method, characterized in that, Used in communication equipment; The communication device includes a first chip and a second chip, and the first chip and the second chip share the same crystal oscillator to provide a reference frequency; the method includes: At the current triggering moment, in response to detecting a trigger signal for the counter synchronization latching unit in the first chip, the first current count value of the first counter in the first chip and the second current count value of the second counter in the second chip at the current triggering moment are obtained; wherein, the trigger signal is used to instruct the counter synchronization latching unit to synchronously latch the first counter and the second counter; Based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time, determine the frequency adjustment amount for the first phase-locked loop in the first chip; The clock frequency of the phase-locked loop is corrected according to the frequency adjustment amount.

2. The method according to claim 1, characterized in that, The step of determining the frequency adjustment amount for the first phase-locked loop in the first chip based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time includes: The first count change amount is determined based on the difference between the first current count value and the first previous count value of the first counter at the previous trigger time; The second count change is determined based on the difference between the second current count value and the second previous count value of the second counter at the previous trigger time; Based on the first count change, the second count change, the first current count value, and the second current count value, determine the frequency adjustment amount for the first phase-locked loop in the first chip.

3. The method according to claim 2, characterized in that, The step of determining the frequency adjustment amount for the first phase-locked loop in the first chip based on the first count change, the second count change, the first current count value, and the second current count value includes: Determine a first numerical relationship between the first count change and the second count change, and a second numerical relationship between the first current count value and the second current count value; Based on the first numerical relationship and the second numerical relationship, the frequency adjustment amount for the first phase-locked loop in the first chip is determined.

4. The method according to claim 3, characterized in that, The step of determining the frequency adjustment amount for the first phase-locked loop in the first chip based on the first numerical relationship and the second numerical relationship includes: In response to the first numerical relationship indicating that the first count change is greater than the second count change, and the second numerical relationship indicating that the first current count value is greater than the second current count value, or in response to the first numerical relationship indicating that the first count change is less than the second count change, and the second numerical relationship indicating that the first current count value is less than the second current count value, the frequency adjustment amount for the first phase-locked loop in the first chip is determined as the target difference. The target difference is the difference between the first count change and the second count change.

5. The method according to claim 4, characterized in that, The step of correcting the clock frequency of the first phase-locked loop in the first chip according to the frequency adjustment amount includes: In response to the first numerical relationship indicating that the first count change is greater than the second count change, the clock frequency of the first phase-locked loop is increased according to the frequency adjustment amount; In response to the first numerical relationship indicating that the first count change is less than the second count change, the clock frequency of the first phase-locked loop is reduced according to the frequency adjustment amount.

6. The method according to any one of claims 1-5, characterized in that, The time interval between two adjacent different trigger times is determined in the following way: Obtain the first digital quantization error of the first phase-locked loop and the second digital quantization error of the second phase-locked loop in the second chip; The total quantization error is determined based on the sum of the first digital quantization error and the second digital quantization error; Based on the totalized error, the time interval between two adjacent different trigger times is determined.

7. A clock frequency correction device, characterized in that, Configured in a communication device, the communication device including a first chip and a second chip, wherein the first chip and the second chip share the same crystal oscillator to provide a reference frequency; the device includes: The value acquisition module is configured to, at the current trigger moment, in response to detecting a trigger signal for the counter synchronization latch unit in the first chip, acquire a first current count value of the first counter in the first chip and a second current count value of the second counter in the second chip at the current trigger moment; wherein, the trigger signal is used to instruct the counter synchronization latch unit to synchronously latch the first counter and the second counter; The adjustment determination module is used to determine the frequency adjustment amount for the first phase-locked loop in the first chip based on the first current count value, the second current count value, the first previous count value of the first counter at the previous trigger time, and the second previous count value of the second counter at the previous trigger time. The frequency correction module is used to correct the clock frequency of the phase-locked loop according to the frequency adjustment amount.

8. A communication device, comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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