An ATE-based ADC multi-channel parallel test crosstalk suppression system and a suppression method thereof

Abstract

This invention discloses an ATE-based ADC multi-channel parallel test crosstalk suppression system, including an ATE test host, a clock synchronization and phase control module, a test signal source allocation module, a data acquisition module, a crosstalk modeling module, a crosstalk digital compensation module, and a channel isolation layout module connected to the ATE test host. This invention also discloses a suppression method for the ATE-based ADC multi-channel parallel test crosstalk suppression system, including steps such as S1, determining the minimum safe distance and shielding structure configuration between each test channel based on the physical layout parameters of each test channel on the multi-channel parallel test board through the channel isolation layout module. This invention can reduce parasitic capacitance coupling, common impedance coupling, and substrate coupling strength between channels from the source; achieve staggered sampling through the clock synchronization and phase control module to avoid instantaneous current surges when multiple channels are sampled simultaneously; and finally, accurately eliminate residual crosstalk through the crosstalk digital compensation module.

Description

Technical Field

[0001] This invention relates to the field of automated chip testing technology, specifically to an ATE-based ADC multi-channel parallel test crosstalk suppression system and its suppression method. Background Technology

[0002] With the widespread application of multi-channel ADCs (high-precision analog-to-digital converters) in phased array radar, 5G communication, and multi-channel data acquisition, higher demands are placed on the efficiency and accuracy of multi-channel parallel testing of ADC chips. In ATE (Automatic Test Equipment) testing scenarios, to improve test throughput and reduce the cost of testing a single chip, a multi-channel parallel testing strategy is typically adopted. This involves simultaneously connecting multiple ADC chips under test or different channels of multi-channel ADC chips to the same test board, sharing ATE test resources (such as test signal sources, clock sources, power supplies, etc.) for parallel stimulation and synchronous acquisition.

[0003] However, multi-channel parallel testing faces a significant technical challenge: inter-channel crosstalk. In high-density PCB layouts, non-ideal signal coupling can occur between analog signal lines in adjacent channels, between power distribution networks, and along substrate coupling paths. Specifically, when a channel (the interference source channel) transmits a large-amplitude test signal, this signal can couple to adjacent channels (the interfered channels) through parasitic capacitance, common impedance, or substrate coupling. This causes the test noise floor of the interfered channel to be raised, the signal-to-noise ratio to deteriorate, and ultimately, the measured results of ADC dynamic parameters (such as signal-to-noise ratio SNR and spurious-free dynamic range SFDR) to deviate from their true values.

[0004] Existing technologies for suppressing crosstalk in multi-channel ADCs mainly include the following categories: Firstly, there are crosstalk suppression schemes based on hardware isolation. These schemes reduce the coupling strength between channels at the physical level by increasing channel spacing, setting protective ground lines, using differential signal transmission, or adding shielding structures between channels. While these schemes can reduce crosstalk amplitude at the source, they are limited by the area constraints of the ATE test board and the physical layout of the probe cards / test sockets. Simple hardware isolation is insufficient to completely eliminate crosstalk, especially in high-density, multi-channel parallel testing scenarios, where the effectiveness of physical isolation has a significant ceiling.

[0005] Secondly, there is the time-interleaved sampling scheme. This scheme employs a time-interleaved sampling architecture, allowing each channel to sample at different times, thus avoiding crosstalk caused by multiple channels sampling simultaneously through a shared drive buffer or reference voltage network. This type of scheme can avoid the instantaneous large current surge coupling caused by simultaneous sampling, but it can only alleviate crosstalk at the sampling moment and is powerless against crosstalk paths such as continuous analog signal line coupling and power supply noise coupling between channels.

[0006] Thirdly, there are detection schemes based on crosstalk diagnosis. This approach diagnoses the presence and intensity of crosstalk by injecting known test signals into each channel during testing and detecting changes in the output of adjacent channels. While this type of scheme can achieve real-time diagnosis and location of crosstalk, it only reaches the "diagnosis" level and does not provide effective crosstalk cancellation or compensation methods.

[0007] Fourth, a calibration scheme based on mismatch compensation. This scheme compensates for gain mismatch, bias mismatch, and sampling time mismatch between channels in a time-interleaved ADC. This type of scheme mainly addresses mismatch errors between channels, rather than crosstalk coupling errors. The physical mechanisms of the two are different: mismatch errors originate from inconsistencies in the analog front-ends of each channel, while crosstalk errors originate from the mutual coupling of signals between channels.

[0008] In summary, there is currently a lack of a complete solution in the existing technology that can systematically solve the problem of crosstalk between channels in the multi-channel parallel testing of high-precision ADCs in ATE, so that it can reduce crosstalk at the source through isolation and timing design at the physical level, and eliminate the impact of residual crosstalk on test accuracy at the digital level through crosstalk modeling and post-compensation. Summary of the Invention

[0009] The purpose of this invention is to overcome the technical deficiency of existing methods in being unable to systematically solve the problem of inter-channel crosstalk in high-precision ADC multi-channel parallel testing using ATE, and to provide an ATE-based ADC multi-channel parallel testing crosstalk suppression system and its suppression method.

[0010] To achieve the above objectives, the present invention employs the following technical solution: a crosstalk suppression system for multi-channel parallel testing of an ATE-based ADC, comprising an ATE test host, a clock synchronization and phase control module, a test signal source allocation module, a data acquisition module, a crosstalk modeling module, a crosstalk digital compensation module, and a channel isolation layout module connected to the ATE test host, and a multi-channel parallel test board connected to the clock synchronization and phase control module, the test signal source allocation module, the data acquisition module, and the channel isolation layout module; the data acquisition module is also connected to the crosstalk digital compensation module and the crosstalk modeling module respectively, and the crosstalk digital compensation module is connected to the crosstalk modeling module.

[0011] Furthermore, the multi-channel parallel test board is equipped with M test channels, M≥2, and each test channel is used to connect to one input channel of an ADC chip under test or a multi-channel ADC chip.

[0012] The channel isolation layout module is used to determine the minimum safe distance between each test channel based on the physical layout parameters of each test channel on the multi-channel parallel test board.

[0013] The constraint condition for the minimum safety distance is: Where i and j are the indices of any two different channels, and the values ​​of i and j are 1, 2, 3, ..., M respectively; M is the total number of test channels; Let be the crosstalk coupling coefficient between channel i and channel j. This is the preset threshold for the crosstalk coupling coefficient.

[0014] The clock synchronization and phase control module independently adjusts the sampling clock phase of each channel to satisfy the following: the time interval ΔT between the sampling times of adjacent channels satisfies the following condition. Where Ts is the sampling period, M is the total number of test channels, and M≥2; This is the fine-tuning phase offset for the i-th channel, used to compensate for the differences in setup time of the analog front-end for each channel; The sampling period.

[0015] A method for suppressing crosstalk in an ATE-based multi-channel parallel test system for ADCs includes the following steps: S1. Based on the physical layout parameters of each test channel on the multi-channel parallel test board, the minimum safe distance and shielding structure configuration between each test channel are determined through the channel isolation layout module, and the signal traces of each test channel are arranged according to the minimum safe distance to reduce the electromagnetic coupling and substrate coupling strength between channels. S2, the clock synchronization and phase control module provides a common sampling clock to each test channel, and independently adjusts the sampling clock phase of each channel through a programmable delay unit, so that the sampling times of adjacent channels are staggered in time, and the time interval ΔT between the sampling times of adjacent channels satisfies ; S3. The crosstalk modeling module performs parametric modeling of the residual crosstalk, establishing the crosstalk transfer function matrix H; the crosstalk transfer function matrix H is an M×M matrix, where the diagonal elements... =1, off-diagonal element Let be the crosstalk transfer function from channel j to channel i; S4. The test signal source distribution module applies test excitation signals to each test channel according to the test configuration parameters, and the data acquisition module acquires the digital output code values ​​of each channel in parallel to obtain the measured output code value vector Y. S5. The crosstalk digital compensation module performs crosstalk cancellation compensation on the measured output code value vector Y based on the crosstalk transfer function matrix H, obtaining the compensated digital output code value vector. The calculation formula is as follows: ,in, This is the inverse matrix of the crosstalk transfer function matrix; S6, The ATE test host outputs a code value vector based on the compensated digital output. Calculate the static and dynamic parameters of the ADC under test for each test channel; S7. Repeat steps S4 to S6 until all test items have been measured.

[0016] The specific method for establishing the crosstalk transfer function matrix H in step S3 includes: S31. Select the p-th channel as the excitation channel and apply a known calibration test signal to the p-th channel. The input terminals of the remaining channels are connected to the reference level; S32. The data acquisition module acquires the digital output code values ​​of each channel in parallel, and records the coupling component generated by the excitation of the p-th channel in the output of the q-th channel (q≠p). ; S33. Calculate the crosstalk transfer function from the p-th channel to the q-th channel. ; S34. Repeat steps S31 to S33 to traverse all channel combinations and establish the complete crosstalk transfer function matrix H.

[0017] As a preferred method, the establishment and updating of the crosstalk transfer function matrix H is performed when the ATE test host is in an idle state, or during the calibration phase before the start of the test batch; when the test environment temperature changes beyond the preset temperature threshold, the recalibration of the crosstalk transfer function matrix H is automatically triggered.

[0018] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention sets minimum safety distance constraints at the physical level through the channel isolation layout module, thereby reducing the parasitic capacitance coupling, common impedance coupling and substrate coupling strength between channels from the source; the clock synchronization and phase control module realizes staggered sampling to avoid instantaneous current impact when multiple channels are sampled at the same time; and finally, the crosstalk digital compensation module accurately eliminates residual crosstalk.

[0019] (2) By traversing all channel combinations for calibration testing, the present invention establishes a complete M×M crosstalk transfer function matrix H. This crosstalk transfer function matrix H contains both amplitude attenuation and phase shift information, which can comprehensively reflect the crosstalk coupling path and transfer characteristics between channels in a multi-channel parallel test system, providing accurate quantitative basis for subsequent digital domain accurate compensation.

[0020] (3) Based on the crosstalk transfer function matrix H, this invention, through The matrix inversion operation is used to accurately reconstruct the true signal of each channel from the measured output vector Y containing crosstalk. Under the condition that physical isolation and timing interleaving have controlled the crosstalk coefficient to a low level, H is a strictly diagonally dominated matrix, and the inversion operation converges stably. This method does not depend on specific crosstalk physical mechanisms and has a unified compensation effect on various crosstalk paths such as capacitive coupling, inductive coupling, and common impedance coupling. It has strong versatility and effectively avoids the cumbersome nature of traditional schemes that require different suppression measures for different crosstalk sources. Attached Figure Description

[0021] Figure 1 This is a system structure block diagram of the present invention.

[0022] Figure 2 This is a schematic diagram of the suppression method of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example

[0024] like Figure 1 As shown, the ATE test host, as the core control and data aggregation center of this system, is connected to the clock synchronization and phase control module, the test signal source distribution module, the data acquisition module, the crosstalk modeling module, the crosstalk digital compensation module, and the channel isolation layout module, respectively. It is used to issue control commands to each module and receive test data.

[0025] The multi-channel parallel test board is simultaneously connected to a clock synchronization and phase control module, a test signal source distribution module, a data acquisition module, and a channel isolation layout module. Specifically, the test signal source distribution module provides the multi-channel parallel test board with M independent analog test excitation signals; the clock synchronization and phase control module provides the multi-channel parallel test board with M identical and phase-adjustable sampling clocks; the data acquisition module acquires the digital output code values ​​of each channel in parallel from the multi-channel parallel test board; and the channel isolation layout module provides the multi-channel parallel test board with a minimum safety spacing and shielding structure configuration scheme.

[0026] The data acquisition module is also connected to the crosstalk digital compensation module and the crosstalk modeling module respectively: the data acquisition module transmits the output code values ​​(including coupling components) of each channel during the calibration stage to the crosstalk modeling module, and transmits the measured output code value vector Y to the crosstalk digital compensation module.

[0027] The crosstalk digital compensation module is connected to the crosstalk modeling module: the crosstalk modeling module transmits the established crosstalk transfer function matrix H to the crosstalk digital compensation module.

[0028] The multi-channel parallel test board serves as the physical layer platform for this system, and it is equipped with M test channels (M≥2). Each test channel is used to connect to one input channel of an ADC chip under test or a multi-channel ADC chip. This test board simultaneously provides the physical connections for analog signal input, sampling clock input, and digital code value output.

[0029] The test signal source distribution module includes a shared arbitrary waveform generator core and M independent signal conditioning and distribution channels. The input of the test signal source distribution module is connected to the ATE test host to receive test excitation configuration instructions, and its output is connected to the analog signal input of the M test channels on the multi-channel parallel test board, which is used to independently provide programmable analog test excitation signals (ramp signals or sine wave signals) to each test channel.

[0030] The input of the clock synchronization and phase control module is connected to the ATE test host to receive the sampling frequency fs and the phase offset of each channel. The configuration parameters are set, and the output terminals are respectively connected to the sampling clock input terminals of M test channels on the multi-channel parallel test board, which are used to provide sampling clocks of the same source and with independently adjustable phases to each channel.

[0031] The clock synchronization and phase control module independently adjusts the sampling clock phase of each channel to meet the time interval between sampling times of adjacent channels. This module staggers the sampling times of adjacent channels in time, allowing M test channels to complete sampling sequentially within a single sampling period Ts. The core purpose of this time-interleaved sampling is to avoid common impedance coupling caused by instantaneous large current surges when multiple channels sample simultaneously, rather than aiming to increase the equivalent sampling rate as in traditional time-interleaved ADCs. This is one of the key methods for suppressing crosstalk at its source in this invention. The time interval between sampling times of adjacent channels. The sampling period is M, and the total number of test channels is M. This represents the fine-tuning phase offset of the i-th channel.

[0032] The input terminals of the data acquisition module are respectively connected to the ATE test host (to transmit the digital code values ​​of each channel) and the digital output terminals of each channel of the multi-channel parallel test board. Its output terminals are respectively connected to the ATE test host, the crosstalk modeling module (to transmit the output code values ​​of each channel containing coupling components during the calibration stage), and the crosstalk digital compensation module to transmit the measured output code value vector Y.

[0033] The input of the channel isolation layout module is connected to the ATE test host to receive PCB layout parameters, and its output is connected to the multi-channel parallel test board to output the minimum safety clearance and shielding structure configuration scheme, which is used to guide the physical layout of the multi-channel parallel test board. The minimum safety clearance output by the channel isolation layout module satisfies the following constraints: Where i and j are the indices of any two different channels, i,j=1,2,3,…,M, and M is the total number of test channels; Let be the crosstalk coupling coefficient between channel i and channel j. A preset crosstalk coupling coefficient threshold is used. In this embodiment, this crosstalk coupling coefficient... It is determined by the interchannel parasitic capacitance, the common power supply impedance, and the substrate coupling impedance. Right now ,in, This represents the parasitic capacitance coupling component between the i-th and j-th channel signal lines. The impedance coupling component of the power / ground network shared by channel i and channel j. This represents the coupling component between the i-th channel and the j-th channel through the semiconductor substrate.

[0034] The input terminals of the crosstalk modeling module are respectively connected to the ATE test host (receiving the calibration start command), the data acquisition module (receiving the output code values ​​of each channel containing coupling components during the calibration stage), and the crosstalk digital compensation module (receiving the recalibration trigger signal via the crosstalk compensation verification module). Its output terminal is connected to the crosstalk digital compensation module to transmit the established crosstalk transfer function matrix H.

[0035] The input terminals of the crosstalk digital compensation module are respectively connected to the ATE test host (receiving compensation enable / bypass commands), the data acquisition module (receiving the measured output code value vector Y), and the crosstalk modeling module (receiving the crosstalk transfer function matrix H), and the output terminal is connected to the ATE test host (outputting the compensated digital output code value vector). ).

[0036] The specific compensation method of this crosstalk digital compensation module is as follows: During operation, the digital output code values ​​of the M channels acquired in parallel by the data acquisition module constitute a vector. ,in Let be the measured output code value of the i-th channel; let the actual signals of each channel form a vector. If the crosstalk transfer function matrix is ​​H, then the measured output and the real signal must satisfy the following condition: , where N is the noise vector.

[0037] The crosstalk digital compensation module obtains an estimate of the true signal through matrix inversion: Finally, The compensated digital output code value vector is output to the ATE test host.

[0038] With physical isolation and timing interleaving controlling the crosstalk coefficient to a low level, the crosstalk transfer function matrix H is a strictly diagonally dominant matrix, and its inversion operation converges stably. This compensation method does not depend on specific crosstalk physical mechanisms and has a uniform compensation effect on various crosstalk paths such as capacitive coupling, inductive coupling, and common impedance coupling. Example

[0039] like Figure 2 As shown, this embodiment is a suppression method implemented based on the system described in Embodiment 1, and its specific steps are as follows: S1. Based on the physical layout parameters of each test channel on the multi-channel parallel test board, determine the minimum safe distance and shielding structure configuration between each test channel through the channel isolation layout module, and arrange the signal traces of each test channel according to the minimum safe distance to reduce the electromagnetic coupling and substrate coupling strength between channels.

[0040] S2, the clock synchronization and phase control module provides a common sampling clock to each test channel, and independently adjusts the sampling clock phase of each channel through a programmable delay unit, so that the sampling times of adjacent channels are staggered in time, and the time interval ΔT between the sampling times of adjacent channels satisfies .

[0041] S3. The crosstalk modeling module performs parametric modeling of the residual crosstalk, establishing the crosstalk transfer function matrix H; the crosstalk transfer function matrix H is an M×M matrix, where the diagonal elements... =1, off-diagonal element Let be the crosstalk transfer function from channel j to channel i.

[0042] The specific method for establishing the crosstalk transfer function matrix H in this crosstalk modeling module includes the following steps: S31. Select the p-th channel as the excitation channel and apply a known calibration test signal to the p-th channel. The input terminals of the remaining channels are connected to a reference level. This reference level is either analog ground AGND or common-mode voltage V. CM .

[0043] S32. The data acquisition module acquires the digital output code values ​​of each channel in parallel, and records the coupling component generated by the excitation of the p-th channel in the output of the q-th channel (q≠p). In this step, the coupling components The data was obtained through calibration testing and signal processing.

[0044] S33. Calculate the crosstalk transfer function from the p-th channel to the q-th channel. .in, and The ratio reflects the transfer coefficient of the p-th channel signal coupled to the q-th channel; The amplitude of the coupling component in the output of the q-th channel caused by the excitation of the p-th channel. The amplitude of the calibration test signal applied to the p-th channel.

[0045] S34. Repeat steps S31 to S33, traversing all channel combinations to establish the complete crosstalk transfer function matrix H. The expression for this crosstalk transfer function matrix H is: Among them, diagonal elements =1 indicates that the signal transmission coefficient of each channel is normalized to 1; off-diagonal elements Let be the crosstalk transfer function from channel j to channel i, which includes amplitude attenuation and phase shift information. Under the condition that physical isolation and timing interleaving have controlled the crosstalk coefficient to a low level, the off-diagonal elements satisfy | | << 1, which makes the crosstalk transfer function matrix H a strictly diagonally dominant matrix.

[0046] It should be noted that the establishment and updating of the crosstalk transfer function matrix H are both performed when the ATE test host is in an idle state, or during the calibration phase before the start of the test batch; when the test environment temperature changes beyond the preset temperature threshold, the recalibration of the crosstalk transfer function matrix H is automatically triggered.

[0047] S4. The test signal source distribution module applies test excitation signals to each test channel according to the test configuration parameters, and the data acquisition module acquires the digital output code values ​​of each channel in parallel to obtain the measured output code value vector Y.

[0048] S5. The crosstalk digital compensation module performs crosstalk cancellation compensation on the measured output code value vector Y based on the crosstalk transfer function matrix H, obtaining the compensated digital output code value vector. ,Should The calculation formula is: ,in, is the inverse of the crosstalk transfer function matrix.

[0049] S6, The ATE test host outputs a code value vector based on the compensated digital output. The static and dynamic parameters of the ADC under test for each test channel are calculated. The static parameters include differential nonlinearity (DNL), integral nonlinearity (INL), offset error, and gain error; the dynamic parameters include signal-to-noise ratio (SNR), signal-to-speaker ratio (SINAD), total harmonic distortion (THD), spurious-free dynamic range (SFDR), and effective number of bits (ENOB).

[0050] S7. Repeat steps S4 to S6 until all test items have been measured.

[0051] As described above, the present invention can be well implemented.

Claims

1. A crosstalk suppression system for multi-channel parallel testing of an ADC based on an ATE (Automatic Test Equipment), characterized in that, The system includes an ATE test host, a clock synchronization and phase control module, a test signal source distribution module, a data acquisition module, a crosstalk modeling module, a crosstalk digital compensation module, and a channel isolation layout module connected to the ATE test host, and a multi-channel parallel test board connected to the clock synchronization and phase control module, the test signal source distribution module, the data acquisition module, and the channel isolation layout module; the data acquisition module is also connected to the crosstalk digital compensation module and the crosstalk modeling module respectively, and the crosstalk digital compensation module is connected to the crosstalk modeling module.

2. The ATE-based ADC multi-channel parallel test crosstalk suppression system according to claim 1, characterized in that, The multi-channel parallel test board has M test channels, M≥2, and each test channel is used to connect to an ADC chip under test or an input channel of a multi-channel ADC chip.

3. The ATE-based ADC multi-channel parallel test crosstalk suppression system according to claim 1, characterized in that, The channel isolation layout module is used to determine the minimum safe distance between each test channel based on the physical layout parameters of each test channel on the multi-channel parallel test board.

4. The ATE-based ADC multi-channel parallel test crosstalk suppression system according to claim 3, characterized in that: The constraint condition for the minimum safety distance is: Where i and j are the indices of any two different channels, and the values ​​of i and j are 1, 2, 3, ..., M respectively; M is the total number of test channels; Let be the crosstalk coupling coefficient between channel i and channel j. This is a preset threshold for the crosstalk coupling coefficient.

5. The ATE-based ADC multi-channel parallel test crosstalk suppression system according to claim 4, characterized in that: The clock synchronization and phase control module independently adjusts the sampling clock phase of each channel to satisfy the following: the time interval ΔT between the sampling times of adjacent channels satisfies the following condition. Where M is the total number of test channels, and M≥2; Let be the fine-tuning phase offset of the i-th channel. The sampling period.

6. The suppression method of the ATE-based ADC multi-channel parallel test crosstalk suppression system according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1. Based on the physical layout parameters of each test channel on the multi-channel parallel test board, the minimum safe distance and shielding structure configuration between each test channel are determined through the channel isolation layout module, and the signal traces of each test channel are arranged according to the minimum safe distance to reduce the electromagnetic coupling and substrate coupling strength between channels. S2, the clock synchronization and phase control module provides a common sampling clock to each test channel, and independently adjusts the sampling clock phase of each channel through a programmable delay unit, so that the sampling times of adjacent channels are staggered in time, and the time interval ΔT between the sampling times of adjacent channels satisfies ; S3. The crosstalk modeling module performs parametric modeling of the residual crosstalk, establishing the crosstalk transfer function matrix H; the crosstalk transfer function matrix H is an M×M matrix, where the diagonal elements... =1, off-diagonal element Let be the crosstalk transfer function from channel j to channel i; S4. The test signal source distribution module applies test excitation signals to each test channel according to the test configuration parameters, and the data acquisition module acquires the digital output code values ​​of each channel in parallel to obtain the measured output code value vector Y. S5. The crosstalk digital compensation module performs crosstalk cancellation compensation on the measured output code value vector Y based on the crosstalk transfer function matrix H, obtaining the compensated digital output code value vector. ,Should The calculation formula is: ,in, This is the inverse matrix of the crosstalk transfer function matrix; S6, The ATE test host outputs a code value vector based on the compensated digital output. Calculate the static and dynamic parameters of the ADC under test for each test channel; S7. Repeat steps S4 to S6 until all test items have been measured.

7. The suppression method for the ATE-based ADC multi-channel parallel test crosstalk suppression system according to claim 6, characterized in that: The specific method for establishing the crosstalk transfer function matrix H in step S3 includes: S31. Select the p-th channel as the excitation channel and apply a known calibration test signal to the p-th channel. The input terminals of the remaining channels are connected to the reference level; S32. The data acquisition module acquires the digital output code values ​​of each channel in parallel, and records the coupling component generated by the excitation of the p-th channel in the output of the q-th channel (q≠p). ; S33. Calculate the crosstalk transfer function from channel p to channel q. ; S34. Repeat steps S31 to S33 to traverse all channel combinations and establish the complete crosstalk transfer function matrix H.

8. The suppression method for the ATE-based ADC multi-channel parallel test crosstalk suppression system according to claim 7, characterized in that: The establishment and updating of the crosstalk transfer function matrix H are performed when the ATE test host is idle, or during the calibration phase before the start of the test batch; when the test environment temperature changes beyond the preset temperature threshold, the recalibration of the crosstalk transfer function matrix H is automatically triggered.

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