A data encoding, error detection and correction method, device and circuit

Abstract

A data encoding, error detection, and error correction method, apparatus, and circuit are disclosed. The method includes: during encoding, encoding a data block based on a first encoding rule to generate a check bit, and encoding the check bit based on a second encoding rule to generate a first parity bit; constructing a check block from the check bit and the first parity bit, and performing global parity checking on the data block and the check block to generate a global parity bit; during decoding, receiving the data block, the check block, and the global parity bit; re-encoding the received check bit based on the second encoding rule to generate a new first parity bit, and combining the new first parity bit with the received first parity bit and the global parity bit to correct errors in the check block to obtain an error-corrected check bit; re-encoding the received data block based on the first encoding rule to generate a new check bit, and combining the new check bit with the error-corrected check bit and the global parity bit to correct errors in the data block. Embodiments of this disclosure can improve error correction accuracy.

Description

Technical Field

[0001] This article relates to data detection technology, and more particularly to a data encoding, error detection and correction method, device and circuit. Background Technology

[0002] In storage media such as Flash memory and SRAM, data bit flipping frequently occurs due to factors such as process defects, voltage fluctuations, and radiation effects. Therefore, Error Checking and Correcting (ECC) technology is typically used to protect the stored data. Among related technologies, ECC schemes mainly include: standard Hamming code and its extensions, and row and column polarity check schemes.

[0003] However, the above schemes typically use the check bit directly to check and correct data blocks during the error correction process, without verifying the correctness of the check bit itself. Once the check bit is erroneous due to bit flipping, the error will propagate directly to the error correction process of the data block, causing the data block to be incorrectly corrected or unable to be correctly corrected, thereby reducing the overall accuracy of error correction. Summary of the Invention

[0004] This disclosure provides a data encoding, error detection and correction method, apparatus and circuit that can prevent the propagation of supervisory bit errors to the data block error correction process and improve the overall error correction accuracy.

[0005] This disclosure provides a data encoding, error detection, and error correction method, including: an encoding process and a decoding process, wherein the encoding process includes: The encoding process includes: The data block to be protected is encoded based on the first encoding rule and a check bit is generated. The check bit is then encoded based on the second encoding rule and a first check bit is generated. A supervisory block is constructed based on the generated supervisory bit and the first parity bit, and a global parity check is performed on the data block and the constructed supervisory block to generate a global parity check bit. The decoding process includes: The system receives the data block, check block, and global parity bit after the encoding process is completed. Based on the second encoding rule, it encodes the received check bit and generates a new first parity bit. Based on the newly generated first parity bit and the received first parity bit, and combined with the global parity check, it judges and corrects errors in the received check block, and obtains the corrected check bit. The global parity check is generated based on the received data block, check block, and global parity bit. The received data block is encoded based on the first encoding rule, and a new check bit is generated. Based on the newly generated check bit and the corrected check bit, and combined with the global checksum, errors in the received data block are judged and corrected.

[0006] In one exemplary instance, the data block comprises: N bits of data, wherein the check bits are P bits, and P satisfies 2^N / 2^N. P The smallest positive integer greater than N-1; Encoding the data block based on the first encoding rule and generating a check bit includes: Obtain all bits of data in the data block whose binary address i-th bit is 0, and perform an XOR operation on all the obtained bits to obtain the value of the i-th bit in the check bit; i∈[0,P-1].

[0007] In one exemplary instance, the second encoding rule includes: Hamming encoding and BCH encoding.

[0008] In one exemplary instance, the global checksum is obtained in the following manner: Perform global parity checking on the received data block and the received check block to obtain a new global parity bit; The global parity bit is obtained based on the new global parity bit and the received global parity bit.

[0009] In one exemplary instance, Based on the newly generated first check bit and the received first check bit, and in conjunction with the global checksum, errors in the received supervisory block are judged and corrected, including: Generate a parity block syntactic based on the newly generated first parity bit and the received first parity bit; If the parity block syndrome is not 0 and the global checksum is 1, indicating that the received parity block has an odd number of errors, then it is determined that there is a single bit error in the received parity block. The error location is determined according to the parity block syndrome and error correction is performed. The global checksum is then updated to 0. If the syndrome of the monitoring block is not 0 and the global checksum is 0, indicating that the received monitoring block has an even number of errors, then it is determined that there are uncorrectable multi-bit errors in the received monitoring block, and the global checksum remains unchanged. If the parity of the monitoring block is 0 and the global parity check is 1, it indicates that there is an error in the received global parity check bit, or if there is an odd number of errors in the received data block, the global parity check remains unchanged.

[0010] In one exemplary instance, based on the newly generated check bits and the corrected check bits, and in conjunction with a global checksum, errors in the received data block are determined and corrected, including: generating a data block syndrome based on the newly generated check bits and the error-corrected check bits; If the data block syndrome is not 0 and the global syndrome obtained after error correction by the check block is 1, which indicates that the received data block has an odd number of errors, it is determined that there is a single-bit error in the received data block, and the error position is determined and error correction is performed according to the data block syndrome; If the data block syndrome is not 0 and the global syndrome obtained after error correction by the check block is 0, which indicates that the received data block has an even number of errors, it is determined that there is an uncorrectable multi-bit error in the data block; If the data block syndrome is 0 and the global syndrome obtained after error correction by the check block is 1, it is determined that there is an error in the received global parity check bit.

[0011] In an exemplary embodiment, determining the error position and performing error correction according to the data block syndrome includes: When it is determined that the data block syndrome is not zero, the data block syndrome is inverted, and the inverted value is used as the address index of the error bit in the received data block to locate the error position.

[0012] In an exemplary embodiment, the encoding the data block based on the first encoding rule and generating check bits includes: dividing the data block into a plurality of data groups, and inputting one of the data groups in each clock cycle; in each clock cycle, for each of the data groups, calculating in parallel an intermediate XOR result corresponding to each bit in the check bits; obtaining the final P check bits based on the intermediate XOR results obtained over a plurality of clock cycles.

[0013] In an exemplary embodiment, the calculating in parallel an intermediate XOR result corresponding to each bit in the check bits for each of the data groups in each clock cycle includes: for the first M check bits, selecting corresponding data bits from the current data group to perform an XOR operation according to the value of the low-order address bit of the current data group, and using the operation result to calculate the intermediate XOR result corresponding to the first M bits in the check bits; for the last P-M check bits, first performing a reduction XOR operation on all data bits of the current data group to obtain a reduction value, then determining whether to use the reduction value to calculate the intermediate XOR result corresponding to the last P-M bits in the check bits according to the value of the high-order address bit of the current data group; where M is a positive integer satisfying 1≤M<P.

[0014] This disclosure provides a data encoding, error detection and correction apparatus, characterized in that the apparatus includes: a memory and a processor, wherein the memory is configured to store an executable program; The processor is configured to read and execute the executable program, performing the data encoding, error detection, and error correction methods as described in any of the preceding claims.

[0015] The data encoding, error detection, and error correction method, apparatus, and circuit provided in this disclosure include an encoding process and a decoding process. The encoding process includes: acquiring a data block; encoding the data block to be protected based on a first encoding rule and generating a check bit; encoding the check bit based on a second encoding rule and generating a first check bit; constructing a check block based on the generated check bit and the first check bit; and performing global parity checking on the data block and the constructed check block to generate a global parity check bit. The decoding process includes: receiving the data block, check block, and global parity check bit after the encoding process is completed; encoding the received check bit based on the second encoding rule and generating a new first check bit; judging and correcting errors in the received check block based on the newly generated first check bit and the received first check bit, combined with a global checksum, and obtaining the corrected check bit. The global checksum is generated based on the received data block, check block, and global parity check bit; the received data block is encoded based on the first encoding rule and a new check bit is generated; the newly generated check bit and the corrected check bit, combined with a global checksum, are used to judge and correct errors in the received data block. This embodiment employs a hierarchical coding and hierarchical error correction strategy for data blocks and check bits. Errors in the check block are corrected first, and then the corrected check bits are used to correct errors in the data block. This avoids the propagation of check bit errors to the data block correction process, improving the overall accuracy of error correction. Simultaneously, a global parity check is introduced for both data blocks and check blocks, and a global parity check bit is generated based on the received data block, check block, and global parity check bit. Error judgment is performed using the global parity check bit in both the check block and data block error correction stages, enhancing the ability to detect erroneous data and further ensuring the reliability of error correction.

[0016] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings. Attached Figure Description

[0017] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0018] Figure 1 This is a flowchart illustrating a data encoding, error detection, and error correction method according to an embodiment of the present disclosure; Figure 2 This provides a framework for a data encoding, error detection, and error correction method according to embodiments of this disclosure; Figure 3 This is a schematic diagram illustrating the resource consumption of a three-level error control architecture according to an embodiment of this disclosure; Figure 4 This is a schematic diagram illustrating the hardware implementation process of a supervisory bit according to an embodiment of this disclosure. Detailed Implementation

[0019] This application describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0020] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes can be made within the scope of the appended claims.

[0021] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0022] This disclosure provides a data encoding, error detection, and error correction method, such as... Figure 1 As shown, the method includes: Step 101, encoding process, the encoding process includes: encoding the data block to be protected based on the first encoding rule and generating a check bit; encoding the check bit based on the second encoding rule and generating a first check bit; constructing a check block based on the generated check bit and the first check bit; and performing global parity check on the data block and the constructed check block to generate a global parity check bit. Step 102, Decoding process, which includes: receiving the data block, check block, and global parity bit after the encoding process is completed; encoding the received check bit according to the second encoding rule and generating a new first parity bit; judging and correcting errors in the received check block based on the newly generated first parity bit and the received first parity bit, and in combination with the global parity check, and obtaining the corrected check bit; wherein, the global parity check is generated based on the received data block, check block, and global parity bit; encoding the received data block according to the first encoding rule and generating a new check bit; judging and correcting errors in the received data block based on the newly generated check bit and the corrected check bit, and in combination with the global parity check.

[0023] For example, the data block to be protected may be binary data stored on a storage medium, which may be data written by the user, system configuration information, or other critical data that needs to be protected from errors. This disclosure does not limit the specific content and source of the data to be protected.

[0024] For example, during the data writing process of storage media such as Flash memory and SRAM, a hierarchical encoding strategy is adopted to protect the written data in order to improve the accuracy and reliability of data error correction. Specifically, firstly, the data block to be written is obtained, and the data block is encoded according to a first encoding rule to generate a set of check bits. These check bits are used to detect and correct errors in the data block during subsequent reading. Subsequently, instead of directly storing the check bits along with the data block, the check bits are further encoded according to a second encoding rule to generate a first check bit. This first check bit is used to detect and correct errors in the check bits themselves. Through this hierarchical encoding mechanism, the correctness of the check bits is additionally protected during the encoding stage. After completing the above encoding, a check block is constructed based on the generated check bits and the first check bit, and a global parity check is performed on the data block and the constructed check block to generate a global parity check bit. This global parity check bit is not used for error correction, but is used to assist in judging whether there are multi-bit errors that exceed the error correction capability of the encoding rules during the decoding stage, thereby providing a reliable error detection fallback capability for the subsequent decoding process. After the encoding process is completed, the data block, check block, and global parity bits are merged and stored in the storage medium. In other words, the input for the encoding process is the data block to be protected, and the result after encoding is the entire data block, check block, and global parity bits.

[0025] For example, during the data reading process of the storage medium, a hierarchical decoding strategy corresponding to the encoding process is adopted for error detection and correction. Specifically, the data block, check block, and global parity bit stored in the storage medium after the encoding process is completed are received first. The received check bit is encoded based on the second encoding rule to generate a new first parity bit. Subsequently, the newly generated first parity bit is compared with the received first parity bit, and the error in the check block is judged and corrected in conjunction with the global parity check: if the comparison result of the first parity bit indicates the existence of an error and the global parity check confirms that the error is within the correctable range, the error in the check block is corrected to obtain the corrected check bit; if the global parity check detects a multi-bit error that exceeds the error correction capability, it is determined to be an uncorrectable error to avoid false correction. The global parity check is generated based on the received data block, check block, and global parity bit. Through this mechanism, it is ensured that the check bit used for subsequent data block error correction is correct, thereby cutting off the path of check bit error propagation to the data block error correction process. Building upon this, the received data block is further encoded using the first encoding rule to generate new check bits. Based on these newly generated check bits and the corrected check bits, combined with the global parity check, errors in the data block are judged and corrected. Since data block error correction relies on the already verified and corrected check bits, and both error correction stages incorporate the global parity check for error judgment, the overall accuracy of error correction is significantly improved. In other words, for the decoding process, the input is the entirety of the data block, check block, and global parity check bits. After decoding, errors in the entirety of the data block, check block, and global parity check bits obtained from the storage medium can be judged and corrected.

[0026] For example, the first and second encoding rules can be implemented using various linear block code schemes. The first encoding rule is used to encode the data block and generate check bits. Its specific scheme can be flexibly selected according to data error correction requirements, such as standard Hamming code, extended Hamming code (adding a global parity bit to the standard Hamming code), BCH code, or RS code. The second encoding rule is used to encode the check bits generated by the first encoding rule and generate the first parity bit. It can be the same as or different from the first encoding rule. For example, when the first encoding rule uses (128, 120) Hamming code to generate 8 check bits, the second encoding rule can use (8, 4) Hamming code to re-encode these 8 check bits, generating a 4-bit first parity bit. By configuring an independent second encoding rule for the check bits, the check bits receive additional error correction protection during storage and transmission, ensuring the reliability of the check bits at the encoding level.

[0027] For example, the construction process of the check block is as follows: the check bits generated by the first encoding rule and the first check bits generated by the second encoding rule are combined according to a preset arrangement rule to form the check block. Specifically, the arrangement of the check bits and the first check bits in the check block can be such that the check bits are at the beginning and the first check bits are at the end, or the first check bits are interspersed among the check bits; this disclosure does not limit this arrangement. The length of the check block is equal to the sum of the number of check bits and the number of first check bits. For example, when the first encoding rule generates 8 check bits and the second encoding rule generates 4 first check bits, the length of the check block is 12 bits.

[0028] For example, the global parity check bit is generated by XORing all bits in the data block and the check block, and is used to assist in determining whether an error is within the correctable range during the decoding stage. The specific judgment logic is as follows: when the comparison result of the first parity check bit indicates an error and the global parity check indicates an odd number of errors, it is determined to be a single-bit error, falling within the correctable range of the second encoding rule. In this case, the error bit is located and corrected based on the error information. When the comparison result of the first parity check bit indicates an error and the global parity check indicates an even number of errors, it is determined to be a multi-bit error (such as a two-bit error), exceeding the correctable range of the second encoding rule. In this case, no error correction operation is performed; instead, an uncorrectable error is reported to the upper layer, which then takes data rereading or other fault-tolerant measures. By introducing the auxiliary judgment of the global parity check, the problem of miscorrection caused by misjudging multi-bit errors as single-bit errors is effectively avoided, further ensuring the reliability of error correction.

[0029] The data encoding, error detection, and error correction method provided in this disclosure adopts a hierarchical encoding and hierarchical error correction strategy for data blocks and check bits. It first corrects errors in the check block, and then uses the corrected check bits to correct errors in the data block, avoiding the propagation of check bit errors to the data block error correction process and improving the overall error correction accuracy. At the same time, a global parity check is introduced for both data blocks and check blocks, and a global checksum is generated based on the received data block, check block, and global parity check bits. Error judgment is performed in conjunction with the global checksum in both the check block error correction and data block error correction stages, enhancing the ability to detect erroneous data and further ensuring the reliability of error correction.

[0030] In one exemplary instance, the data block includes: N bits of data, wherein the check bit is P bits, and P satisfies 2^N / 2^N. P The smallest positive integer greater than N-1; Encoding the data block based on the first encoding rule and generating a check bit includes: Obtain all bits of data in the data block whose (i-1)th binary address is 0, and perform an XOR operation on all the obtained bits to obtain the value of the i-th bit in the check bit; i∈[1,P].

[0031] For example, when encoding a data block based on the first encoding rule, it is first necessary to determine the number of parity bits P. Specifically, the data block contains N bits of data, and the parity bits are P bits, where P satisfies 2^N / N. P The smallest positive integer greater than N-1. This constraint stems from the coding principle: P parity bits can represent 2^N. P There are several different states that need to cover at least N data bits for error location and an all-zero state (representing no error). For example, when the data block length N = 128 bits, it needs to satisfy 2 P The smallest positive integer greater than 127 is P=7, therefore 7 check bits are needed; when N=256 bits, P=8. The value of P determined in this way ensures that the check bits have sufficient error location capability, while avoiding the storage overhead waste caused by excessive check bit redundancy.

[0032] For example, after determining the number of bits P in the check bit, each bit in the check bit is generated bit by bit as follows. Specifically, each of the N bits in the data block is assigned a binary address number from 0 to N-1, and each address number is represented by a P-bit binary number. For the generation of the i-th bit in the check bit (where i∈[1,P]), all bits of data in the data block whose (i-1)-th bit of the binary address is 0 are obtained, and an XOR operation is performed on all the obtained bits. The result of the operation is the value of the i-th bit in the check bit. A specific explanation is given using N=4 and P=3 as an example. The 4 bits of the data block correspond to address numbers 0 (000), 1 (001), 2 (010), and 3 (011), respectively, and each address is represented by a 3-bit binary number. For the first parity bit (i=1), retrieve the bit data where the 0th bit of the address number is 0, that is, the bits corresponding to address 0 (000) and address 2 (010), and perform an XOR operation on these two bits to obtain the value of the first parity bit; For the second parity bit (i=2), retrieve the bit data where the 1st bit of the address number is 0, that is, the bits corresponding to address 0 (000) and address 1 (001), and perform an XOR operation on these two bits to obtain the value of the second parity bit; For the third parity bit (i=3), retrieve the bit data where the 2nd bit of the address number is 0, that is, the bits corresponding to address 0 (000), address 1 (001), address 2 (010), and address 3 (011), and perform an XOR operation on these four bits to obtain the value of the third parity bit.

[0033] For example, the essence of the above-described parity bit generation method is to construct multiple parity check relationships for the data block. Each parity bit corresponds to a set of parity check relationships, which consists of all bits in the data block whose (i-1)th bit of the binary address is 0. The value of the i-th parity bit is the parity value of that set of bits. In this way, each bit in the data block is included in multiple different parity check relationships (specifically, the number of 0 bits in the address number determines how many parity check relationships the bit is included in). When a bit in the data block flips, the parity check result of the parity check relationship containing that bit changes, thus causing the corresponding parity bit check result to be abnormal. Since the address condition combinations satisfied by bits at different address numbers are different, by analyzing which parity bit check results are abnormal, the location of the bit that caused the error can be uniquely determined, thereby achieving precise location and correction of single-bit errors.

[0034] In one exemplary instance, the second encoding rule includes: Hamming encoding and BCH encoding.

[0035] For example, the second encoding rule can be implemented using various encoding schemes that possess at least one-bit error correction and two-bit error detection capabilities. "One-bit error correction and two-bit error detection" refers to the encoding rule's ability to correct a single-bit error and detect two-bit errors. For instance, the second encoding rule can employ Hamming encoding, extended Hamming encoding, BCH encoding, etc., and this disclosure does not limit its use. Hamming encoding has the ability to correct a single-bit error; extended Hamming encoding adds a global parity check bit to the standard Hamming encoding, enabling further detection of two-bit errors, thus achieving one-bit error correction and two-bit error detection; BCH encoding allows for flexible configuration of error correction capabilities based on design parameters, and when configured to correct a single-bit error, it also meets the requirements of the second encoding rule. By selecting an encoding scheme with at least one-bit error correction and two-bit error detection capabilities as the second encoding rule, automatic error correction can be achieved when a single-bit error occurs in the check bit, and detection and reporting can be achieved when a two-bit error occurs, thereby effectively ensuring the reliability of the check bit during storage and transmission.

[0036] For example, when the second encoding rule uses Hamming encoding, its core advantages lie in its simple encoding structure, low hardware implementation overhead, and low encoding / decoding latency. Specifically, Hamming code is a linear block code capable of correcting single-bit errors, with high encoding efficiency and low check bit overhead. When Hamming encoding is used in the second encoding rule, the input is the P-bit check bits generated by the first encoding rule. After Hamming encoding, several check bits are generated, which together with the original check bits constitute the check block. Since the number of check bits P is usually much smaller than the number of data blocks N (e.g., P=7 when N=128), the encoding scale of the second encoding rule is small. Even with the relatively basic error correction capability of Hamming encoding, it is sufficient to provide effective single-bit error correction protection for the check bits. In addition, the encoding and decoding process of Hamming encoding only requires XOR gates and simple combinational logic, without the need for complex finite field operations. It occupies less hardware area and consumes less power in SSD controllers or memory controllers, making it suitable for applications sensitive to area and power consumption.

[0037] For example, when the second encoding rule uses BCH encoding, its core advantage lies in its stronger error correction capability, capable of correcting multi-bit errors. Specifically, BCH code is a type of cyclic code, and its error correction capability can be flexibly configured through design parameters, for example, it can be configured to correct 2, 3, or even more bit errors. When BCH encoding is used in the second encoding rule, the input is still the P-bit check bits generated by the first encoding rule. After BCH encoding, the number of check bits generated will be more than that of Hamming encoding, but in return, it provides stronger error protection for the check block. This scheme is particularly suitable for application scenarios with high storage medium error rates or extremely stringent data reliability requirements, such as enterprise-grade SSDs and aerospace-grade memory. In these scenarios, the check block itself may also have multi-bit errors due to physical degradation of the storage medium (such as Flash cell wear, charge leakage, etc.). Relying solely on the single-bit error correction capability of Hamming code may not be sufficient to guarantee the correctness of the check bits, while the multi-bit error correction capability of BCH code can effectively cope with such situations, further improving the overall reliability of the scheme.

[0038] For example, in practical engineering, the choice between Hamming encoding and BCH encoding for the second encoding rule can depend on a trade-off of the following factors: First, the number of check bits, P. When P is small (e.g., P≤8), the overall length of the check block is short, and the probability of multiple bit errors is low. Hamming coding can meet the reliability requirements while maintaining low coding overhead and hardware complexity. When P is large, the length of the check block increases, and the probability of multiple bit errors increases accordingly. In this case, BCH coding can provide more adequate protection.

[0039] Secondly, the error rate level of the storage medium. For storage media with low error rates (such as SLC Flash and SRAM), the probability of the parity block itself being faulty is small, and Hamming encoding is sufficient. For storage media with high error rates (such as QLC Flash and Flash that has undergone a large number of erase and write cycles), the risk of multiple bit errors in the parity block increases, and BCH encoding should be used to enhance protection.

[0040] Thirdly, there are constraints on area and power consumption. Hamming encoding requires only a small number of XOR gates in its hardware implementation, resulting in minimal area and power overhead. BCH encoding, on the other hand, involves polynomial operations over finite fields, leading to relatively higher complexity and power consumption in the encoding and decoding circuits. In embedded scenarios where area and power consumption budgets are tight, Hamming encoding has a greater advantage.

[0041] In one exemplary instance, the global checksum is obtained in the following manner: Perform global parity checking on the received data block and the received check block to obtain a new global parity bit; The global parity bit is obtained based on the new global parity bit and the received global parity bit.

[0042] For example, a global parity check is used during the decoding stage to assist in determining whether there are errors in the received data block and check block that exceed the error correction capability of the encoding rules. It is obtained as follows: First, a global parity check is performed on the received data block and the received check block to obtain a new global parity bit. Specifically, this global parity check can be performed by XORing all bits in the received data block with all bits in the received check block; the result is the new global parity bit. Then, the newly obtained global parity bit is compared with the received global parity bit, and the global parity check is obtained based on the comparison result. Specifically, the new global parity bit and the received global parity bit can be XORed. If they are the same, the global parity check is a first value (e.g., 0), indicating that the received data block and check block as a whole have no errors, or have an even number of errors; if they are different, the global parity check is a second value (e.g., 1), indicating that the received data block and check block as a whole have an odd number of errors.

[0043] For example, the introduction of a global checksum provides additional global dimension information for error correction judgment during the decoding process. In the check block error correction stage, after encoding the received check bits according to the second encoding rule to generate a new first check bit, if the new first check bit is inconsistent with the received first check bit, it indicates an error in the check block. At this point, the global checksum is used to further determine the nature of the error: if the global checksum is the second value (indicating an odd number of errors), the error in the check block is determined to be a single-bit error, falling within the correctable range of the second encoding rule, and can be located and corrected based on the error information; if the global checksum is the first value (indicating an even number of errors), the error in the check block is determined to be a multi-bit error (such as a double-bit error), exceeding the correctable range of the second encoding rule, and error correction is not performed to avoid false correction. Similarly, in the data block error correction stage, after encoding the received data block according to the first encoding rule to generate a new check bit, if the new check bit is inconsistent with the corrected check bit, it indicates an error in the data block. At this point, the global checksum is also used to determine whether the error is within the correctable range, thereby deciding whether to perform error correction. By introducing global checksums for auxiliary judgment in both the supervision block error correction and data block error correction stages, the problem of misjudging multi-bit errors as single-bit errors is effectively avoided, further ensuring the reliability of the overall error correction.

[0044] In one exemplary instance, based on the newly generated first check bit and the received first check bit, and in conjunction with the global checksum, errors in the received supervisory block are judged and corrected, including: Generate a parity block syntactic based on the newly generated first parity bit and the received first parity bit; If the parity block syndrome is not 0 and the global checksum is 1, indicating that the received parity block has an odd number of errors, then it is determined that there is a single bit error in the received parity block. The error location is determined according to the parity block syndrome and error correction is performed. The global checksum is then updated to 0. If the syndrome of the monitoring block is not 0 and the global checksum is 0, indicating that the received monitoring block has an even number of errors, then it is determined that there are uncorrectable multi-bit errors in the received monitoring block, and the global checksum remains unchanged. If the parity of the monitoring block is 0 and the global parity check is 1, it indicates that there are an odd number of errors in the received data block or that there are errors in the received global parity check bit, and the global parity check remains unchanged.

[0045] For example, in the decoding phase, a global parity check is first obtained. Specifically, the global parity check is obtained by performing a global parity check on the received data block and the received check block to obtain a new global parity bit. Specifically, each bit in the received data block is XORed with each bit in the received check block, and the result is the new global parity bit, which has a value of 1 bit. Subsequently, the newly obtained global parity bit is compared with the received global parity bit, and the global parity check is obtained based on the comparison result. Specifically, the new global parity bit and the received global parity bit are XORed to obtain the global parity check. If the global parity check is 1, it indicates that there are an odd number of bit errors in the data block and the check block; if the global parity check is 0, it indicates that there are an even number of bit errors in the data block and the check block, or no errors. The calculation of this global parity check only requires one set of XOR gates, with extremely low hardware overhead, and it is independent of the parity check calculation of the check block, and can be completed in parallel within the same clock cycle without introducing additional decoding latency.

[0046] For example, in the decoding stage, the received check bits are encoded based on the second encoding rule to generate a new first check bit. The newly generated first check bit is compared with the received first check bit to obtain the check result of the check block. Errors in the check block are then judged and processed in conjunction with the global checksum. Specifically, this includes the following cases: In the first scenario, when the parity block synastry is not 0 and the global checksum is 1, it indicates that the received parity block contains an odd number of errors, suggesting a single-bit error, which is a correctable error type. The criteria are as follows: a non-zero parity block synastry indicates at least one error in the parity block; a global checksum of 1 indicates an odd number of errors overall. Combined with the non-zero synastry, it can be inferred that the number of erroneous bits in the parity block is odd. Under the premise that the second encoding rule is Hamming code (single-bit error correction), the most likely scenario among an odd number of errors is a single-bit error. In this case, the value of the synastry uniquely corresponds to the bit position where the error occurred in the parity block. The specific error correction process is as follows: using the value of the parity block synastry as an address index, the erroneous bit in the parity block is directly located through a lookup table or combinational logic. This bit is then flipped (0 becomes 1, 1 becomes 0), completing the error correction, and the global checksum is updated to 0. The parity bit obtained after error correction is the correct parity bit, which can be used for subsequent error correction of data blocks.

[0047] In the second scenario, when the syntagmatic property of the check block is not zero and the global checksum is zero, it indicates that the received check block contains an even number of errors. This suggests the presence of uncorrectable multi-bit errors (such as double-bit errors) in the check block, exceeding the correctable range of the second coding rule. In this case, the global checksum remains unchanged, and no error correction is performed. Instead, the uncorrectable error is reported to the upper layer, which then takes measures such as data rereading or other fault-tolerance measures. By introducing the auxiliary judgment of the global checksum, the problem of misclassifying multi-bit errors as single-bit errors is effectively avoided, further ensuring the reliability of error correction.

[0048] In the third case, when the parity check is 0 and the global parity check is 1, it indicates that there is an error in the received global parity check bit, or that there is an odd number of errors in the received data block. In the subsequent error correction of the data block, the global parity check remains unchanged, and the received parity check bit is directly used as the parity check bit after error correction for subsequent error correction of the data block.

[0049] In the fourth case, when the syntactic property of the check block is 0 and the global checksum is 0, it indicates that there is no error in the check block. No error correction operation is required, the global checksum is not updated, and the received check bits are directly used as the corrected check bits for subsequent error correction of the data block.

[0050] In one exemplary instance, based on the newly generated check bits and the corrected check bits, and in conjunction with a global checksum, errors in the received data block are determined and corrected, including: Data block compositing is generated based on the newly generated check bits and the error-corrected check bits; If the data block syndrome is not 0 and the global checksum obtained after error correction by the supervisory block is 1, indicating that the received data block has an odd number of errors, then it is determined that there is a single bit error in the received data block, and the error location is determined according to the data block syndrome and error correction is performed. If the syntactic expression of the data block is not 0 and the global checksum obtained after error correction by the supervisory block is 0, indicating that the received data block has an even number of errors, then it is determined that there are uncorrectable multi-bit errors in the data block. If the data block syntactic is 0 and the global parity bit obtained after error correction by the supervisory block is 1, then it is determined that the received global parity bit is incorrect.

[0051] For example, after obtaining the newly generated check bits, a data block syndrome is generated based on the newly generated check bits and the error-corrected check bits. Specifically, the newly generated check bits and the error-corrected check bits can be XORed bit by bit to obtain the data block syndrome. The i-th bit of the data block syndrome is equal to the XOR result of the i-th bit of the error-corrected check bits and the i-th bit of the newly generated check bits. The essence of this XOR operation is to compare the differences between the two sets of check bits: if the XOR result of a certain bit is 0, it indicates that the parity of the check group corresponding to that bit is consistent in the encoding and verification stages, that is, the data block bits covered by that check group have no errors; if the XOR result of a certain bit is 1, it indicates that the parity of the check group corresponding to that bit is inconsistent in the encoding and verification stages, that is, there are errors in the data block bits covered by that check group. Since each bit of the data block syndrome corresponds to an independent check group, the P-bit data block syndrome fully reflects the parity check results of all check groups, forming a comprehensive description of the error state of the data block.

[0052] For example, after obtaining the syntactic expression of the data block, the global checksum obtained after the check block error correction is used to judge and process errors in the data block. It should be noted that the global checksum used here is the global checksum obtained after the check block error correction stage. That is, if single-bit error correction is performed on the check block during the check block error correction stage, the global checksum has been updated to 0; if no error correction operation is performed during the check block error correction stage, the global checksum remains unchanged.

[0053] Errors in received data blocks are judged and corrected based on the data block synergy and the global checksum obtained after supervised block error correction, specifically including the following cases: In the first scenario, when the data block synastry is not 0 and the global checksum obtained after error correction by the check block is 1, it indicates that the received data block contains an odd number of errors, indicating a single-bit error, which is a correctable error type. The judgment is based on the following: a non-zero data block synastry indicates at least one bit error in the data block; a global checksum of 1 indicates an odd number of errors overall. Combined with the non-zero synastry, it can be inferred that the number of erroneous bits in the data block is odd. Under the premise that the first encoding rule is Hamming code (single-bit error correction), the most likely scenario among an odd number of errors is a single-bit error. In this case, the value of the data block synastry uniquely corresponds to the bit position where the error occurred in the data block. The specific error correction process is as follows: using the value of the data block synastry as an address index, the erroneous bit in the data block is directly located through a lookup table or combinational logic. The bit is then flipped (0 becomes 1, 1 becomes 0), thus completing the error correction.

[0054] In the second scenario, when the data block's symptom is not zero and the global checksum obtained after error correction by the supervisory block is zero, it indicates that the received data block contains an even number of errors. This indicates the presence of uncorrectable multi-bit errors (such as double-bit errors) in the data block, exceeding the correctable range. Therefore, no error correction is performed, and the uncorrectable error is reported to the upper layer, which then takes measures such as data rereading or other fault-tolerance measures. By introducing the auxiliary judgment of the global checksum, the problem of misclassifying multi-bit errors as single-bit errors is effectively avoided, further ensuring the reliability of error correction.

[0055] In the third case, when the data block synastry is 0 and the global parity bit obtained after error correction by the check block is 1, it indicates that the data block itself is not erroneous (because the data block synastry is 0, which means that the check bit recalculated based on the data block is completely consistent with the check bit after error correction), but the global parity bit is still 1. In this case, it is determined that the received global parity bit is erroneous.

[0056] In the fourth case, when the data block symptom is 0 and the global checksum obtained after error correction by the supervisory block is 0, it indicates that there are no errors in the data block, and the global checksum also indicates that there are no odd number of errors in the whole. No error correction operation is required, and the received data block is directly output as the error-corrected data block.

[0057] The core improvement of the solution provided in this disclosure compared to related technical solutions lies in the fact that in related technical solutions, the check bit is stored and read together with the data block. If the check bit itself is faulty, it will directly lead to the failure of data block error correction or even false correction. However, the solution provided in this disclosure uses a hierarchical error correction strategy to ensure the correctness of the check bit before correcting the data block, thereby cutting off the error propagation path and significantly improving the overall accuracy of error correction.

[0058] In one exemplary instance, determining the error location and performing error correction based on the data block's syntactic features includes: When it is determined that the syndrome of the data block is not zero, the syndrome of the data block is inverted, and the inverted value is used as the address index of the error bit in the data block to locate the error position.

[0059] For example, let's take P=3 and data block length N=4 as an example for specific explanation. Assume that the bit at address 2 (binary 010) in the data block has a flip error. After calculating the syndrome, the syndrome of the data block is 101 (i.e., the bitwise inversion of address 010). Then, inverting the bits of syndrome 101 yields 010, which is decimal 2. This value is the address index of the bit in the data block where the error occurred. Subsequently, the address decoder maps address index 2 to the position of the second bit in the data block, and flips that bit (0 becomes 1 or 1 becomes 0), thus completing the error correction.

[0060] Let's take P=7 and data block length N=128 as an example. Assume an error occurs in bit 93 (binary 1011101) of the data block. After calculating the syndrome, the syndrome is 0100010 (the bitwise inverse of 1011101). Inverting the syndrome 0100010 gives 1011101, which is decimal 93, precisely locating the 93rd bit in the data block. In this way, regardless of the data block length, error location can be completed in O(1) time, without needing to traverse the data block bit by bit, resulting in extremely high location efficiency.

[0061] In one exemplary instance, encoding the data block based on the first encoding rule and generating a check bit includes: The data block is divided into multiple data groups, and one of the data groups is input in each clock cycle; Within each clock cycle, for each data group, the intermediate XOR result corresponding to each bit in the supervisory bit is calculated in parallel; The final P-bit supervisory bit is obtained based on the intermediate XOR results obtained over multiple clock cycles.

[0062] For example, obtaining the final P-bit check bit based on the intermediate XOR results obtained over multiple clock cycles can be achieved by performing a cumulative XOR operation on the intermediate XOR results obtained over multiple clock cycles. Specifically, this can be done by performing an XOR operation on the intermediate XOR result obtained in the current clock cycle and the cumulative result from the previous clock cycle, and using the result as the cumulative result for the current clock cycle, until all data groups have been processed to obtain the final P-bit check bit.

[0063] For example, the cumulative XOR process can be performed recursively cycle by cycle. Specifically, within each clock cycle, the intermediate XOR result calculated in the current clock cycle is XORed bit by bit with the cumulative result saved at the end of the previous clock cycle. The result is used as the cumulative result for the current clock cycle and written to a register, overwriting the old value saved in the previous cycle. In the first clock cycle, since there is no cumulative result from the previous cycle, the initial value of the cumulative result is all zeros. Therefore, the cumulative result for the first clock cycle is equal to the intermediate XOR result of the first clock cycle itself. Thereafter, the cumulative result is updated according to the above recursive relationship in each clock cycle until all data groups have been processed.

[0064] For example, when encoding a data block based on the first encoding rule, the N-bit data block is not input into the encoding logic as a whole at once. Instead, the data block is divided into multiple data groups, each containing several bits. Specifically, the division method of the data groups can be flexibly configured according to the bit width and timing requirements of the encoding hardware. For example, when the data block length is 128 bits and the input bit width of the encoding hardware is 32 bits, the data block can be divided into 4 data groups, each containing 32 bits; when the input bit width of the encoding hardware is 16 bits, it can be divided into 8 data groups, each containing 16 bits. The size of the data group determines the amount of data involved in the operation in each clock cycle, thus affecting the encoding throughput and hardware resource consumption. By reasonably setting the size of the data group, an optimal balance can be achieved between encoding latency and hardware overhead.

[0065] For example, during the encoding process, a pipelined approach is used to input data packets cycle by cycle. Specifically, in the first clock cycle, the first data packet is input; in the second clock cycle, the second data packet is input; and so on, until all data packets have been input. Within each clock cycle, for the currently input data packet, the intermediate XOR result corresponding to each bit in the check bit is calculated in parallel. Specifically, for the i-th bit (i∈[1,P]) in the check bit, according to the first encoding rule, all bits in the data block whose binary address bit (i-1) is 0 need to be filtered and XORed. Since the data block is divided into multiple input packets, only the bits in the current packet that satisfy the condition that the address bit (i-1) is 0 can be obtained within each clock cycle. Therefore, the result calculated within each clock cycle is not the final value of the i-th check bit, but an intermediate XOR result, that is, the XOR value of all bits in the current packet participating in the i-th check group. Since there are P bits in total for the parity bits, P intermediate XOR results need to be calculated simultaneously in each clock cycle. The calculation of these P intermediate XOR results is independent of each other and can be completed simultaneously by P groups of parallel XOR logic, thereby making full use of the hardware's parallel computing capabilities and improving the computational efficiency in each clock cycle.

[0066] For example, since the data block is divided into multiple groups and input sequentially over multiple clock cycles, each clock cycle generates only one set of intermediate XOR results. Therefore, the final check bits need to be obtained step by step through cumulative XOR. Specifically, P registers are set up to store the cumulative XOR values ​​of the P check bits. At the beginning of each clock cycle, each register stores the cumulative XOR values ​​generated by the data groups input in the previous few clock cycles. In the current clock cycle, the newly calculated P intermediate XOR results are XORed with the values ​​of the corresponding registers, and the results are written back to the registers to update the cumulative values. After all the clock cycles corresponding to the data groups have passed, the values ​​stored in each register are the final P check bits.

[0067] For example, specific description is provided with N=128, P=7, and a data packet size of 32 bits as an instance. The data block is divided into 4 data packets: Packet 0 (bit 0 to bit 31), Packet 1 (bit 32 to bit 63), Packet 2 (bit 64 to bit 95), and Packet 3 (bit 96 to bit 127). The encoding process takes up 4 clock cycles. In the first clock cycle, 32 bits of Packet 0 are input, and intermediate XOR results are calculated respectively for the 7 bits of the check bits. For example, for the 0th bit of the check bits, bits whose 0th bit of the address is 0 in Packet 0 are selected (that is, bits with even addresses: 0, 2, 4, 6, ..., 30, 16 bits in total), and XOR operation is performed on these 16 bits to obtain the intermediate XOR result of the 0th bit of the check bits. Similarly, the intermediate XOR results of the remaining 6 check bits are also calculated synchronously. After the calculation is completed, the 7 intermediate XOR results are respectively written into the corresponding 7 registers. In the second clock cycle, 32 bits of Packet 1 are input, 7 intermediate XOR results are calculated in the same way, and XOR operation is performed with the accumulated values in the registers respectively to update the registers. The third and fourth clock cycles follow the same analogy. After 4 clock cycles, the values in the 7 registers are the final 7-bit check bits. The entire encoding process only requires 4 clock cycles, the scale of XOR operation in each cycle is only the XOR of 16 inputs, and both the logic depth and hardware overhead are greatly reduced.

[0068] In an exemplary embodiment, the step of, in each clock cycle, for each of the data packets, calculating in parallel the intermediate XOR result corresponding to each bit in the check bits comprises: For the first M check bits, select corresponding data bits from the current data packet for XOR operation according to the value of the low-order address bit of the current data packet, and use the operation result to calculate the intermediate XOR result corresponding to the first M bits in the check bits; For the last P-M check bits, first perform a reduction XOR operation on all data bits of the current data packet to obtain a reduction value, then determine whether to use the reduction value to calculate the intermediate XOR result corresponding to the last P-M bits in the check bits according to the value of the high-order address bit of the current data packet; M is a positive integer satisfying 1≤M<P.

[0069] For example, in a pipelined coding architecture, only one data packet is input per clock cycle, making it impossible to complete the full calculation of all P-bit check bits within one cycle. This disclosure divides the P-bit check bits into two parts for separate processing: the first M check bits and the last PM check bits. These two parts employ different calculation strategies to adapt to the characteristics of pipelined packet input, maximizing hardware parallel efficiency while ensuring functional correctness. Specifically, the address of each data bit in the data block can be divided into a low-order address portion and a high-order address portion: the low-order address portion is used to locate the specific data bit within the data packet, and the high-order address portion is used to identify the sequence number of the data packet. The calculation of the first M check bits is associated with the low-order address portion, and the calculation of the last PM check bits is associated with the high-order address portion.

[0070] For example, the calculation of the first M check bits is based on a selective XOR operation on the low-order addresses of each data bit within the current data block. Specifically, for the i-th bit (i∈[1,M]) in the first M check bits, the corresponding filtering condition is the value of the i-th bit in the low-order address of each data bit within the current data block. In each clock cycle, for the currently input data block, all data bits within the block are traversed, and data bits with a low-order address of (i-1)-th bit being 0 are selected. An XOR operation is performed on these selected data bits, and the result is the intermediate XOR result of the i-th bit in the first M check bits within the current clock cycle. Since the first M check bits consist of M bits, and the filtering condition and XOR operation for each bit are independent, all M intermediate XOR results can be calculated simultaneously within the same clock cycle through M sets of parallel XOR logic. Let's take a specific numerical example. Assume the data block size is 32 bits, the low-order address of each data bit within the block is 5 bits (addresses 0 to 31), and M=5. For the 0th bit in the first 5 parity bits, select the data bits whose lowest address 0th bit is 0 in the current group (i.e., the 16 data bits with addresses 0, 2, 4, 6, ..., 30), and XOR these 16 data bits to obtain the intermediate XOR result of the 0th parity bit. For the 1st bit, select the data bits whose lowest address 1st bit is 0 (i.e., the 16 data bits with addresses 0, 1, 4, 5, 8, 9, ..., 28, 29), and XOR them to obtain the intermediate XOR result. The remaining bits are processed in the same way. The 5 sets of XOR logic work in parallel, completing the calculation of all 5 intermediate XOR results within the same clock cycle.

[0071] For example, the calculation of the post-PM check bit is divided into two steps: first, a reduction XOR operation is performed, and then a conditional judgment is made based on the high-order address.

[0072] The first step is the reduction XOR operation. Within each clock cycle, a full reduction XOR operation is performed on all data bits in the current input data block, i.e., XORing each data bit in the block one by one to obtain a 1-bit reduction value. This reduction value reflects the overall parity of all data bits in the current data block. The reduction XOR operation and the parallel computation of the aforementioned first M parity bits can be performed synchronously within the same clock cycle. Both share the same set of input data, and only an additional tree-structured XOR operation is needed to complete the reduction operation, resulting in a very small increase in hardware overhead.

[0073] The second step is conditional judgment. After the reduced value is calculated, for each bit in the post-PM parity bit, based on the value of the corresponding bit in the high-order address of the current data block, it is determined whether to use the reduced value to calculate the intermediate XOR result of the post-PM bit in the parity bit. Specifically, for the j-th bit (j∈[M+1,P]) in the post-PM parity bit, the corresponding filtering condition is the value of the (jM-1)-th bit in the high-order address of the current data block. If the (jM-1)-th bit in the high-order address is 0, then the reduced value is used to calculate the intermediate XOR result of the post-PM bit in the parity bit; if the (jM-1)-th bit in the high-order address is 1, then the reduced value is not used to calculate the intermediate XOR result of the j-th bit in the post-PM parity bit within the current clock cycle.

[0074] For example, the fundamental reason for using different calculation strategies for the first M parity bits and the last PM parity bits lies in the interaction between the address filtering conditions and the data block structure in the encoding rules. For the first M parity bits (corresponding to the low-order addresses), the filtering condition is "the (i-1)th bit of the address is 0", where i∈[1, M]. Since the addresses of the data bits within a data block are different in the low-order part (covering all values ​​of the low-order addresses), only some data bits in each data block meet the filtering condition, requiring selective extraction of the data bits that meet the condition from the block for XOR. For the last PM parity bits (corresponding to the high-order addresses), the filtering condition is "the jth bit of the address is 0", where j∈[M+1, P]. Since the high-order addresses identify the sequence number of the data block, the high-order addresses of all data bits are the same within the same data block. Therefore, when the high-order address bit is 0, all data bits in the current group satisfy the filtering condition, which is equivalent to a reduction XOR of all data bits in the group; when the high-order address bit is 1, none of the data bits in the current group satisfy the filtering condition, and the intermediate XOR result is 0. Based on this address structure characteristic, the calculation of the post-PM check bit can be simplified to a two-step operation of "full group reduction + condition judgment", avoiding the overhead of selective filtering within the group.

[0075] This disclosure provides a data encoding, error detection, and error correction method. The method involves a three-level error control architecture, combining a first encoding rule (e.g., data block polarity-checked encoding) and a second encoding rule (e.g., check bit Hamming encoding), supplemented by global parity checking to achieve error detection and correction across the entire encoding domain. Level 1: Data block polarity check coding - pair 2 P Establish P-bit check bits for a bit data block: For example, establish 11 check bits for a 254-byte data block to accurately locate single-bit errors based on the bit mapping relationship of the data address; Level 2: Hamming coding of check bits - Add Kp check bits (corresponding to the first check bit in the above embodiment) to the P check bits to form check block K, and use the corresponding Hamming code to realize "correction 1 and check 2" of the check block, so as to avoid misjudgment caused by the error of the check bits themselves. For example, add 4 check bits to the 11 check bits to form check block K, and use (15, 11) Hamming code. Level 3: Global Parity Check - Performs global parity checks on data blocks and check blocks as the highest level of integrity check.

[0076] The data encoding, error detection, and error correction methods provided in this disclosure have the following framework: Figure 2 As shown, during the encoding stage, the 254-byte data block D first undergoes first-level polarity parity coding to generate 11 parity bits, P1 to P11. Subsequently, these 11 parity bits enter second-level Hamming coding to produce Kp parity bits. The parity bits P and the parity bits combine to form parity block K. Finally, the original data block D and the 15-bit parity code output from the second level are input into the third-level global parity check module to generate a 1-bit global parity check bit G. Ultimately, the 15-bit parity codes K0 to K14 and the 1-bit global parity check bit G combine to form a 16-bit ECC code output.

[0077] During the decoding phase, the data block D' and the check code at the receiving end enter parallel processing paths. Data block D' first undergoes polarity parity check (CP) calculation, yielding P'1 to P'11; simultaneously, the check code enters the first-stage K-block Hamming check, outputting K or K'. Subsequently, the results of the CP calculation, P'1 to P'11, along with the output K or K' from the first-stage Hamming check, are input to the second-stage D-block error location module, ultimately outputting the error status and error address information, completing the detection and location of erroneous bits in data block D'.

[0078] Regarding the resource consumption of a three-level error control architecture, as follows: Figure 3 As shown, taking a 254-byte data block input as an example, the first level requires 11 bits of check bits, the second level requires the corresponding check block encoding, the parity bit Kp requires 4 bits, and the third level requires 1 bit of global parity bit, for a total of 16 bits.

[0079] The sum of the data block to be protected and the check code requires corresponding check bits as shown in Table 1. Table 1 only takes the second level as an example of Hamming check, which is different from the implementation of BCH code.

[0080] Table 1 Level 1: Data block polarity check coding is as follows: The data block size is 254 bytes (2032 bits), the data address width is 11 bits (addr[10:0]), it can address 2048 data bit positions, and the number of check bits is 11 bits (P1~P11). Data is formatted as word=2. L For bit input, taking 32-bit as an example, the data block input is completed in 64 cycles.

[0081] In the above embodiments, the rules for generating the supervisory bit are as follows: For each data Di in the data block, its binary address is addr[10:0]. When a bit in the address is 0, that data bit participates in the XOR operation of the corresponding parity bit: P1 = D0⊕D2⊕D4⊕...⊕D(all bits where addr[0] = 0) P2 = D0⊕D1⊕D4⊕D5⊕...⊕D(all bits where addr[1] = 0) ... P11=D0⊕D1⊕...⊕D1023(all bits where addr

[10] =0) Among them, the supervisory bit hardware can be as follows Figure 4 As shown below: In hardware implementation, data is formatted as word=2. L For bit input, a hardware implementation scheme for 32-bit Word data input utilizes the incrementing pattern of the data address to perform a recursive XOR operation: The first M parity bits are calculated as P1~P5 (half-bit XOR accumulation): For each parity bit Pi (i=1~5), the lower address bit addr[i-1] is used. For din[31:0], 16 bits (data bits where the address is 0) are selected based on the value of addr[i-1]. These 16 bits are XORed and accumulated into the Pi register. A total of 5 × 16 = 80 XOR operations are performed for the 5 parity bits.

[0082] The parity bits P6~P11 are calculated using recursive XOR + conditional XOR of the higher address bits: First, a 32-bit reduction XOR is performed on din[31:0] to obtain ^Word (1 bit). Then, based on the higher address bits addr[10:5], it is determined whether to XOR ^Word with Pj: when addr[j]=0, Pj←Pj⊕^Word; when addr[j]=1, no operation is performed. Only 32+6=38 XOR operations are needed for the 6 parity bits.

[0083] The error localization principle is as follows: When a bit Di in a data block is faulty, the address of the faulty data bit can be uniquely determined by parsing the XOR result (compound expression) of the 11 parity bits. The faulty address is then directly concatenated after inverting the 11-bit compound expression Q1~Q11. Error address err_position_w = ~{Q11, Q10, Q9, Q8, Q7, Q6} Error position address err_position_b = ~{Q5, Q4, Q3, Q2, Q1} Level 2: Hamming coding with supervisory bits Add 4 parity bits kp0~kp3 to the 11-bit check bits P1~P11 to form a 15-bit check block K, using (15, 11) Hamming code. Parity bit generation rules: kp0=P1⊕P2⊕P4⊕P5⊕P7⊕P9⊕P11 ... kp3=P5⊕P6⊕P7⊕P8⊕P9⊕P10⊕P11 Level 3: Global Parity Check The global parity check bit G performs overall parity checking on the data block and the check block: G = D0⊕D1⊕...⊕D2031⊕K0⊕K1⊕...⊕K14. The functions of G are: 1) to distinguish between data block errors and check block errors; 2) to detect odd-numbered bit error combinations; and 3) to ensure the completeness of the "correction 1, check 2" process.

[0084] Redundancy check bits are composed of: P1~P11 (11 bits) + kp0~kp3 (4 bits) + G (1 bit) = 16 bits ecc_code.

[0085] The decoding and error correction scheme is as follows: Decoding adopts a two-stage joint judgment mechanism: Phase 1: Hamming check of supervised block K Calculate the adjoint expression hamming(K) and the global checksum Gs of the supervised block, and make a judgment based on hamming(K) and Gs: hamming(K)=0, Gs=0 → No error in the supervision block, proceed to the second stage; hamming(K)=0, Gs=1 → Data block 1-bit error or G error, proceed to the second stage; hamming(K)≠0, Gs=1→Supervise block 1 bit error, correct the error to get K', invert Gs, and enter the second stage; hamming(K)≠0, Gs=0→2-bit error, error message and exit.

[0086] Phase Two: Error Location of Data Block D Calculate the data block's syndrome Qi = Ki ⊕ P'i (i = 1, ..., 11), and make judgments based on Q1~Q11 and Gs: Q=0, Gs=0 → No errors in the data block; Q=0, Gs=1→G error, G bit inverted; Q≠0, Gs=1→1 bit error in data block. Locate the error address based on Q and correct the error. Q≠0, Gs=0→2-bit error in data block, error message and exit.

[0087] The data encoding, error detection, and error correction methods provided in this disclosure have the following advantages: 1. Precise error location: The location of any one bit error in the data block can be precisely located by using 11 polarity check bits. The error address is directly obtained by inverting the syndrome, without the need for complex table lookup or iterative calculations.

[0088] 2. Self-protection of the parity bit: The parity bit is encoded with (15, 11) Hamming code, which can detect 2 errors / correct 1 error, effectively avoiding misjudgment caused by errors in the parity bit itself. This is a capability that traditional row and column polarity ECC schemes do not have.

[0089] 3. Low hardware resource consumption: Through recursive XOR operation multiplexing, XOR resource consumption is only about 151, which is about 33% less than the row-column polarity ECC scheme (226) and more than 98% less than the standard Hamming code scheme (11,176+).

[0090] 4. Low coding redundancy: A 254-byte data block requires only 16 bits of redundancy check bits, with a coding redundancy of 0.79%, which is on par with standard Hamming code and 33% lower than row-column polarity ECC (1.18%).

[0091] 5. Multi-layer protection system and full probability detection: It adopts a three-level architecture with a 2-bit error detection rate of 100%, which is a significant improvement over the high probability detection of row and column polarity ECC.

[0092] 6. Good timing determinism: Fixed 64-cycle data input + 2~4-cycle verification, the total processing time is determined, which facilitates system integration.

[0093] 7. High-bit error recognition capability: 3-bit error reporting rate of 97.73% and 5-bit error reporting rate of over 96.38%, avoiding false positives.

[0094] The following is an embodiment of a data encoding, error detection and correction method. For page-level error checking and correction of Flash memory, a composite Hamming encoding scheme is adopted to expand the 2032-bit user data (corresponding to the data block to be protected in the above embodiment) into a 2048-bit codeword (corresponding to the data block, check block and global parity bit in the above embodiment). The three-level parity structure is used to realize the correction of single-bit errors and the detection of double-bit errors.

[0095] I. PageECC Data Structure Definition In this embodiment, the ECC protection unit of the Flash page is defined as 2048 bits (i.e., 256 bytes). Its physical layout is strictly divided into four regions at the machine level: data block D, check bit P, first parity bit K, and global parity bit G.

[0096] Data block D: Occupies bits 1 to 2032 (bit[0] to bit

[2031] ), with a length of 2032 bits (254 bytes), and is used to store actual user data.

[0097] Check bits P: Occupying bits 2033 to 2043 (bit

[2032] to bit

[2042] ), with a length of 11 bits, denoted as P1 to P11. These are check bits generated based on the Hamming (2043, 2032) algorithm and are used for error location of data blocks.

[0098] The first check bit K occupies bits 2044 to 2047 (bit

[2043] to bit

[2046] ), with a length of 4 bits, denoted as K1 to K4. These 4 bits are used for a second Hamming check of the P block to protect the check bit itself.

[0099] Global parity bit G: Occupies bit 2048 (bit

[2047] ), with a length of 1 bit. It performs parity checks on all 2047 bits of data in D, P, and K.

[0100] Inside the machine, corresponding index constants are defined to manage these regions. For example, the starting index of the data is 0, the starting index of the P block is 2032, the starting index of the K block is 2043, the starting index of the G bit is 2047, and the total length is 2048 bits.

[0101] II. Encoding Process (Writing to FlashPage) When data needs to be written to Flash, the encoding process begins. The input is 254 bytes of user data, which is treated as a 2032-bit data stream, typically input in 64 cycles of 32-bit words. The output is a 16-bit redundancy check code, containing P1~P11, K1~K4, and G, which is ultimately written to bytes 254 and 255 of the Flash page.

[0102] 1. First level: P-block generation (also known as data block polarity-checked coding) An 11-bit parity check (P1-P11) is generated by iterating through each bit of the input data. For each bit of input data, the binary characteristics of its address (addr) determine which parity bits it participates in the calculation.

[0103] P1 covers all data bits where the 0th bit of the address binary is 0 (e.g., address 0, 2, 4...).

[0104] P2 covers all data bits where the first bit of the address binary is 0 (e.g., address 0, 1, 4, 5...).

[0105] This process continues until P11 covers all data bits where the 10th bit of the address binary is 0.

[0106] At the machine level, this means that for each input cycle and each bit within the word, its address index is checked. If the (i-1)th bit of the address is 0, the value of that data bit is XORed with Pi, thereby gradually accumulating to generate values ​​P1 to P11.

[0107] 2. Second level: K-block generation (also known as check bit Hamming encoding) After generating the P block, a 4-bit first parity bit (K1-K4) is generated using the Hamming (15, 11) encoding principle to protect the P block.

[0108] K1 is generated by XORing P1, P2, P4, P5, P7, P9, and P11.

[0109] K2 is generated by XORing P1, P3, P4, P6, P7, P10, and P11.

[0110] K3 is generated by XORing P2, P3, P4, P8, P9, P10, and P11.

[0111] K4 is generated by XORing P5, P6, P7, P8, P9, P10, and P11.

[0112] This step ensures that any single-bit error in block P can be located by block K.

[0113] 3. Third level: G-bit generation (global parity check) Finally, the global parity bit G is calculated. It is an XOR operation performed on all bits of data block D, all bits of block P, and all bits of block K. The purpose is to ensure that the number of "1"s in the entire 2048-bit codeword is even.

[0114] 4. Encoded Output The final 16-bit checksum (P1~P11, K1~K4, G) is combined and written to the end of the Flash page. P1~P8 are written to the 254th byte, and P9~P11, K1~K4, and G are written to the 255th byte.

[0115] III. Storage and Retrieval When data is written to Flash, it follows a strict order: first, the user data from 0 to 253 bytes; then, bytes 254 (P1 to P8); and finally, bytes 255 (remaining parity bits).

[0116] During reading, a 2048-bit codeword is read at a time. Due to the physical characteristics of Flash memory, the read data (received_codeword) may contain bit-flipping errors.

[0117] IV. Decoding and Error Correction Process (Reading Flash Page) The decoding process is a phased logical judgment process designed to identify the location of errors and correct them.

[0118] 1. Pre-calculation: Global checksum First, perform an XOR operation on all 2048 bits of data read to generate a new global parity bit. This new global parity bit is then XORed with the received global parity bit to generate a global parity check. If the result is 0, it means that the overall parity check passed (no errors or an even number of errors); if the result is 1, it means that an odd number of errors occurred.

[0119] 2. First stage: K-block verification (P-block error detection and correction) The parity bits written to Flash are encoded and a new first parity bit is generated. The parity block syntactic is obtained by XORing the newly generated first parity bit with the first parity bit written to Flash.

[0120] Logical judgment: If the parity block symmetric is not 0 and the global checksum is 1, it indicates that a single-bit error has occurred in block P or block K. The specific index of the error is located by looking up the table (K_ERROR_MAP) (e.g., parity block symmetric 0011 corresponds to a P1 error), that bit is flipped for error correction, and the global checksum is also flipped.

[0121] If the parity check is not 0 and the global checksum is 0, it indicates a double-bit error has occurred (because parity check shows an even number of errors, but the parity check shows an error), and the error cannot be corrected.

[0122] If the syntactic expression of the monitoring block is 0, it means that blocks P and K are correct, and the second stage of checking the data blocks begins.

[0123] 3. Second stage: D-block verification (data block error location) After confirming that the check bits are correct (or have been corrected), begin checking data block D.

[0124] The data block written to Flash is encoded and a new check bit is generated. The check bit is then XORed with the error-corrected check bit to obtain the data block symptom.

[0125] Logical judgment: If the data block's comma is all 0 and the global checksum is 0: the data is completely correct.

[0126] If the data block's symmetric bits are all 0 and the global parity bit is 1, it means that only the global parity bit G itself has been flipped, and correcting the G bit is sufficient.

[0127] If the data block synastry is not 0 and the global checksum is 1, it indicates a single-bit error has occurred in data block D. The value of the data block synastry directly corresponds to the address index of the error bit (mapped via ERROR_MAP). Locate the bit and toggle it to correct the error.

[0128] If the data block's symptom is not 0 and the global parity is 0, it indicates that a double-bit error has occurred in the data block (the symptom shows an error, but the global parity shows an even number of errors), and the error cannot be corrected.

[0129] V. Complete Workflow Sequence The entire process is closely coordinated in terms of hardware timing: Encoding timing: The first 64 clock cycles are used to input 32-bit data words and update P1~P11 bit by bit; the 65th cycle calculates the K block and G bits, and outputs the final ECC code to write to Flash.

[0130] Decoding timing: Data is read in and the syndrome is calculated in the first 64 cycles; in the 65th cycle, the global checksum and K-block syndrome are calculated to complete the first stage judgment; in the 66th cycle, the D-block syndrome is calculated to complete the second stage judgment; in the 67th cycle, the error status and location information are output.

[0131] VI. Error Status Output Finally, a 2-digit status code (err_status) is output to indicate the result: 00: No errors, data is normal.

[0132] 01: A 1-bit error has occurred in the data block. The error has been located and can be corrected (output the error location).

[0133] 10: A 1-bit error has occurred in the checksum. It is recommended to update the stored checksum.

[0134] 11: If a 2-bit or higher error occurs, the ECC cannot correct it and an unrecoverable interrupt is triggered.

[0135] VII. Specific numerical examples To illustrate the effectiveness of this mechanism, consider the following scenarios: Single-bit data error: Assume data bit D

[100] is flipped. In the first stage, block K is checked (parity block synastry = 0), but global checksum = 1. In the second stage, the non-zero data block synastry is calculated, the table is looked up to locate index 100, the bit is flipped, and the data is restored.

[0136] P-block error: Assume P5 is flipped. In the first stage, the parity check is calculated to point to P5, and the global parity bit is 1. P5 is directly corrected, and the global parity bit is flipped. The second stage verification passes, and the data is normal.

[0137] Two-bit error: Assume D[0] and D

[100] flip simultaneously. The first stage K-block check passes. The second stage calculates the syndrome of the non-zero data block, but since the global checksum = 0, it is judged as a two-bit error, and the system exits without error correction to prevent false correction.

[0138] The following is an embodiment of a data encoding, error detection and correction method for page-level error checking and correction of Flash memory. This embodiment adopts a composite encoding scheme to expand 8168-bit user data (corresponding to the data block to be protected in the above embodiment) into an 8190-bit codeword (corresponding to the data block, check block and global parity bit in the above embodiment). The three-level parity structure is used to realize the correction of single-bit errors and the detection of double-bit errors.

[0139] I. PageECC Data Structure Definition In this embodiment, the ECC protection unit of the Flash page is defined as 8190 bits (actual storage is aligned to 1024 bytes / 8192 bits, with the extra 2 bits padded with 0). Its physical layout is strictly divided into five regions at the machine level: data block D, check bit P, first parity bit K, global parity bit G, and padding bit PAD.

[0140] Data block D: Occupies bits 1 to 8168 (bit[0] to bit

[8167] ), with a length of 8168 bits (1021 bytes), and is used to store actual user data.

[0141] Check bit P: Occupies bits 8169 to 8181 (bit

[8168] to bit

[8180] ), with a length of 13 bits, denoted as P1 to P13. This is a check bit generated based on the data block polarity check algorithm.

[0142] The first check bit K occupies bits 8182 to 8189 (bit

[8181] to bit

[8188] ), with a length of 8 bits, denoted as K1 to K8. These 8 bits are used for secondary check of the P block using BCH(21,13) code, and are used to protect the check bit itself.

[0143] Global parity bit G: Occupies bit 8190 (bit

[8189] ), with a length of 1 bit. It performs parity checks on all 8189 bits of data in D, P, and K.

[0144] Padding bit PAD: Occupies bits 8191 to 8192 (bit

[8190] to bit

[8191] ), with a length of 2 bits, and is always filled with 0s for byte alignment.

[0145] Inside the machine, corresponding index constants are defined to manage these regions. For example, the starting index of the data is 0, the starting index of the P block is 8168, the starting index of the K block is 8181, the starting index of the G bit is 8189, and the total effective length is 8190 bits.

[0146] II. Encoding Process (Writing to FlashPage) When data needs to be written to Flash, the encoding process begins. The input is 1021 bytes of user data, which is treated as an 8168-bit data stream. It is typically input in 128 cycles of 64-bit words (64 bits per cycle for the first 127 cycles, and only 40 bits are valid in the 128th cycle, with the high 24 bits filled with 0). The output is a 22-bit redundancy check code, including P1~P13, K1~K8, and G, which is finally written to bytes 1021 to 1023 of the Flash page.

[0147] 1. First level: P-block generation (also known as data block polarity-checked coding) A 13-bit parity check (P1-P13) is generated by iterating through each bit of the input data. For each bit of input data, the binary characteristics of its address (addr) determine which parity bits it participates in the calculation.

[0148] P1 covers all data bits where the 0th bit of the address binary is 0 (e.g., address 0, 2, 4...).

[0149] P2 covers all data bits where the first bit of the address binary is 0 (e.g., address 0, 1, 4, 5...).

[0150] This process continues until P13 covers all data bits where the 12th bit of the address binary is 0.

[0151] At the machine level, this means that for each input cycle and each bit within the word, its address index is checked. If the (i-1)th bit of the address is 0, the value of that data bit is XORed with Pi, thereby gradually accumulating to generate values ​​P1 to P13.

[0152] 2. Second level: K-block generation (also known as BCH(21,13) encoding) After generating the P block, the first 8-bit parity bit (K1-K8) is generated using the BCH(21,13) encoding principle to protect the P block.

[0153] Encoding parameters: Code length n=21 (P+K total length), information bits k=13 (P blocks), check bits r=8 (K blocks), minimum distance d_min=4.

[0154] The generating polynomial has coefficients of g(x) [1, 0, 1, 1, 1, 1, 1, 0, 1].

[0155] Machine-level computation: Encoding is performed using an 8-stage shift register (LFSR). Bits P1 through P13 are used as information bits, shifted into the register sequentially from the most significant bit to the least significant bit. During the shift process, an XOR operation is performed based on the feedback tap position of the generator polynomial. After the shift is complete, the remaining 8 bits in the register are K1 through K8.

[0156] 3. Third level: G-bit generation (global parity check) Finally, the global parity bit G is calculated. It is an XOR operation performed on all bits of data block D, all bits of block P, and all bits of block K. The purpose is to ensure that the number of "1"s in the entire 8189-bit valid codeword is even.

[0157] 4. Encoded Output The final 22-bit checksum (P1~P13, K1~K8, G) is combined and written to the end of the Flash page. Specifically, P1~P8 are written to the 1021st byte, P9~P13 and K1~K3 are written to the 1022nd byte, and K4~K8, G, and 2 padding bits are written to the 1023rd byte.

[0158] III. Storage and Retrieval When data is written to Flash, it follows a strict order: first, the user data from bytes 0 to 1020, followed by the checksum from bytes 1021 to 1023.

[0159] During reading, an 8192-bit codeword (including 2 bits of padding) is read at once. Due to the physical characteristics of Flash memory, the read data (received_codeword) may contain bit-flipping errors.

[0160] IV. Decoding and Error Correction Process (Reading Flash Page) The decoding process is a phased logical judgment process designed to identify the location of errors and correct them.

[0161] 1. Pre-calculation: Global checksum First, perform an XOR operation on all 8190 bits of valid data read to generate a new global parity bit. This new global parity bit is then XORed with the received global parity bit to generate a global parity check. If the result is 0, it means that the overall even parity check passed (no errors or an even number of errors); if the result is 1, it means that an odd number of errors occurred.

[0162] 2. First stage: K-block BCH SEC-DED verification (P-block error detection and correction) The parity bits written to Flash are encoded and a new first parity bit is generated. The parity block syntactic is obtained by XORing the newly generated first parity bit with the first parity bit written to Flash.

[0163] First, check the integrity of the parity bit itself. Then, determine whether there is an error in the P or K block by calculating the BCH syndrome (S3, S7, S9).

[0164] Complementary calculation: in GF(2) 6 In a finite field, Horner's rule is used to evaluate the P+K block (21 bits) to calculate three 6-bit syndromes S3, S7, and S9.

[0165] Logical judgment: No errors: If the companion function and global checksum of the supervision block are all 0, it means that the P+K block has no errors and proceeds directly to the second stage.

[0166] Single-bit error: If S3 is not 0, attempt single-bit error localization. Calculate the error location factor X (X0) using algebraic operations. 4 =S7·S3 -1 , X=(X 4 ) 16 And verify whether X satisfies S3=X 3 S7=X 7 S9=X 9 If the verification passes, it indicates a single-bit error. Locate the error position (0~20) based on the value of X, flip the bit to correct the error, and flip the global parity flag G.

[0167] Two-bit or higher error: If S3 is not 0 but the verification fails, or S3 is 0 but S7 / S9 is not 0, it means that two or more errors have occurred, and the error cannot be corrected.

[0168] 3. Second stage: D-block verification (data block error location) After confirming that the check bits are correct (or have been corrected), begin checking data block D.

[0169] The data block written to Flash is encoded and a new check bit is generated. The newly generated check bit and the error-corrected check bit are XORed to obtain the data block syndrome. Logical judgment: No errors: If the data block's comma is all 0 and the global checksum is 0, the data is completely correct.

[0170] G-bit error: If the data block's symmetric bits are all 0 and the global parity bit is 1, it means that only the global parity bit G itself has been flipped, and the G bit can be corrected.

[0171] Single-bit error in data block: If the data block synastry is not 0 and the global checksum is 1, it indicates that a single-bit error has occurred in data block D. The value of the data block synastry directly corresponds to the address index of the error bit through the pre-computed error mapping table (ERROR_MAP). The bit is located and toggled for error correction.

[0172] Data block double-bit error: If the data block symptom is not 0 and the global parity is 0, it means that a double-bit error has occurred in the data block (the symptom shows an error, but the global parity shows an even number of errors), and the error cannot be corrected.

[0173] V. Complete Workflow Sequence The entire process is closely coordinated in terms of hardware timing: Encoding timing: The first 128 clock cycles are used to input 64-bit data words and update P1~P13 bit by bit; in the 129th cycle, K blocks of LFSR encoding are performed to generate K1~K8, G bits are calculated, and the final ECC code is output and written to Flash.

[0174] Decoding timing: Data is read in and the syndrome is calculated in the first 128 cycles; in the 129th cycle, the ecc_code is input, the global checksum and BCH syndrome are calculated, and the first stage judgment is completed; in the 130th cycle, the D block syndrome is calculated, and the second stage judgment is completed; in the 131st cycle, the error status and location information are output.

[0175] VI. Error Status Output Finally, a 2-digit status code (err_status) is output to indicate the result: 00: No errors, data is normal.

[0176] 01: A 1-bit error has occurred in the data block. The error has been located and can be corrected (output the error location).

[0177] 10: A 1-bit error has occurred in the checksum. It is recommended to update the stored checksum.

[0178] 11: If a 2-bit or higher error occurs, the ECC cannot correct it and an unrecoverable interrupt is triggered.

[0179] VII. Specific numerical examples To illustrate the effectiveness of this mechanism, consider the following scenarios: Single-bit data error: Assume data bit D

[500] is flipped. In the first stage, the BCH check passes (parcel block comma = 0), but the global checksum G = 1. In the second stage, the non-zero data block comma is calculated, the table is looked up to locate index 500, the bit is flipped, and the data is restored.

[0180] P-block error: Assume P5 (BCH bit 12) is flipped. In the first stage, the parity block adjoint is calculated, and BCH bit 12 is located through algebraic operations. P5 is directly corrected by flipping the global parity bit. The second stage verification passes, and the data is normal.

[0181] Two-bit error: Assume D[0] and D

[500] flip simultaneously. The first stage BCH check passes. The second stage calculates the syndrome of the non-zero data block, but since the global checksum = 0, it is judged as a two-bit error, and the system exits without error correction to prevent false correction.

[0182] This disclosure also provides a data encoding, error detection and correction method apparatus, the apparatus comprising: a memory and a processor, the memory being configured to store an executable program; The processor is configured to read and execute the executable program, performing the data encoding, error detection, and error correction methods as described in any of the above embodiments.

[0183] This disclosure provides a data encoding, error detection, and error correction circuit integrated into an integrated circuit chip, wherein the data encoding, error detection, and error correction circuit is configured to perform the data encoding, error detection, and error correction method as described in any of the above embodiments.

[0184] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term "computer storage medium" includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A data encoding, error detection, and error correction method, comprising: The encoding and decoding processes are characterized by, The encoding process includes: The data block to be protected is encoded based on the first encoding rule and a check bit is generated. The check bit is then encoded based on the second encoding rule and a first check bit is generated. A supervisory block is constructed based on the generated supervisory bit and the first parity bit, and a global parity check is performed on the data block and the constructed supervisory block to generate a global parity check bit. The decoding process includes: The system receives the data block, check block, and global parity bit after the encoding process is completed. Based on the second encoding rule, it encodes the received check bit and generates a new first parity bit. Based on the newly generated first parity bit and the received first parity bit, and combined with the global parity check, it judges and corrects errors in the received check block, and obtains the corrected check bit. The global parity check is generated based on the received data block, check block, and global parity bit. The received data block is encoded based on the first encoding rule, and a new check bit is generated. Based on the newly generated check bit and the corrected check bit, and combined with the global checksum, errors in the received data block are judged and corrected.

2. The method according to claim 1, characterized in that, The data block includes: N bits of data, and the check bit is P bits, where P satisfies 2^N / P. P The smallest positive integer greater than N-1; Encoding the data block based on the first encoding rule and generating a check bit includes: Obtain all bits of data in the data block whose (i-1)th binary address is 0, and perform an XOR operation on all the obtained bits to obtain the value of the i-th bit in the check bit; i∈[1,P].

3. The method according to claim 1, characterized in that, The second encoding rule includes: Hamming encoding and BCH encoding.

4. The method according to claim 1, characterized in that, The global checksum is obtained in the following way: Perform global parity checking on the received data block and the received check block to obtain a new global parity bit; The global parity bit is obtained based on the new global parity bit and the received global parity bit.

5. The method according to claim 1, 3, or 4, characterized in that, Based on the newly generated first check bit and the received first check bit, and in conjunction with the global checksum, errors in the received supervisory block are judged and corrected, including: Generate a parity block syntactic based on the newly generated first parity bit and the received first parity bit; If the parity block syndrome is not 0 and the global checksum is 1, indicating that the received parity block has an odd number of errors, then it is determined that there is a single bit error in the received parity block. The error location is determined according to the parity block syndrome and error correction is performed. The global checksum is then updated to 0. If the syndrome of the monitoring block is not 0 and the global checksum is 0, indicating that the received monitoring block has an even number of errors, then it is determined that there are uncorrectable multi-bit errors in the received monitoring block, and the global checksum remains unchanged. If the parity of the monitoring block is 0 and the global parity check is 1, it indicates that there is an error in the received global parity check bit, or if there is an odd number of errors in the received data block, the global parity check remains unchanged.

6. The method according to claim 5, characterized in that, Based on the newly generated check bits and the corrected check bits, and combined with the global checksum, errors in the received data blocks are judged and corrected, including: Data block compositing is generated based on the newly generated check bits and the error-corrected check bits; If the syndrome of the data block is not 0 and the global syndrome obtained after error correction by the check block is 1, which indicates that the received data block has an odd number of errors, it is determined that there is a single-bit error in the received data block, and the error position is determined according to the syndrome of the data block to perform error correction; If the syndrome of the data block is not 0 and the global syndrome obtained after error correction by the check block is 0, which indicates that the received data block has an even number of errors, it is determined that there is an uncorrectable multi-bit error in the data block; If the syndrome of the data block is 0 and the global syndrome obtained after error correction by the check block is 1, it is determined that there is an error in the received global parity check bit.

7. The method according to claim 6, characterized in that, Determining the error position according to the syndrome of the data block and performing error correction includes: When it is determined that the syndrome of the data block is not zero, invert the syndrome of the data block, and take the inverted value as the address index of the error bit in the received data block to locate the error position.

8. The method according to claim 2, characterized in that, Encoding the data block based on the first coding rule and generating check bits includes: Dividing the data block into a plurality of data groups, and inputting one of the data groups in each clock cycle; In each clock cycle, for each of the data groups, parallelly calculate the intermediate XOR result corresponding to each bit in the check bits; Obtain the final P check bits based on the intermediate XOR results obtained over a plurality of clock cycles.

9. The method according to claim 8, characterized in that, Said in each clock cycle, for each of the data groups, parallelly calculating the intermediate XOR result corresponding to each bit in the check bits includes: For the first M check bits, select corresponding data bits from the current data group for XOR operation according to the value of the low-order address bit of the current data group, and use the operation result to calculate the intermediate XOR result corresponding to the first M bits in the check bits; For the last P-M check bits, first perform a reduction XOR operation on all data bits of the current data group to obtain a reduction value, then determine whether to use the reduction value to calculate the intermediate XOR result corresponding to the last P-M bits in the check bits according to the value of the high-order address bit of the current data group; M is a positive integer satisfying 1≤M<P.

10. A data encoding, error detection and correction device, characterized in that, The apparatus includes: a memory and a processor, the memory is configured to store an executable program; The processor is configured to read and execute the executable program to perform the data encoding, error detection and error correction method according to any one of claims 1 to 9.

11. A data encoding, error detection, and error correction circuit, integrated into an integrated circuit chip, characterized in that, The data encoding, error detection and error correction circuit is configured to perform the data encoding, error detection and error correction method according to any one of claims 1 to 9.

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