A CPLD-based optical module test bus switching control method, device and medium

Abstract

This invention provides a CPLD-based optical module test bus switching control method, device, and medium, comprising: locking the global system clock and constructing a phase mapping table; obtaining a reference clock line and combining it with the global system clock to obtain a phase offset reference value and write it into the phase mapping table; obtaining a bus switching command to extract pending busy / idle states to determine a stable idle state; obtaining a time offset queue to calculate the real-time phase shift value, and then combining it with the phase mapping table to determine the final phase value and update the phase mapping table; calculating a time compensation amount and mapping it to a delay chain control code; applying a trigger pulse and combining it with the delay chain control code to generate a switching pulse for connection interface switching and enable signal setting; obtaining an acknowledgment signal and combining it with the time compensation amount for switching determination; obtaining the current phase value for threshold comparison; and then writing the delay chain control code into the phase mapping table. This improves the reliability, timing accuracy, and adaptability to phase changes of the optical module test bus switching control method.

Description

Technical Field

[0001] This invention relates to the field of complex programmable circuits, and specifically to a method, device, and medium for switching control of optical module test bus based on CPLD. Background Technology

[0002] In the optical module test bus switching control method, the test equipment needs to quickly switch between multiple optical modules under test to complete parallel or sequential testing. Each optical module is connected to the test equipment through an independent bus. The core is to switch the bus interface of the test equipment master control from the current bus to the target bus so that the master control can establish communication with the target optical module.

[0003] In existing methods, CPLDs are often used as bus switching controllers, mainly focusing on physical layer on / off control. They ignore the random phase offset between different bus reference clock lines and the CPLD system clock, which causes the switching signal's transition edge to fall within the target channel clock's runtime window, leading to metastability and test data misalignment.

[0004] Therefore, there is an urgent need for a CPLD-based optical module test bus switching control method. This method uses a cascaded carry chain within the CPLD to measure the phase offset of the bus reference clock line and establish a phase mapping table. During switching, the switching pulse is phase-modulated based on the measured phase to ensure that the switching pulse is precisely aligned to the low-level center region of the bus clock, thereby achieving timing control and maintenance of the entire bus switching process. Summary of the Invention

[0005] In view of the aforementioned problems, the present invention provides a CPLD-based optical module test bus switching control method, comprising:

[0006] Based on CPLD locking of the global system clock and construction of phase mapping table, the reference clock line is obtained and the time difference is calculated in combination with the global system clock. After extreme value removal and averaging, the phase offset reference value is obtained and written into the phase mapping table.

[0007] Obtain bus switching instructions to extract the pending busy / idle state of the target bus, obtain the two-dimensional level of the target bus and combine it with the pending busy / idle state to determine the idle state, and then configure the TDC phase detector to obtain the time offset queue.

[0008] The real-time phase shift value is obtained by removing the extreme values ​​from the time offset queue and averaging. The drift amount is calculated based on the phase mapping table and combined with the real-time phase shift value. The drift amount is then used to determine the final phase value and update the phase mapping table.

[0009] The time compensation amount is calculated based on the final phase value, converted into a positive delay amount, and mapped to a delay chain control code. A trigger pulse is applied and combined with the delay chain control code to generate a switching pulse. The connection interface is switched and the enable signal is set based on the switching pulse.

[0010] After acquiring the response signal and making a switching determination based on the time compensation amount, the current phase value is obtained through phase fast sampling and compared with the target phase value for a threshold. Then, the delay chain control code is written into the phase mapping table.

[0011] Preferably, based on the CPLD locking of the global system clock and the construction of a phase mapping table, a reference clock line is obtained, and the time difference is calculated in combination with the global system clock. After extreme value removal and averaging, a phase offset reference value is obtained, and the phase offset reference value is written into the phase mapping table, including:

[0012] After obtaining the reference clock, the phase-locked loop in the CPLD is used to multiply the reference clock to obtain the global system clock, and a phase mapping table is constructed through the memory inside the CPLD.

[0013] The time difference is calculated by capturing the rising edge of the reference clock line of each optical module test bus using a CPLD and combining it with the rising edge of the global system clock.

[0014] After acquiring the time difference multiple times for each optical module test bus, sort them, remove the maximum and minimum values, calculate the average value to obtain the phase offset reference value of the corresponding optical module test bus, and write it into the phase mapping table.

[0015] Preferably, the process involves obtaining a bus switching command to extract the pending busy / idle state of the target bus, obtaining the two-dimensional level of the target bus and combining it with the pending busy / idle state to determine idle status, and then configuring a TDC phase detector to obtain a time offset queue, including:

[0016] After obtaining the bus switching command, the target bus to be switched is parsed out from it, and the pending busy / idle status of the target bus to be switched is queried. The pending busy / idle status includes busy status and idle status.

[0017] After obtaining the two-dimensional level including the clock line level and the data line level, the busy / idle state is determined by combining the pending busy / idle state to obtain a stable idle state;

[0018] When the target bus is switched to a stable idle state, a TDC phase detector is configured inside the CPLD to inject the global system clock into the cascade carry chain inside the CPLD.

[0019] After latching the propagation position of the global system clock on the cascade carry chain based on the rising edge of the reference clock line of the switching target bus, the propagation thermometer code is obtained. The propagation thermometer code is then encoded and converted to calculate the original time offset.

[0020] The rising edge of the reference clock line is sampled multiple times for the target bus being switched, and the original time offset is calculated to obtain the corresponding time offset queue.

[0021] Preferably, after acquiring the two-dimensional level including the clock line level and the data line level, the busy / idle state is determined by combining the pending busy / idle state to obtain a stable idle state, including:

[0022] Read the clock line level and data line level of the target bus from the input buffer of the CPLD;

[0023] A glitch filtering window is preset. If the pending busy / idle state of the target bus is idle, and both the clock line level and the data line level are high for a duration exceeding the glitch filtering window, then the target bus is determined to be in a stable idle state.

[0024] If the pending busy / idle state of the target bus being switched becomes busy within the glitch filtering window, or if the clock line level and data line level become low within the glitch filtering window, then the target bus being switched is determined to be in a non-idle state.

[0025] A preset time threshold is set, and busy / idle determination is continuously performed within the time threshold until the target bus is determined to be in a stable idle state. If the target bus remains in a non-idle state within the time threshold, a switching error is output and the switching control process is terminated.

[0026] Preferably, the real-time phase shift value is obtained by averaging the time offset queue after removing extreme values. The drift is calculated based on the phase mapping table and the real-time phase shift value. The drift is then used to determine the final phase value and update the phase mapping table, including:

[0027] After removing the maximum and minimum values ​​of the original time offsets from the time offset queue, the average of the remaining original time offsets is used to obtain the real-time phase shift value of the target bus for the switching.

[0028] Extract the phase offset reference value from the phase mapping table, and calculate the drift amount based on the phase offset reference value and the real-time phase shift value;

[0029] If the first drift threshold is less than the absolute value of the drift, then the real-time phase shift value will be used as the final phase value.

[0030] If the second drift threshold < the absolute value of the drift amount ≤ the first drift threshold, then the weighted average of the phase offset reference value and the real-time phase shift value is taken as the final phase value;

[0031] If the absolute value of the drift is less than or equal to the second drift threshold, then the phase offset reference value will be used as the final phase value.

[0032] The final phase value is used as the new phase offset reference value to update the phase mapping table.

[0033] Preferably, the time compensation amount is calculated based on the final phase value, converted into a positive delay amount, and mapped to a delay chain control code. A trigger pulse is applied and combined with the delay chain control code to generate a switching pulse. Based on the switching pulse, the connection interface is switched and the enable signal is set, including:

[0034] The time compensation amount is calculated by combining the preset target phase value with the final phase value.

[0035] If the time compensation is ≥0, it is taken as the positive delay; if the time compensation is <0, the early trigger flag is recorded, and the positive delay is calculated based on the global system clock and the time compensation.

[0036] The positive delay amount is mapped to a delay chain control code for the CPLD, where the delay chain control code is represented as a digital control word used to control the application of a positive delay amount to the delay chain within the CPLD;

[0037] After obtaining the trigger pulse based on the global system clock and the early trigger flag, a switching pulse is generated by combining the CPLD, the delay chain control code, and the positive delay amount.

[0038] At the rising edge of the switching pulse, the bus interface in the CPLD is connected to the target bus for switching to perform the connection interface switching, and at the same time the bus enable signal of the target bus is set to the active state.

[0039] Preferably, after obtaining the trigger pulse based on the global system clock and the early trigger flag, a switching pulse is generated by combining the CPLD, the delay chain control code, and the positive delay amount, including:

[0040] If an early trigger flag exists, the application time is determined based on the early trigger flag and the global system clock to apply the trigger pulse;

[0041] Otherwise, the application time is determined based on the global system clock to apply the trigger pulse, where the trigger pulse is represented as a pulse signal that initiates the physical connection switching;

[0042] The trigger pulse is input into the delay chain configured with the delay chain control code in the CPLD. The delay chain applies a positive delay to the trigger pulse to obtain the switching pulse.

[0043] Preferably, after acquiring the response signal and performing a switching determination based on the time compensation amount, the current phase value is obtained through phase fast sampling and compared with the target phase value to a threshold. Then, the delay chain control code is written into the phase mapping table, including:

[0044] The target bus is continuously monitored by the CPLD. If an acknowledgment signal is detected within the preset verification window, the delay chain control code is written into the phase mapping table.

[0045] If no response signal is detected within the verification window, multiple candidate compensation values ​​are generated to both sides of the time compensation value as the center point according to the preset steps. Then, the switching pulse is regenerated based on the candidate compensation values, and the connection interface is switched and the enable signal is set.

[0046] Continuously monitor the response signals of each candidate compensation quantity, and write the delay chain control code of the candidate compensation quantity corresponding to the first captured response signal into the phase mapping table;

[0047] If no response signal is captured for any of the candidate compensation quantities, a switching bus fault is output and the current switching control process is terminated.

[0048] The current phase value is obtained by fast phase sampling and the phase difference is calculated by combining it with the final phase value. If the absolute value of the phase difference is greater than the phase threshold, the delay chain control code is corrected based on the phase difference and written into the phase mapping table; otherwise, no processing is performed.

[0049] In a second aspect, the present invention also provides a computer-readable storage medium, characterized in that it is used to store a computer program, which, when executed by a processor, implements the aforementioned CPLD-based optical module test bus switching control method.

[0050] In another aspect, the present invention also provides a computer device, characterized in that the computer device includes a processor and a memory, the memory storing a computer program that can run on the processor, and the processor executing the computer program to implement the aforementioned CPLD-based optical module test bus switching control method.

[0051] Compared with the prior art, the present invention has the following beneficial effects:

[0052] This method measures the phase offset of the test bus of each optical module through the cascaded carry chain inside the CPLD to determine the phase offset reference value, so that the CPLD can obtain the phase information of the target bus when performing bus switching, thus eliminating the influence of random phase offset between different bus reference clock lines and the CPLD system clock on the switching timing.

[0053] By combining bus edge activity detection with real-time level reading from the CPLD through a bus idle determination mechanism, and setting a glitch filtering window to confirm the duration of level stability, the target bus is ensured to be in a true stable idle state before switching. At the same time, the drift amount is determined by dual threshold judgment to obtain the final phase value, which is then converted into a delay chain control code to modulate the phase of the switching pulse. This ensures that the switching pulse is precisely aligned to the low-level center region of the target bus clock, avoiding metastability and data misalignment caused by the switching signal transition edge falling into the target clock running time window.

[0054] The phase compensation effect is verified by listening to the response signal of the target bus. At the same time, after a successful switch, the current phase of the target bus is collected and compared with the final phase value to correct the delay chain control code and write it into the phase mapping table. This ensures that the phase compensation accuracy is always in the optimal state during the test, and improves the reliability, timing accuracy and adaptability to phase changes of the optical module test bus switching control method. Attached Figure Description

[0055] Figure 1 This is a schematic diagram illustrating the steps of a CPLD-based optical module test bus switching control method provided in an embodiment of the present invention;

[0056] Figure 2 This is a flowchart of a CPLD-based optical module test bus switching control method provided in an embodiment of the present invention. Detailed Implementation

[0057] The present invention will now be described in detail with reference to the specification and accompanying drawings. Figure 1 This is a schematic diagram illustrating the steps of a CPLD-based optical module test bus switching control method provided in an embodiment of the present invention. Figure 2 This is a flowchart of a CPLD-based optical module test bus switching control method provided in an embodiment of the present invention.

[0058] Specifically, a CPLD-based optical module test bus switching control method includes the following steps:

[0059] Step S1: Lock the global system clock based on CPLD and construct a phase mapping table. Obtain the reference clock line and calculate the time difference with the global system clock. Then perform extreme value removal and averaging to obtain the phase offset reference value. Write the phase offset reference value into the phase mapping table.

[0060] In this embodiment, step S1 specifically includes steps S1-1 to S1-3:

[0061] Step S1-1: After obtaining the reference clock, the reference clock is multiplied using the phase-locked loop in the CPLD to obtain the global system clock, and a phase mapping table is constructed through the memory inside the CPLD.

[0062] Specifically, after the CPLD is powered on, the reference clock is first acquired, and then the phase-locked loop in the CPLD is used to multiply the reference clock, for example, multiplying the reference clock to 200MHz, in order to obtain a stable global system clock.

[0063] After acquiring the global system clock, a phase mapping table is constructed using the memory inside the CPLD. The phase mapping table is represented as a lookup table structure for storing test bus data of each optical module, wherein each optical module test bus corresponds to a storage unit in the phase mapping table.

[0064] Step S1-2: After capturing the rising edge of the reference clock line of each optical module test bus using the CPLD, calculate the time difference by combining it with the rising edge of the global system clock.

[0065] The CPLD continuously captures the rising edge of the reference clock line corresponding to the test bus of each optical module through the edge detection circuit inside the CPLD. The reference clock line is the clock signal line used for synchronous data transmission between the CPLD and the optical module.

[0066] When the rising edge of the reference clock line is detected, it is latched, and the rising edge of the global system clock is recorded. The difference between the rising edge of the reference clock line and the rising edge of the global system clock is calculated as the time difference of the corresponding optical module test bus. It is understandable that due to the differences in physical trace length, input capacitance, etc. of each optical module test bus, there are different phase offsets between the reference clock line and the global system clock of each optical module test bus. Therefore, it is necessary to calculate the time difference to characterize the offset of the two clock signals in the phase dimension.

[0067] Step S1-3: After acquiring the time difference of each optical module test bus multiple times, sort them, remove the maximum and minimum values, calculate the average value to obtain the phase offset reference value of the corresponding optical module test bus, and write it into the phase mapping table.

[0068] The time difference calculation process of step S1-2 is repeated for each optical module test bus. For example, the time difference is obtained 8 times to form a set of time difference sequences for the corresponding optical module test bus. The time difference sequence is arranged from largest to smallest, and the maximum and minimum values ​​are removed. The average of the remaining time differences is used as the phase offset reference value for the corresponding optical module test bus to eliminate random noise and occasional interference that may be introduced by a single time difference calculation. The phase offset reference value is written into the corresponding position of the phase mapping table.

[0069] Understandably, there is no fixed phase relationship between the reference clock line of each optical module and the global system clock in the optical module test bus. The phase difference is random and drifts with temperature. Therefore, it is necessary to calculate the phase offset reference value of each optical module test bus and store it in a pre-built phase mapping table.

[0070] Step S1 establishes a phase reference mapping relationship between the test bus reference clock line of each optical module and the global system clock through phase-locked loop frequency multiplication and extreme value removal averaging in the CPLD, and quantifies it into a storable, comparable and compensable phase offset reference value, providing a data reference for subsequent steps and significantly improving the phase accuracy of bus switching control.

[0071] Step S2: Obtain bus switching instructions to extract the pending busy / idle state of the target bus, obtain the two-dimensional level of the target bus and combine it with the pending busy / idle state to determine the idle state, and then configure the TDC phase detector to obtain the time offset queue.

[0072] In this embodiment, step S2 specifically includes steps S2-1 to S2-5:

[0073] Step S2-1: After obtaining the bus switching instruction, parse out the target bus to be switched and query the pending busy / idle status of the target bus. The pending busy / idle status includes busy status and idle status.

[0074] The test equipment receives a bus switching command from its main control unit. The bus switching command is represented by a control word that includes at least the number of the target bus to be switched. The target bus to be switched is extracted from the bus switching command. At the same time, the edge activity of the target bus to be switched is detected to determine its pending busy / idle state. When edge activity is detected, the busy state is taken as the pending busy / idle state of the corresponding target bus to be switched. When no edge activity is detected, the idle state is taken as the pending busy / idle state of the corresponding target bus to be switched. Edge activity is represented by a signal transition that occurs on the target bus to be switched.

[0075] Step S2-2: After obtaining the two-dimensional level including the clock line level and the data line level, combine it with the pending busy / idle state to determine the busy / idle state and obtain a stable idle state.

[0076] Specifically, step S2-2 includes steps S2-2-1 to S2-2-4:

[0077] Step S2-2-1: Read the clock line level and data line level of the target bus from the input buffer of the CPLD.

[0078] Specifically, the CPLD reads the clock line level and data line level of the target bus through the input buffer of its I / O pins. The clock line is a physical line used to carry synchronous clock signals, and the clock line level represents the real-time logic level of the clock signal line of the target bus. The data line is a physical line used to carry serial data, and the data line level represents the real-time logic level of the data signal line of the target bus. The clock line level and data line level together reflect the current actual communication occupancy status of the target bus.

[0079] It should be noted that the input buffer converts the voltage signal from the external pin into a logic signal. When the voltage signal from the external pin is higher than the high-level input threshold, the input buffer outputs logic 1 to indicate that the corresponding clock line level or data line level is high. When the voltage signal from the external pin is lower than the low-level input threshold, the input buffer outputs logic 0 to indicate that the corresponding clock line level or data line level is low. The high-level input threshold and the low-level input threshold are electrical characteristic parameters of the input buffer within the CPLD. The specific values ​​are subject to the datasheet of the selected CPLD. For example, for a 3.3V powered CPLD, the high-level input threshold is approximately 2.31V and the low-level input threshold is approximately 0.99V.

[0080] Step S2-2-2: Set a glitch filtering window. If the pending busy / idle state of the target bus is idle, and both the clock line level and the data line level are high for a duration exceeding the glitch filtering window, then the target bus is determined to be in a stable idle state.

[0081] The glitch filtering window is preset based on the global system clock cycle of the CPLD and the signal noise characteristics of the optical module test bus. For example, in a specific embodiment, the global system clock is 200MHz, and the corresponding global system clock cycle is calculated to be 5ns. The typical signal noise value of the optical module test bus is between 5ns and 15ns. Therefore, the glitch filtering window can be preset to 4 global system clock cycles, which is 20ns, to meet the condition that the length of the glitch filtering window must be an integer multiple of the global system clock cycle and greater than the typical signal noise value.

[0082] If the pending busy / idle state of the target bus is idle and the duration exceeds the glitch filtering window, and both the clock line level and the data line level are high and the duration exceeds the glitch filtering window, then the target bus is considered to be in a stable idle state.

[0083] Understandably, since the pending busy / idle status may have update delays or fail to reflect instantaneous level jitter, the pending busy / idle status alone is insufficient to confirm that the target bus has entered a stable idle state. However, by reading the clock line level and data line level from the CPLD input buffer and combining them with the pending busy / idle status, the busy / idle determination result can be made more reliable.

[0084] Step S2-2-3: If the pending busy / idle state of the target bus being switched is busy within the glitch filtering window, or if the clock line level and data line level are low within the glitch filtering window, then the target bus being switched is determined to be in a non-idle state.

[0085] If the pending busy / idle state of the target bus is busy within the glitch filtering window, or if the clock line level and data line level are low within the glitch filtering window, it indicates that there is edge activity or data transmission is in progress on the target bus. Therefore, the target bus does not currently meet the conditions for safe switching, and the target bus is determined to be in a non-idle state.

[0086] Step S2-2-4: Set a time threshold and continuously determine whether the bus is busy or idle within the time threshold until the target bus is determined to be in a stable idle state. If the target bus remains in a non-idle state within the time threshold, output a switching error and terminate the current switching control process.

[0087] The time threshold is preset according to the maximum transmission time of a single frame of the optical module test bus. For example, if the maximum transmission time of a single frame of a certain optical module test bus is 200μs, the time threshold can be set to 1.5 times its maximum transmission time of a single frame, that is, 300μs, to ensure that normal communication frame transmission will not be mistakenly judged as timeout.

[0088] Within this time threshold, the pending busy / idle state, clock line level, and data line level of the target bus are continuously detected to perform the busy / idle determination process from step S2-2-2 to step S2-2-3 until the target bus is determined to be in a stable idle state.

[0089] If the target bus is not determined to be in a stable idle state within the time threshold, it is considered that the target bus is abnormal or continuously busy and cannot complete the switching control preparation within a reasonable time. In this case, a switching error is output and the switching control process is terminated.

[0090] Step S2-3: When the target bus is switched to a stable idle state, configure the TDC phase detector inside the CPLD to inject the global system clock into the cascade carry chain inside the CPLD.

[0091] When the target bus is switched to a stable idle state, a TDC phase detector is configured inside the CPLD. The TDC phase detector is a high-precision time measurement circuit implemented based on the cascaded carry chain inside the CPLD.

[0092] After the TDC phase detector is configured, the global system clock is injected into the cascade carry chain inside the CPLD through the TDC phase detector, and the global system clock propagates step by step along the cascade carry chain.

[0093] Step S2-4: After latching the propagation position of the global system clock on the cascade carry chain based on the rising edge of the reference clock line of the target bus, the propagation thermometer code is obtained. The propagation thermometer code is encoded and converted to calculate the original time offset.

[0094] After the global system clock propagates step by step along the cascade carry chain, the rising edge of the reference clock line corresponding to the target bus is used as the latching time. The current position of the global system clock signal propagated on the cascade carry chain is latched. Since the global system clock flips and sets the carry units connected in series in the cascade carry chain to 1 when it propagates in the cascade carry chain, the state of the cascade carry chain at the latching time shows the characteristic of being arranged sequentially from flipped to unflipped. The latching result is represented as a string of thermometer code, which is the propagation thermometer code, such as 111111100000.

[0095] The transmitted thermometer code is converted into binary code to obtain a corresponding numerical value, which serves as the original time offset for the target bus being switched. The conversion formula is as follows:

[0096] ;

[0097] in, Represented as the original time offset, This is represented by the number of consecutive 1s in the propagation thermometer code. It is represented as the carry unit step size that propagates step by step in the cascaded carry chain.

[0098] Understandably, the original time offset is represented as the quantized value of the time difference between the rising edge of the reference clock line and the rising edge of the global system clock in the cascade carry chain delay dimension.

[0099] Step S2-5: Multiple times sample the rising edge of the reference clock line of the target bus and calculate the original time offset to obtain the corresponding time offset queue.

[0100] Repeat steps S2-3 to S2-4 for the target bus to acquire the reference clock line rising edge and calculate the original time offset. For example, repeat 8 times. Arrange the original time offsets obtained from multiple calculations in the order of acquisition to form the time offset queue corresponding to the target bus to be switched.

[0101] Through the above operations, the dual confirmation of the pending busy / idle status of the target bus before the switching control process is executed, and the high-precision sampling of the phase relationship of the reference clock line based on the TDC phase detector and cascaded carry chain is achieved. This overcomes the limitations of relying solely on a single busy / idle flag for switching judgment, which is prone to switching conflicts due to the target bus not actually being idle. At the same time, the cascaded carry chain structure enables the measurement of the original time offset with a accuracy far exceeding that of ordinary counters.

[0102] Step S3: After removing the extreme values ​​from the time offset queue, the real-time phase shift value is obtained. The drift amount is calculated based on the phase mapping table and combined with the real-time phase shift value. The drift amount is then used to determine the final phase value and update the phase mapping table.

[0103] In this embodiment, step S3 specifically includes steps S3-1 to S3-6:

[0104] Step S3-1: After removing the maximum and minimum values ​​of the original time offsets in the time offset queue, the average of the remaining original time offsets is taken to obtain the real-time phase shift value of the target bus for the switching.

[0105] The raw time offsets in the time offset queue are sorted from largest to smallest. After removing the maximum and minimum values ​​to eliminate extreme outliers, the arithmetic mean of the remaining raw time offsets is calculated to obtain the real-time phase shift value of the corresponding switching target bus. The real-time phase shift value represents the actual measured phase offset between the reference clock line of the switching target bus and the global system clock at the current moment.

[0106] Step S3-2: Extract the phase offset reference value from the phase mapping table, and calculate the drift amount based on the phase offset reference value and the real-time phase shift value.

[0107] After extracting the phase offset reference value of the target bus from the phase mapping table, the drift amount of the corresponding target bus is calculated based on the phase offset reference value and the real-time phase shift value. The calculation formula is as follows:

[0108] ;

[0109] in, Expressed as drift amount, Represented as real-time phase shift value, The drift is expressed as a phase offset reference value. The drift amount is used to characterize the degree of change of the real-time phase shift value of the switching target bus relative to its phase offset reference value. The larger the drift amount, the more significant the phase offset of the switching target bus.

[0110] Step S3-3: If the first drift threshold is less than the absolute value of the drift amount, then the real-time phase shift value is taken as the final phase value.

[0111] Based on the delay characteristics of the cascaded carry chain within the CPLD, a first drift threshold and a second drift threshold are preset. For example, the first drift threshold can be set to a carry unit step size of 16 carry units to determine abnormal phase changes, and the second drift threshold can be set to a carry unit step size of 4 carry units to determine normal phase drift.

[0112] If the first drift threshold is less than the absolute value of the drift, it indicates that the current phase relationship of the corresponding target bus has deviated significantly from the phase offset reference value. This may be due to phase shift caused by factors such as changes in ambient temperature or device aging. In this case, the phase offset reference value has lost its reference significance, so the real-time phase shift value is used as the final phase value.

[0113] Step S3-4: If the second drift threshold < the absolute value of the drift amount ≤ the first drift threshold, then the weighted average of the phase offset reference value and the real-time phase shift value is taken as the final phase value.

[0114] If the second drift threshold < the absolute value of the drift amount ≤ the first drift threshold, it indicates that the current phase relationship of the corresponding target bus has changed slowly relative to the phase offset reference value. This change may be caused by slow temperature drift or slow power supply voltage change, which is a normal phase offset. In this case, the phase offset reference value and the real-time phase shift value are weighted and averaged to obtain the final phase value.

[0115] In a specific embodiment, the weighting coefficient of the phase offset reference value is set to 0.7, and the weighting coefficient of the real-time phase shift value is set to 0.3, so that the final phase value retains the offset reference while changing slowly according to the current phase offset, avoiding sudden changes in the final phase value due to single noise.

[0116] Step S3-5: If the absolute value of the drift amount is less than or equal to the second drift threshold, then the phase offset reference value is taken as the final phase value.

[0117] If the absolute value of the drift is less than or equal to the second drift threshold, it indicates that the change in the current phase relationship of the corresponding target bus relative to the phase offset reference value is extremely small. This change is insufficient to affect the switching control process, so the phase offset reference value is used as the final phase value.

[0118] Step S3-6: Use the final phase value as the new phase offset reference value to update the phase mapping table.

[0119] The final phase value corresponding to each switching target bus is used as the new phase offset reference value and written into the corresponding storage unit of the phase mapping table to replace the original phase offset reference value, thus completing the update of the phase mapping table.

[0120] The extreme value averaging and drift determination mechanism in step S3 suppresses single random noise while achieving differentiated control of the update amplitude of the phase mapping table. That is, the larger the drift, the more timely the update, and the smaller the drift, the more conservative the update. This overcomes the limitations of fixed periodic full update leading to noise or long-term non-update causing the phase offset reference to decouple from the current phase relationship, and provides a final phase value that is both stable and timely for subsequent steps.

[0121] Step S4: Calculate the time compensation amount based on the final phase value, convert it into a positive delay amount and map it into a delay chain control code. Apply a trigger pulse and generate a switching pulse in combination with the delay chain control code. Based on the switching pulse, switch the connection interface and set the enable signal.

[0122] In this embodiment, step S4 specifically includes steps S4-1 to S4-5:

[0123] Step S4-1: After setting the target phase value, calculate the time compensation amount by combining it with the final phase value.

[0124] The target phase value is preset according to the global system clock cycle. For example, if the global system clock with a frequency of 200MHz corresponds to a cycle of 5ns, the target phase value can be preset to 2.5ns, which is half of the global system clock cycle. Switching at this point can maintain the maximum setup time and sufficient time margin between the rising edge of the switching pulse and the edge of the global system clock, ensuring that the switching control process is completed within the most stable window.

[0125] The difference between the target phase value and the final phase value is calculated as the time compensation amount for the corresponding target bus switching. The time compensation amount is the phase offset amount required to adjust the final phase of the target bus switching to the target phase. Its positive or negative sign can be used for subsequent direction adjustment.

[0126] Step S4-2: If the time compensation amount is ≥0, then it is taken as the positive delay amount; if the time compensation amount is <0, then the early trigger flag is recorded, and the positive delay amount is calculated based on the global system clock and the time compensation amount.

[0127] It is understandable that when the time compensation amount is ≥0, it indicates that the final phase of the target bus is before the target phase. In this case, there is no need to trigger in advance, and the time compensation amount is directly used as the positive delay amount.

[0128] When the time compensation amount is less than 0, it indicates that the final phase of the target bus being switched is after the target phase. Since the delay chain in the CPLD only supports positive delay and does not have negative delay capability, this method adopts the approach of advancing the final phase by one full global system clock cycle. Therefore, the corresponding target bus being switched is given an advance trigger flag, and the sum of the time compensation amount and the global system clock cycle is used as the positive delay amount.

[0129] Step S4-3: Map the positive delay amount to a delay chain control code for the CPLD, wherein the delay chain control code is a digital control word used to control the application of a positive delay amount to the delay chain within the CPLD.

[0130] Specifically, since the delay chain within the CPLD is composed of multiple delay units connected in series, and each delay unit has the same and fixed delay unit step size, the following mapping method is obtained: the positive delay amount is divided by the delay unit step size and then rounded down to obtain the delay unit level. Then, the delay unit level is converted into binary code and used as the delay chain control code of the corresponding CPLD on the target bus. The delay chain control code is represented as a digital control word used to control the delay chain within the CPLD to apply a positive delay amount.

[0131] For example, in a specific embodiment, the delay chain of the CPLD consists of 1024 delay units connected in series, with each delay unit having a delay unit step size of 10 ps. Therefore, the delay chain control code is a 10-bit binary number. If the forward delay is 10 ps, ​​the delay unit level is calculated as 10 divided by 10, resulting in 1, and the corresponding delay chain control code is 0000000001. If the forward delay is 98 ps, the delay unit level is calculated as 98 divided by 10, resulting in 9.8, which is rounded down to 9, and the corresponding delay chain control code is 0000001001. If the forward delay is 10230 ps, ​​the delay unit level is calculated as 10230 divided by 10, resulting in 1023, and the corresponding delay chain control code is 1111111111.

[0132] It should be noted that if the positive delay exceeds the adjustable range of the CPLD, an alarm flag indicating insufficient phase compensation will be triggered.

[0133] Step S4-4: After obtaining the trigger pulse based on the global system clock and the early trigger flag, generate a switching pulse by combining the CPLD, delay chain control code and positive delay amount.

[0134] Specifically, step S4-4 includes steps S4-4-1 to S4-4-3:

[0135] Step S4-4-1: If an early trigger flag exists, the application time is determined based on the early trigger flag and the global system clock to apply the trigger pulse.

[0136] If an early trigger flag exists, the rising edge preceding the current rising edge of the global system clock is selected as the application time, and a trigger pulse is applied at that application time by the pulse generator within the CPLD.

[0137] Step S4-4-2: Otherwise, determine the application time based on the global system clock to apply the trigger pulse, where the trigger pulse is represented as a pulse signal that initiates the physical connection switching.

[0138] If there is no early trigger flag, the current rising edge of the global system clock is selected as the application time, and a trigger pulse is applied at this application time by the pulse generator in the CPLD. The trigger pulse is represented by the pulse signal that starts the physical connection switching.

[0139] Step S4-4-3: Input the trigger pulse into the delay chain configured with the delay chain control code in the CPLD. The delay chain applies a positive delay to the trigger pulse to obtain the switching pulse.

[0140] The trigger pulse is input into the corresponding CPLD, which is configured with a delay chain control code. The delay chain applies a positive delay to the trigger pulse through the delay chain control code and then uses it as a switching pulse. The switching pulse represents the actual switching control signal after positive delay compensation. Its edge time is strictly aligned with the phase of the target bus, which is equivalent to aligning the trigger pulse to the target phase value.

[0141] Step S4-5: On the rising edge of the switching pulse, connect the bus interface in the CPLD to the target bus to switch the connection interface, and at the same time set the bus enable signal of the target bus to the active state.

[0142] The rising edge of the switching pulse is used as the trigger signal. The bus interface inside the CPLD is connected to the I / O pin of the target bus to switch the connection interface through the multiplexer inside the CPLD. The input of the multiplexer is connected to the bus interface inside the CPLD, and the output is connected to the I / O pin corresponding to each optical module test bus. Only one optical module test bus is connected at any given time.

[0143] At the same time, when the rising edge of the switching pulse arrives, the bus enable signal of the target bus is set to an active state, such as a high level, so that the target bus enters the available mode. It can be understood that the rising edge of the switching pulse has been strictly aligned with the target phase value of the target bus. Therefore, the transient disturbances generated when switching the connection interface and setting the enable signal are all within the stable idle state of the target bus and will not interfere with the normal operation of the target bus.

[0144] Step S4 is the key execution step of the entire method. It takes the final phase value as input and calculates the time compensation amount to determine the positive delay amount in combination with the target phase value. Then, it maps the positive delay amount to a delay chain control code and applies it to the delay chain in the CPLD. Finally, it determines the switching pulse by using the advance trigger flag and the delay chain to perform connection interface switching and enable signal setting. This overcomes the limitation that the delay chain in the CPLD can only apply positive delay. It realizes phase compensation for lagging and leading phase scenarios based solely on the native positive delay capability of the CPLD, without introducing additional negative delay hardware, and avoids interference of connection interface switching and enable signal setting on the normal operation of the target bus.

[0145] Step S5: After obtaining the response signal and making a switching determination based on the time compensation amount, the current phase value is obtained through phase fast sampling and compared with the target phase value for a threshold. Then, the delay chain control code is written into the phase mapping table.

[0146] In this embodiment, step S5 specifically includes steps S5-1 to S5-5:

[0147] Step S5-1: Continuously monitor the target bus switching via CPLD. If an acknowledgment signal is detected within the preset verification window, write the delay chain control code into the phase mapping table.

[0148] Based on the response delay of the optical module and the internal signal propagation delay of the CPLD, a verification window is preset. For example, if the response time of the optical module to return an acknowledgment signal after receiving a command is 50ns to 100ns, and the internal signal propagation delay of the CPLD is 20ns, the verification window can be set to twice the sum of the upper limit of the optical module's response delay and the internal signal propagation delay of the CPLD, i.e., 240ns, so as to effectively capture the acknowledgment signal and avoid missed detection due to fluctuations in response delay.

[0149] The input buffer in the CPLD continuously monitors the data line of the target bus to be switched and detects whether an acknowledgment signal is received within the verification window. If an acknowledgment signal is detected within the preset verification window, it indicates that the connection interface has been successfully switched. At this time, the delay chain control code is written into the phase mapping table to the memory unit corresponding to the target bus to be switched.

[0150] Step S5-2: If no response signal is detected in the verification window, multiple candidate compensation values ​​are generated to both sides with the time compensation value as the center point and the preset steps are followed by regenerating the switching pulse based on the candidate compensation values ​​and switching the connection interface and setting the enable signal.

[0151] If no response signal is detected in the verification window, it indicates that the time compensation amount used in this connection interface switching has failed to accurately align with the target phase value of the target bus. At this time, with the time compensation amount as the center point, multiple candidate compensation amounts are generated on both sides of the center point according to the preset steps. For example, three candidate compensation amounts are generated on both sides of the center point. In order of distance from the center point from near to far, the process of generating switching pulses, switching connection interfaces, and setting enable signals in step S4 is repeated for each candidate compensation amount. The candidate compensation amount is represented as multiple alternative compensation values ​​generated on both sides according to the preset steps based on the time compensation amount.

[0152] It should be noted that the specific value of the preset step is set according to the jitter characteristics of the optical module. For example, if the jitter tolerance of the optical module is large, the preset step can be set to 200ps; if the jitter tolerance of the optical module is small, the preset step can be set to 150ps. However, it must be ensured that the specific value of the preset step is an integer multiple of the step size of the corresponding delay unit of the delay chain in the CPLD.

[0153] Step S5-3: Continuously monitor the response signals of each candidate compensation quantity, and write the delay chain control code of the candidate compensation quantity corresponding to the first captured response signal into the phase mapping table.

[0154] After the current candidate compensation quantity completes the connection interface switching and the enable signal is set, the input buffer in the CPLD continuously monitors the data line of the target bus to be switched, detects whether an acknowledgment signal is received within the verification window, and writes the delay chain control code of the candidate compensation quantity corresponding to the first captured acknowledgment signal into the storage unit corresponding to the target bus in the phase mapping table.

[0155] If the current candidate compensation amount does not capture a response signal within the verification window, then jump to the next candidate compensation amount in order of distance from the center point from the nearest to the farthest. Understandably, prioritizing the candidate compensation amount that is closest to the time compensation amount in order of distance from the center point from the nearest to the farthest can minimize the phase offset while finding the candidate compensation amount.

[0156] Step S5-4: If no response signal is captured for any of the candidate compensation quantities, output a switching bus fault and terminate the current switching control process.

[0157] If all candidate compensation quantities fail to capture an acknowledgment signal within the verification window after completing the connection interface switching and setting the enable signal, it indicates that the physical link of the target bus is faulty and cannot be restored to normal operation by switching to the target bus. At this time, a bus fault is output and the current switching control process is terminated.

[0158] Step S5-5: Obtain the current phase value through phase fast sampling and calculate the phase difference value in combination with the final phase value. If the absolute value of the phase difference value is greater than the phase threshold, then correct the delay chain control code based on the phase difference value and write it into the phase mapping table; otherwise, no processing is performed.

[0159] After writing the delay chain control code into the phase mapping table to switch the corresponding storage unit of the target bus, the target bus is fast sampled at a preset fast sampling period to obtain its current phase value. The fast sampling period is preset based on the phase drift tracking accuracy requirements. For example, in a certain optical module test scenario, the temperature change rate is less than 1℃ / s, and the phase drift caused by each ℃ temperature change is about 500ps. If the temperature drift tracking accuracy requirement is high, the fast sampling period can be set to 100ms to ensure that at least one phase sampling can be completed when the temperature changes by 0.1℃. If the temperature drift tracking accuracy requirement is low, the fast sampling period can be set to 200ms to further reduce power consumption.

[0160] Specifically, a phase threshold is preset based on the carry unit step size of the cascaded carry chain within the CPLD. For example, the phase threshold is set to a 4-level carry unit step size to distinguish between the actual phase drift and the influence of measurement noise. Then, the difference between the current phase value and the target phase value is calculated as the phase difference value. If the absolute value of the phase difference value is less than or equal to the phase threshold, it indicates that the phase drift is within an acceptable range. At this time, no operation is required, and the current delay chain control code is maintained.

[0161] If the absolute value of the phase difference is greater than the phase threshold, it indicates that the phase drift is significant and the delay chain control code needs to be corrected. At this time, the positive delay amount and the phase difference are summed and divided by the delay unit step size and rounded down to obtain the delay unit level. The delay unit level is then converted into the delay chain control code through the binary encoding conversion method in step S4-3. The delay chain control code is then written into the phase mapping table to switch the memory unit corresponding to the target bus.

[0162] This method, through the coordinated operation of the above five steps, constructs a bus switching control method that ranges from global system clock locking and phase offset reference value calibration, dual confirmation of busy / idle status and phase drift filtering correction, to precise delay chain compensation and switching pulse generation, response signal detection and phase fast sampling tracking. It elevates the CPLD-based optical module test bus switching control from fixed delay or simple busy / idle judgment to refined timing control based on high-precision timing measurement and delay chain phase compensation using CPLD cascade carry chains. This effectively avoids switching failures or operational anomalies caused by bus phase drift, misjudgment of busy / idle status, and switching timing deviations, improving the reliability, timing accuracy, and adaptive capability to phase changes of bus switching.

[0163] In addition, the present invention also provides a computer-readable storage medium, characterized in that it is used to store a computer program, which, when executed by a processor, implements the aforementioned CPLD-based optical module test bus switching control method.

[0164] In another aspect, the present invention also provides a computer device, characterized in that the computer device includes a processor and a memory, the memory storing a computer program that can run on the processor, and the processor executing the computer program to implement the aforementioned CPLD-based optical module test bus switching control method.

[0165] In summary, the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A CPLD-based optical module test bus switching control method, characterized in that, include: Based on CPLD locking of the global system clock and construction of phase mapping table, the reference clock line is obtained and the time difference is calculated in combination with the global system clock. After extreme value removal and averaging, the phase offset reference value is obtained and written into the phase mapping table. Obtain bus switching instructions to extract the pending busy / idle state of the target bus, obtain the two-dimensional level of the target bus and combine it with the pending busy / idle state to determine the idle state, and then configure the TDC phase detector to obtain the time offset queue. The real-time phase shift value is obtained by removing the extreme values ​​from the time offset queue and averaging. The drift amount is calculated based on the phase mapping table and combined with the real-time phase shift value. The drift amount is then used to determine the final phase value and update the phase mapping table. The time compensation amount is calculated based on the final phase value, converted into a positive delay amount, and mapped to a delay chain control code. A trigger pulse is applied and combined with the delay chain control code to generate a switching pulse. The connection interface is switched and the enable signal is set based on the switching pulse. After acquiring the response signal and making a switching determination based on the time compensation amount, the current phase value is obtained through phase fast sampling and compared with the target phase value for a threshold. Then, the delay chain control code is written into the phase mapping table.

2. The CPLD-based optical module test bus switching control method according to claim 1, characterized in that, Based on CPLD locking of the global system clock and construction of a phase mapping table, a reference clock line is obtained, and the time difference is calculated in conjunction with the global system clock. After extreme value removal and averaging, a phase offset reference value is obtained and written into the phase mapping table, including: After obtaining the reference clock, the phase-locked loop in the CPLD is used to multiply the reference clock to obtain the global system clock, and a phase mapping table is constructed through the memory inside the CPLD. The time difference is calculated by capturing the rising edge of the reference clock line of each optical module test bus using a CPLD and combining it with the rising edge of the global system clock. After acquiring the time difference multiple times for each optical module test bus, sort them, remove the maximum and minimum values, calculate the average value to obtain the phase offset reference value of the corresponding optical module test bus, and write it into the phase mapping table.

3. The CPLD-based optical module test bus switching control method according to claim 1, characterized in that, Obtain bus switching instructions to extract the pending busy / idle state of the target bus, acquire the two-dimensional level of the target bus and combine it with the pending busy / idle state to determine idle status, then configure the TDC phase detector to obtain the time offset queue, including: After obtaining the bus switching command, the target bus to be switched is parsed out from it, and the pending busy / idle status of the target bus to be switched is queried. The pending busy / idle status includes busy status and idle status. After obtaining the two-dimensional level including the clock line level and the data line level, the busy / idle state is determined by combining the pending busy / idle state to obtain a stable idle state; When the target bus is switched to a stable idle state, a TDC phase detector is configured inside the CPLD to inject the global system clock into the cascade carry chain inside the CPLD. After latching the propagation position of the global system clock on the cascade carry chain based on the rising edge of the reference clock line of the switching target bus, the propagation thermometer code is obtained. The propagation thermometer code is then encoded and converted to calculate the original time offset. The rising edge of the reference clock line is sampled multiple times for the target bus being switched, and the original time offset is calculated to obtain the corresponding time offset queue.

4. The CPLD-based optical module test bus switching control method according to claim 3, characterized in that, After acquiring the two-dimensional level including the clock line level and the data line level, the busy / idle state is determined by combining the pending busy / idle state to obtain a stable idle state, including: Read the clock line level and data line level of the target bus from the input buffer of the CPLD; A glitch filtering window is preset. If the pending busy / idle state of the target bus is idle, and both the clock line level and the data line level are high for a duration exceeding the glitch filtering window, then the target bus is determined to be in a stable idle state. If the pending busy / idle state of the target bus being switched becomes busy within the glitch filtering window, or if the clock line level and data line level become low within the glitch filtering window, then the target bus being switched is determined to be in a non-idle state. A preset time threshold is set, and busy / idle determination is continuously performed within the time threshold until the target bus is determined to be in a stable idle state. If the target bus remains in a non-idle state within the time threshold, a switching error is output and the switching control process is terminated.

5. The CPLD-based optical module test bus switching control method according to claim 1, characterized in that, The real-time phase shift value is obtained by averaging the extreme values ​​of the time offset queue. The drift is calculated based on the phase mapping table and the real-time phase shift value. The drift is then used to determine the final phase value and update the phase mapping table, including: After removing the maximum and minimum values ​​of the original time offsets from the time offset queue, the average of the remaining original time offsets is used to obtain the real-time phase shift value of the target bus for the switching. Extract the phase offset reference value from the phase mapping table, and calculate the drift amount based on the phase offset reference value and the real-time phase shift value; If the first drift threshold is less than the absolute value of the drift, then the real-time phase shift value will be used as the final phase value. If the second drift threshold < the absolute value of the drift amount ≤ the first drift threshold, then the weighted average of the phase offset reference value and the real-time phase shift value is taken as the final phase value; If the absolute value of the drift is less than or equal to the second drift threshold, then the phase offset reference value will be used as the final phase value. The final phase value is used as the new phase offset reference value to update the phase mapping table.

6. The CPLD-based optical module test bus switching control method according to claim 1, characterized in that, The time compensation amount is calculated based on the final phase value, converted into a positive delay amount, and mapped to a delay chain control code. A trigger pulse is applied and combined with the delay chain control code to generate a switching pulse. Based on the switching pulse, the connection interface is switched and the enable signal is set, including: The time compensation amount is calculated by combining the preset target phase value with the final phase value. If the time compensation is ≥0, it is taken as the positive delay; if the time compensation is <0, the early trigger flag is recorded, and the positive delay is calculated based on the global system clock and the time compensation. The positive delay amount is mapped to a delay chain control code for the CPLD, where the delay chain control code is represented as a digital control word used to control the application of a positive delay amount to the delay chain within the CPLD; After obtaining the trigger pulse based on the global system clock and the early trigger flag, a switching pulse is generated by combining the CPLD, the delay chain control code, and the positive delay amount. At the rising edge of the switching pulse, the bus interface in the CPLD is connected to the target bus for switching to perform the connection interface switching, and at the same time the bus enable signal of the target bus is set to the active state.

7. The CPLD-based optical module test bus switching control method according to claim 6, characterized in that, After obtaining the trigger pulse based on the global system clock and the early trigger flag, a switching pulse is generated by combining the CPLD, delay chain control code, and positive delay amount, including: If an early trigger flag exists, the application time is determined based on the early trigger flag and the global system clock to apply the trigger pulse; Otherwise, the application time is determined based on the global system clock to apply the trigger pulse, where the trigger pulse is represented as a pulse signal that initiates the physical connection switching; The trigger pulse is input into the delay chain configured with the delay chain control code in the CPLD. The delay chain applies a positive delay to the trigger pulse to obtain the switching pulse.

8. The CPLD-based optical module test bus switching control method according to claim 1, characterized in that, After acquiring the response signal and determining the switch based on the time compensation amount, the current phase value is obtained through phase fast sampling and compared with the target phase value for a threshold. The delay chain control code is then written into the phase mapping table, including: The target bus is continuously monitored by the CPLD. If an acknowledgment signal is detected within the preset verification window, the delay chain control code is written into the phase mapping table. If no response signal is detected within the verification window, multiple candidate compensation values ​​are generated to both sides of the time compensation value as the center point according to the preset steps. Then, the switching pulse is regenerated based on the candidate compensation values, and the connection interface is switched and the enable signal is set. Continuously monitor the response signals of each candidate compensation quantity, and write the delay chain control code of the candidate compensation quantity corresponding to the first captured response signal into the phase mapping table; If no response signal is captured for any of the candidate compensation quantities, a switching bus fault is output and the current switching control process is terminated. The current phase value is obtained by fast phase sampling and the phase difference is calculated by combining it with the final phase value. If the absolute value of the phase difference is greater than the phase threshold, the delay chain control code is corrected based on the phase difference and written into the phase mapping table; otherwise, no processing is performed.

9. A computer-readable storage medium, characterized in that, Used to store a computer program, which, when executed by a processor, implements a CPLD-based optical module test bus switching control method as described in any one of claims 1-8.

10. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that can run on the processor, and the processor executing the computer program implements a CPLD-based optical module test bus switching control method as described in any one of claims 1-8.

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