Serial port parameter detection and data transmission method and device based on dynamic window

Abstract

This application discloses a method and apparatus for serial port parameter detection and data transmission based on a dynamic window. Before parameter locking, the method samples and buffers the input signal at the highest baud rate; based on signal activity and noise estimation, it dynamically adjusts at least one of the preset comparison window length and the number of consecutive comparison pulses; within the window, it measures the pulse width, selecting the pulse with the smallest width that meets the time width condition as a single-bit pulse to determine the candidate baud rate; it decodes the combination of the preset candidate baud rate and candidate data format, and locks the baud rate after consistency verification; based on the locked baud rate, it reconstructs the buffered signal bits, continuously matching them with multiple preset data formats, locking the data format when only one is successfully matched; after locking, it restores the signal output from the buffer. This application requires no cooperation from the sender, can adapt to different signal qualities, and achieves rapid blind detection of serial port parameters and lossless data transmission.

Description

Technical Field

[0001] This application relates to the field of serial communication technology, specifically to a method and apparatus for serial port parameter detection and data transmission based on dynamic windows. Background Technology

[0002] In serial communication applications, both parties typically need to pre-agree on the baud rate and data format for normal interaction. However, in scenarios where the other party's configuration is unknown, existing technologies mainly employ two automatic detection methods: one is the software polling matching method, which confirms parameters by trying baud rates one by one and waiting for known data feedback. This method is slow and heavily reliant on the sender's cooperation. The other is the hardware detection method integrated into a specific MCU, which is faster but requires the sender to send predefined flag characters, making it inflexible for general-purpose processor solutions. Furthermore, during the parameter detection process, the receiving end often fails to complete the correct configuration, leading to the loss of valid communication data during the detection period, affecting the integrity and reliability of communication.

[0003] Furthermore, in actual industrial environments or complex electromagnetic environments, serial port input signals are often accompanied by noise, glitches, edge jitter, and clock skew. If baud rate detection relies solely on a fixed window and a fixed number of pulses, insufficient samples may lead to misjudgments when signal activity is low, and glitches may cause errors in extracting the narrowest pulse width when noise is high. Therefore, improving the adaptability and reliability of baud rate detection under different signal qualities without relying on the sender's cooperation, while ensuring no data loss during detection, has become an urgent problem to solve. Summary of the Invention

[0004] To address the problems of poor universality and easy data loss during blind detection of serial port parameters in existing technologies, this application proposes a serial port parameter detection and data transmission method and apparatus based on dynamic windows, which realizes universal serial port parameter fast adaptive detection and lossless data transmission without the need for the sender's cooperation.

[0005] To achieve the above objectives, this application adopts the following technical solution: A serial port parameter detection and data transmission method based on a dynamic window includes: before locking the serial port communication parameters, sampling the input signal at a sampling rate not lower than the highest supported baud rate and storing it in an input buffer to obtain a buffered signal; dynamically adjusting at least one of the length of a preset comparison window and the number of consecutively compared pulses based on the activity and noise estimation of the input signal; within the preset comparison window, continuously measuring the pulse width of the input signal according to the number of consecutively compared pulses, taking the pulse that meets the preset time width condition and has the smallest width as a single-bit pulse, determining a pulse width candidate baud rate based on the single-bit pulse, and using the pulse width candidate baud rate as the baud rate; performing bit reconstruction on the buffered signal based on the determined baud rate to generate a bit stream, continuously matching the bit stream with multiple preset data formats, and locking the successfully matched preset data format as the data format when only one preset data format is continuously matched; after both the baud rate and the data format are locked, recovering the buffered signal from the input buffer and outputting it.

[0006] The above scheme buffers the input signal at the highest sampling rate covering all possible baud rates before parameter locking, ensuring no loss of the original signal during detection. Simultaneously, it utilizes a narrowest pulse width optimization mechanism to accurately extract the baud rate without specific marker characters, and combines unique continuous matching logic to eliminate data format ambiguities. Finally, after parameter locking, the signal output is recovered from the buffer, thus achieving zero-loss transmission of communication data while ensuring detection accuracy. Furthermore, by dynamically adjusting the comparison window length and / or the number of pulse comparisons based on the activity and noise estimation of the input signal, the baud rate detection can adapt to different signal qualities and data stream characteristics. It increases the sample size to improve reliability under low activity, expands the statistical window to suppress glitches under high noise, and shortens the detection time under high activity and low noise, thereby improving the detection's adaptability and robustness.

[0007] Preferably, the step of determining the pulse width candidate baud rate based on the single-bit pulse further includes: decoding the buffered signal for each candidate combination consisting of multiple preset candidate baud rates and multiple candidate data formats to obtain the decoding confidence of each candidate combination; performing a consistency check between the pulse width candidate baud rate and the decoding candidate baud rate in the candidate combination with the highest decoding confidence and exceeding a preset confidence threshold; if the consistency check passes, then executing the step of using the pulse width candidate baud rate as the baud rate; if the consistency check fails, then continuing to detect or outputting an error reset signal.

[0008] Preferably, the step of decoding the buffered signals to obtain the decoding confidence of each candidate combination includes: for each candidate combination, calculating the number of sampling points occupied by a single bit according to the preset candidate baud rate in the candidate combination, and sequentially reading sampling points from the input buffer according to the number of sampling points, extracting the sampling value at the midpoint of each bit period, and generating a candidate bit stream corresponding to the candidate combination; segmenting the candidate bit stream into frames according to the candidate data format in the candidate combination to obtain start bits, data bits, and stop bits of multiple consecutive frames, and when the candidate data format includes a parity bit, also obtaining the parity bit; and The frame interval is determined based on the time interval between two adjacent frames; start bit verification, data bit counting, and stop bit detection are performed on each frame; when the candidate data format includes a check bit, check bit calculation is performed on each frame; the frame interval between two adjacent frames is detected; using frames as the statistical unit, the proportion of frames in a series of consecutive frames where all checks are correct is calculated out of the total number of consecutive frames to obtain the verification pass rate of the candidate combination; wherein, "all checks are correct" means that the start bit verification, data bit counting, and stop bit detection of a certain frame are all correct, and the check bit calculation of that frame is also correct when the candidate data format includes a check bit. Furthermore, the frame interval detection between this frame and adjacent frames is correct; the verification pass rate is the frame-level full-item pass rate; the field-level matching rates of the start bit, data bit, stop bit, and frame interval with the candidate data format are calculated separately in multiple consecutive frames; when the candidate data format includes a check bit, the field-level matching rate of the check bit with the candidate data format in multiple consecutive frames is also calculated; when the candidate data format does not include a check bit, the field-level matching rate of the check bit is taken as a preset value; wherein, for any field, the field-level matching rate of the field is the percentage of the number of items of the field that match the candidate data format in multiple consecutive frames. The proportion of the total number of checks; for the frame interval field, the total number of checks is the number of adjacent frame pairs in multiple consecutive frames; the field-level matching rate of the start bit, the field-level matching rate of the data bit, the field-level matching rate of the stop bit, the field-level matching rate of the check bit, and the field-level matching rate of the frame interval are weighted and summed according to preset field weights to obtain the frame structure fit of the candidate combination; the frame structure fit is a weighted value of the field-level matching rate, allowing some fields to be mismatched and not requiring all checks in the entire frame to be correct; the verification pass rate and the frame structure fit are weighted and summed according to preset weights to obtain the decoding confidence of the candidate combination.

[0009] Preferably, the step of reconstructing the buffered signal based on the determined baud rate to generate a bitstream, and continuously matching the bitstream with multiple preset data formats, wherein when only one preset data format is successfully matched, the successfully matched preset data format is locked as the data format, includes: calculating the number of sampling points occupied by a single bit according to the determined baud rate; extracting the sampling value of the intermediate point of the number of sampling points as the current bit value to generate the bitstream; and matching the bitstream with the multiple preset data formats, wherein when a preset number of frames are continuously matched and only one preset data format is successfully matched at the same time, the successfully matched preset data format is locked as the data format.

[0010] Preferably, the step of continuously matching the bitstream with multiple preset data formats includes: calculating the field-level matching rate for the start bit, data bit, and stop bit of multiple consecutive frames; calculating the field-level matching rate for the check bit of multiple consecutive frames when the preset data format includes a check bit; calculating the field-level matching rate for the frame interval between two adjacent frames; wherein, for any field, the field-level matching rate is the proportion of the number of items that match the preset data format in multiple consecutive frames to the total number of items checked in the field; for the frame interval field, the total number of items checked is the number of adjacent frame pairs in multiple consecutive frames; when the preset data format does not include a check bit, the field-level matching rate of the check bit is a preset value; the field-level matching rate of the start bit, the field-level matching rate of the data bit, the field-level matching rate of the stop bit, the field-level matching rate of the check bit, and the field-level matching rate of the frame interval are weighted and summed according to preset field weights to obtain a joint score; only when the joint score of only one preset data format exceeds a preset score threshold is the preset data format locked as the data format.

[0011] Preferably, after the baud rate and the data format are locked, the error rate of the input signal, the stop bit anomaly rate and the frame interval anomaly rate are continuously counted. If any of them exceeds the corresponding threshold, a reset is triggered to re-execute the serial port parameter detection and data transmission method based on dynamic window.

[0012] Preferably, the input buffer is a ring FIFO with a high watermark and a low watermark. During the sampling and buffering process, a single-bit period counter is used for bit sampling, and the single-bit period counter is reset each time a signal transition edge of the input signal is detected. The buffer capacity of the input buffer is monitored, and if the high watermark is reached, a buffer alarm is output in advance. If the buffer capacity is full, an error reset signal is output to clear the input buffer and re-execute the detection.

[0013] Furthermore, this application also provides a serial port parameter detection and data transmission device based on a dynamic window, comprising: an input buffer module configured to sample the input signal at a sampling rate not lower than the highest supported baud rate and store it in the input buffer module before the serial port communication parameters are locked, thereby obtaining a buffered signal; and a baud rate detection module configured to dynamically adjust at least one of the length of a preset comparison window and the number of consecutively compared pulses based on the activity and noise estimation of the input signal, continuously measure the pulse width of the input signal within the preset comparison window according to the number of consecutively compared pulses, take the pulse that satisfies the preset time width condition and has the smallest width as a single-bit pulse, determine the pulse width candidate baud rate based on the single-bit pulse, and then... The pulse width candidate baud rate is used as the baud rate; the data format detection module is configured to perform bit reconstruction on the buffer signal based on the determined baud rate to generate a bit stream, and continuously match the bit stream with multiple preset data formats. When only one preset data format is successfully matched, the successfully matched preset data format is locked as the data format; the output buffer module is configured to recover the buffer signal from the input buffer module and output it after both the baud rate and the data format are locked; the main control module is connected to the input buffer module, the baud rate detection module, the data format detection module, and the output buffer module, and is configured to schedule each module to execute the above-described serial port parameter detection and data transmission method based on dynamic windows.

[0014] The technical solution provided in this application fundamentally solves the data loss problem caused by receiver configuration lag in traditional blind detection by using a sampling rate no lower than the highest baud rate to buffer the input signal in real time during the parameter unlocking stage, thus ensuring the integrity of communication data. Regarding baud rate identification, a dynamic optimization mechanism with the narrowest pulse width within a preset window is adopted, which can accurately extract single-bit periods from any data stream without relying on specific flag characters from the sender, breaking through the protocol limitations of dedicated hardware detection schemes. Furthermore, by dynamically adjusting the comparison window length and / or the number of pulse comparisons based on the input signal activity and noise estimation, the detection process can adapt to different signal qualities: increasing the sample size to avoid misjudgment in low activity, expanding the window to suppress glitches in high noise, and accelerating the locking speed in high activity and low noise. Regarding data format identification, bit reconstruction of the buffered signal is performed based on the locked baud rate, and a unique continuous matching strategy is used to effectively avoid the risk of format misjudgment caused by idle bits or similar waveforms. Furthermore, by combining the buffer recovery output mechanism after detection with the abnormal reset protection logic, the system can achieve fast, accurate, adaptive detection and stable transmission of serial communication parameters while ensuring zero data loss. Attached Figure Description

[0015] Figure 1This is a flowchart of the serial port parameter detection and data transmission method based on dynamic windows in this application.

[0016] Figure 2 This is a block diagram of the serial port parameter detection and data transmission device based on dynamic windows according to this application.

[0017] Figure 3 This is a flowchart of the candidate combination decoding and consistency verification process for this application.

[0018] Figure 4 This is the state flowchart of the main control module of this application.

[0019] Figure 5 This is a schematic diagram illustrating the working principle of the serial port parameter detection and data transmission device based on dynamic windows in this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0022] Example 1: As Figure 1 As shown, this embodiment provides a serial port parameter detection and data transmission method based on a dynamic window. This method is implemented on a CPLD (Complex Programmable Logic Device) hardware platform and adopts a modular design approach, such as... Figure 2 As shown, the CPLD mainly consists of five modules: a main control module, a baud rate detection module, a data format detection module, an input buffer module, and an output buffer module. The main control module is the top-level module, and the other four modules are sub-modules, which are uniformly scheduled and managed by the main control module. The CPLD's hardware parallel processing characteristics enable it to perform signal sampling, pulse width measurement, and buffer read / write operations simultaneously, while the embedded RAM resources inside the CPLD provide the physical basis for high-speed sampling buffering. This embodiment takes the support of seven commonly used baud rates (4800bps, 9600bps, 14400bps, 19200bps, 38400bps, 57600bps, and 115200bps) as an example. More baud rates can be supported by simply modifying the lookup table parameters. Specifically, the method includes the following steps:

[0023] S1: Before the serial communication parameters are locked, the input signal is sampled at a sampling rate no lower than the highest supported baud rate and stored in the input buffer to obtain the buffered signal.

[0024] Since the receiving end does not yet know the actual baud rate of the transmitting end during the initial detection stage, using a fixed or lower sampling rate can lead to signal aliasing or information loss when the actual baud rate is higher than the sampling rate, resulting in incorrect parsing. Therefore, this embodiment uses the highest sampling rate covering all possible baud rates for acquisition. In this embodiment, the sampling rate is set according to the highest supported baud rate of 115200bps, meaning that each bit corresponds to one sampling point at a baud rate of 115200bps. This conforms to the basic principles of signal processing and ensures that every level transition edge in the original waveform is completely recorded regardless of the actual communication rate. Simultaneously, considering that the parameter detection process itself consumes a certain time period, directly discarding valid communication data during this period would result in information loss. Therefore, an input buffer mechanism is introduced to temporarily store the original signal. In this embodiment, the input buffer is implemented using the FIFO (First-In-First-Out) structure within the CPLD, constructed using the CPLD's embedded RAM blocks, providing high-speed read / write capabilities to meet the real-time writing requirements at the highest sampling rate. This design allows the detection algorithm to analyze cached data in the background without blocking or losing the real-time data stream input from the front end, providing a physical basis for the subsequent "detect first, then restore" process.

[0025] As a preferred solution, the input buffer is a circular FIFO with high-water mark and low-water mark. During sampling, the buffer capacity is monitored. If the high-water mark is reached, a buffer alarm is output in advance, indicating that the system detection may take too long. If the buffer capacity is full, an error reset signal is output to clear the input buffer and re-execute the detection. During sampling and buffering, a single-bit cycle counter is used for bit sampling, and the single-bit cycle counter is reset every time a signal transition edge of the input signal is detected, thereby limiting the clock error to a single bit cycle and preventing error accumulation across bits.

[0026] S2: Based on the activity and noise estimation of the input signal, dynamically adjust at least one of the length of the preset comparison window and the number of pulses for continuous comparison.

[0027] In this embodiment, before or during baud rate detection, the activity and noise of the input signal are statistically estimated in real time, and at least one of the following is dynamically adjusted: the length of the preset comparison window used for pulse width measurement and the number of pulses for continuous comparison.

[0028] The activity level is used to characterize how frequently the input signal transitions within the observation window. Activity level can be obtained by statistically analyzing at least one of the following: the number of level transitions per unit time, the number of pulses, the edge density, or the proportion of low levels. For example, low activity level occurs when the input signal remains at an idle high level for an extended period without transitions; high activity level occurs when the data stream is densely transmitted.

[0029] The noise estimation is used to characterize the severity of glitches, jitter, or abnormally narrow pulses in the input signal. Noise estimation can be obtained by statistically analyzing at least one of the following: the number of extremely narrow pulses with a width less than a preset minimum single-bit time width, the proportion of extremely narrow pulses, pulse width dispersion, or edge jitter. Since this embodiment pre-stores the single-bit time width range corresponding to all supported baud rates, it can identify obviously excessively narrow pulses and include them in the noise estimation without locking the baud rate.

[0030] The dynamic adjustment rules are as follows: When the activity level is lower than the preset activity level threshold and the noise estimate is higher than the preset noise threshold, the length of the preset comparison window is increased; or the number of pulses in continuous comparison is increased.

[0031] When the activity level is higher than the preset activity level threshold and the noise estimate is lower than the preset noise threshold, the length of the preset comparison window is reduced; or the number of pulses in continuous comparison is reduced.

[0032] The above adjustments aim to obtain more samples, improve the reliability of the narrowest pulse width screening, or speed up the locking process and reduce power consumption. During adjustment, the maximum window length, minimum window length, maximum number of pulse alignments, and minimum number of pulse alignments should be set to prevent indefinite extension or excessive shortening.

[0033] Furthermore, the dynamic adjustment is performed according to a preset step size, and the length of the adjusted preset comparison window is no greater than the maximum window length and no less than the minimum window length, and the number of consecutively compared pulses is no greater than the maximum number of pulses compared and no less than the minimum number of pulses compared. When the number of extremely narrow pulses or the proportion of extremely narrow pulses exceeds a preset noise tolerance threshold, it is preferentially determined as a baud rate error and an error reset signal is output; if it does not exceed the preset noise tolerance threshold, then the steps of increasing or decreasing the length of the preset comparison window and / or the number of consecutively compared pulses are executed according to the activity and noise estimation. This avoids conflicts when noise tolerance judgment and dynamic adjustment rules are triggered simultaneously, and ensures that the adjustment result falls within a preset range.

[0034] It should be noted that a small number of extremely narrow pulses are only used for noise estimation and to trigger window adjustment; only when the number or proportion of extremely narrow pulses exceeds the preset noise tolerance threshold is it determined to be a baud rate error and an error reset signal is output. This avoids premature reset in high-noise environments and ensures that the system can self-heal in extreme abnormal situations.

[0035] S3: Within the preset comparison window, the pulse width of the input signal is continuously measured according to the number of pulses in the continuous comparison. The pulse that meets the preset time width condition and has the smallest width is taken as a single-bit pulse. The pulse width candidate baud rate is determined based on the single-bit pulse, and the pulse width candidate baud rate is taken as the baud rate.

[0036] Asynchronous serial communication does not have an independent clock line; the receiving end must extract the timing reference from the data stream. In the UART (Universal Asynchronous Receiver / Transmitter) protocol, the time width of a single bit (Tbit) is constant. However, due to the randomness of the data content, long pulses (e.g., multiple consecutive 1s or 0s) may appear on the signal line, or short pulses may appear due to a single bit flip. According to protocol characteristics, any valid serial data frame must contain at least one pulse of single-bit width (such as a start bit or a specific combination of data bits), and long pulses must be integer multiples of the single-bit width. In this embodiment, the baud rate detection module pre-calculates the single-bit time width for each baud rate using parameters calculated as "clock frequency / baud rate," while considering an error tolerance of ±2.5%. For example, if the CPLD's system clock is 50MHz, then the single-bit time width corresponding to 115200bps is approximately 434 clock cycles, and the single-bit time width corresponding to 4800bps is approximately 10417 clock cycles. These pre-calculated values ​​are stored inside the CPLD in the form of a lookup table.

[0037] In the idle state of serial communication, the signal is at a high level. When a falling edge is detected, the time width of each pulse (i.e., the number of clock cycles between two consecutive signal transition edges) is checked one by one and compared with seven pre-calculated single-bit time widths. Within the adjusted preset comparison window, the pulse width is continuously compared according to the adjusted number of consecutively compared pulses. If the current pulse width meets the preset single-bit time width range and is less than the previously recorded pulse width, the current pulse width is updated to the narrowest pulse width. The finally determined narrowest pulse width is used as the pulse width of the single-bit pulse, and a candidate baud rate is determined based on this single-bit pulse. This candidate baud rate is then used as the baud rate. This "validity verification + minimum value optimization" screening mechanism can accurately extract the true single-bit reference from a data stream containing a large number of long pulses, effectively eliminating long pulse interference caused by changes in data content and noise spikes that exceed the range. It does not require the sender to send specific flag characters, achieving universal blind detection for any data stream.

[0038] If, after continuously comparing a preset number of pulse widths, a pulse width conforming to the preset single-bit time width range is still not obtained, it is determined to be a baud rate error; if the number or proportion of pulses smaller than the preset minimum single-bit time width detected exceeds the noise tolerance threshold, it is determined to be a baud rate error. In response to the determination of a baud rate error, an error reset signal is output to trigger re-detection.

[0039] S4: Based on the determined baud rate, perform bit reconstruction on the buffer signal to generate a bit stream, and continuously match the bit stream with multiple preset data formats. When only one preset data format is successfully matched, lock the successfully matched preset data format as the data format.

[0040] After obtaining the accurate baud rate, the number of sampling points corresponding to each bit can be calculated, and then the previously buffered original waveform can be digitally reconstructed to restore the standard bitstream sequence. In this embodiment, the number of sampling points occupied by a single bit is calculated as "115200 / locked baud rate". For example, if the locked baud rate is 9600bps, then the number of sampling points occupied by a single bit is 12. The sample value of the middle point of the number of sampling points is extracted as the current bit value to generate the bitstream. The middle point is selected because the edges of serial port signals usually have jitter or overshoot caused by level transitions, while the level in the central region of the bit period is the most stable and least affected by noise and timing deviations.

[0041] Existing technologies for data format identification often employ trial-and-error methods, which can easily lead to ambiguity during idle periods or under specific data patterns (for example, a frame of data in 5N1 format with some idle high levels might be misidentified as 6N1 or 7N1). To address this issue, this embodiment employs a unique continuous matching strategy. In this embodiment, the preset data format is a set of data format combinations without format conflicts, specifically supporting three data formats: 8N1 ​​(8 data bits, no parity, 1 stop bit), 8O1 (8 data bits, odd parity, 1 stop bit), and 8E1 (8 data bits, even parity, 1 stop bit). These three formats, while sharing the same number of data bits, are clearly distinguished by the presence or absence of a parity bit and the difference in parity type. The bitstream is matched against multiple preset data formats. When a preset number of frames are matched consecutively (e.g., 3 or 5 consecutive frames) and only one preset data format is successfully matched simultaneously, the successfully matched preset data format is locked as the data format. If two or more preset data formats meet the conditions simultaneously during continuous matching, or if the matching result jumps between different preset data formats, it is determined that the match is not locked and the system continues to wait for a more specific feature sequence.

[0042] As a preferred embodiment, during continuous matching, the start bit, data bit, and stop bit of multiple consecutive frames, as well as the check bit when the preset data format includes a check bit, are jointly scored, and the frame interval between two adjacent frames is jointly scored. Only when the joint score of only one preset data format exceeds the preset score threshold is the preset data format locked as the data format.

[0043] Specifically, the joint scoring can be as follows: calculate the field-level matching rate for the start bit, data bit, and stop bit of multiple consecutive frames; when the preset data format includes a check bit, calculate the field-level matching rate for the check bit of multiple consecutive frames; calculate the field-level matching rate for the frame interval between two adjacent frames; wherein, for any field, the field-level matching rate of that field is the proportion of the number of items that match the preset data format in multiple consecutive frames to the total number of items checked in that field; for the frame interval field, its total number of items checked is the number of adjacent frame pairs in multiple consecutive frames; when the preset data format does not include a check bit, the field-level matching rate of the check bit is taken as a preset value; the field-level matching rate of the start bit, the field-level matching rate of the data bit, the field-level matching rate of the stop bit, the field-level matching rate of the check bit, and the field-level matching rate of the frame interval are weighted and summed according to the preset field weights to obtain the joint score; only when the joint score of only one preset data format exceeds the preset score threshold is that preset data format locked as the data format.

[0044] S5: After the baud rate and the data format are locked, the buffered signal is recovered from the input buffer and output.

[0045] Once the above detection process is completed and the parameters are reliably locked, the system enters normal transmission mode. At this time, the original signals temporarily stored in the input buffer to cooperate with the detection are not discarded, but are completely read and forwarded to the back-end processor according to the locked timing parameters. In this embodiment, after the baud rate and data format are locked, the main control module allows the output buffer module to output signals. The output buffer module still needs to wait for the output enable signal from the processor before it can output signals. During output, the sampling points of each buffer are restored to the output signal line at the same baud rate of 115200 as the input sampling. This output restoration action ensures that all communication data during the period from the start to the end of the detection is preserved without loss, realizing a seamless connection between the detection process and the data transmission process. For the back-end processor, the data stream it receives is completely consistent with the directly connected sending end in terms of timing and content. There are no data breakpoints or packet loss caused by parameter adaptive detection, thus truly achieving the technical effect of transparent transmission.

[0046] Preferably, after the baud rate and data format are locked, the error rate, stop bit anomaly rate, and frame interval anomaly rate of the input signal are continuously statistically analyzed. The number of frames with error, stop bit width anomaly, and frame interval anomaly within a preset number of frames is counted using a sliding window method, and the error rate, stop bit anomaly rate, and frame interval anomaly rate are calculated respectively. If the error rate exceeds a first threshold, the stop bit anomaly rate exceeds a second threshold, or the frame interval anomaly rate exceeds a third threshold, an error reset signal is output to clear the current locking state and the detection is re-executed. If a change in the actual data format is detected, or waveform characteristics that do not match the locked parameters appear, the system automatically triggers an internal reset and re-executes the complete detection process from baud rate detection to data format detection. The first, second, and third thresholds are all preset values ​​and can be configured according to the communication rate, data format, error tolerance, or application scenario. The first, second, and third thresholds can be the same or different. For example, in one embodiment, the first threshold can be set to 5%, the second threshold can be set to 10%, and the third threshold can be set to 10%; in another embodiment, the above thresholds can be dynamically adjusted based on historical communication quality.

[0047] Through the coordinated operation of steps S100 to S500, this embodiment achieves complete data caching during the detection period, autonomous blind detection of communication parameters, and lossless recovery and output of data after the detection is completed. It completes the automatic identification of baud rate and data format without knowing the communication parameters of the sending end in advance, while ensuring that communication data is not lost or interrupted during the detection process.

[0048] Example 2: This example, based on Example 1, further details the candidate combination decoding and consistency verification.

[0049] Specifically, while determining the candidate baud rate based on the narrowest pulse width, the buffered signal is decoded for multiple candidate combinations composed of multiple preset candidate baud rates and multiple candidate data formats to obtain the decoding confidence of each candidate combination.

[0050] The preset candidate baud rate set includes, for example, 4800bps, 9600bps, 14400bps, 19200bps, 38400bps, 57600bps, and 115200bps; the preset candidate data format set includes, for example, 8N1, 8O1, and 8E1. The number of combinations is 7 × 3 = 21. For example... Figure 3 As shown, for each candidate combination, the decoding confidence is calculated as follows: The first step is to generate candidate bitstreams.

[0051] For each candidate combination, the number of sampling points occupied by a single bit is calculated according to the preset candidate baud rate in that combination. For example, if the highest sampling rate is 115200 and the candidate baud rate is 9600, then the number of sampling points occupied by a single bit is 115200 / 9600 = 12. Sampling points are read sequentially from the input buffer according to this number, and the sample value at the midpoint of each bit period is extracted to generate the candidate bitstream corresponding to that candidate combination. That is, the level value of the midpoint (e.g., the 6th point) of every 12 sampling points is taken and arranged sequentially to form the candidate bitstream.

[0052] The second step is frame segmentation.

[0053] The candidate bitstream is segmented into frames according to the candidate data formats in the candidate combination. For example, when the candidate data format is 8E1, the frame structure is: 1 start bit, 8 data bits, 1 even parity bit, and 1 stop bit. The candidate bitstream is segmented into multiple consecutive frames according to this structure. The segmentation yields the start bit, data bits, and stop bits of multiple consecutive frames; when the candidate data format includes a parity bit (such as 8O1, 8E1), the parity bit is also obtained. The frame interval is determined based on the time interval between two adjacent frames: that is, the idle time between the end of the stop bit of the previous frame and the start bit of the next frame. The frame interval is not a field present in every frame, but rather a relationship between two adjacent frames; therefore, frame interval detection is performed on adjacent frames in multiple consecutive frames.

[0054] The third step is to calculate the verification pass rate.

[0055] For each frame, start bit verification, data bit counting, and stop bit detection are performed separately. When the candidate data format includes a check bit, check bit calculation is performed for each frame. Frame interval detection is performed between adjacent frames. Using frames as the statistical unit, the percentage of frames with all checks correct out of the total number of consecutive frames is calculated to obtain the verification pass rate of the candidate combination. Here, "all checks correct" means that the start bit verification, data bit counting, and stop bit detection of a frame are all correct; when the candidate data format includes a check bit, the check bit calculation of that frame is also correct; and the frame interval detection between that frame and adjacent frames is correct. For candidate data formats that do not include a check bit, check bit calculation is not performed, but the start bit, data bits, stop bits, and frame interval checks must all be correct to be considered a qualified frame. For example, if only 4 out of 5 consecutive frames have all checks correct, the verification pass rate is 4 / 5 = 80%. Therefore, the verification pass rate is the overall pass rate of the entire frame, not a weighted value of the matching rates of individual fields.

[0056] The fourth step is to calculate the frame structure fit.

[0057] Unlike the pass rate, frame structure fit is not based on whether the entire frame is fully qualified, but is calculated separately for each field. Specifically, for multiple consecutive frames, the number of items matching the candidate data format for the start bit, data bits, stop bits, and frame interval is counted separately. When the candidate data format includes a check bit, the number of items matching the check bit with the candidate data format in multiple consecutive frames is also counted. When the candidate data format does not include a check bit, the field-level matching rate of the check bit is set to a preset value. For each field, the field-level matching rate is calculated, which is the ratio of the number of items matching the candidate data format in multiple consecutive frames to the total number of items checked in the field in multiple consecutive frames. For the frame interval field, the total number of items checked is the number of adjacent frame pairs in multiple consecutive frames. The start bit field-level matching rate, data bit field-level matching rate, stop bit field-level matching rate, check bit field-level matching rate, and frame interval field-level matching rate are weighted and summed according to preset field weights to obtain the frame structure fit of the candidate combination. The frame structure fit rate allows for some field mismatches and does not require all check items in a frame to be correct; even if a frame fails the overall frame pass assessment, the matched fields can still be included in the field-level match rate of the corresponding field. Therefore, the frame structure fit rate is a weighted value of the field-level match rate, which differs from the statistical object, statistical granularity, and calculation method of the pass rate.

[0058] The fifth step is to calculate the decoding confidence.

[0059] The decoding confidence of the candidate combination is obtained by weighting and summing the verification pass rate and frame structure matching according to preset weights. For example: Decoding confidence = α × verification pass rate + β × frame structure fit α and β are preset weights, which can be equal or adjusted according to the format type. The pass rate is the overall pass rate of the entire frame, with frames as the statistical unit; the frame structure matching degree is a weighted value of the field-level matching rate, with fields as the statistical unit.

[0060] Step 6: Consistency check.

[0061] After obtaining the decoding confidence of each candidate combination, the pulse width candidate baud rate is checked for consistency with the decoding candidate baud rate of the candidate combination with the highest decoding confidence that exceeds the preset confidence threshold.

[0062] For example, if the narrowest pulse width corresponds to a candidate baud rate of 9600bps, and the candidate combination with the highest decoding confidence is 9600bps+8E1, then the two baud rates are consistent, the consistency check passes, and the step of using the candidate baud rate as the baud rate is executed, i.e., locking 9600bps as the baud rate. If the narrowest pulse width corresponds to 9600bps, but the candidate combination with the highest decoding confidence is 19200bps+8N1, then it indicates a conflict between physical layer features and data layer features, the consistency check fails, the baud rate is not locked, and detection continues or an error reset signal is output.

[0063] This enhancement scheme significantly reduces the risk of baud rate misjudgment due to noise, distortion, or coincidental data content through dual evidence verification at both the physical and data layers, thereby improving the reliability of baud rate locking.

[0064] Example 3: As Figure 2 As shown, this embodiment provides a serial port parameter detection and data transmission device based on a dynamic window. This device is implemented on a CPLD hardware platform and employs a modular hardware architecture to execute the detection and transmission methods described in the preceding embodiments. Each module is implemented as a hardware logic unit within the CPLD and interconnected through the CPLD's internal wiring resources. Specifically, the device includes an input buffer module, a baud rate detection module, a data format detection module, an output buffer module, and a main control module.

[0065] The input buffer module is configured to sample the input signal at a sampling rate no lower than the highest supported baud rate and store it in the input buffer module before the serial communication parameters are locked, thus obtaining a buffered signal. The input buffer module is implemented using the FIFO structure inside the CPLD, preferably a ring FIFO, with high-water mark and low-water mark. The input buffer module is directly connected to the external serial port input signal line, and its sampling clock is independent of the back-end parsing logic, always running at the highest rate supported by the system. In this embodiment, the sampling rate is set according to the highest baud rate of 115200bps. The input buffer module and the baud rate detection module have a parallel receiving structure, and both acquire the same input signal simultaneously, so that the parameter detection process does not block the data writing path, fundamentally ensuring zero data loss during detection.

[0066] The baud rate detection module is configured to dynamically adjust at least one of the following based on the activity and noise estimation of the input signal: the length of the preset comparison window and the number of consecutively compared pulses. Within the preset comparison window, the pulse width of the input signal is continuously measured according to the number of consecutively compared pulses. The pulse with the smallest width that meets the preset time width condition is taken as a single-bit pulse. A candidate baud rate is determined based on the single-bit pulse, and this candidate baud rate is used as the actual baud rate. The baud rate detection module internally stores a lookup table for single-bit time widths corresponding to seven baud rates. The single-bit time width for each baud rate is calculated using "clock frequency / baud rate" and considering an error tolerance of ±2.5%. The baud rate detection module compares the pulse width with the valid range in the lookup table in real time using a hardware comparator and maintains a dynamically updated extreme value register internally. When a pulse width that meets the valid range and is smaller than the currently recorded value is detected, the reference is automatically updated and gradually converges to the true baud rate. Once the lock is successful, the baud rate detection module sends a lock flag signal to the main control module.

[0067] The data format detection module is configured to reconstruct the buffered signal based on a determined baud rate to generate a bitstream. This bitstream is then continuously matched against multiple preset data formats. When only one preset data format is successfully matched consecutively, that format is locked as the data format. The data source for the data format detection module is the buffered signal temporarily stored in the input buffer module. This "buffer first, read later" path design is key to the device's non-destructive testing capabilities: it allows the format detection logic to backtrack and analyze previously received but unparsed data frames after the baud rate is locked. The data format detection module calculates the number of sampling points corresponding to each bit according to the formula "115200 / locked baud rate" based on the baud rate parameters issued by the main control module, and reads data from the input buffer module in this rhythm for reconstruction and matching. During bit reconstruction, the data format detection module extracts the sample value of the intermediate point from the number of sampling points as the current bit value to generate the bitstream. During continuous matching, the data format detection module performs a joint score on the start bit, data bit, and stop bit of multiple consecutive frames, as well as the check bit when the preset data format includes a check bit. It also performs a joint score on the frame interval between two adjacent frames. Only when the joint score of only one preset data format exceeds the preset score threshold is the preset data format locked.

[0068] The output buffer module is configured to recover the buffered signal from the input buffer module and output it after both the baud rate and data format are locked. The output buffer module also uses the FIFO structure within the CPLD and is located at the end of the data path. Its output gating logic is strictly controlled by the main control module. Before the parameters are locked or an enable signal from the external processor is received, the output buffer module remains in a high-impedance state or an idle state, and does not send any data to the backend. Once it receives a release command from the main control module, the output buffer module begins to read the previously temporarily stored complete data stream from the input buffer module and recovers each buffered sampling point onto the output signal line at the same baud rate of 115200 as the input sampling.

[0069] The main control module is connected to the input buffer module, baud rate detection module, data format detection module and output buffer module respectively, and is configured to schedule each module to execute the aforementioned serial port parameter detection and data transmission method based on dynamic window.

[0070] Preferably, the input buffer module and the baud rate detection module receive the same input signal in parallel; after the baud rate is locked, the data format detection module reads the buffer signal back from the input buffer module for bit reconstruction and matching; the output buffer module maintains a high impedance state or an idle state when the baud rate and data format are not locked or no output enable signal is received; the input buffer module adopts a ring FIFO and sets a high watermark and a low watermark.

[0071] Example 4: Figure 4 As shown, this embodiment provides a detailed description of the finite state machine, register module, and interrupt module of the main control module.

[0072] The main control module is implemented using a finite state machine (FSM), which includes four states: initial state S_IDLE, baud rate detection state S_BAUD_DET, data format detection state S_FMT_DET, and detection completion state S_DET_VALID.

[0073] In the S_IDLE state, the state machine is in the initial state when the clock is reset. It does not detect any signals and jumps directly to the S_BAUD_DET state. This state is mainly used for error detection to generate a reset signal.

[0074] In the S_BAUD_DET state, it waits for the baud rate detection module's detection flag. If the baud rate is locked, it transitions to the S_FMT_DET state, simultaneously allowing the input buffer module to output signals to subsequent modules; if a baud rate detection error occurs or the input buffer is full, it transitions to the S_IDLE initial state, simultaneously generating an output error reset signal.

[0075] In the S_FMT_DET state, it waits for the data format detection module's detection flag. If the data format is locked, it transitions to the S_DET_VALID state, simultaneously allowing the output buffer module to output signals to the port and generating a detection success flag. If a higher baud rate is detected, it indicates that the previous baud rate detection was incorrect, and it transitions to the S_BAUD_DET state to re-detect the baud rate. If the output buffer is full, it transitions to the S_IDLE initial state, simultaneously generating an output error reset signal.

[0076] In the S_DET_VALID state, if the buffer is empty and the serial port has timed out in the idle state, or a higher baud rate is detected, or a change in data format is detected, or the check error rate exceeds the threshold, the system will switch to the S_IDLE initial state and generate an output error reset signal.

[0077] The main control module controls the start / stop of each module and the switching of data paths through the aforementioned state transition conditions, thereby achieving global scheduling.

[0078] The state transition conditions of the finite state machine include: baud rate lock, data format lock, baud rate detection error, input buffer full, output buffer full, serial port idle timeout, detection of higher baud rate, detection of data format change, and verification error rate exceeding the threshold.

[0079] like Figure 5 As shown, the device also includes a register module and an interrupt module. The register module is configured to store a defined baud rate and data format, and the interrupt module is configured to generate an interrupt signal to notify the processor after both the baud rate and data format are locked.

[0080] In this embodiment, in addition to the aforementioned serial port detection module, the CPLD also includes a register module and an interrupt module. The serial port input signal is first detected by the CPLD; if the detection is successful, it is forwarded to the processor's serial port. The processor connects to the register module within the CPLD via a bus interface to read the determined baud rate and data format, and sends an output enable signal to the device. The register module serves as the data interaction window between the CPLD and the processor; the serial port detection module writes the detected baud rate and data format parameters into the register module for the processor to read. The interrupt module uses the successful detection flag from the serial port detection module to generate an interrupt signal, which is then sent to the processor via a GPIO pin.

[0081] During actual operation of the device, when the main control module within the CPLD confirms that the baud rate and data format are reliably locked, it writes these two key parameters into the register module. Simultaneously, the interrupt module immediately generates a hardware interrupt request. After responding to the interrupt, the processor first reads the baud rate and data format values ​​from the register module via the bus interface and configures its internal UART peripheral accordingly, ensuring its communication parameters fully match those of the external device. Only after its own UART configuration is complete will the processor write an output enable flag back to the register module. The main control module within the CPLD detects that this enable flag is set and then enables the output gating of the output buffer module, restoring the historical data previously temporarily stored in the input buffer module according to the correct timing and forwarding it to the processor's serial port. This handshake process fundamentally eliminates the risk of data corruption or loss due to processor configuration lag, achieving truly lossless data transmission.

[0082] During normal communication, if the serial port parameters of an external device change, the detection device can detect this immediately through the aforementioned continuous monitoring mechanism. Once it detects that the actual waveform no longer matches the locked parameters, the detection device will automatically trigger an internal reset and re-execute the parameter detection process. When the new parameters are locked again, the interrupt module in the CPLD will generate an interrupt to notify the processor to update the serial port configuration, and the system will repeat the complete interactive cycle of "store register - send interrupt - wait for enable - transfer data". The entire process requires no manual intervention or device restart, enabling the device to maintain stable adaptive capabilities in complex and ever-changing communication environments.

[0083] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for serial port parameter detection and data transmission based on a dynamic window, characterized in that, The method includes: Before the serial communication parameters are locked, the input signal is sampled at a sampling rate no lower than the highest supported baud rate and stored in the input buffer to obtain the buffered signal; Based on the activity and noise estimation of the input signal, at least one of the following is dynamically adjusted: the length of the preset comparison window and the number of pulses for continuous comparison. Within the preset comparison window, the pulse width of the input signal is continuously measured according to the number of pulses in the continuous comparison. The pulse that meets the preset time width condition and has the smallest width is taken as a single-bit pulse. The pulse width candidate baud rate is determined based on the single-bit pulse, and the pulse width candidate baud rate is taken as the baud rate. The buffered signal is reconstructed based on the determined baud rate to generate a bit stream. The bit stream is then continuously matched with multiple preset data formats. When only one preset data format is successfully matched, the successfully matched preset data format is locked as the data format. After the baud rate and the data format are locked, the buffered signal is recovered from the input buffer and output.

2. The serial port parameter detection and data transmission method based on dynamic windows according to claim 1, characterized in that, The step of determining the pulse width candidate baud rate based on the single-bit pulse further includes: decoding the buffered signal for each candidate combination consisting of multiple preset candidate baud rates and multiple candidate data formats to obtain the decoding confidence of each candidate combination; performing a consistency check between the pulse width candidate baud rate and the decoding candidate baud rate in the candidate combination with the highest decoding confidence and exceeding a preset confidence threshold; if the consistency check passes, then executing the step of using the pulse width candidate baud rate as the baud rate; if the consistency check fails, then continuing to detect or outputting an error reset signal.

3. The serial port parameter detection and data transmission method based on dynamic windows according to claim 2, characterized in that, The step of decoding the buffered signals to obtain the decoding confidence of each candidate combination includes: For each candidate combination, the number of sampling points occupied by a single bit is calculated according to the preset candidate baud rate in the candidate combination, and the sampling points are read sequentially from the input buffer according to the number of sampling points. The sampling value of the midpoint of each bit period is extracted to generate the candidate bit stream corresponding to the candidate combination. The candidate bitstream is segmented into frames according to the candidate data format in the candidate combination to obtain start bits, data bits and stop bits of multiple consecutive frames. When the candidate data format includes a check bit, a check bit is also obtained. The frame interval is determined according to the time interval between two adjacent frames. For each frame, start bit verification, data bit counting, and stop bit detection are performed. When the candidate data format includes a check bit, check bit calculation is performed for each frame. Frame interval detection is performed between adjacent frames. Using frames as the statistical unit, the proportion of frames with all checks correct out of the total number of consecutive frames is calculated to obtain the verification pass rate of the candidate combination. Here, "all checks correct" means that the start bit verification, data bit counting, and stop bit detection of a frame are all correct, the check bit calculation of that frame is also correct when the candidate data format includes a check bit, and the frame interval detection between that frame and adjacent frames is correct. The verification pass rate is the frame-level full pass rate. The field-level matching rates of the start bit, data bit, stop bit, and frame interval with the candidate data format are calculated separately for each of the following consecutive frames: When the candidate data format includes a check bit, the field-level matching rate of the check bit with the candidate data format is also calculated for each consecutive frame; when the candidate data format does not include a check bit, the field-level matching rate of the check bit is set to a preset value; wherein, for any field, the field-level matching rate is the ratio of the number of items matching the candidate data format with the field in consecutive frames to the total number of items checked for the field in consecutive frames; for the frame interval field, the total number of items checked is the number of adjacent frame pairs in consecutive frames; the field-level matching rates of the start bit, data bit, stop bit, check bit, and frame interval are weighted and summed according to preset field weights to obtain the frame structure fit of the candidate combination; the frame structure fit is a weighted value of the field-level matching rates, allowing some fields to be mismatched and not requiring all items checked in the entire frame to be correct; The verification pass rate and the frame structure matching degree are weighted and summed according to preset weights to obtain the decoding confidence of the candidate combination.

4. The serial port parameter detection and data transmission method based on dynamic windows according to claim 1, characterized in that, The step of reconstructing the buffered signal based on the determined baud rate to generate a bitstream, and continuously matching the bitstream with multiple preset data formats, wherein when only one preset data format is successfully matched consecutively, the successfully matched preset data format is locked as the data format, including: The number of sampling points occupied by a single bit is calculated based on the determined baud rate; Extract the sample value of the middle point among the sampling points as the current bit value to generate the bit stream; The bitstream is matched with the various preset data formats. When a preset number of frames are matched consecutively and only one preset data format is matched successfully at the same time, the successfully matched preset data format is locked as the data format.

5. The serial port parameter detection and data transmission method based on dynamic windows according to claim 1, characterized in that, The step of continuously matching the bitstream with multiple preset data formats includes: calculating the field-level matching rate for the start bit, data bit, and stop bit of multiple consecutive frames; calculating the field-level matching rate for the check bit of multiple consecutive frames when the preset data format includes a check bit; calculating the field-level matching rate for the frame interval between two adjacent frames; wherein, for any field, the field-level matching rate is the proportion of the number of items that match the preset data format in multiple consecutive frames to the total number of items checked in the field; for the frame interval field, the total number of items checked is the number of adjacent frame pairs in multiple consecutive frames; when the preset data format does not include a check bit, the field-level matching rate of the check bit is taken as a preset value; the field-level matching rate of the start bit, the field-level matching rate of the data bit, the field-level matching rate of the stop bit, the field-level matching rate of the check bit, and the field-level matching rate of the frame interval are weighted and summed according to preset field weights to obtain a joint score; only when the joint score of only one preset data format exceeds a preset score threshold is the preset data format locked as the data format.

6. The serial port parameter detection and data transmission method based on dynamic windows according to claim 1, characterized in that, After the baud rate and the data format are locked, the error rate of the input signal, the stop bit anomaly rate, and the frame interval anomaly rate are continuously counted. If any of them exceeds the corresponding threshold, a reset is triggered to re-execute the serial port parameter detection and data transmission method based on dynamic window.

7. The serial port parameter detection and data transmission method based on dynamic windows according to claim 1, characterized in that, The input buffer is a ring FIFO with a high watermark and a low watermark. During the sampling and buffering process, a single-bit period counter is used for bit sampling, and the single-bit period counter is reset each time a signal transition edge of the input signal is detected. The buffer capacity of the input buffer is monitored, and if the high watermark is reached, a buffer alarm is output in advance. If the buffer capacity is full, an error reset signal is output to clear the input buffer and re-execute the detection.

8. A serial port parameter detection and data transmission device based on a dynamic window, characterized in that, The device includes: The input buffer module is configured to sample the input signal at a sampling rate not lower than the highest supported baud rate and store it in the input buffer module before the serial communication parameters are locked, so as to obtain a buffered signal; The baud rate detection module is configured to dynamically adjust at least one of the length of a preset comparison window and the number of consecutively compared pulses based on the activity and noise estimation of the input signal. Within the preset comparison window, the pulse width of the input signal is continuously measured according to the number of consecutively compared pulses. The pulse that satisfies the preset time width condition and has the smallest width is taken as a single-bit pulse. A pulse width candidate baud rate is determined based on the single-bit pulse, and the pulse width candidate baud rate is taken as the baud rate. The data format detection module is configured to perform bit reconstruction on the buffer signal based on the determined baud rate to generate a bit stream, and to continuously match the bit stream with multiple preset data formats. When only one preset data format is successfully matched, the successfully matched preset data format is locked as the data format. The output buffer module is configured to recover the buffered signal from the input buffer module and output it after both the baud rate and the data format are locked. The main control module is connected to the input buffer module, the baud rate detection module, the data format detection module, and the output buffer module, respectively, and is configured to schedule each module to execute the serial port parameter detection and data transmission method based on dynamic windows as described in any one of claims 1 to 7.

9. The serial port parameter detection and data transmission device based on a dynamic window according to claim 8, characterized in that, The input buffer module and the baud rate detection module receive the same input signal in parallel; after the baud rate is locked, the data format detection module reads the buffer signal back from the input buffer module for bit reconstruction and matching; the output buffer module maintains a high impedance state or an idle state when the baud rate and the data format are not locked or no output enable signal is received; the input buffer module adopts a ring FIFO and sets a high watermark and a low watermark.

10. The serial port parameter detection and data transmission device based on a dynamic window according to claim 8 or 9, characterized in that, The main control module employs a finite state machine, which includes an initial state, a baud rate detection state, a data format detection state, and a detection completion state. The state transition conditions of the finite state machine include at least one of the following: baud rate locking, data format locking, baud rate detection error, input buffer full, output buffer full, serial port idle timeout, detection of a higher baud rate, detection of a data format change, and verification error rate exceeding a threshold. The device also includes a register module and an interrupt module. The register module is configured to store the determined baud rate and data format, and the interrupt module is configured to generate an interrupt signal to notify the processor after both the baud rate and the data format are locked.

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