sending end domain controller, routing switch, receiving end domain controller, and system

Abstract

This application discloses a sending-end domain controller, a routing switch, a receiving-end domain controller, and a system for preventing tampering and forgery. The sending-end domain controller includes: a tenant identifier parsing circuit, a physically unclonable function circuit, a high-precision time protocol clock circuit, and a hash circuit. The tenant identifier parsing circuit receives tenant configuration instructions from the baseboard management controller and parses the instructions to obtain the corresponding tenant identifier. The physically unclonable function circuit generates a sending-end hardware inherent feature vector of the sending-end domain controller. The high-precision time protocol clock circuit provides a timestamp. The hash circuit hashes and concatenates the tenant identifier, the sending-end hardware inherent feature vector, the receiving-end hardware inherent feature vector, and the timestamp to obtain a fingerprint, wherein the receiving-end hardware inherent feature vector is data transmitted by the receiving-end domain controller via an encrypted channel.

Description

Technical Field

[0001] This application relates to the field of graphics processor clusters, and more particularly to transmitting domain controllers, routing switches, receiving domain controllers, and systems. Background Technology

[0002] In multi-tenant shared scenarios on AI cloud platforms, to meet user needs, a multi-domain interconnected architecture suitable for graphics processing unit (GPU) cluster deployment is typically built. In existing solutions, to prevent data crosstalk or theft between multiple tenants, software verifies the tenant's identifier during data transmission; if the verification fails, the data is blocked, thereby limiting the GPUs that a tenant can access and achieving isolation.

[0003] However, in existing solutions, tenant identifiers are easily tampered with or forged, leading to isolation failures and low data security. Summary of the Invention

[0004] To address the technical problem of easy tampering and forgery in the background art, embodiments of this application provide a sending domain controller, a routing switch, a receiving domain controller, and a system for preventing tampering and forgery.

[0005] The first aspect of this application provides a transmitting domain controller for a computing domain, including a tenant identifier resolution circuit, a physically unclonable function circuit, a high-precision time protocol clock circuit, and a hash circuit; The tenant identifier parsing circuit is used to receive the tenant configuration command issued by the baseboard management controller, parse the tenant configuration command, and obtain the corresponding tenant identifier; A physically non-clonable function circuit is used to generate the transmitter hardware intrinsic feature vector of the transmitter domain controller; A high-precision time protocol clock circuit is used to provide timestamps; The hash circuit is used to hash and concatenate the tenant identifier, the sender's hardware inherent feature vector, the receiver's hardware inherent feature vector, and the timestamp to obtain a fingerprint. The receiver's hardware inherent feature vector is the data sent by the receiver's domain controller through an encrypted channel.

[0006] A second aspect of this application provides a routing switch, including: a receiving circuit, a transmitting circuit, and a routing verification circuit; The receiving circuit is used to receive micro-chip data containing watermark micro-chip header data sent by the transmitting domain controller. The watermark micro-chip header data is the data obtained by the transmitting domain controller performing an XOR operation on the initial micro-chip header data and the result obtained by truncating the fingerprint with a preset length mask. The initial micro-chip header data is the data generated based on a preset protocol. The routing verification circuit is used to send a signal to the transmitting circuit when the watermark micro-chip header data meets the preset conditions, so that the transmitting circuit sends the micro-chip data to the receiving domain controller; when the watermark micro-chip header data does not meet the preset conditions, the micro-chip data is discarded.

[0007] A third aspect of this application provides a receiver domain controller for a computing domain, including a physical decoding circuit, a receiver verification circuit, a physical non-clonable function circuit, and a high-precision time protocol clock circuit. The physical decoding circuit is used to receive the micro-chip data containing the watermark micro-chip header data sent by the routing switch, and decode the watermark micro-chip header data to obtain the corresponding tenant fingerprint and tenant identifier. A physically non-clonable function circuit is used to generate the receiver hardware intrinsic feature vector of the receiver domain controller; A high-precision time protocol clock circuit is used to provide a timestamp consistent with the timestamp of the transmitting domain controller; The receiver verification circuit is used to verify the tenant fingerprint based on the pre-generated receiver fingerprint corresponding to the tenant identifier. The receiver fingerprint is obtained by hashing the tenant identifier obtained by parsing the tenant configuration instruction, the sender hardware inherent feature vector, the receiver hardware inherent feature vector, and the timestamp. The sender hardware inherent feature vector is the data sent by the sender domain controller through the encrypted channel.

[0008] A fourth aspect of this application provides a control system for a graphics processor cluster, including a transmitting domain controller, a routing switch, and a receiving domain controller as described above.

[0009] A fifth aspect of this application provides a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the aforementioned method.

[0010] A sixth aspect of this application provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the aforementioned method.

[0011] As can be seen from the above technical solutions, the embodiments of this application have the following advantages: The transmitting domain controller of this application includes a physically unclonable function circuit that can generate a transmitting hardware inherent feature vector of the transmitting domain controller. This hardware inherent feature vector is generated based on the inherent features of the domain controller's physical chip and cannot be tampered with or forged. Consequently, the fingerprint cannot be tampered with or forged either. This greatly improves the success rate of fingerprint-based isolation and significantly enhances data security.

[0012] Additional aspects and advantages of embodiments of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of embodiments of this application. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0014] Figure 1 This is a schematic diagram of an embodiment of a transmitting domain controller disclosed in this application; Figure 2 This is a schematic diagram of another embodiment of a transmitting domain controller disclosed in this application; Figure 3 This is a schematic diagram of an embodiment of a routing switch disclosed in this application; Figure 4 This is a schematic diagram of an embodiment of a receiving domain controller disclosed in this application; Figure 5 This is a schematic diagram of one embodiment of the isolation process disclosed in this application.

[0015] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0016] In an AI cloud platform, a GPU cluster multi-domain interconnection architecture can be used to achieve multi-tenant data isolation and ensure security. In the first existing solution, to prevent data crosstalk or theft between multiple tenants, software verifies the tenant's identifier during data transmission. If the verification fails, the data is blocked, thus limiting the GPUs the tenant can access and achieving isolation. However, the tenant identifiers involved in this existing solution are easily tampered with and forged, leading to isolation failure and low data security. Furthermore, it utilizes at least 15% of the GPU's computing power for verification, resulting in high data latency. Additionally, the software verification is not bound to physical characteristics, and the tenant identifier is static and easily forged, all contributing to low data security. In the second existing solution, transmission channels are divided into a fixed number, with each tenant having its own dedicated group, relying on hardware switches for physical isolation. However, this solution has low resource utilization and lacks underlying signal-level protection, making it susceptible to forgery and tampering. To address the above technical problems, this application provides a sending-end domain controller, a routing switch, a receiving-end domain controller, and a system for preventing tampering and forgery. The transmitting domain controller of this application includes a physically unclonable function circuit that can generate a transmitting hardware inherent feature vector of the transmitting domain controller. This hardware inherent feature vector is generated based on the inherent features of the domain controller's physical chip and cannot be tampered with or forged. Consequently, the fingerprint cannot be tampered with or forged either. This greatly improves the success rate of fingerprint-based isolation and significantly enhances data security.

[0017] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the embodiments of this application, and should not be construed as limiting the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of the embodiments of this application.

[0018] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The terms "first," "second," "third," "fourth," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. In the description of embodiments of this application, "a plurality of" means two or more, unless otherwise expressly specified.

[0019] In the embodiments of this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0020] The following describes one type of transmitting domain controller according to this application. Please refer to [link / reference]. Figure 1 One embodiment of a sending domain controller according to this application includes: a tenant identifier resolution circuit, a physically unclonable function circuit, a high-precision time protocol clock circuit, and a hash circuit; The tenant identifier parsing circuit receives tenant configuration commands from the baseboard management controller (BMC), parses the commands, and obtains the corresponding tenant identifier. The tenant configuration command includes at least the tenant identifier, and may also include information such as the GPUs the tenant can access; specific details are not limited here.

[0021] A physically unclonable function (PUF) circuit is used to generate the transmitter hardware inherent characteristic vector of the transmitter domain controller. The PUF circuit utilizes random process variations generated during chip manufacturing, such as physical differences in oscillators or transistors, to ensure the uniqueness of hardware identity. Specifically, the transmitter hardware inherent characteristic vector can be obtained through micro-hour timing deviations of the chip or the power-on state of the static random access memory.

[0022] A high-precision time protocol clock circuit is used to provide timestamps. These timestamps can be static or dynamic, and can be set according to actual needs.

[0023] The hash circuit is used to hash and concatenate the tenant identifier, the sender's hardware inherent feature vector, the receiver's hardware inherent feature vector, and the timestamp to obtain a fingerprint. The receiver's hardware inherent feature vector is the data sent by the receiver's domain controller through an encrypted channel. That is, the hardware inherent feature vector is exchanged between the two parties in an encrypted session based on a security protocol to provide a basis for generating the fingerprint.

[0024] In this embodiment, the sending domain controller includes a physically unclonable function circuit that can generate a sending hardware inherent feature vector of the sending domain controller. This hardware inherent feature vector is generated based on the inherent features of the domain controller's physical chip and cannot be tampered with or forged. Consequently, the fingerprint cannot be tampered with or forged either, thus greatly improving the success rate of fingerprint-based isolation and significantly enhancing data security.

[0025] Please see Figure 2 Another embodiment of a sending domain controller according to this application includes: a tenant identifier resolution circuit, a physically unclonable function circuit, a high-precision time protocol clock circuit, and a hash circuit; The tenant identifier parsing circuit receives tenant configuration instructions from the baseboard management controller and parses them to obtain the corresponding tenant identifier. The tenant configuration instructions include at least the tenant identifier and may also include information such as the GPUs the tenant can access; specific details are not limited here.

[0026] A physically unclonable function circuit is used to generate the transmitter hardware inherent characteristic vector of the transmitter domain controller. It leverages random process differences during chip manufacturing, such as physical differences in oscillators or transistors, to ensure the uniqueness of the hardware identity. Specifically, the transmitter hardware inherent characteristic vector can be obtained through micro-hour timing deviations of the chip or the power-on state of the static random access memory, as detailed in the implementation methods below.

[0027] A high-precision time protocol (PTP) clock circuit is used to provide timestamps, enabling sub-nanosecond hardware clock synchronization. The timestamps can be static or dynamic, depending on actual needs. In this embodiment, the timestamps are dynamic, changing with the period.

[0028] A hash circuit is used to hash and concatenate the tenant identifier, the sender's hardware intrinsic feature vector, the receiver's hardware intrinsic feature vector, and a timestamp to obtain a fingerprint. The receiver's hardware intrinsic feature vector is data sent by the receiver's domain controller via an encrypted channel; that is, the hardware intrinsic feature vector is exchanged between the two devices in an encrypted session based on a security protocol, providing the basis for fingerprint generation. The hash circuit uses a third-generation hash algorithm or a secure hash algorithm-256; other types are also possible, but not limited here. The fingerprint's bit length can be 128, or other values, but not limited here.

[0029] Specifically, there are at least two implementations of physically non-clonable function circuits to generate the intrinsic feature vector of the transmitting end hardware, and the specific implementation is not limited here. Two of these implementations are illustrated below.

[0030] In the first implementation, the physically unclonable function circuit is specifically used to acquire the oscillation periods of multiple oscillators in the transmitting domain controller; the calculation of each comparison result is as follows: the first oscillator and the second oscillator are randomly selected from the multiple oscillators. If the oscillation period of the first oscillator is less than the oscillation period of the second oscillator, the value of the comparison result is a first preset value (e.g., 0). If the oscillation period of the first oscillator is greater than the oscillation period of the second oscillator, the value of the comparison result is a second preset value (e.g., 1). The n comparison results are sequentially concatenated to obtain a transmitting hardware inherent feature vector with n bits, where n is a positive integer.

[0031] In the second implementation, the physically non-clonable function circuit is specifically used to read the output levels (the output level values ​​are 0 or 1) of multiple static random access memories at the moment when multiple static random access memories in the transmitting domain controller are powered on and stabilized, and to concatenate the multiple output levels to obtain the corresponding transmitting hardware inherent feature vector.

[0032] In addition, since the sending domain controller and the receiving domain controller corresponding to the same tenant identifier are connected to the same master clock and adopt the PTP mechanism, under the premise of exchanging the inherent feature vectors of the hardware of both parties, the fingerprints calculated based on the same fingerprint algorithm are the same, and both parties calculate the fingerprints independently and simultaneously on their local machines. This can eliminate the problem of cross-domain synchronization delay.

[0033] Furthermore, to ensure the reliability of data isolation, a verification can be performed at the sending end. Specifically, the sending domain controller also includes resource management circuitry, sending verification circuitry, and physical encoding circuitry. The resource management circuit assigns unique instance numbers to the tenant identifier resolution circuit, physical non-cloning function circuit, high-precision time protocol clock circuit, and hash circuit involved in fingerprint generation. It then writes the tenant identifier, tenant activation flag, and corresponding instance number into a pre-defined tenant registry. The tenant activation flag is obtained by parsing tenant configuration instructions. The tenant activation flag indicates whether the corresponding tenant identifier is active. Each instance number corresponds to a set of circuits, which includes at least one tenant identifier resolution circuit, one physical non-cloning function circuit, one high-precision time protocol clock circuit, and one hash circuit.

[0034] The transmitting end verification circuit first receives the verification identifier and verification number reported by the graphics processing unit (GPU) in the same domain. If the verification identifier matches the tenant identifier in the tenant registry, the corresponding tenant activation flag in the tenant registry is registered and activated, and the verification number matches the corresponding instance number, then a signal is sent to the physical encoding circuit to enable encoding. This application's data isolation involves three levels of verification. The first level of verification is handled by the transmitting end verification circuit, which mainly verifies the tenant identifier, tenant activation flag, and corresponding instance number to ensure system reliability. It is understood that if verification fails, the request can be directly discarded on the bus side and the corresponding error code returned.

[0035] The physical coding sublayer (PCS) circuit generates initial microchip header data based on a preset protocol. It then XORs this initial microchip header data with the result of truncating the fingerprint using a preset-length mask to obtain the watermark microchip header data. The microchip data containing the watermark microchip header data is then sent to the routing switch. Specifically, the initial microchip header data is the initial header of the microchip data. The fingerprint is first truncated using a preset-length mask, and then the truncated result is XORed with the initial header to obtain the watermark microchip header data. Simply put, a watermark corresponding to the fingerprint is embedded in the microchip data header, preventing fingerprint leakage. This process requires no software program, is completed solely by hardware gate circuits, has a processing delay of no more than 2 nanoseconds, does not alter the carrier phase or amplitude of the signal, and has a low bit error rate.

[0036] Furthermore, to enhance the security and reliability of data isolation, in addition to embedding the watermark in the microchip header, a related checksum, such as a cyclic redundancy check (CRC), can also be embedded in the header. Specific details are not limited here; the following example uses a CRC checksum. In one implementation, the physical encoding circuit specifically generates initial microchip header data based on a preset protocol, and performs an XOR operation between the initial microchip header data and the result obtained by truncating the fingerprint using a preset length mask to obtain a first result. A corresponding CRC checksum is generated for the first result, and the first result and the CRC checksum are concatenated to obtain the watermarked microchip header data. The microchip data containing the watermarked microchip header data is then sent to the routing switch. Simply put, the watermark and CRC checksum are embedded together in the header of the microchip data. The receiving domain controller can then perform further CRC verification, increasing system security. The watermark bit length can be 8 bits or other values, depending on actual requirements.

[0037] Furthermore, to ensure normal fingerprint recognition even with slight clock jitter at both ends and increase fault tolerance, a "double-buffered rolling" mechanism can be employed. This involves using two hardware registers to store the fingerprints for the current and next cycles respectively, with a smooth switching interval (preferably 10ns) between adjacent cycles. During this interval, both fingerprints can be recognized, and the receiving domain controller only needs to recognize either fingerprint to pass verification. Within a given cycle, only the fingerprint corresponding to that cycle is verified; fingerprints from the next cycle are not allowed. Specifically, a high-precision time protocol clock circuit is used to provide the timestamps for the current and next cycles.

[0038] The hash circuit is specifically used for fingerprint calculation in the current period and the next period: it hashes and concatenates the tenant identifier, the sender's hardware inherent feature vector, the receiver's hardware inherent feature vector, and the timestamp of the current period or the next period to obtain the fingerprint of the current period or the next period.

[0039] Furthermore, to enhance data security and prevent tampering and forgery, dynamic fingerprints can be set, specifically, the timestamp changes with the period. Preferably, the period interval is 5 microseconds, but it can be set according to actual needs; no specific limitation is made here.

[0040] In this embodiment of the application, by embedding the watermark corresponding to the fingerprint into the microchip data header and performing first-level verification at the sending end, the security of data isolation can be greatly improved.

[0041] The routing switch of this application is described below. Please refer to... Figure 3One embodiment of a routing switch according to this application includes: a receiving circuit, a transmitting circuit, and a routing verification circuit; The receiving circuit is used to receive micro-chip data containing watermark micro-chip header data sent by the transmitting domain controller. The watermark micro-chip header data is obtained by the transmitting domain controller performing an XOR operation between the initial micro-chip header data and the result obtained by truncating the fingerprint using a preset length mask. The initial micro-chip header data is generated based on a preset protocol. For details regarding the watermark micro-chip header data, please refer to the above embodiments; specific details will not be repeated here.

[0042] The routing verification circuit is used to send a signal to the transmitting circuit when the watermark micro-chip header data meets preset conditions, so that the transmitting circuit sends the micro-chip data to the receiving domain controller; when the watermark micro-chip header data does not meet the preset conditions, the micro-chip data is discarded. Routing verification is the second level in the three-level data isolation verification of this application.

[0043] There are at least two ways to implement the preset conditions, which can be set according to actual needs. The specific implementation is not limited here. Two of the implementation methods are illustrated below.

[0044] In the first implementation, the route verification circuit is specifically used to extract the tenant identifier from the watermark micro-chip header data and determine the corresponding tenant fingerprint based on the tenant identifier in a pre-set routing table storing multiple fingerprints; it then performs an XOR operation on the preset original route micro-chip header data (generated by a preset fixed protocol) and the result obtained by truncating the tenant fingerprint using a preset length mask to obtain the route watermark micro-chip header data; when the watermark micro-chip header data is the same as the route watermark micro-chip header data, a signal is sent to the transmitting circuit to cause the transmitting circuit to send the micro-chip data to the receiving domain controller. The method by which the routing switch calculates the route watermark micro-chip header data is basically the same as that of the transmitting domain controller; therefore, under normal circumstances, the micro-chip header data embedded with the watermark obtained by both will naturally be the same.

[0045] In the second implementation, the routing verification circuit is specifically used to extract the first fingerprint watermark field and tenant identifier from the watermark microchip header data; determine the corresponding tenant fingerprint based on the tenant identifier in a pre-set routing table storing multiple fingerprints; generate a corresponding second fingerprint watermark field based on the tenant fingerprint; and when the first fingerprint watermark field and the second fingerprint watermark field are the same, send a signal to the transmitting circuit so that the transmitting circuit sends the microchip data to the receiving domain controller. Simply put, it extracts the watermark field, only compares whether the watermark fields are the same; if they are the same, the verification passes; otherwise, it discards the data.

[0046] In this embodiment, secondary verification can be performed based on the local fingerprint of the routing table, which greatly improves the security and reliability of data isolation.

[0047] The following describes a receiving domain controller according to an embodiment of this application. Please refer to... Figure 4 One embodiment of a receiving domain controller for a computing domain in this application includes: a physical decoding circuit, a receiving verification circuit, a physical non-cloning function circuit, and a high-precision time protocol clock circuit; The physical decoding circuit (corresponding to the physical encoding circuit at the transmitting end, used for decoding) is used to receive the micro-chip data containing the watermark micro-chip header data sent by the routing switch, and to decode the watermark micro-chip header data to obtain the corresponding tenant fingerprint and tenant identifier. A physically non-clonable function circuit is used to generate the receiver hardware intrinsic feature vector of the receiver domain controller; A high-precision time protocol clock circuit is used to provide a timestamp consistent with the timestamp of the transmitting domain controller; The receiver verification circuit verifies the tenant fingerprint based on a pre-generated receiver fingerprint corresponding to the tenant identifier. The receiver fingerprint is obtained by hashing and concatenating the tenant identifier (obtained by parsing the tenant configuration command), the sender's inherent hardware feature vector, the receiver's inherent hardware feature vector, and a timestamp. The sender's inherent hardware feature vector is data transmitted by the sender's domain controller via an encrypted channel. In short, the receiver fingerprint is independently generated by the receiver domain controller using the same fingerprint generation method as the sender domain controller. Generally, the tenant identifier, sender's inherent hardware feature vector, receiver's inherent hardware feature vector, and timestamp generated by both ends are identical, and the independently generated fingerprints from both ends are also generally the same.

[0048] Specifically, there are at least two implementation methods for verification, which can be set according to actual needs. No specific method is limited here; two implementation methods will be described below. For "double-buffered rolling," please refer to the description of the above embodiments; details will not be repeated here.

[0049] In the first embodiment, the receiving end verification circuit is specifically used to block the transmission channel from the sending end domain controller to the receiving end domain controller when there are tenant fingerprints in the same period that are different from the receiving end fingerprint within m consecutive periods, where m is a positive integer greater than 1; and to confirm the security of the microchip data when there are tenant fingerprints in the same period that are the same as the receiving end fingerprint within m periods. Preferably, m is 3.

[0050] In the second embodiment, the receiving end verification circuit is specifically used to block the transmission channel from the sending end domain controller to the receiving end domain controller when the tenant fingerprint is different from the receiving end fingerprint; and to confirm the security of the microchip data when the tenant fingerprint is the same as the receiving end fingerprint.

[0051] In this embodiment, the verification of the receiving domain controller belongs to the third level of the three-level data isolation verification, which can perform a final verification to compare whether the fingerprint is correct, thereby improving the system security and reliability.

[0052] This application also provides a control system for a graphics processor cluster, including the aforementioned transmitting domain controller, the aforementioned routing switch, and the aforementioned receiving domain controller.

[0053] The following example illustrates the entire isolation process. Please refer to [link / reference]. Figure 5 The baseboard management controller (BMC) assigns tenant identifiers and specifies the GPU corresponding to each tenant identifier based on the tenant configuration instructions. Domain controllers (including the sending and receiving domain controllers) within the compute domain where the GPU resides exchange physical hardware characteristics and are connected to the same PTP clock domain to ensure that both domain controllers (specifically, hardware hash circuits) can independently and simultaneously calculate the fingerprint corresponding to the tenant identifier locally. The double-buffered rolling mechanism requires calculating the fingerprints for the current and next cycles. When a tenant initiates a transmission request, the GPU sends the service data to the sending domain controller. The sending domain controller performs a first-level verification, generates a watermark corresponding to the fingerprint, embeds the watermark in the chip header, and sends it to the routing switch. The routing switch performs a mask comparison (second-level verification). If the verification passes, the receiving domain controller performs a third-level verification. If the fingerprint comparison fails for three consecutive cycles, the channel is blocked, and an interrupt alarm is sent to the baseboard management controller. If the third-level verification passes, the service data continues to be transmitted to the GPU in the receiving compute domain. When the tenant's service ends, the BMC initiates a shutdown command to release resources.

[0054] This application also provides a computer-readable storage medium including instructions that, when executed on a computer, cause the computer to perform the methods described in the foregoing embodiments.

[0055] This application also provides a computer program product containing instructions that, when run on a computer, cause the computer to perform the methods described in the foregoing embodiments.

[0056] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0057] It should be noted that although the steps in the flowcharts of the various embodiments are drawn sequentially according to the arrows, unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the various embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0058] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0059] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0060] The above are merely preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural transformations made using the description and drawings of the present application under the inventive concept of the present application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present application.

Claims

1. A sending domain controller of a computing domain, characterized in that, This includes tenant identifier resolution circuitry, physically unclonable function circuitry, high-precision time protocol clock circuitry, and hash circuitry. The tenant identifier parsing circuit is used to receive the tenant configuration command issued by the baseboard management controller, and parse the tenant configuration command to obtain the corresponding tenant identifier. The physically unclonable function circuit is used to generate the transmitter hardware inherent feature vector of the transmitter domain controller; The high-precision time protocol clock circuit is used to provide timestamps; The hash circuit is used to hash and concatenate the tenant identifier, the sender hardware inherent feature vector, the receiver hardware inherent feature vector, and the timestamp to obtain a fingerprint, wherein the receiver hardware inherent feature vector is data sent by the receiver domain controller through an encrypted channel.

2. The transmitting domain controller according to claim 1, characterized in that, The physically unclonable function circuit is specifically used to acquire the oscillation periods of multiple oscillators in the transmitting domain controller. The calculation of each comparison result involves: randomly selecting the first and second oscillators from the multiple oscillators; if the oscillation period of the first oscillator is less than the oscillation period of the second oscillator, the comparison result is a first preset value; if the oscillation period of the first oscillator is greater than the oscillation period of the second oscillator, the comparison result is a second preset value; and sequentially concatenating the n comparison results yields a transmitting hardware intrinsic feature vector with n bits, where n is a positive integer.

3. The transmitting domain controller according to claim 1, characterized in that, The physically unclonable function circuit is specifically used to read the output levels of the multiple static random access memories at the moment of power-on stability in the transmitting domain controller, and to concatenate the multiple output levels to obtain the corresponding transmitting hardware inherent feature vector.

4. The transmitting end domain controller of claim 1, wherein, The transmitting domain controller also includes a resource management circuit, a transmitting verification circuit, and a physical encoding circuit; The resource management circuit is used to assign a unique instance number to the tenant identifier parsing circuit, the physical unclonable function circuit, the high-precision time protocol clock circuit, and the hash circuit that participate in generating the fingerprint, and write the tenant identifier, the tenant activation flag, and the corresponding instance number into a preset tenant registry, wherein the tenant activation flag is obtained by parsing the tenant configuration instruction; The sending end verification circuit is used to receive the verification identifier and verification number reported by the graphics processor in the same domain; when the verification identifier is the tenant identifier in the tenant registry, the corresponding tenant activation mark in the tenant registry is registered and activated, and the verification number is the corresponding instance number, the circuit sends a signal to the physical encoding circuit to enable the physical encoding circuit to perform encoding. The physical encoding circuit is used to generate initial microchip header data based on a preset protocol, and to perform an XOR operation on the initial microchip header data and the result obtained by truncating the fingerprint with a preset length mask to obtain watermark microchip header data; and to send the microchip data containing the watermark microchip header data to the routing switch.

5. The transmitting domain controller according to claim 4, characterized in that, The physical encoding circuit is specifically used to generate initial microchip header data based on a preset protocol, and to perform an XOR operation on the initial microchip header data and the result obtained by truncating the fingerprint with a preset length mask to obtain a first result. A corresponding cyclic redundancy check code is generated for the first result, and the first result and the cyclic redundancy check code are concatenated to obtain watermark microchip header data. The microchip data containing the watermark microchip header data is sent to the routing switch.

6. The transmitting domain controller according to claim 1, characterized in that, The high-precision time protocol clock circuit is specifically used to provide timestamps for the current period and the next period. The hash circuit is specifically used for fingerprint calculation in the current period and the next period: the tenant identifier, the inherent feature vector of the sending end hardware, the inherent feature vector of the receiving end hardware, and the timestamp of the current period or the next period are hashed and concatenated to obtain the fingerprint of the current period or the next period.

7. The transmitting domain controller according to claim 1, characterized in that, The timestamp changes as the period changes.

8. The transmitting domain controller according to claim 1, characterized in that, The hash circuit is a circuit that uses the third-generation hash algorithm or the secure hash algorithm-256.

9. A routing switch, characterized in that, Includes receiving circuitry, transmitting circuitry, and route verification circuitry; The receiving circuit is used to receive micro-chip data containing watermark micro-chip header data sent by the transmitting domain controller. The watermark micro-chip header data is the data obtained by the transmitting domain controller performing an XOR operation on the initial micro-chip header data and the result obtained by truncating the fingerprint with a preset length mask. The initial micro-chip header data is data generated based on a preset protocol. The routing verification circuit is used to send a signal to the transmitting circuit when the watermark micro-chip header data meets the preset conditions, so that the transmitting circuit sends the micro-chip data to the receiving domain controller; and to discard the micro-chip data when the watermark micro-chip header data does not meet the preset conditions.

10. The routing switch according to claim 9, characterized in that, The routing verification circuit is specifically used to extract the tenant identifier from the header data of the watermark micro-chip, and determine the corresponding tenant fingerprint based on the tenant identifier in a pre-set routing table that stores multiple fingerprints. The preset route original micro-chip header data is XORed with the result obtained by truncating the tenant fingerprint using a preset length mask to obtain the route watermark micro-chip header data; when the watermark micro-chip header data is the same as the route watermark micro-chip header data, a signal is sent to the transmitting circuit so that the transmitting circuit sends the micro-chip data to the receiving domain controller.

11. The routing switch according to claim 9, characterized in that, The routing verification circuit is specifically used to extract a first fingerprint watermark field and a tenant identifier from the header data of the watermark microchip; determine the corresponding tenant fingerprint in a pre-set routing table that stores multiple fingerprints based on the tenant identifier; generate a corresponding second fingerprint watermark field based on the tenant fingerprint; and send a signal to the transmitting circuit when the first fingerprint watermark field and the second fingerprint watermark field are the same, so that the transmitting circuit sends the microchip data to the receiving domain controller.

12. A receiving domain controller for a computing domain, characterized in that, This includes physical decoding circuitry, receiver verification circuitry, physical non-clonable function circuitry, and high-precision time protocol clock circuitry. The physical decoding circuit is used to receive micro-chip data containing watermark micro-chip header data sent by the routing switch, and to decode the watermark micro-chip header data to obtain the corresponding tenant fingerprint and tenant identifier. The physically unclonable function circuit is used to generate the receiver hardware intrinsic feature vector of the receiver domain controller; The high-precision time protocol clock circuit is used to provide a timestamp consistent with the timestamp of the transmitting domain controller; The receiving end verification circuit is used to verify the tenant fingerprint based on a pre-generated receiving end fingerprint corresponding to the tenant identifier. The receiving end fingerprint is obtained by hashing the tenant identifier obtained by parsing the tenant configuration instruction, the sending end hardware inherent feature vector, the receiving end hardware inherent feature vector, and the timestamp. The sending end hardware inherent feature vector is data sent by the sending end domain controller through an encrypted channel.

13. The receiving domain controller according to claim 12, characterized in that, The receiving end verification circuit is specifically used to block the transmission channel from the sending end domain controller to the receiving end domain controller when there are cases where the tenant fingerprint in the same period is different from the receiving end fingerprint in m consecutive periods, where m is a positive integer greater than 1; and to confirm the security of the microchip data when there are cases where the tenant fingerprint in the same period is the same as the receiving end fingerprint in m periods.

14. The receiving domain controller according to claim 12, characterized in that, The receiving end verification circuit is specifically used to block the transmission channel from the sending end domain controller to the receiving end domain controller when the tenant fingerprint is different from the receiving end fingerprint; and to confirm the security of the microchip data when the tenant fingerprint is the same as the receiving end fingerprint.

15. A control system for a graphics processing unit cluster, comprising a transmitting domain controller as claimed in any one of claims 1 to 8, a routing switch as claimed in any one of claims 9 to 11, and a receiving domain controller as claimed in any one of claims 12 to 14.

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