Intelligent data acquisition terminal, device monitoring system and data analysis method

Abstract

This disclosure relates to an intelligent data acquisition terminal, including a 16-channel signal acquisition interface for synchronously acquiring N analog signals from a data source device; a data sampling module including a 16-channel signal acquisition channel, an analog-to-digital converter chip, and a main control chip, wherein the main control chip is used to drive the analog-to-digital converter chip to acquire signals according to the sampling frequency based on the FMC strategy; a communication module including a communication chip, a network port circuit, and an internal communication circuit, wherein the communication chip is used to automatically encapsulate private data frames into standard UDP network packets via all-hardware UDP; and an AI chip equipped with a UDP listening port, a CPU, and an NPU, wherein the UDP listening port is used to capture standard UDP network packets in real time, and the data samples after parsing and preprocessing the standard UDP network packets are used as input to a neural network model, and the NPU performs accelerated inference or the NPU and CPU perform collaborative inference to obtain the analysis results.

Description

Technical Field

[0001] This disclosure relates to the field of data analysis, specifically to the fields of industrial data acquisition, analysis and Internet of Things communication technology, and particularly to an intelligent data acquisition terminal, equipment monitoring system and data analysis method. Background Technology

[0002] As large electro-hydraulic equipment such as cranes and tunnel boring machines continue to develop towards greater complexity and intelligence, the requirements for operational reliability are becoming increasingly stringent. In fields such as equipment anomaly monitoring, fault diagnosis, and industrial automation, collecting physical monitoring signals is fundamental to accurately understanding the operating status of equipment. Conducting intelligent operation and maintenance based on these monitoring signals is an effective means of ensuring the long-term stable operation of large electro-hydraulic equipment and preventing major safety accidents. However, existing signal acquisition equipment still has shortcomings in terms of accurate, real-time acquisition of high-frequency signals and support for intelligent diagnostic methods. Summary of the Invention

[0003] According to a first aspect of the present disclosure, an intelligent data acquisition terminal is provided, comprising:

[0004] A 16-channel signal acquisition interface is used to synchronously acquire N analog signals from the data source device. The N analog signals include electrical signals and / or integrated electronic piezoelectric IEPE vibration signals, where 1≤N≤16.

[0005] The data sampling module includes 16 signal acquisition channels, an analog-to-digital converter (ADC) chip, and a main control chip. The ADC chip is connected to the 16 signal acquisition interfaces through the 16 signal acquisition channels and is used to convert N analog signals into N digital signals. The ADC chip is connected to the main control chip, which is used to drive the ADC chip to acquire signals according to the sampling frequency based on the Flexible Memory Control (FMC) strategy, and to process the N digital signals to generate private data frames. The sampling frequency is an autonomous frequency that the intelligent data acquisition terminal can adjust within a preset frequency range.

[0006] The communication module includes a communication chip, a network port circuit, and an internal communication circuit. The communication chip is connected to the main control chip via a serial peripheral interface (SPI) bus. The communication chip is connected to the network port circuit, and the network port circuit is connected to the internal communication circuit. The communication chip automatically encapsulates private data frames into standard UDP network packets using the all-hardware User Datagram Protocol (UDP). The network port circuit is used to receive standard UDP network packets and send standard UDP network packets via the internal communication circuit.

[0007] The AI ​​chip, connected to the communication module, is equipped with a UDP listening port, a central processing unit (CPU), and a neural network processing unit (NPU). The UDP listening port is used to capture standard UDP network packets in real time. The data samples obtained after parsing and preprocessing the standard UDP network packets are used as input to the neural network model. At least some network layers of the neural network model are deployed on the NPU. The NPU performs accelerated inference of the neural network model, or the NPU and CPU perform collaborative inference of the neural network model to obtain the analysis results corresponding to the data samples. Collaborative inference includes accelerated inference of the neural network model performed by the NPU and local inference of the neural network model performed by the CPU. The analysis results are used to indicate the operational health status of the data source device. The AI ​​chip is also used to autonomously adjust the sampling frequency of the data sampling module.

[0008] According to a second aspect of the present disclosure, a device monitoring system is provided, comprising:

[0009] Data source devices are used to provide real-time operational data;

[0010] The intelligent data acquisition terminal proposed in the first aspect of this disclosure is used to acquire N analog signals of real-time operating data from a data source device, and obtain analysis results by performing accelerated inference or collaborative inference of a neural network model. The analysis results indicate the operating health status of the data source device.

[0011] A host computer or cloud server is used to perform model training to obtain a neural network model;

[0012] Peripheral devices are connected to intelligent data acquisition terminals to acquire and visualize analysis results.

[0013] According to a third aspect of the embodiments of this disclosure, a data analysis method is proposed, applied to an intelligent data acquisition terminal, comprising:

[0014] The AI ​​chip in the intelligent data acquisition terminal determines the autonomously controlled sampling frequency within a preset frequency range and configures the sampling frequency for the data sampling module;

[0015] N analog signals from the data source device are simultaneously acquired through a 16-channel signal acquisition interface. The N analog signals include electrical signals and / or integrated electronic piezoelectric (IEPE) vibration signals.

[0016] The analog-to-digital converter chip in the data sampling module converts N analog signals into N digital signals.

[0017] The main control chip in the data sampling module drives the analog-to-digital converter chip based on the flexible memory control (FMC) strategy to acquire signals according to the sampling frequency and process the N digital signals to obtain private data frames.

[0018] The communication chip automatically encapsulates private data frames into standard UDP network packets using the all-hardware User Datagram Protocol (UDP).

[0019] Standard UDP network packets are sent to the AI ​​chip via the network port circuit and internal communication circuit.

[0020] The AI ​​chip's UDP listening port captures standard UDP network packets in real time. The data samples obtained after parsing and preprocessing the standard UDP network packets are used as input to the neural network model.

[0021] The analysis results corresponding to the data samples are obtained by accelerating the inference of the neural network model through the NPU or by performing collaborative inference of the neural network model through the NPU and CPU. Collaborative inference includes accelerating the inference of the neural network model through the NPU and performing local inference of the neural network model through the CPU. The analysis results are used to represent the operating health status of the data source device.

[0022] In summary, the intelligent data acquisition terminal provided in this disclosure achieves a multi-channel synchronous high-frequency acquisition capability of up to 30 kSPS through the coordinated operation of 16 signal acquisition interfaces and a data sampling module. It also directly supports the mixed access of IEPE vibration signals and ordinary electrical signals at the front end of the acquisition link, ensuring the integrity of the acquired data and the flexibility of the acquisition scheme from the source. Based on this, the main control chip, using the FMC strategy, drives the analog-to-digital converter chip for signal acquisition. Leveraging the high throughput capability of the FMC parallel bus, it efficiently reads and processes N digital signals into private data frames, overcoming the data transport bottleneck in multi-channel high-frequency acquisition scenarios. Subsequently, the communication chip automatically encapsulates the private data frames into standard UDP network packets via all-hardware UDP and sends them to the AI ​​chip through internal communication circuitry. This eliminates the need for the main control chip's CPU computing power for UDP packet encapsulation and transmission, significantly reducing end-to-end transmission latency from acquisition to communication. The AI ​​chip captures standard UDP network packets in real time through a UDP listening port. After parsing and processing, the packets are input into the neural network model. The AI ​​chip's NPU performs accelerated inference or the CPU and NPU perform collaborative inference to obtain analysis results that characterize the health status of the data source device. At the same time, the AI ​​chip also autonomously adjusts the sampling frequency of the data sampling module within a preset frequency range based on the analysis results or operating strategies. This constructs a complete data closed loop from adaptive sampling rate adjustment, high-frequency acquisition, data forwarding, to model inference, and then back to adaptive sampling rate adjustment. This allows data to complete the entire process from acquisition to intelligent analysis within the terminal without relying on the cloud for data analysis. This eliminates network transmission latency and data security concerns caused by cloud inference, and through the dedicated hardware acceleration architecture of the NPU, it breaks through the computing power bottleneck of general-purpose processors that are difficult to achieve real-time inference. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings required for the description of the embodiments are introduced below. The following drawings are only some embodiments of this disclosure and do not impose specific limitations on the protection scope of this disclosure.

[0024] Figure 1 This is one of the structural schematic diagrams of an intelligent data acquisition terminal provided according to an embodiment of the present disclosure;

[0025] Figure 2 This is a second schematic diagram of the structure of an intelligent data acquisition terminal provided according to an embodiment of the present disclosure;

[0026] Figure 3 This is a three-dimensional schematic diagram of a circuit board for an intelligent data acquisition terminal according to an embodiment of the present disclosure;

[0027] Figure 4 This is a schematic diagram of a circuit board for an intelligent data acquisition terminal according to an embodiment of the present disclosure;

[0028] Figure 5 This is a schematic diagram illustrating the entire process from model training to model inference according to an embodiment of the present disclosure;

[0029] Figure 6 This is a schematic diagram of an equipment monitoring system provided according to an embodiment of the present disclosure;

[0030] Figure 7 This is a flowchart of a data analysis method provided according to an embodiment of the present disclosure.

[0031] Figure label:

[0032] 1. Housing; 2. Power interface; 3. Step-down chip; 4. 16-channel signal acquisition interface; 5. Signal conditioning circuit; 6. Analog-to-digital converter chip; 7. Main control chip; 8. Communication chip; 9. Network port circuit; 10. Internal communication circuit; 11. AI chip; 12. USB interface; 13. Ethernet interface; 14. WiFi antenna interface; 15. 5G antenna interface; 16. Hardware programming port. Detailed Implementation

[0033] This disclosure presents an intelligent data acquisition terminal, an equipment monitoring system, and a data analysis method.

[0034] This disclosure is not exhaustive, but merely illustrative of some embodiments, and is not intended to limit the scope of protection of this disclosure. Unless otherwise specified, each step, component, part, device, or apparatus in a particular embodiment can be implemented as an independent embodiment, and these steps, components, parts, devices, and apparatuses can be arbitrarily combined. For example, the solution after removing some steps, components, parts, devices, or apparatuses in a particular embodiment can also be implemented as an independent embodiment, and the order of steps in a particular embodiment can be arbitrarily interchanged. Furthermore, the optional implementation methods in a particular embodiment can be arbitrarily combined; moreover, the embodiments can be arbitrarily combined. For example, some or all steps, components, parts, devices, and apparatuses of different embodiments can be arbitrarily combined, and a particular embodiment can be arbitrarily combined with the optional implementation methods of other embodiments. In all embodiments of this disclosure, unless otherwise specified or logically conflicting, the terminology and / or descriptions between the embodiments are consistent and can be mutually referenced. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0035] The terminology used in the embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure.

[0036] Large electro-hydraulic equipment such as cranes and tunnel boring machines play a crucial supporting role in national economic construction. As this equipment continues to develop towards greater complexity and size, the requirements for overall operational reliability are becoming increasingly stringent. In fields such as equipment anomaly monitoring, fault diagnosis, and industrial automation, monitoring data contains rich fault characteristic information. High-frequency monitoring signal acquisition is the foundation for accurately grasping the operating status of equipment. Intelligent operation and maintenance based on monitoring signals is an effective means to ensure the long-term stable operation of large electro-hydraulic equipment and prevent major safety accidents.

[0037] As monitoring scenarios become increasingly complex, multi-channel high-frequency continuous sampling generates massive amounts of raw monitoring data. In related technologies, the device side cannot provide the computing power to support artificial intelligence (AI) model inference. All collected data needs to be uploaded to the cloud for unified processing, which not only significantly consumes network bandwidth resources but also causes data transmission delays and processor operation response delays. This centralized computing mode, which is highly dependent on the network, also restricts the real-time performance of intelligent operation and maintenance health monitoring.

[0038] Therefore, in order to solve the above problems, this solution proposes an intelligent data acquisition terminal, an equipment monitoring system, and a data analysis method. Specifically, it is an intelligent high-frequency data acquisition and analysis terminal equipped with an artificial intelligence chip and having artificial intelligence edge computing function, and a method for high-speed data acquisition and transmission and real-time AI analysis and reasoning based on the terminal.

[0039] Figure 1 This is one of the structural schematic diagrams of an intelligent data acquisition terminal provided according to an embodiment of this disclosure. In some embodiments, such as... Figure 1 As shown, the intelligent data acquisition terminal includes: a 16-channel signal acquisition interface, a data sampling module, a communication module, and an AI chip.

[0040] In some embodiments, the 16-channel signal acquisition interface can be connected to a data source device to acquire data or signals from the data source device. The data source device can be a monitored device or a device that requires data analysis. In this disclosure, the data source device can be various industrial equipment, such as large electro-hydraulic equipment like cranes and tunnel boring machines, and this disclosure does not limit its scope.

[0041] In some embodiments, the 16-channel signal acquisition interface is used to synchronously acquire N analog signals from the data source device, where 1 ≤ N ≤ 16. Each analog signal can be an electrical signal or an integrated electronic piezoelectric (IEPE) vibration signal. The electrical signal can be a current or voltage signal acquired by a pressure / temperature / displacement sensor in the data source device, and the IEPE vibration signal can be acquired by an IEPE sensor in the data source device.

[0042] This disclosure supports the simultaneous acquisition of ordinary electrical signals and IEPE vibration signals, and can be adapted to various types of data source devices (such as accelerometers, pressure sensors, microphones, etc.), greatly expanding the application scenarios for terminal data acquisition and analysis detection of various industrial equipment.

[0043] In some embodiments, the 16 data acquisition interfaces can perform data acquisition independently. The signals acquired by each interface can be of the same or different types, and each interface can perform data acquisition simultaneously. In other words, the 16 data acquisition channels corresponding to the 16 data acquisition interfaces can perform independent data acquisition. Each channel can be equipped with a signal conditioning circuit, and the signal conditioning circuit is equipped with an independent DIP switch. Different switch combinations correspond to different signal categories. When the IEPE power supply circuit supplies power to the vibration sensor of the data source device, the IEPE vibration signal is acquired. The signal conditioning circuit performs noise reduction and filtering processing on the acquired IEPE vibration signal. When the IEPE power supply circuit stops supplying power, an electrical signal is acquired, and the electrical signal does not pass through the signal conditioning circuit.

[0044] In some embodiments, the data sampling module includes 16 signal acquisition channels, an analog-to-digital converter chip, and a main control chip. The analog-to-digital converter chip is connected to 16 signal acquisition interfaces through the 16 signal acquisition channels, and is used to convert N analog signals into N digital signals.

[0045] In some embodiments, the main control chip is connected to the analog-to-digital converter (ADC) chip to drive the ADC chip to acquire signals at a sampling frequency based on a Flexible Memory Controller (FMC) strategy. For example, the FMC strategy can involve signal acquisition and reading via the FMC bus. In other words, to overcome the bottleneck of General-Purpose Input / Output (GPIO) data reading, this solution uses FMC bus address mapping technology to achieve data acquisition. The main control chip, through configuration, maps the data address of the ADC chip to its own memory space, directly accessing the data within the ADC chip at high speed according to its self-controlled sampling frequency. This allows the main control chip to directly access the FMC memory mapping area via the memory pointer during interrupt responses without executing time-consuming pin toggling instructions, reading the 16-channel parallel bus data in real time, and quickly storing it in a circular buffer.

[0046] In some embodiments, the sampling frequency is a frequency that the intelligent data acquisition terminal autonomously adjusts within a preset frequency range. For example, the AI ​​chip can autonomously adjust the sampling frequency within a preset frequency range and configure the autonomously adjusted sampling frequency to the data sampling module, enabling the main control chip to drive the analog-to-digital converter chip to acquire signals through a 16-channel signal acquisition interface according to the configured sampling frequency. For instance, the configuration command sent by the main control chip to the analog-to-digital converter chip can be a PWM variable frequency square wave, where the frequency of the square wave corresponds to the sampling frequency. The analog-to-digital converter chip can then dynamically sample based on the received sampling frequency. Through adaptive sampling control, the AI ​​chip can autonomously adjust the sampling frequency within a preset frequency range according to actual application requirements, achieving dynamic optimization of the acquisition strategy and balancing the needs of high-precision monitoring and low-power operation under different working conditions.

[0047] For example, the preset frequency range can be (0 kSPS, 30 kSPS) or [25 kSPS, 30 kSPS]. In other words, the intelligent data acquisition terminal can autonomously adjust the sampling frequency according to the monitoring needs of the data source device and the actual application situation in the data sampling module. Through real-time sampling of high-frequency data, it can accurately grasp the operating status of the equipment, ensure the long-term stable operation of industrial equipment, and effectively prevent major safety accidents.

[0048] In some embodiments, the main control chip can process N digital signals to obtain private data frames. For example, the main control chip can construct private data frames from digital signals in a circular buffer. The private data frames may have a 2-byte frame header, a 4-byte timestamp, and a 2-byte checksum. For example, the private data frames may also include a 16-byte data portion.

[0049] In some embodiments, the communication module includes a communication chip, a network port circuit, and an internal communication circuit. The communication chip is connected to the main control chip via a Serial Peripheral Interface (SPI) bus. The communication chip is connected to the network port circuit, and the network port circuit is connected to the internal communication circuit. The communication chip automatically encapsulates private data frames into standard UDP network packets using the all-hardware User Datagram Protocol (UDP). The network port circuit is used to receive standard UDP network packets and send standard UDP network packets via the internal communication circuit.

[0050] This disclosure utilizes full hardware UDP for message encapsulation, significantly freeing up the CPU computing power of the main control chip. This solves problems such as latency, insufficient computing power, and poor real-time monitoring caused by high-frequency data acquisition in related technologies. Furthermore, the main control chip and communication chip communicate via SPI register read / write operations (similar to operating local RAM). This not only shortens the development cycle but also fundamentally eliminates the risk of system crashes due to protocol stack vulnerabilities (such as memory leaks and pointer out-of-bounds errors), greatly improving the on-site operational stability of the terminal.

[0051] In some embodiments, the AI ​​chip is connected to the communication module. The AI ​​chip is equipped with a UDP listening port, a central processing unit (CPU), and a neural processing unit (NPU). The UDP listening port is used to capture standard UDP network packets in real time. The data samples obtained after parsing and preprocessing the standard UDP network packets are used as input to the neural network model. At least some network layers of the neural network model are deployed on the NPU. The NPU performs accelerated inference of the neural network model, or the NPU and CPU perform collaborative inference of the neural network model to obtain the analysis results corresponding to the data samples. Collaborative inference includes the NPU performing accelerated inference of the neural network model and the CPU performing local inference of the neural network model. The analysis results are used to represent the operating health status of the data source device.

[0052] For example, the CPU of the AI ​​chip controls the UDP listening port to parse the packets. The CPU further performs preprocessing on the acquired signals, such as segmentation, normalization, and time-frequency transformation, to generate input data adapted to the neural network model. The AI ​​chip sends the input data to the NPU for inference calculation through the internal data interface.

[0053] In some embodiments, the AI ​​chip is also used to autonomously adjust the sampling frequency of the data sampling module. For example, during downlink transmission from the AI ​​chip to the data sampling module via the communication chip, the AI ​​chip sends a control command to the communication chip, indicating a sampling frequency that the AI ​​chip autonomously adjusts. The control command is then fed back into the communication chip via the Ethernet port circuit. The communication chip performs level conversion and data verification on the control command to generate a standard digital signal. The standard digital signal is stored in the transmission register of the communication chip and transmitted back to the main control chip via the SPI bus. The main control chip parses the standard digital signal through its application layer and sends a configuration command to the analog-to-digital converter chip, thereby configuring the autonomously adjustable sampling frequency for the data sampling module.

[0054] For example, the analog-to-digital converter chip in this disclosure can be the AD7616 chip, the main control chip can be the STM32 chip, and the communication chip can be the W5500 communication chip. This disclosure does not limit the choice of chip.

[0055] In summary, the intelligent data acquisition terminal provided in this disclosure achieves a multi-channel synchronous high-frequency acquisition capability of up to 30 kSPS through the coordinated operation of 16 signal acquisition interfaces and a data sampling module. It also directly supports the mixed access of IEPE vibration signals and ordinary electrical signals at the front end of the acquisition link, ensuring the integrity of the acquired data and the flexibility of the acquisition scheme from the source. Based on this, the main control chip, using the FMC strategy, drives the analog-to-digital converter chip for signal acquisition. Leveraging the high throughput capability of the FMC parallel bus, it efficiently reads and processes N digital signals into private data frames, overcoming the data transport bottleneck in multi-channel high-frequency acquisition scenarios. Subsequently, the communication chip automatically encapsulates the private data frames into standard UDP network packets via all-hardware UDP and sends them to the AI ​​chip through internal communication circuitry. This eliminates the need for the main control chip's CPU computing power for UDP packet encapsulation and transmission, significantly reducing end-to-end transmission latency from acquisition to communication. The AI ​​chip captures standard UDP network packets in real time through a UDP listening port. After parsing and processing, the packets are input into the neural network model. The AI ​​chip's NPU performs accelerated inference or the CPU and NPU perform collaborative inference to obtain analysis results that characterize the health status of the data source device. At the same time, the AI ​​chip also autonomously adjusts the sampling frequency of the data sampling module within a preset frequency range based on the analysis results or operating strategies. This constructs a complete data closed loop from adaptive sampling rate adjustment, high-frequency acquisition, data forwarding, to model inference, and then back to adaptive sampling rate adjustment. This allows data to complete the entire process from acquisition to intelligent analysis within the terminal without relying on the cloud for data analysis. This eliminates network transmission latency and data security concerns caused by cloud inference, and through the dedicated hardware acceleration architecture of the NPU, it breaks through the computing power bottleneck of general-purpose processors that are difficult to achieve real-time inference.

[0056] Figure 2 This is a second structural schematic diagram of an intelligent data acquisition terminal provided according to an embodiment of the present disclosure. Figure 1 On the basis of, such as Figure 2 As shown, the intelligent analysis terminal also includes at least one of a signal conditioning circuit, a power supply module, and an interface module.

[0057] In some embodiments, each of the 16 signal acquisition channels is provided with a signal conditioning circuit. The analog-to-digital converter chip is connected to the 16 signal acquisition interface through the signal conditioning circuit. The signal conditioning circuit is provided with an IEPE power supply circuit and a high-frequency anti-aliasing filter circuit. The high-frequency anti-aliasing filter circuit is used to perform noise reduction filtering on the acquired N analog signals. When the IEPE power supply circuit is turned on, it powers the IEPE sensor of the data source device to acquire the IEPE vibration signal. When the IEPE power supply circuit is turned off, it acquires electrical signals, which do not pass through the signal conditioning circuit.

[0058] In some embodiments, the power module includes a power interface and a step-down chip. The step-down chip is used to convert the external input voltage into a multi-level voltage, which is used to meet the power supply requirements of the IEPE power supply circuit, the data sampling module, the communication chip, and the AI ​​chip in the signal conditioning circuit.

[0059] In some embodiments, the interface module includes at least one of a USB interface, an Ethernet interface, a WiFi antenna interface, a 5G antenna interface, and a hardware programming port, and the AI ​​chip is connected to the interface module via a Peripheral Component Interconnect Express (PCIe) bus.

[0060] The terminal has an independent power supply module with a step-down chip as its core, which can regulate the 24V external input power supply to multi-level power supplies such as 1.8V, 3.3V, 5V, and 12V to meet the power supply requirements of interface conversion module, signal conditioning module, data sampling module, AI chip, and communication chip, thus building a highly integrated, low-interference, and stable hardware architecture at both the physical and functional levels.

[0061] Therefore, in this disclosure, the IEPE power supply circuit in the signal conditioning circuit can be turned on or off as needed, making the same channel compatible with piezoelectric sensors and ordinary voltage output sensors. At the same time, the high-frequency anti-aliasing filter circuit filters out noise in advance, ensuring the purity of the signal under high-frequency signal acquisition from the source. The power module converts a single external input voltage into multi-level voltages to meet the differentiated power needs of different modules in the terminal. The interface module connects the AI ​​chip and multiple types of interfaces such as USB / Ethernet / WiFi / 5G through the PCIe high-speed bus, enabling the terminal to have both wired local area networking and wireless wide area transmission capabilities.

[0062] In some embodiments, the data sampling module is provided with a first hardware programming port, and the AI ​​chip is provided with a second hardware programming port. The first and second hardware programming ports are independent and isolated from each other. The hardware programming ports are used for firmware downloading and updating of the data sampling module and the AI ​​chip.

[0063] For example, the data sampling module and the AI ​​chip each have their own dedicated programming interface (e.g., two different pin headers or connectors on a circuit board). The signal lines of these two programming ports are electrically isolated (e.g., using isolation chips or optocouplers). When programming the AI ​​chip, even if the AI ​​chip is accidentally short-circuited or experiences an abnormal voltage, it will not damage the data sampling module chip through the programming port. The data sampling module and the AI ​​chip may communicate via an internal bus (such as SPI, FMC) or via a network port, but during programming, the programming operation of one module will not interfere with the normal operation or internal state of the other module. This allows the two modules to be upgraded separately without interference, and the electrical isolation effectively prevents secondary damage caused by static electricity or abnormal voltage on one programming port being conducted to the other module.

[0064] In some embodiments, the main control chip triggers a pulse width modulation (PWM) signal via a timer to drive the analog-to-digital converter (ADC) chip to acquire N analog signals and initiate multi-channel timing conversion to convert the N analog signals into N digital signals.

[0065] For example, multi-channel timing conversion can be performed by converting signals from multiple channels according to their timing sequence. Taking the acquisition of 16 signals as an example, the 16 signals are converted sequentially, for a total of 16 conversions. When using the AD7616 chip, the dual ADC core of the AD7616 chip can include two conversion channels (e.g., A and B). In one conversion of the chip, two data channels (e.g., A0 and B0) can be converted simultaneously. Therefore, the 16 data channels can be converted in 8 conversions by the chip.

[0066] After the analog-to-digital converter (ADC) chip completes a multi-channel timing conversion, the sequencer inside the ADC chip inputs N digital signals to the ADC chip's 16-bit parallel bus interface. The status output terminal of the ADC chip generates a flag transition signal. After the port data register of the main control chip captures the flag transition signal, it triggers the external interrupt controller in the main control chip to generate an interrupt start signal.

[0067] For example, in a 16-bit parallel bus interface, each interface is used to transmit one bit of data for one signal. If the 16-bit parallel bus interface transmits one signal at a time, then the 16 signals will be transmitted 16 times in total.

[0068] The main control chip includes an FMC controller, a ring buffer, and an SPI data transmission register. The main control chip obtains the digital signal output by the analog-to-digital converter chip according to the sampling frequency through the FMC bus address mapping method. When the main control chip generates an interrupt start signal, it directly accesses the FMC controller through the memory pointer without waiting for the pin toggle instruction, and immediately reads the digital signal output by the 16-bit parallel bus interface and stores it in the ring buffer. The main control chip constructs a private data frame from the digital signal in the ring buffer.

[0069] Private data frames in the circular buffer are sent to the SPI data transmit register.

[0070] For example, the SPI data transmit register can be a Static Random-Access Memory (SRAM) transmit area. Private data frames in the circular buffer can be organized before being sent to the SPI data transmit register. This organization can, for example, arrange 16 signals according to the transmit frame format. The signals are moved to the SRAM transmit area by Direct Memory Access (DMA) or the CPU.

[0071] Therefore, the intelligent data acquisition terminal disclosed herein ensures that the sampling start time of the 16 channels is strictly consistent through PWM synchronous triggering, eliminating phase measurement errors between channels; the main control chip directly accesses the FMC controller through the memory pointer without waiting for the pin toggling instruction when the interrupt is triggered, matching the high-speed data reading requirements and effectively preventing the loss of sampling points; the ring buffer decouples the rate difference between the high-speed input of the acquisition end and the output of the SPI transmitter, so that the sampling process is not blocked when the communication link is momentarily congested, thereby ensuring uninterrupted operation of high-frequency acquisition.

[0072] In some embodiments, during the uplink transmission from the data sampling module to the AI ​​chip via the communication module, the main control chip constructs a private data frame with a 2-byte frame header, a 4-byte timestamp, and a 2-byte checksum in a circular buffer. The private data frame is sent to the SPI data transmission register. The private data frame is input to the communication chip in the form of an SPI serial data stream. After the private data frame forms a standard UDP network packet in the communication chip, it is output to the network port circuit as an electrical signal through the data transmission register of the communication chip. After voltage calibration by the network isolation transformer in the network port circuit, it is sent to the AI ​​chip through the internal communication circuit. After receiving the standard UDP network packet, the AI ​​chip parses it into hexadecimal data according to the private data frame format through the UDP listening port. The hexadecimal data is processed according to the sample input format requirements of the neural network model and then sent to the neural network model deployed on the AI ​​chip for inference and outputs the analysis results. The AI ​​chip can call the NPU for accelerated inference and / or call the CPU for local inference.

[0073] For example, in the input of N signals / data, each signal / data consists of 24 bytes, including a 16-bit data portion, a 2-byte frame header, a 4-byte timestamp, and a 2-byte checksum. The standard UDP network packet size includes the size of the N signals / data (N*24 bytes) plus the bytes occupied by the UDP protocol encapsulation.

[0074] Therefore, the intelligent data acquisition terminal provided in this disclosure minimizes transmission overhead by using an 8-byte private frame header (including frame header, timestamp, and checksum), thereby improving the effective data payload rate. The network isolation transformer performs voltage calibration on the Ethernet signal, effectively suppressing the impact of common-mode interference in industrial environments on transmission reliability. Furthermore, the uplink acquisition, framing, network packetization, and AI inference form a parallel architecture. While the main control chip processes the current frame, the communication chip is framing the previous frame, and the AI ​​chip is inferring the previous frame, thus significantly reducing the overall latency from analog input to output.

[0075] In some embodiments, during the downlink transmission from the AI ​​chip to the data sampling module via the communication chip, the AI ​​chip sends a control command to the communication chip, indicating a sampling frequency. The control command is then fed back into the communication chip via the Ethernet port circuit. The communication chip performs level conversion and data verification on the control command to generate a standard digital signal. The standard digital signal is stored in the transmission register of the communication chip and transmitted back to the main control chip via the SPI bus. The main control chip parses the standard digital signal through its application layer and sends a configuration command to the analog-to-digital converter chip, thereby configuring the sampling frequency for the data sampling module.

[0076] Therefore, this disclosure utilizes the same Ethernet and SPI physical link shared with the uplink data stream to establish a reverse control channel, enabling the AI ​​chip to transmit dynamically determined sampling frequency commands to the data sampling module via downlink configuration signaling. In this disclosure, the sampling frequency is not a static preset value, but a dynamic value that is adjusted in real time according to the device's operating health status. In steady state, the frequency is reduced to save power and bandwidth, and when abnormal symptoms appear, the frequency is increased to obtain fine fault characteristics. Through this dynamic adjustment strategy, on-demand allocation of acquisition resources and dynamic optimization of the overall power consumption of the terminal are achieved.

[0077] In some embodiments, the AI ​​chip further includes: a shared memory region and an internal communication interface; the CPU and NPU can read data from the shared memory region and communicate through the internal communication interface. The CPU has at least one of the following functions:

[0078] Obtain a general model file of the neural network model from a host computer or cloud server. The general model file includes multiple operators, operator information for each operator, and data transfer relationships between multiple operators. The operator information includes at least one of the following: operator type, input tensor information, output tensor information, weight parameter information, and data type.

[0079] During the model deployment phase, the general model files are processed, including: converting the general model files into dedicated model files that can be deployed to AI chips; generating an operator set based on the neural network model, and matching the operator set with the operator capability descriptions supported by the NPU according to the acceleration execution conditions of the AI ​​chip, dividing the operators into first operators that meet the acceleration execution conditions and second operators that do not meet the acceleration execution conditions; quantizing the first operators, and deploying the quantized first operators to the NPU, and deploying the second operators to the CPU;

[0080] During the model deployment phase, configuration files are generated, including: generating inference program files, hardware runtime configuration files, and model version information corresponding to the dedicated model files, and encapsulating the dedicated model files, inference program files, hardware runtime configuration files, and model version information into a terminal task package;

[0081] During the model deployment phase, the terminal task package is parsed to obtain the first operator weight parameters and the second operator weight parameters, and the first operator weight parameters and the second operator weight parameters are stored in the shared storage area to complete the deployment of the neural network model.

[0082] During the model inference phase, the storage address of the first operator weight parameters in the shared storage space is sent to the NPU, and the inference program file and hardware runtime configuration file are executed; the first intermediate result obtained by the NPU executing the first operator is received, the second intermediate result obtained by the CPU executing the second operator is sent to the NPU, and the analysis results are sent to the host computer or cloud server after the model inference is completed.

[0083] In some embodiments, the CPU is also used to: perform preprocessing on the acquired monitoring signals, such as segmentation, normalization, and time-frequency transformation, to generate input data adapted to a dedicated neural network model.

[0084] Therefore, AI chips accelerate inference through NPU execution or through collaboration between the CPU and NPU, thereby accelerating data analysis and computational division of labor. After quantizing and mapping the neural network model, the AI ​​chip encapsulates the model file, inference program, hardware configuration, and version information into a terminal task package and stores it in shared storage, enabling the terminal to have fully offline autonomous deployment capabilities. During inference, the AI ​​chip loads the task package and collaborates with the local CPU and NPU to accelerate inference; the task package carries version information, giving the model traceability and rollback capabilities, improving maintainability and iterative deployment efficiency for long-term field operation.

[0085] In some embodiments, the neural network model can be completely parsed into a first operator that can be accelerated by the NPU. In such scenarios, the NPU independently performs inference computation. The NPU receives input data from the CPU and returns the inference results, so that the CPU is responsible for data distribution and result collection. The two are asynchronous and run in parallel, minimizing inference latency and meeting the real-time processing requirements of high-frequency acquisition at the front end.

[0086] Based on the above Figure 1 and Figure 2 The embodiment shown, Figure 3 This is a three-dimensional schematic diagram of a circuit board for an intelligent data acquisition terminal according to an embodiment of the present disclosure. Figure 4 This is a schematic diagram of a circuit board for an intelligent data acquisition terminal according to an embodiment of this disclosure. Figure 3 and Figure 4As shown, the intelligent data acquisition terminal includes: left and right aluminum alloy side shells 1 as the main frame, used for physical support and dust protection; a 24V power interface 2 located on the wiring side of the shell, connected to an external independent power supply for powering the entire unit, and equipped with a step-down chip 3; a 16-channel signal acquisition interface 4 for synchronously acquiring multiple channels of raw analog signals; a signal conditioning circuit 5 (e.g., including a Sallen-Key filter circuit) for filtering out noise signals; an analog-to-digital converter chip 6 (e.g., AD7616) for receiving analog signals and converting them into digital signals; and a main control chip 7 (e.g., STM32) for achieving high-frequency sampling (e.g., 20V) based on FMC bus technology. The terminal's data sampling module consists of an analog-to-digital converter chip 6 (with kSPS or even higher) and a main control chip 7. A communication chip 8 (e.g., W5500) is used for packet uploading of the collected data. A network port circuit 9 connects to the main control chip 7 and transmits data. An internal communication circuit 10 inputs signals to the AI ​​chip 11 for edge computing. The AI ​​chip 11 captures message signals in real time, parses and processes the data, and uses a neural network model for inference to monitor and analyze data sources. A USB interface 12 (e.g., USB 3.0) and an Ethernet interface 13 (e.g., RJ45) are used for efficient wired network communication. A WiFi antenna interface 14 and a 5G antenna interface 15 are used for wireless bidirectional communication between the terminal and peripheral devices. A hardware programming port 16 is used to update the operating system programs corresponding to the main control chip and the AI ​​chip in the data sampling module. The hardware programming ports for the data sampling module and the AI ​​chip are independently configured (the independent effect is not shown in the figure). The overall dimensions of the circuit board are 170 mm × 150 mm × 55 mm. Figure 3 and Figure 4 The structures not numbered in the figure represent other functional structures of the intelligent data acquisition terminal, which are not improved in this disclosure and therefore will not be described in detail here, but are shown in the figure for the sake of product completeness and authenticity.

[0087] Figure 5 This is a schematic diagram illustrating the entire process from model training to model inference according to an embodiment of this disclosure.

[0088] During the model training phase, the host computer / cloud server acquires the raw monitoring data, performs data processing such as noise reduction and time-frequency domain transformation, uses the processed data to execute model training, and sends the general model file of the trained neural network model to the AI ​​chip. The host computer or cloud server acquires the general model file of the neural network model, which includes multiple operators, operator information for each operator, and data transfer relationships between multiple operators; the operator information includes at least one of the following: operator type, input tensor information, output tensor information, weight parameter information, and data type.

[0089] For example, the intelligent data acquisition terminal acquires raw monitoring data (such as the N analog signals described in the above embodiments) in real time and sends the raw monitoring data to a host computer or cloud server connected to it. The raw monitoring data may include voltage signals, current signals, and IEPE vibration signals. The host computer or cloud server performs at least one of the following processing on the received raw monitoring data: data segmentation, noise reduction, time-domain transformation, frequency-domain transformation, data annotation, and dataset partitioning. The processed data is then input into an AI training framework for training to obtain a neural network model with anomaly monitoring function (monitoring abnormal equipment conditions), fault diagnosis function (classifying equipment fault types), and health status prediction function (predicting equipment health assessment indicators, remaining lifespan, etc.). This model is not limited to a specific algorithm or a specific network structure. The trained neural network model may include, but is not limited to, convolutional networks, residual networks, multilayer perceptrons, long short-term memory networks, autoencoder networks, attention networks, feature fusion networks, etc.

[0090] In some embodiments, during training, a host computer or cloud server can map the original one-dimensional signal into a two-dimensional feature image containing time-domain and frequency-domain information. Core features are extracted and confidence scores are calculated from the two-dimensional feature image. The loss value is calculated by comparing the image with real fault labels, and backpropagation is performed to update the weight parameters based on the loss value. This process is iterated until the loss value converges, resulting in a trained model. After training, the host computer or cloud server stores the trained model as a general-format model file and sends it to the AI ​​chip of the intelligent data acquisition terminal. The AI ​​chip then performs subsequent model conversion and deployment. This disclosure uses a two-dimensional feature image as an example of the input format for training data; however, this disclosure does not limit the use of other input formats such as one-dimensional signals.

[0091] During the model deployment phase, the AI ​​chip processes the general model file, including: converting the general model file into a dedicated model file that can be deployed to the AI ​​chip; generating an operator set based on the neural network model, and matching the operator set with the operator capability description supported by the NPU according to the acceleration execution conditions of the AI ​​chip, dividing the operators into first operators that meet the acceleration execution conditions and second operators that do not meet the acceleration execution conditions; quantizing the first operators, and deploying the quantized first operators to the NPU, and deploying the second operators to the CPU.

[0092] During the model deployment phase, the AI ​​chip also generates configuration files, including: generating inference program files corresponding to the dedicated model files, hardware operation configuration files, and model version information, and encapsulating the dedicated model files, inference program files, hardware operation configuration files, and model version information into a terminal task package.

[0093] During the model deployment phase, the AI ​​chip also parses the terminal task package to obtain the first operator weight parameters and the second operator weight parameters, and stores the first operator weight parameters and the second operator weight parameters in the shared storage area to complete the deployment of the neural network model.

[0094] During the model inference phase, the data sampling module transmits the raw monitoring data collected in real time to the AI ​​chip. The AI ​​chip processes the raw monitoring data and generates data samples adapted to the format requirements of the neural network model as model input. The AI ​​chip sends the storage address of the first operator weight parameters in the shared storage space to the NPU and executes the inference program file and hardware runtime configuration file. During the NPU's accelerated inference or the NPU and CPU's collaborative inference, the CPU can receive the first intermediate result obtained by the NPU executing the first operator, and the CPU can also send the second intermediate result obtained by the CPU executing the second operator to the NPU, thus obtaining the final analysis result. After completing the model inference, the CPU can send the analysis result to the host computer or cloud server for result storage, display, analysis, or subsequent processing. The intelligent acquisition terminal can also present the monitoring and analysis results intuitively through on-site audio-visual signals, enabling maintenance personnel to quickly complete on-site fault location and status inspection without external debugging equipment, lowering the maintenance threshold. In addition, the CPU can send the analysis result to peripheral devices, or upload the raw acquisition signal for analysis and processing by the host computer or cloud server before sending the processed result to peripheral devices for further visualization.

[0095] This disclosure also provides an equipment monitoring system. Figure 6 This is a schematic diagram of a device monitoring system provided according to an embodiment of the present disclosure, such as... Figure 6 As shown, the equipment monitoring system includes data source devices, intelligent analysis terminals, a host computer or cloud server, and peripheral devices. The data source devices provide real-time operational data, and the intelligent data acquisition terminals are as described above. Figures 1 to 5 In this embodiment, N analog signals of the aforementioned real-time operational data are acquired from the data source device, and analysis results are obtained by performing accelerated inference or collaborative inference of a neural network model. These analysis results represent the operational health status of the data source device, which will not be elaborated further here. A host computer or cloud server is used to perform model training to obtain the neural network model. Peripheral devices are connected to the intelligent data acquisition terminal to acquire real-time operational data or analysis results and store or visualize them.

[0096] This disclosure also provides a data analysis method, applicable to, for example... Figures 1 to 5 The intelligent data acquisition terminal described Figure 7 This is a flowchart of a data analysis method provided according to an embodiment of the present disclosure, such as... Figure 7 As shown, the method includes the following steps:

[0097] Step S701: The AI ​​chip in the intelligent data acquisition terminal determines the autonomously controlled sampling frequency within a preset frequency range and configures the sampling frequency for the data sampling module.

[0098] Step S702: Synchronously acquire N analog signals from the data source device through the 16-channel signal acquisition interface. The N analog signals include electrical signals and / or IEPE vibration signals, where 1≤N≤16.

[0099] Step S703: Convert N analog signals into N digital signals using the analog-to-digital converter chip in the data sampling module;

[0100] Step S704: The main control chip in the data sampling module drives the analog-to-digital converter chip to acquire signals according to the sampling frequency based on the FMC strategy, and processes the N digital signals to obtain private data frames.

[0101] Step S705: The communication chip automatically encapsulates the private data frame into a standard UDP network packet via UDP.

[0102] Step S706: Send a standard UDP network message to the AI ​​chip via the network port circuit and the internal communication circuit.

[0103] Step S707: The AI ​​chip's UDP listening port captures standard UDP network packets in real time. The data samples obtained after parsing and preprocessing the standard UDP network packets are used as input to the neural network model.

[0104] In step S708, the AI ​​chip obtains the analysis results corresponding to the data samples by performing accelerated inference of the neural network model through the NPU or by performing collaborative inference of the neural network model through the NPU and CPU. Collaborative inference includes accelerated inference of the neural network model performed by the NPU and local inference of the neural network model performed by the CPU. The analysis results are used to represent the operating health status of the data source device.

[0105] In some embodiments, the AI ​​chip in the intelligent data acquisition terminal determines an autonomously adjustable sampling frequency within a preset frequency range and configures the sampling frequency for the data sampling module. This includes: during downlink transmission from the AI ​​chip to the data sampling module via the communication chip, the AI ​​chip sends a control command to the communication chip, the control command indicating a sampling frequency; the control command is then sent back to the communication chip via a network port circuit; the communication chip performs level conversion and data verification on the control command to generate a standard digital signal and stores it in the communication chip's transmit register; the standard digital signal is then transmitted back to the main control chip via the SPI bus; the main control chip parses the standard digital signal through its application layer and sends a configuration command to the analog-to-digital converter chip, thereby configuring the sampling frequency for the data sampling module.

[0106] In some embodiments, the method further includes: obtaining a general model file of a neural network model from a host computer or a cloud server, the general model file including multiple operators, operator information of each operator, and data transfer relationships between multiple operators; the operator information includes at least one of operator type, input tensor information, output tensor information, weight parameter information, and data type;

[0107] During the model deployment phase, the general model files are processed, including: converting the general model files into dedicated model files that can be deployed to AI chips; generating an operator set based on the neural network model, and matching the operator set with the operator capability descriptions supported by the NPU according to the acceleration execution conditions of the AI ​​chip, dividing the operators into first operators that meet the acceleration execution conditions and second operators that do not meet the acceleration execution conditions; quantizing the first operators, and deploying the quantized first operators to the NPU, and deploying the second operators to the CPU;

[0108] During the model deployment phase, configuration files are generated, including: generating inference program files, hardware runtime configuration files, and model version information corresponding to the dedicated model files, and encapsulating the dedicated model files, inference program files, hardware runtime configuration files, and model version information into a terminal task package;

[0109] During the model deployment phase, the terminal task package is parsed to obtain the first operator weight parameters and the second operator weight parameters, and the first operator weight parameters and the second operator weight parameters are stored in the shared storage area to complete the deployment of the neural network model.

[0110] During the model inference phase, the storage address of the first operator weight parameters in the shared storage space is sent to the NPU, and the inference program file and hardware runtime configuration file are executed; the first intermediate result obtained by the NPU executing the first operator is received, the second intermediate result obtained by the CPU executing the second operator is sent to the NPU, and the analysis results are sent to the host computer or cloud server after the model inference is completed.

[0111] In some embodiments, the method further includes, for example: Figures 1 to 5 The various functional steps described in the intelligent data acquisition terminal of the embodiments will not be repeated here.

[0112] In some embodiments, this disclosure also includes virtual devices, storage media, etc., capable of performing the above-described data analysis methods, which will not be elaborated here.

[0113] In this disclosure, unless otherwise stated, elements expressed in the singular form, such as "a," "an," "the," "the," "the," "the," "the," "the," "this," etc., can mean "one and only one," or "one or more," "at least one," etc. For example, when using articles such as "a," "an," "the," etc. in translation, the noun following the article can be understood as either a singular or a plural expression.

[0114] In the embodiments disclosed herein, "multiple" refers to "two or more", "at least two", etc. The terms "at least one of A or B", "at least one of A and B", "one or more", "a plurality of", "multiple" etc. can be used interchangeably.

[0115] In some embodiments, the notation "A or B" may include the following technical solutions, depending on the situation: in some embodiments, A (execute A regardless of whether a branch B exists); in some embodiments, B (execute B regardless of whether a branch A exists); in some embodiments, execution is selected from A and B (A and B are selectively executed). The same applies when there are more branches such as A, B, and C.

[0116] The prefixes "first," "second," etc., used in the embodiments of this disclosure are merely for distinguishing different descriptive objects and do not impose restrictions on the position, order, priority, quantity, or content of the descriptive objects. The description of the descriptive objects is found in the claims or the context of the embodiments, and the use of prefixes should not constitute unnecessary restrictions. For example, if the descriptive object is a "field," the ordinal numbers preceding "field" in "first field" and "second field" do not restrict the position or order of the "fields." "First" and "second" do not restrict whether the "fields" they modify are in the same message, nor do they restrict the order of "first field" and "second field." Similarly, if the descriptive object is a "level," the ordinal numbers preceding "level" in "first level" and "second level" do not restrict the priority between "levels." Furthermore, the number of descriptive objects is not limited by ordinal numbers and can be one or more. For example, in "first device," the number of "devices" can be one or more. Furthermore, the objects modified by different prefixes can be the same or different. For example, if the object being described is "device", then "first device" and "second device" can be the same device or different devices, and their types can be the same or different. Similarly, if the object being described is "information", then "first information" and "second information" can be the same information or different information, and their content can be the same or different.

[0117] In some embodiments, terms such as “in response to…”, “in response to determining…”, “in the case of…”, “when…”, “when…”, “if…”, etc. can be used interchangeably. These descriptions all refer to the device making a corresponding action under certain objective circumstances. They do not necessarily limit the time, nor do they require the device to make a judgment action when implementing it, nor do they mean that there must be other limitations.

[0118] In some embodiments, the terms “greater than,” “greater than or equal to,” “not less than,” “more than,” “more than or equal to,” “not less than,” “higher than,” “higher than or equal to,” “not lower than,” and “above” can be used interchangeably, as can the terms “less than,” “less than or equal to,” “not greater than,” “less than,” “less than or equal to,” “not more than,” “lower than,” “lower than or equal to,” “not higher than,” and “below”.

[0119] In some embodiments, devices, etc., may be interpreted as physical or virtual, and their names are not limited to those described in the embodiments. Terms such as “device,” “equipment,” “device,” “node,” “unit,” “section,” “system,” “entity,” and “body” are interchangeable.

[0120] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of this disclosure and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of this disclosure should be included within the protection scope of this disclosure.

Claims

1. An intelligent data acquisition terminal, characterized in that, include: A 16-channel signal acquisition interface is used to synchronously acquire N analog signals from a data source device. The N analog signals include electrical signals and / or integrated electronic piezoelectric (IEPE) vibration signals, where 1 ≤ N ≤ 16. The data sampling module includes 16 signal acquisition channels, an analog-to-digital converter chip, and a main control chip. The analog-to-digital converter chip is connected to the 16 signal acquisition interfaces through the 16 signal acquisition channels. The analog-to-digital converter chip is used to convert the N analog signals into N digital signals. The analog-to-digital converter chip is connected to the main control chip. The main control chip is used to drive the analog-to-digital converter chip to acquire signals according to the sampling frequency based on the flexible memory control (FMC) strategy, and to process the N digital signals to obtain private data frames. The sampling frequency is the frequency that the intelligent data acquisition terminal can autonomously adjust within a preset frequency range. The communication module includes a communication chip, a network port circuit, and an internal communication circuit. The communication chip is connected to the main control chip via a serial peripheral interface (SPI) bus. The communication chip is connected to the network port circuit, and the network port circuit is connected to the internal communication circuit. The communication chip is used to automatically encapsulate the private data frame into a standard UDP network packet using the hardware-wide User Datagram Protocol (UDP). The network port circuit is used to receive the standard UDP network packet and send the standard UDP network packet via the internal communication circuit. An artificial intelligence (AI) chip, connected to the communication module, is equipped with a UDP listening port, a central processing unit (CPU), and a neural network processing unit (NPU). The UDP listening port is used to capture standard UDP network packets in real time. Data samples obtained after parsing and preprocessing the standard UDP network packets are used as input to a neural network model. At least some network layers of the neural network model are deployed on the NPU. The NPU performs accelerated inference of the neural network model, or the NPU and the CPU perform collaborative inference of the neural network model to obtain the analysis results corresponding to the data samples. The collaborative inference includes accelerated inference of the neural network model performed by the NPU and local inference of the neural network model performed by the CPU. The analysis results are used to indicate the operational health status of the data source device. The AI ​​chip is also used to autonomously adjust the sampling frequency of the data sampling module.

2. The intelligent data acquisition terminal according to claim 1, characterized in that, The main control chip triggers a pulse width modulation (PWM) signal via a timer to drive the analog-to-digital converter chip to acquire the N analog signals and start multi-channel timing conversion to convert the N analog signals into the N digital signals. After the analog-to-digital converter (ADC) completes one multi-channel timing conversion, the sequencer inside the ADC inputs the N digital signals to the 16-bit parallel bus interface of the ADC, and the status output terminal of the ADC generates a flag transition edge signal. After the port data register of the main control chip captures the flag transition edge signal, it triggers the external interrupt controller in the main control chip to generate an interrupt start signal. The main control chip includes an FMC controller, a ring buffer, and an SPI data transmission register. The main control chip obtains the digital signal output by the analog-to-digital converter chip according to the sampling frequency through the FMC bus address mapping method. When the interrupt start signal is generated, the main control chip directly accesses the FMC controller through the memory pointer without waiting for the pin toggle instruction, and immediately reads the digital signal output by the 16-bit parallel bus interface and stores it in the ring buffer. The main control chip constructs the private data frame from the digital signal in the ring buffer. The private data frame in the circular buffer is sent to the SPI data transmission register.

3. The intelligent data acquisition terminal according to claim 2, characterized in that, During the uplink transmission from the data sampling module to the AI ​​chip via the communication module, the main control chip constructs a private data frame with a 2-byte frame header, a 4-byte timestamp, and a 2-byte checksum from the digital signal in the circular buffer. The private data frame is sent to the SPI data transmission register. The private data frame is input to the communication chip in the form of an SPI serial data stream. After the private data frame forms a standard UDP network packet in the communication chip, it is output as an electrical signal to the network port circuit through the data transmission register of the communication chip. After voltage calibration by the network isolation transformer in the network port circuit, it is sent to the AI ​​chip through the internal communication circuit. After receiving the standard UDP network packet, the AI ​​chip parses it into hexadecimal data according to the private data frame format via the UDP listening port. The hexadecimal data is processed according to the sample input format requirements of the neural network model and then sent to the NPU and / or the CPU.

4. The intelligent data acquisition terminal according to claim 2, characterized in that, During the downlink transmission from the AI ​​chip to the data sampling module via the communication chip, the AI ​​chip sends a control command to the communication chip, which indicates the sampling frequency. The control command is then transmitted back to the communication chip via the network port circuit. The communication chip performs level conversion and data verification on the control command to generate a standard digital signal. The standard digital signal is stored in the transmission register of the communication chip and transmitted back to the main control chip via the SPI bus. The main control chip parses the standard digital signal through its application layer and sends a configuration command to the analog-to-digital converter chip, thereby configuring the sampling frequency for the data sampling module.

5. The intelligent data acquisition terminal according to claim 1, characterized in that, The AI ​​chip also includes: a shared storage area and an internal communication interface; the CPU and the NPU communicate through the shared storage area and the internal communication interface; The CPU is used to perform at least one of the following: Obtain the general model file of the neural network model from a host computer or cloud server. The initial model file includes multiple operators, operator information for each operator, and data transfer relationships between multiple operators. The operator information includes at least one of the following: operator type, input tensor information, output tensor information, weight parameter information, and data type. During the model deployment phase, the general model file is processed, including: converting the general model file into a dedicated model file that can be deployed to the AI ​​chip; generating an operator set based on the neural network model, and matching the operator set with the operator capability description supported by the NPU according to the acceleration execution conditions of the AI ​​chip, dividing the operators into a first operator that meets the acceleration execution conditions and a second operator that does not meet the acceleration execution conditions; quantizing the first operator, and deploying the quantized first operator to the NPU, and deploying the second operator to the CPU; During the model deployment phase, a configuration file is generated, including: generating an inference program file, a hardware runtime configuration file, and model version information corresponding to the dedicated model file, and encapsulating the dedicated model file, the inference program file, the hardware runtime configuration file, and the model version information into a terminal task package; During the model deployment phase, the terminal task package is parsed to obtain the first operator weight parameter and the second operator weight parameter, and the first operator weight parameter and the second operator weight parameter are stored in the shared storage area to complete the deployment of the neural network model. During the model inference phase, the storage address of the first operator weight parameter in the shared storage space is sent to the NPU, and the inference program file and the hardware runtime configuration file are executed; the first intermediate result obtained by the NPU executing the first operator is received, the second intermediate result obtained by the CPU executing the second operator is sent to the NPU, and after the model inference is completed, the analysis result is sent to the host computer or the cloud server.

6. The intelligent data acquisition terminal according to any one of claims 1 to 5, characterized in that, It also includes at least one of the following: The signal conditioning circuit is provided in each of the 16 signal acquisition channels. The analog-to-digital converter chip is connected to the 16 signal acquisition interfaces through the signal conditioning circuit. The signal conditioning circuit is provided with an IEPE power supply circuit and a high-frequency anti-aliasing filter circuit, which are used to perform noise reduction and filtering processing on the acquired N analog signals. When the IEPE power supply circuit is turned on, it powers the IEPE sensor of the data source device to acquire the IEPE vibration signal; when the IEPE power supply circuit is turned off, it acquires the electrical signal, which does not pass through the signal conditioning circuit. The power module includes a power interface and a step-down chip. The step-down chip is used to convert the external input voltage into a multi-level voltage. The multi-level voltage is used to meet the power supply requirements of the IEPE power supply circuit in the signal conditioning circuit, the data sampling module, the communication chip, and the AI ​​chip. The interface module includes at least one of a USB interface, an Ethernet interface, a WiFi antenna interface, a 5G antenna interface, and a hardware programming port. The AI ​​chip is connected to the interface module via a PCIe bus for rapid interconnection of peripheral components.

7. The intelligent data acquisition terminal according to claim 6, characterized in that, The data sampling module is provided with a first hardware programming port, and the AI ​​chip is provided with a second hardware programming port. The first hardware programming port and the second hardware programming port are independent and isolated. The hardware programming port is used to download and update firmware for the data sampling module and the AI ​​chip.

8. An equipment monitoring system, characterized in that, include: Data source devices are used to provide real-time operational data; The intelligent data acquisition terminal as described in any one of claims 1 to 7 is used to acquire N analog signals of the real-time operating data from the data source device, and obtain analysis results by performing accelerated inference or collaborative inference of a neural network model, wherein the analysis results represent the operating health status of the data source device; A host computer or cloud server is used to perform model training to obtain the neural network model; Peripheral devices are connected to the intelligent data acquisition terminal to acquire and visualize the analysis results.

9. A data analysis method, characterized in that, The intelligent data acquisition terminal as described in any one of claims 1 to 7 includes: The AI ​​chip in the intelligent data acquisition terminal determines the autonomously adjustable sampling frequency within a preset frequency range and configures the sampling frequency for the data sampling module. N analog signals from the data source device are simultaneously acquired through a 16-channel signal acquisition interface. The N analog signals include electrical signals and / or integrated electronic piezoelectric (IEPE) vibration signals. The N analog signals are converted into N digital signals by the analog-to-digital converter chip in the data sampling module; The main control chip in the data sampling module, based on the Flexible Memory Control (FMC) strategy, drives the analog-to-digital converter chip to acquire signals according to the sampling frequency and processes the N digital signals to obtain private data frames. The communication chip automatically encapsulates the private data frame into a standard UDP network packet using the all-hardware User Datagram Protocol (UDP). The standard UDP network message is sent to the AI ​​chip via the network port circuit and the internal communication circuit; The AI ​​chip's UDP listening port captures the standard UDP network packets in real time, and the data samples obtained after parsing and preprocessing the standard UDP network packets are used as input to the neural network model. The analysis results corresponding to the data samples are obtained by the NPU performing accelerated inference of the neural network model or by the NPU and the CPU performing collaborative inference of the neural network model. The collaborative inference includes the accelerated inference of the neural network model performed by the NPU and the local inference of the neural network model performed by the CPU. The analysis results are used to indicate the operational health status of the data source device.

10. The method according to claim 9, characterized in that, The AI ​​chip in the intelligent data acquisition terminal determines an autonomously adjustable sampling frequency within a preset frequency range and configures the sampling frequency for the data sampling module, including: During the downlink transmission from the AI ​​chip to the data sampling module via the communication chip, the AI ​​chip sends a control command to the communication chip, the control command indicating the sampling frequency; The control command is sent in reverse to the communication chip via the network port circuit; The communication chip performs level conversion and data verification on the control command to generate a standard digital signal, which is then stored in the transmission register of the communication chip. The standard digital signal is transmitted back to the main control chip via the SPI bus; The main control chip parses the standard digital signal through its application layer and sends a configuration command to the analog-to-digital converter chip, thereby configuring the sampling frequency for the data sampling module.

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