A high-speed camera system for engine test sites and application method

Abstract

This invention discloses a high-speed camera system and its application method for engine testing sites, relating to the field of liquid rocket engine testing and monitoring technology. The high-speed camera system includes an explosion-proof housing, an image acquisition unit, a control and processing unit, and a host computer. The control and processing unit receives a trigger signal, records the trigger time, and initiates image acquisition. It receives each frame of image and records the corresponding transmission time. The trigger time, each frame of image, and its corresponding transmission time are encapsulated into a custom data frame. The host computer acquires the custom data frame, parses and extracts the trigger time and the corresponding transmission time for each frame of image, calculates the actual relative shooting time for each frame of image, and superimposes the pixel data of each frame of image with its corresponding actual relative shooting time to generate a video file. This invention can significantly reduce the hardware cost of the high-speed camera system while achieving microsecond-level timing synchronization accuracy.

Description

Technical Field

[0001] This invention relates to the field of liquid rocket engine test monitoring technology, and in particular to a high-speed camera system and its application method for engine test sites. Background Technology

[0002] Ground testing of liquid rocket engines is a core verification step in the development and delivery of these engines. It aims to verify the engine's structural reliability and performance stability by simulating real-world operating conditions. The test site contains a large amount of high-temperature, high-pressure combustion gases, accompanied by the risk of deflagration due to leaks of flammable and explosive media. Abnormal transients during the test (such as leaks, deflagration, nozzle vibration, and plume distortion) can be accurately captured by high-speed cameras, providing image evidence and data support for fault analysis and localization.

[0003] Traditional high-speed camera equipment faces two major problems when applied to ground testing sites of liquid rocket engines, hindering both monitoring effectiveness and engineering economics. The first problem lies in the high cost of hardware procurement and maintenance, resulting in poor cost-effectiveness for mass deployment. Existing high-speed camera systems require dedicated high-performance controllers to achieve high frame rate real-time encoding and compression, with the hardware cost of a single control unit reaching tens of thousands of yuan, driving up the camera's total lifecycle cost. This high cost makes multi-camera deployment difficult, hindering coverage of the entire engine area (such as nozzles, combustion chambers, and pipeline joints), easily missing transient anomalies, affecting the completeness and accuracy of fault tracing, and delaying engine development progress. The second problem is insufficient synchronization accuracy and unintuitive timing information, making multi-source data linkage analysis impossible. Existing systems mostly use network commands such as TCP to trigger recording, and the trigger signal transmission is susceptible to network fluctuations, leading to random deviations between the actual recording time and the start-up time. Even systems using hardware signal triggering do not consider the time difference between the trigger time and the actual first frame capture time, assuming the actual first frame capture time is synchronized with the trigger time (i.e., time 0), resulting in inherent timing deviations. Furthermore, the existing system does not consider integrating timing information into the video stream, resulting in video files lacking accurate and intuitive timing information. This makes it impossible to directly link and analyze the data with the test bench sensors and valve data, reducing the analytical value of the data and the efficiency and accuracy of fault location.

[0004] In summary, existing high-speed camera systems for liquid rocket engine power test sites have significant shortcomings in terms of hardware cost, cost-effectiveness of mass deployment, timing synchronization accuracy, and intuitiveness of timing information, making it difficult to meet the high-speed camera monitoring requirements for low-cost, high-precision timing synchronization in extreme scenarios. Summary of the Invention

[0005] The technical problem this invention aims to solve is to address the shortcomings of existing technologies, specifically the high hardware cost of existing high-speed camera systems leading to poor cost-effectiveness in mass deployment, insufficient trigger synchronization accuracy, and the lack of precise timing information in video files, which prevents linkage analysis with test bench sensor data. Specifically, this invention provides a high-speed camera system and application method for engine testing sites, as detailed below: 1) In a first aspect, the present invention provides a high-speed camera system for engine testing sites, the specific technical solution of which is as follows: Explosion-proof enclosure; An image acquisition unit, located inside the explosion-proof enclosure, is used to acquire images of the engine test site and transmit each frame of the image back. The control processing unit is located inside the explosion-proof enclosure and is connected to the image acquisition unit and the host computer. The control processing unit is used to receive trigger signals, send start shooting commands to the image acquisition unit, read the system clock and record it as the trigger time. The control processing unit is also used to receive each frame of image returned by the image acquisition unit and record the corresponding return time, and encapsulate the trigger time, each frame of image and its corresponding return time into a custom data frame. The host computer is used to acquire the custom data frame, parse and extract the trigger time and the return time corresponding to each frame image in the custom data frame, calculate the actual shooting relative time corresponding to each frame image, and superimpose the pixel data of each frame image with its corresponding actual shooting relative time to generate a video file.

[0006] The advantages of the high-speed camera system for engine testing sites provided by this invention are as follows: An explosion-proof enclosure is used to protect the internal units from explosion. The image acquisition unit acquires images of the engine test site and transmits each frame back. After receiving the trigger signal, the control processing unit sends a start shooting command to the image acquisition unit and reads the system clock to record the trigger time. At the same time, it receives each frame of image and records the corresponding transmission time. The trigger time, each frame of image and its corresponding transmission time are encapsulated into a custom data frame. After the host computer obtains the custom data frame, it parses and extracts the trigger time and the corresponding transmission time of each frame of image and calculates the actual shooting relative time of each frame of image. Then, the pixel data of each frame of image and its corresponding actual shooting relative time are superimposed to generate a video file. Therefore, this high-speed camera system, through the division of labor and collaboration between the control processing unit and the host computer, migrates high-computing tasks to the host computer, thereby reducing the hardware cost of the control processing unit. This facilitates batch deployment of multiple cameras to cover key areas of the entire engine domain. At the same time, by recording the trigger time and the time of each frame's return with dual timestamps and calculating the relative time, it eliminates the inherent timing deviation between the trigger time and the first frame's shooting time, and directly superimposes the precise relative time onto the video image, giving the video file intuitive and accurate timing information. This allows for direct linkage analysis with test bench sensor data, thereby improving the efficiency and accuracy of fault location.

[0007] Based on the above solution, the present invention can be further improved as follows.

[0008] Furthermore, the control processing unit receives the trigger signal through the GPIO interface, detects the trigger signal through the interrupt mechanism of the GPIO interface, and simultaneously performs two operations: sending a start shooting command to the image acquisition unit and reading the system clock and recording it as the trigger time.

[0009] Furthermore, it also includes a start signal conversion circuit; The start signal conversion circuit is connected to the start electrical signal output terminal of the test bench and is used to convert the start electrical signal emitted by the test bench into a trigger signal that matches the control processing unit.

[0010] Furthermore, it also includes storage units; The storage unit is located inside the explosion-proof enclosure and is connected to the control processing unit. It is used to receive and store custom data frames output by the control processing unit.

[0011] 2) In a second aspect, the present invention also provides an application method for a high-speed camera system used in engine testing sites, the specific technical solution of which is as follows: S1, the host computer sends an image acquisition parameter configuration instruction to the control processing unit; after receiving the configuration instruction, the control processing unit configures the image acquisition parameters according to the configuration instruction. S2, after receiving the trigger signal, the control processing unit sends a start shooting command to the image acquisition unit, reads the system clock and records it as the trigger time; the image acquisition unit acquires images of the engine test site according to the start shooting command and the image acquisition parameters, and transmits each frame of image back to the control processing unit; the control processing unit receives each frame of image and records the corresponding transmission time. S3, the control processing unit encapsulates the trigger time, each frame of image and its corresponding return time into a custom data frame; S4, the host computer acquires the custom data frame, parses and extracts the trigger time and the return time corresponding to each frame image in the custom data frame, calculates the actual shooting relative time corresponding to each frame image, and superimposes the pixel data of each frame image with its corresponding actual shooting relative time to generate a video file.

[0012] Based on the above solution, the present invention can be further improved as follows.

[0013] Furthermore, the control processing unit receives the trigger signal through the GPIO interface, detects the trigger signal through the interrupt mechanism of the GPIO interface, and simultaneously performs two operations: sending a start shooting command to the image acquisition unit and reading the system clock and recording it as the trigger time.

[0014] Furthermore, before receiving the trigger signal, the control processing unit also includes: The start signal conversion circuit receives the start electrical signal emitted by the test bench and converts the start electrical signal into a trigger signal that matches the control processing unit.

[0015] Furthermore, S1 also includes: The control processing unit creates multiple memory queues and storage threads corresponding to the number of memory queues; The memory queue is used to cache the custom data frame, and the storage thread is used to read the custom data frame corresponding to the memory queue in parallel and write it to the storage unit.

[0016] 3) In a third aspect, the present invention also provides a computer device, the computer device including a processor coupled to a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor to enable the computer device to implement any of the above methods.

[0017] 4) In a fourth aspect, the present invention also provides a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor to enable a computer to implement any of the above methods.

[0018] It should be noted that the beneficial effects of the technical solutions of the second to fourth aspects of the present invention and their corresponding possible implementations can be found in the above description of the technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0019] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings: Figure 1 This is a schematic diagram of the hardware structure of a low-cost explosion-proof high-speed camera according to an embodiment of the present invention; Figure 2 This is a schematic diagram of the interface relationships of a high-speed camera system according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the start signal conversion circuit structure according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the overall data flow processing of the application method of the high-speed camera system according to an embodiment of the present invention; Figure 5 This is a schematic diagram of a custom data frame structure according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention; Figure 1 In the diagram, 1 is an industrial image sensor, 2 is a control unit, 3 is a storage unit, and 4 is an explosion-proof housing. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0021] The following is a unified explanation of the English abbreviations used throughout the entire implementation method: The Universal Serial Bus (USB) 3.2 Gen1 interface is a wired high-speed data transmission interface standard. The actual transmission bandwidth needs to be higher than the size of the video stream data to ensure that image data can be transmitted in real time and without obstruction.

[0022] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard used to connect high-speed peripherals.

[0023] Transmission Control Protocol (TCP) is a connection-oriented, reliable, byte-stream-based transport layer communication protocol.

[0024] Secure Shell (SSH) is an encrypted network protocol that provides secure remote login and command execution over a network.

[0025] File Transfer Protocol (FTP) is a standard network protocol used to transfer files between clients and servers over a network.

[0026] OpenCV is an open-source computer vision and machine learning software library that provides a rich set of image and video processing functions.

[0027] Direct Memory Access (DMA) is a technology that allows hardware devices to directly read and write system memory without the intervention of the central processing unit (CPU).

[0028] On-screen display (OSD) is a display technology that overlays text or graphic information onto video images.

[0029] The high-speed camera system for engine test sites proposed in this invention consists of an explosion-proof high-speed camera, a host computer, and a start-up signal conversion circuit. Figure 1 This is a schematic diagram of the hardware structure of a low-cost explosion-proof high-speed camera. The hardware structure of the explosion-proof high-speed camera includes: an image acquisition unit (corresponding to...) Figure 1 "Industrial image sensor 1" and control processing unit (corresponding to Figure 1 "Control Unit 2" and storage unit (corresponding to) Figure 1 "Storage Unit 3" in the middle), explosion-proof casing (corresponding to Figure 1 In addition to the "explosion-proof enclosure 4" mentioned in the text, the hardware structure of the explosion-proof high-speed camera also includes the following integrated into the control processing unit: sensor drive interface, storage interface, power interface, network cable interface, and trigger interface sealed connector. Each interface is led out from the wall of the explosion-proof enclosure through the sealed connector. The host computer establishes an SSH connection with the image acquisition unit via a gigabit local area network to realize device management, data management, and data processing functions. The start signal conversion circuit consists of a solid-state relay and a linearly adjustable power supply, used to convert the standard start electrical signal output from the test bench into a trigger signal matched with the control processing unit.

[0030] The engine test site involved in this invention refers to a ground test site for liquid rocket engines. This site contains a large amount of high-temperature, high-pressure combustion gases, and carries the risk of deflagration due to leakage of flammable and explosive media. The images acquired by the system are of key areas (such as nozzles, combustion chambers, and pipe joints) during engine testing, used to capture abnormal transients during the test, providing image evidence and data support for fault analysis and location. The system and application method proposed in this invention can also be extended to high-speed camera monitoring scenarios with extreme environments such as solid rocket engine testing and aero-engine ground testing, which involve high temperature, high pressure, strong vibration, and high risk of deflagration.

[0031] like Figure 1 as well as Figure 2 As shown, an embodiment of the present invention provides a high-speed camera system for engine testing sites, including an explosion-proof housing and an image acquisition unit (corresponding to...). Figure 2 "Industrial image sensor" and control processing unit (corresponding to) Figure 2 The interface relationship between the "control unit" and the host computer is as follows: the control processing unit communicates through the storage interface and the sensor drive interface (corresponding to...). Figure 2 The "drive interface" in the text drives the image acquisition unit and acquires image data; the control processing unit uses a wired high-speed storage interface (corresponding to...) Figure 2 The storage unit is connected via "local transfer" in the code; the control processing unit connects via the GPIO interface (corresponding to...). Figure 2 The “electrical signal” in the circuit is connected to the start signal conversion circuit (corresponding to the start signal conversion circuit). Figure 2 The "start signal generator" in the middle receives the start electrical signal; the control processing unit receives the start electrical signal through the network interface (corresponding to...). Figure 2 The "network communication unit" in the middle is connected to the host computer.

[0032] The explosion-proof enclosure is constructed from standardized 304 stainless steel profiles, forming a flameproof structure that meets industrial explosion-proof standards. Industrial explosion-proof standards refer to the safety design and manufacturing specifications for electrical equipment in potentially explosive environments. The explosion-proof enclosure has a protection rating of at least IP67 and a vibration acceleration resistance of at least 10g, effectively resisting the harsh environments of the testing site, including high temperatures, high pressures, flammable media, and strong vibrations, ensuring the safe and stable operation of internal electronic components and storage units. IP67 is the enclosure protection rating standard set by the International Electrotechnical Commission (IEC), where "6" indicates complete dust protection and "7" indicates short-term immersion in water up to 1 meter without impact. As an alternative, the explosion-proof enclosure material can be replaced with a material with better corrosion resistance, such as 316L stainless steel; in another alternative, the protection rating can be upgraded to IP68 to adapt to even more demanding testing environments.

[0033] The image acquisition unit, housed within an explosion-proof enclosure, is used to acquire images from the engine test site and transmit each frame back. The unit employs an industrial-grade high-speed image sensor, with core performance requirements of 480P (640×480 pixels resolution) @ 500FPS (frames per second) or higher, and a wide operating temperature range of -20℃ to 85℃ to adapt to the extreme high and low temperature environments of the test site. Image data transmission utilizes a USB 3.2 Gen1 wired high-speed storage interface, ensuring the actual bandwidth exceeds the video stream data size for high-speed and stable image data transmission. The image acquisition unit captures images of the external test scene through a sealed window or lens interface within the explosion-proof enclosure. Alternatively, other devices meeting 480P (640×480 pixels resolution) @ 500FPS or higher recording specifications and a wide operating temperature range of -20℃ to 85℃ can be used as the image acquisition unit, such as any specific model of a Basler or Point Grey industrial camera that meets the required recording specifications and wide operating temperature range.

[0034] The control processing unit is housed inside an explosion-proof enclosure and connects to both the image acquisition unit and the host computer. The control processing unit receives trigger signals, sends start-shooting commands to the image acquisition unit, reads the system clock, and records it as the trigger time. It also receives each frame of image data transmitted back from the image acquisition unit and records the corresponding transmission time, encapsulating the trigger time, each frame of image data, and its corresponding transmission time into a custom data frame. The control processing unit is based on a general-purpose embedded single-board computer and runs a real-time operating system. This general-purpose embedded single-board computer is a low-cost computing board with multi-threaded processing capabilities and high-speed peripheral interfaces (PCIe interface, USB 3.2 Gen1 interface, etc.), such as a Raspberry Pi single-board computer. This single-board computer runs a real-time operating system to perform functions such as camera parameter configuration, shooting action control, image data caching and forwarding, timing recording, network communication, and interaction with the host computer. The core responsibilities of the control processing unit include four aspects: First, camera parameter configuration and shooting action control, i.e., configuring parameters such as frame rate, resolution, and exposure time of the image acquisition unit through software instructions and controlling the start and stop of shooting; Second, caching and forwarding of raw image data, i.e., receiving each frame of image returned by the image acquisition unit, temporarily storing it in memory, and preparing to forward it to the storage unit; Third, high-precision timing recording, i.e., listening to trigger signals in real time through the GPIO interface and collecting microsecond-level timestamps of the trigger moment and the time of each frame's return; Fourth, network communication and interaction with the host computer, i.e., exchanging data and commands with the host computer through the local area network. The core innovation of the control processing unit lies in migrating the high-computing-power video encoding and compression task to the host computer, while the control processing unit only retains the raw data transmission and basic control functions, thereby significantly reducing the hardware cost and computing power requirements of the control processing unit.

[0035] In a preferred embodiment, the control processing unit receives a trigger signal via a GPIO interface. After detecting the trigger signal through the interrupt mechanism of the GPIO interface, it simultaneously performs two operations: sending a start-up shooting command to the image acquisition unit and reading the system clock and recording it as the trigger time. Specifically, the GPIO interface of the control processing unit is configured in rising-edge trigger mode and hardware anti-shake filtering is enabled to filter out noise interference on the signal lines. When the trigger signal arrives at the GPIO interface, the interrupt mechanism of the GPIO interface is activated, and the control processing unit immediately performs two operations upon responding to the interrupt. The first operation is to send a start-up shooting command to the image acquisition unit. The start-up shooting command is transmitted to the image acquisition unit through the sensor driver interface. After receiving the start-up shooting command, the image acquisition unit begins to acquire images according to preset parameters within a response delay of no more than 50μs. The second operation is to read the system's local real-time clock and obtain the timestamp of the trigger time t_trigger, with an accuracy of microseconds. In an alternative embodiment, the interrupt priority of the GPIO interface is set to the highest level to ensure that the response of the trigger signal is not delayed due to other system tasks. In another alternative embodiment, the GPIO interface can be configured in falling-edge trigger mode to accommodate the output signal polarity of different test benches. In another alternative, the parameters of the hardware anti-shake filter can be adjusted according to the electromagnetic environment on site to adapt to different levels of interference.

[0036] In a preferred embodiment, the system further includes a start signal conversion circuit; the start signal conversion circuit is connected to the start electrical signal output terminal of the test bench, and is used to convert the start electrical signal emitted by the test bench into a trigger signal that matches the control processing unit. Figure 3 As shown, the start signal conversion circuit includes: a test start signal, a solid-state relay, a linearly adjustable power supply, and a control processing unit GPIO interface (corresponding to...). Figure 3The "control unit GPIO port" is mentioned in the text. Specifically, the start signal conversion circuit consists of a solid-state relay and a linearly adjustable power supply. At the start of the test, the test bench outputs a standard 5V start signal, which is connected to the input of the solid-state relay. The output of the solid-state relay is connected in series with the linearly adjustable power supply, which provides a 3.3V level. When the 5V start signal from the test bench is input to the solid-state relay, the relay conducts, and its output, connected in series with the 3.3V power supply, outputs a 3.3V high-level signal. This 3.3V signal serves as a trigger signal connected to the GPIO interface of the control processing unit. When the test ends, the test bench outputs a 0V low-level signal, the solid-state relay turns off, and the GPIO interface level drops to a low level (0V). Through this level conversion and isolation transmission, voltage matching and electrical isolation between the 5V start signal from the test bench and the 3.3V level of the GPIO interface of the control processing unit are achieved. In an alternative solution, the output voltage of the linearly adjustable power supply can be adjusted within the range of 3.0V to 3.6V to adapt to the GPIO interface level specifications of different single-board computer models. In another alternative, solid-state relays can be replaced by optocoupler-isolated relays to achieve a higher level of electrical isolation.

[0037] In a preferred embodiment, please continue to refer to Figure 1 The system also includes a storage unit 3; this storage unit is located inside the explosion-proof enclosure and connected to the control processing unit, used to receive and store custom data frames output by the control processing unit. The storage unit uses a high-speed solid-state drive (SSD), which is located inside the explosion-proof enclosure and connected to the control processing unit via a storage interface. The SSD's interface has a continuous write speed of no less than 500MB / s, matching the bandwidth requirements of video stream data transmission, enabling real-time, frame-loss-free writing and storage of high-speed camera data. The SSD also features vibration resistance and a small size, making it suitable for the strong vibration environment of the test site. The custom data frames output by the control processing unit are transmitted to the SSD via the high-speed storage interface.

[0038] The host computer acquires custom data frames, parses and extracts the trigger time and the corresponding transmission time for each frame, and calculates the actual relative shooting time for each frame. It then overlays the pixel data of each frame with its corresponding actual relative shooting time to generate a video file. The host computer is a standard computer connected to the control processing unit via a gigabit LAN using an SSH connection. After acquiring the binary stream data of the custom data frames from the storage unit, the host computer executes the data processing flow. It parses the binary stream, extracts the trigger time (t_trigger) and transmission time (t_frame) from the header of each custom data frame, and calculates the actual relative shooting time (t_actual) for that frame. The formula is the difference between the trigger time and the transmission time: t_actual = t_frame - t_trigger. The host computer transcodes the pixel data of each custom data frame into the original image format and uses the OpenCV library to overlay the relative shooting time information. During overlay, 16-point red font with a black outline (2-pixel spacing between characters) is used to avoid overlap between the overlaid timing information and experimental image content such as flames. The superimposed image is compressed into a standard MP4 video file using H.264 encoding format and stored on the host computer's local hard drive for analysis and fault tracing in conjunction with sensor data from the test bench.

[0039] This high-speed camera system, through the division of labor and collaboration between the control processing unit and the host computer, migrates the high-computing-power video encoding and compression task to the host computer. This eliminates the need for a dedicated high-performance encoding processor in the control processing unit, significantly reducing its hardware cost and solving the problem of poor cost-effectiveness in mass deployment. It also makes it possible to cover the entire critical area of ​​the engine with multiple cameras. Furthermore, this high-speed camera system eliminates the inherent timing deviation between the trigger moment and the first frame capture moment by recording dual timestamps for both the trigger moment and the frame return moment, achieving microsecond-level timing synchronization. In addition, through the equivalent replacement design of hardware modules and the decoupled architecture of software logic, this high-speed camera system can be adapted to different sensor models and host computer systems; it supports unified management of camera groups and can be quickly expanded to different test scenarios, reducing customized development costs.

[0040] like Figure 4 As shown, the application method of the high-speed camera system for engine test sites proposed in this invention has the following overall data flow processing flowchart: Each frame of image is acquired by the image acquisition unit (corresponding to...) Figure 4 The "original bitmap" in the image is controlled by the processing unit (corresponding to...). Figure 4 The "control unit" adds and stores timestamps in real time, which are then parsed and calculated by the host computer for encoding and compression, outputting a complete video file. The method includes the following steps: S1, the host computer sends an image acquisition parameter configuration command to the control processing unit; after receiving the configuration command, the control processing unit configures the image acquisition parameters according to the configuration command. The specific implementation method is as follows.

[0041] During system startup, the control processing unit loads the real-time operating system after power-on. The host computer establishes a secure network connection with the control processing units of each high-speed camera via the SSH protocol. The host computer sends image acquisition parameter configuration commands to the control processing units, which carry the frame rate, resolution, and exposure time parameters of the image sensor. After receiving the configuration commands, the control processing units parse the image acquisition parameter values ​​and write these parameters into the registers of the image acquisition units through the sensor driver interface, enabling the image acquisition units to operate according to the specified parameters. In a preferred embodiment, the configured image acquisition parameters are: frame rate 500 FPS, resolution 640×480 pixels (480P), and exposure time 500 μs. After configuration, the control processing units enter a standby state, waiting for a trigger signal. In an alternative embodiment, the host computer can simultaneously send the same configuration commands to multiple control processing units via SSH connection to achieve unified configuration of camera group parameters.

[0042] In a preferred embodiment, S1 further includes a control processing unit creating multiple memory queues and storage threads corresponding to the number of memory queues; the memory queues are used to cache custom data frames, and the storage threads are used to read custom data frames from the corresponding memory queues in parallel and write them to the storage units. Specifically, during the system startup phase, the control processing unit also performs storage module initialization operations after receiving configuration instructions. The control processing unit creates multiple memory queues and a number of storage threads equal to the number of memory queues based on its CPU core count. The memory queues are circular buffers in memory, each with a capacity of 128 frames, used to temporarily store custom data frames encapsulated in S3, serving as a data buffer to prevent data loss due to fluctuations in the write speed of the storage units. The storage threads are background threads running in the control processing unit, each uniquely corresponding to a memory queue, responsible for reading custom data frames from that memory queue and writing them to the storage units. When the control processing unit creates memory queues and storage threads, it matches the number of CPU cores of the control processing unit, thereby performing CPU core binding. In a preferred embodiment, the control processing unit's CPU has 4 cores, and the control processing unit creates 3 memory queues and 3 storage threads. The acquisition thread is bound to CPU0 core and is responsible for receiving image data returned by the image acquisition unit and recording the return time. The main thread is responsible for evenly distributing the custom data frames encapsulated in S3 to three memory queues through a polling method. Three storage threads are bound to CPU1 core and CPU3 core respectively, and read the custom data frames in their respective memory queues in parallel, writing the custom data frames to the SSD. Each storage thread also initializes the DMA channel during initialization, which is used to receive image data returned by the image acquisition unit later to reduce CPU usage. In an alternative solution, the number of memory queues can be adjusted within the range of ≥2, and the thread binding strategy can also be optimized according to the actual number of CPU cores. As long as frame-loss-free storage is achieved by distributing raw data through the main thread and multi-threaded cache storage, it is considered an equivalent implementation.

[0043] In the application of the high-speed camera system of this application, the camera configuration parameters are centrally managed by the host computer, realizing the unified configuration and status monitoring of the camera group and improving the system operation and maintenance efficiency. Through the multi-threaded parallel storage design, the parallel work of multiple memory queues and storage threads is utilized to effectively balance the difference between the high-speed image data stream and the writing speed of the storage medium, ensuring no frame loss under continuous shooting conditions and guaranteeing data integrity.

[0044] S2, after receiving the trigger signal, the control processing unit sends a start-up shooting command to the image acquisition unit, reads the system clock and records it as the trigger time; the image acquisition unit acquires images of the engine test site according to the image acquisition parameters based on the start-up shooting command, and transmits each frame of image back to the control processing unit; the control processing unit receives each frame of image and records the corresponding transmission time. The specific implementation method is as follows.

[0045] At the start of the test, the test bench emits a start-up electrical signal, which is converted into a trigger signal receivable by the GPIO interface of the control processing unit via a start-up signal conversion circuit. After receiving the trigger signal through the GPIO interface, the control processing unit performs two operations. First, it sends a start-up shooting command to the image acquisition unit. This command is transmitted to the image acquisition unit via the sensor driver interface, initiating the image acquisition process. Second, it reads the system's local real-time clock, obtains the current microsecond-level timestamp as the trigger time t_trigger, and stores it in the memory of the control processing unit. Upon receiving the start-up shooting command, the image acquisition unit begins continuously acquiring images of the engine test site according to the image acquisition parameters configured in S1 (frame rate 500FPS, resolution 640×480 pixels, exposure time 500μs). The image acquisition unit then transmits the raw pixel data of each acquired frame back to the control processing unit via a USB 3.2 Gen1 interface. The control processing unit receives each frame of image data through the initialized DMA channel. When the reception of each frame of image is completed, the control processing unit reads the local real-time clock of the system, obtains the return time t_frame of the frame of image, and stores it in memory.

[0046] In a preferred embodiment, the control processing unit receives a trigger signal via the GPIO interface. After detecting the trigger signal through the interrupt mechanism of the GPIO interface, it simultaneously performs two operations: sending a start-up shooting command to the image acquisition unit and reading the system clock and recording it as the trigger time. Specifically, the GPIO interface is configured in rising-edge trigger mode to enable hardware image stabilization filtering to eliminate glitches on the signal lines. When the trigger signal arrives at the GPIO interface and generates a rising edge, the interrupt mechanism of the GPIO interface is activated, and the CPU of the control processing unit immediately responds to the interrupt request. In the interrupt service routine, the control processing unit performs two operations: the first operation is to send a start-up shooting command to the image acquisition unit, transmitting the start command to the control register of the image acquisition unit through the sensor driver interface; the response delay of this operation does not exceed 50μs. The second operation is to read the system real-time clock and obtain the current time as the trigger time t_trigger, with a timestamp accuracy in the microsecond range.

[0047] In a preferred embodiment, before the control processing unit receives the trigger signal, a start signal conversion circuit is included to receive the start electrical signal emitted by the test bench and convert it into a trigger signal that matches the control processing unit. Specifically, the start signal conversion circuit consists of a solid-state relay and a linearly adjustable power supply. The connection is as follows: the input terminal of the solid-state relay is connected to the start electrical signal output terminal of the test bench, and the output terminal of the solid-state relay is connected in series with the linearly adjustable power supply and then connected to the GPIO interface of the control processing unit. At the start of the test, the test bench emits a 5V standard start electrical signal, which is input to the input terminal of the solid-state relay, driving the internal switch of the solid-state relay to close. After the solid-state relay is turned on, its output terminal is connected in series with the 3.3V level output of the linearly adjustable power supply, generating a 3.3V high-level trigger signal at the output terminal. This trigger signal is transmitted to the GPIO interface of the control processing unit through a wire. Through the above level conversion and isolation transmission, voltage matching and electrical isolation between the 5V start electrical signal of the test bench and the 3.3V level of the GPIO interface of the control processing unit are achieved, ensuring that the control processing unit can correctly identify the trigger signal without being damaged by high voltage. By utilizing the electrical isolation characteristics of solid-state relays, the high-voltage side of the test bench is isolated from the low-voltage side of the control processing unit, thus achieving both level matching and protecting the safety of the control processing unit.

[0048] In this application, GPIO hardware triggering replaces traditional TCP network command triggering, eliminating the impact of network transmission delay and fluctuation on trigger synchronization accuracy; simultaneous execution through GPIO interrupt mechanism ensures strict synchronization between triggering action and timing record, achieving millisecond-level timing synchronization accuracy.

[0049] S3, the control processing unit encapsulates the trigger time, each frame of image and its corresponding return time into a custom data frame. The specific implementation method is as follows.

[0050] like Figure 5As shown, the custom data frame structure is as follows: the frame header is 16 bytes of timestamp data (the first 8 bytes are the trigger time t_trigger, and the last 8 bytes are the corresponding return time t_frame), followed by each frame image, i.e., pixel data. For each frame image returned by the image acquisition unit, the control processing unit performs a packaging operation. Specifically, the control processing unit reads the trigger time t_trigger corresponding to the frame image (i.e., the trigger time recorded in S2; for all frame images acquired in the same experiment, the trigger time is the same timestamp value) and the return time t_frame corresponding to the frame image from memory. The control processing unit packages the data according to the custom binary frame structure: 16 bytes of header information are added before the original pixel data of each frame image; the first 8 bytes are written with the timestamp value of the trigger time t_trigger, and the last 8 bytes are written with the timestamp value of the return time t_frame of the frame image, forming a complete custom data frame. The format of the custom data frame is: [trigger time t_trigger 8 bytes][return time t_frame 8 bytes][pixel data]. For each image frame, the trigger time (t_trigger) in its custom data frame is the same timestamp value, while the return time (t_frame) is a timestamp value unique to that image frame. After encapsulation, the custom data frame is temporarily stored in the memory of the control processing unit, awaiting writing to the storage unit. In an implementation scheme including a multi-threaded storage architecture, the encapsulated custom data frames are evenly distributed to various memory queues by the main thread through a polling method. Each storage thread reads the custom data frames in its corresponding memory queue in parallel and writes them to the SSD, achieving high-speed, frame-loss-free data storage.

[0051] In this embodiment, by simultaneously encapsulating the trigger time and the return time of each frame into the image data header, the binding storage of timing information and image data is ensured, providing a complete data foundation for the host computer to analyze and calculate the relative time.

[0052] S4, the host computer acquires a custom data frame, parses and extracts the trigger time and the corresponding transmission time of each frame, and calculates the actual shooting relative time for each frame. The pixel data of each frame is then superimposed with its corresponding actual shooting relative time to generate a video file. The specific implementation is as follows.

[0053] After the experiment, the host computer connected to the control processing unit via FTP protocol and downloaded the binary stream data of all custom data frames stored in the storage unit. After reading the binary stream, the host computer parsed each frame of data sequentially according to the format of the custom data frames. For each custom data frame, the host computer extracted the trigger time t_trigger from the first 8 bytes of the frame header, the return time t_frame from the last 8 bytes of the frame header, and the pixel data from the subsequent bytes of the frame header. The host computer calculated the actual relative shooting time t_actual of the frame image based on the extracted t_trigger and t_frame. The calculation method was to subtract the return time from the trigger time, i.e., t_actual = t_frame - t_trigger. The calculation result reflects the actual shooting time of the frame image relative to the start time of the experiment. The host computer transcodes the pixel data of each frame of the image into the original image format. Using the OpenCV library, OSD overlay of relative time information is implemented. `t_actual` is retained to three decimal places, with the unit being milliseconds. The timing information is overlaid onto the image using 16-point red font with a black outline (2-pixel spacing between characters), avoiding overlap between the timing information and experimental image content such as flames, which could lead to indistinguishability. The overlaid image sequence is compressed into a standard MP4 video file using H.264 encoding and stored on the host computer's local hard drive. Each frame of the final video file contains precise relative time values ​​overlaid. This video file can be directly used for time-axis alignment and linkage analysis with test bench sensor data and valve data.

[0054] In one alternative, the host computer retrieves the binary stream data of the custom data frame from the storage unit via the FTP protocol. In another alternative, the host computer can retrieve the data via other network file transfer methods such as SSH File Transfer Protocol (SFTP) or Network File System (NFS).

[0055] By calculating and superimposing the actual shooting time onto the video frame using a host computer, the generated video file has accurate and intuitive timing information, eliminating the inherent timing deviation between the trigger time and the first frame shooting time. It can achieve accurate time alignment with sensor data without manual back-calculation, thus improving the efficiency of fault location.

[0056] At the end of the test run, the test bench sends a stop signal, and the output level of the start signal conversion circuit drops to a low level (0V). Upon detecting a falling edge on the GPIO interface, the control processing unit sends a stop-capture command to the image acquisition unit. After the image acquisition unit stops image acquisition, each storage thread continues to write the remaining custom data frames in the memory queue to the storage unit, clears the memory queue, closes the DMA channel, and the control program returns to standby mode, waiting for the next trigger.

[0057] The steps and collaborative relationships for implementing the core functions of the control processing logic of this invention are not limited to specific programming languages ​​or code implementations. Regardless of the programming language used, such as C++ or Python, as long as the core process of acquiring the microsecond-level timestamps of the trigger time t_trigger and the frame return time t_frame, encapsulating them into the video stream, having the host computer parse and calculate the relative time, and superimposing them onto the video frame is implemented, it falls within the protection scope of this invention. Furthermore, the modular and decoupled software design supports multi-language development and cross-platform adaptation, allowing for rapid expansion to different test drive scenarios and reducing customized development costs.

[0058] In the above embodiments, although the steps are numbered S1, S2, etc., they are only specific embodiments given by the present invention. Those skilled in the art can adjust the execution order of S1, S2, etc. according to the actual situation, and these situations are also within the protection scope of the present invention. It can be understood that in some embodiments, some or all of the above embodiments may be included.

[0059] Furthermore, the acquisition process of the data involved in this application follows the principles of legality, legitimacy, and necessity. Based on obtaining the explicit authorization and consent of the user, only the minimum necessary information required to achieve the purpose is collected, and data security protection obligations are fulfilled in accordance with the law.

[0060] It should be noted that the beneficial effects of the application method of the high-speed camera system for engine test sites provided in the above embodiments are the same as the beneficial effects of the high-speed camera system for engine test sites described above, and will not be repeated here. Furthermore, the system provided in the above embodiments is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the system can be divided into different functional modules according to the actual situation to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, and will not be repeated here.

[0061] like Figure 6 As shown, an embodiment of the present invention provides a computer device 300, which includes a processor 320 coupled to a memory 310. The memory 310 stores at least one computer program 330, which is loaded and executed by the processor 320 to enable the computer device 300 to implement any of the above-described methods. Specifically: The computer device 300 can vary considerably due to differences in configuration or performance. It may include one or more processors 320 (Central Processing Units, CPUs) and one or more memories 310. The one or more memories 310 store at least one computer program 330, which is loaded and executed by the one or more processors 320 to enable the computer device 300 to implement the high-speed camera system for engine test sites provided in the above embodiments. Of course, the computer device 300 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The computer device 300 may also include other components for implementing device functions, which will not be elaborated here.

[0062] An embodiment of the present invention provides a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor to enable a computer to implement any of the above-described methods.

[0063] Alternatively, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0064] In an exemplary embodiment, a computer program product or computer program is also provided, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform any of the aforementioned high-speed camera systems for engine test sites.

[0065] It should be noted that the terms "first," "second," etc., used in the specification of this application are used to distinguish similar objects and do not imply a specific order or sequence. Where appropriate, the order of use for similar objects can be interchanged so that the embodiments of this application described herein can be implemented in an order other than that shown in the figures or description.

[0066] Those skilled in the art will recognize that this invention can be implemented as a system, method, or computer program product. Therefore, this disclosure can be specifically implemented in the following forms: it can be entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." Furthermore, in some embodiments, the invention can also be implemented as a computer program product contained in one or more computer-readable media, which includes computer-readable program code.

[0067] Any combination of one or more computer-readable media may be used. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0068] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A high-speed camera system for engine testing sites, characterized in that, include: Explosion-proof enclosure; An image acquisition unit, located inside the explosion-proof enclosure, is used to acquire images of the engine test site and transmit each frame of the image back. The control processing unit is located inside the explosion-proof enclosure and is connected to the image acquisition unit and the host computer. The control processing unit is used to receive trigger signals, send start shooting commands to the image acquisition unit, read the system clock and record it as the trigger time. The control processing unit is also used to receive each frame of image returned by the image acquisition unit and record the corresponding return time, and encapsulate the trigger time, each frame of image and its corresponding return time into a custom data frame. The host computer is used to acquire the custom data frame, parse and extract the trigger time and the return time corresponding to each frame image in the custom data frame, and calculate the actual shooting relative time corresponding to each frame image. The pixel data of each frame is superimposed with its corresponding actual shooting time to generate a video file.

2. The high-speed camera system for engine testing sites according to claim 1, characterized in that, The control processing unit receives the trigger signal through the GPIO interface. After detecting the trigger signal through the interrupt mechanism of the GPIO interface, it simultaneously performs two operations: sending a start shooting command to the image acquisition unit and reading the system clock and recording it as the trigger time.

3. The high-speed camera system for engine testing sites according to claim 1, characterized in that, It also includes a start signal conversion circuit; The start signal conversion circuit is connected to the start electrical signal output terminal of the test bench and is used to convert the start electrical signal emitted by the test bench into a trigger signal that matches the control processing unit.

4. A high-speed camera system for engine testing sites according to claim 1, characterized in that, It also includes storage units; The storage unit is located inside the explosion-proof enclosure and is connected to the control processing unit. It is used to receive and store custom data frames output by the control processing unit.

5. An application method for a high-speed camera system used in engine testing sites, characterized in that, include: S1, the host computer sends an image acquisition parameter configuration instruction to the control processing unit; after receiving the configuration instruction, the control processing unit configures the image acquisition parameters according to the configuration instruction. S2, after receiving the trigger signal, the control processing unit sends a start shooting command to the image acquisition unit, reads the system clock and records it as the trigger time; the image acquisition unit acquires images of the engine test site according to the start shooting command and the image acquisition parameters, and transmits each frame of image back to the control processing unit; the control processing unit receives each frame of image and records the corresponding transmission time. S3, the control processing unit encapsulates the trigger time, each frame of image and its corresponding return time into a custom data frame; S4, the host computer acquires the custom data frame, parses and extracts the trigger time and the return time corresponding to each frame image in the custom data frame, and calculates the actual shooting relative time corresponding to each frame image. The pixel data of each frame is superimposed with its corresponding actual shooting time to generate a video file.

6. The application method of a high-speed camera system for engine testing sites according to claim 5, characterized in that, The control processing unit receives the trigger signal through the GPIO interface. After detecting the trigger signal through the interrupt mechanism of the GPIO interface, it simultaneously performs two operations: sending a start shooting command to the image acquisition unit and reading the system clock and recording it as the trigger time.

7. The application method of a high-speed camera system for engine testing sites according to claim 5, characterized in that, Before the control processing unit receives the trigger signal, it also includes: The start signal conversion circuit receives the start electrical signal emitted by the test bench and converts the start electrical signal into a trigger signal that matches the control processing unit.

8. The application method of a high-speed camera system for engine testing sites according to claim 5, characterized in that, S1 further includes: The control processing unit creates multiple memory queues and storage threads corresponding to the number of memory queues; The memory queue is used to cache the custom data frame, and the storage thread is used to read the custom data frame corresponding to the memory queue in parallel and write it to the storage unit.

9. A computer device, characterized in that, The computer device includes a processor coupled to a memory storing at least one computer program, which is loaded and executed by the processor to enable the computer device to implement the application method of a high-speed camera system for engine test sites as described in any one of claims 5 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores at least one computer program, which is loaded and executed by a processor to enable the computer to implement the application method of a high-speed camera system for engine test sites as described in any one of claims 5 to 8.

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