LED drive intelligent configuration platform supporting NFC parameter writing

Abstract

This invention discloses an intelligent configuration platform for LED drivers supporting NFC parameter writing, applied in the fields of digital power electronic control and embedded arithmetic optimization. It includes: an NFC parameter configuration module that parses messages to extract scaling identifiers and configuration baseline duty cycles, and locks the configuration scaling factor; a scaling migration module that maps the target current and sampled feedback current to a unified scaling domain; a hierarchical prediction module that calculates the optimal duty cycle based on an attenuation-type target error compensation algorithm and an explicit cost function including a configuration bias penalty term; a hardware scaling module that uses a multiplication-free shift graph and a right-shift anti-overflow mechanism of a periodic state accumulator to ensure arithmetic safety; and an encoding module that converts the duty cycle into control commands and writes them to the driver chip. This invention eliminates time-varying drift, overcompensated oscillations, and fixed-point arithmetic overflow problems, improving control stability and hardware resource utilization.

Description

Technical Field

[0001] This invention relates to the field of digital power electronic control and embedded arithmetic optimization, and in particular to an LED driver intelligent configuration platform that supports NFC parameter writing. Background Technology

[0002] NFC technology, due to its passive and convenient characteristics, is widely used in the offline parameter configuration of intelligent LED driver power supplies. In digitally controlled LED driver systems, microcontrollers typically use fixed-point arithmetic operations for high-frequency pulse width modulation (PWM) control, and improve the calculation accuracy and dynamic range in the fixed-point domain by scaling the target configuration parameters with the sensor sampling feedback.

[0003] However, existing technologies have significant drawbacks when integrating NFC parameter writing with high-frequency fixed-point predictive control: First, dynamically adjusting the scaling factor can easily lead to misalignment between the numerical references of the configuration target domain and the real-time feedback domain, resulting in steady-state deviations; second, traditional error compensation logic can easily amplify sampling noise under limited word lengths of fixed-point numbers, causing duty cycle overshoot and high-frequency oscillations; third, overflow prevention designs for state accumulators often come at the cost of sacrificing ADC resolution, or causing arithmetic overflow of the fixed-point register due to continuous high-frequency accumulation; in addition, existing predictive control algorithms have high computational overhead and lack effective constraints on deviations from the initial NFC configuration reference. Furthermore, the direct coupling between NFC communication verification and the underlying physical bus write operation severely restricts the real-time response performance and system reliability of the high-frequency control loop.

[0004] Currently, no system can achieve NFC unified scaling domain locking, oscillation-free error compensation, and explicit cost function minimization of LED driver configuration while ensuring that fixed-point arithmetic does not overflow. Summary of the Invention

[0005] This invention completely eliminates the hidden dangers of time-varying drift, overcompensated oscillation, and arithmetic overflow by introducing a unified scaling domain with a fixed scaling factor (USD), a decaying target error compensator (TEC), an anti-overflow mechanism based on a periodically right-shifted state accumulator, and an explicit cost function minimization engine, thus achieving safe and stable control under high-frequency PWM cycles.

[0006] In a first aspect, this application provides an LED driver smart configuration platform that supports NFC parameter writing, including an NFC parameter configuration module, a scaling migration module, a hierarchical prediction module, a hardware scaling module, an encoding module, and an environment manager; The NFC parameter configuration module is used to receive NFC data exchange format messages, perform a sixteen-bit cyclic redundancy check calculation, and when the check passes, parse and extract the scaling identifier, the original target current value and the configuration reference duty cycle, and lock the configuration scaling factor. The scaling migration module retrieves the discrete shift addition spectrum of the hardware scaling module based on the scaling identifier, maps the original target current value and the original feedback current value sampled by the analog-to-digital converter to a unified scaling domain, and generates a unified scaling domain target current and a unified scaling domain feedback current. The hierarchical prediction module is used to calculate the compensated target current through the attenuation-type target error compensation algorithm, and iterate through the duty cycle search space to display the candidate duty cycle corresponding to the minimum value of the weighted cost as the optimal duty cycle. The hardware scaling module is used to store the discrete shift addition spectrum, and when the pulse width modulation control cycle count reaches the preset cycle value four times, it performs a bit width overflow prevention control operation on the state accumulation register inside the hierarchical prediction module. The encoding module is used to perform interval clamping restriction on the optimal duty cycle, generate corresponding register address mapping data, and send it to the duty cycle control register of the LED driver chip through the hardware physical bus. The environment manager is used to read LED temperature sensor data and input voltage sensor data at a low-frequency cycle independent of pulse width modulation control interruption. When the temperature change or voltage fluctuation exceeds the preset boundary, it sends a reconfiguration request to the NFC parameter configuration module.

[0007] As an optional implementation, the specific logic for locking the configuration scaling factor in the NFC parameter configuration module includes: When the NFC parameter writing action is triggered or a reconfiguration request is received from the environment manager, the scaling identifier in the message is extracted and the configuration scaling factor in the current configuration period is locked. Within the same pulse width modulation high-frequency control cycle, the value of the configuration scaling factor is kept fixed so that the target current in the unified scaling domain and the feedback current in the unified scaling domain are consistent with the reference in the fixed-point Q12 format.

[0008] As an optional implementation, the processing logic of the scaling migration module includes: During the configuration period in which the scaling factor remains fixed, the discrete shift mapping function corresponding to the scaling identifier in the hardware scaling module is invoked to convert the original target current value in unsigned integer format into a unified scaling domain target current in fixed-point format. At the moment when the analog-to-digital converter completes sampling, the original feedback current value in unsigned integer format is converted into a uniform scaling domain feedback current in fixed-point Q12 format through the discrete shift mapping function.

[0009] As an optional implementation, the hierarchical prediction module includes a decaying target error compensator (TEC) and an explicit cost function minimization solver. The attenuation-type target error compensator (TEC) includes a target current calculated after compensation using an attenuation-type target error compensation algorithm. Its processing logic includes: The difference between the target current and the feedback current in the unified scaling domain under the current pulse width modulation period is calculated to obtain the unified scaling domain current error value. The unified scaling domain current error value is then arithmetically shifted right by two bits to introduce a quarter attenuation coefficient. The right-shifted uniform scaling domain current error value is superimposed on the uniform scaling domain target current to generate the compensated target current.

[0010] As an optional implementation, the explicit cost function minimization solver is used to solve for the optimal duty cycle, and its processing logic includes: Obtain the actual duty cycle output of the previous pulse width modulation cycle, and construct a duty cycle search space with the actual duty cycle as the center, including five consecutive integer candidate values; Based on the 16-bit signed state accumulator register maintained by the hardware scaling module, the predicted current value corresponding to each candidate duty cycle is calculated using the discrete prediction function. For each candidate duty cycle in the duty cycle search space, the weighted sum of costs consisting of the current tracking error term, the duty cycle smoothing term, and the configuration bias penalty term that deviates from the NFC configuration baseline duty cycle is calculated by explicitly calculating the cost function. Iterate through and compare the weighted total cost corresponding to the five candidate duty cycles, extract the candidate duty cycle that minimizes the weighted total cost, and assign it to the optimal duty cycle.

[0011] As an optional implementation, the hardware scaling module is connected to both the scaling-transfer module and the hierarchical prediction module, and incorporates a multiplier-free discrete shift-add graph, which includes: The first mode is to directly output the input data; The second mode is the input data superimposed with the data itself after arithmetic right shift by one bit; The third mode is the input data superimposed with the data itself after arithmetic right shift by two bits; The fourth mode is the input data minus the data after arithmetic right shift by two bits; The fifth mode is to successively superimpose the input data with the data itself arithmetically shifted one position to the right and the data itself arithmetically shifted three positions to the right.

[0012] As an optional implementation, the logic for performing bit-width overflow prevention control on the status accumulator register includes: Define the status accumulator register as a 16-bit signed integer register; In each pulse width modulation cycle, the uniform scaling domain current error value is accumulated to the status accumulation register, and the pulse width modulation cycle counter is incremented once. When the pulse width modulation period counter reaches four times, the current accumulated value in the status accumulator register is shifted right by one bit using binary arithmetic, and the pulse width modulation period counter is cleared, so that the dynamic upper limit of the value in the status accumulator register is maintained within the boundary of the largest positive number of a 16-bit signed integer.

[0013] As an optional implementation, the encoding module is connected to the hierarchical prediction module, and its processing logic includes: Receive the optimal duty cycle and determine the magnitude of the optimal duty cycle compared to the preset lower limit duty cycle and the preset upper limit duty cycle; When the optimal duty cycle is lower than the preset lower duty cycle value, the optimal duty cycle is corrected to the preset lower duty cycle value; When the optimal duty cycle is higher than the preset upper limit duty cycle value, the optimal duty cycle is corrected to the preset upper limit duty cycle value; The corrected optimal duty cycle is converted into 16-bit binary data, combined with the physical register address of the LED driver chip to generate a control frame, which is then written to the LED driver chip via the hardware bus.

[0014] As an optional implementation, the environment manager is connected in bypass connection to the NFC parameter configuration module and connects the LED onboard temperature sensor and the input voltage sampling ADC. When the detected temperature change is greater than 15 degrees Celsius or the input voltage fluctuation exceeds the preset safety limit, the environment manager evaluates and determines the new scaling requirement, sends a reconfiguration request to the first-layer NFC parameter configuration module, updates the scaling identifier and remaps the unified scaling domain target current.

[0015] As an optional implementation, a dual-rate collaborative operation architecture for the high-frequency control main pipeline and the low-frequency bypass pipeline is also included, the logic of which is as follows: The scaling migration module, hierarchical prediction module, hardware scaling module, and encoding module constitute the high-frequency control main pipeline, which runs in a 100kHz pulse width modulation control interrupt. The entire process uses fixed-point Q12 format for addition, subtraction, and binary shift operations, without hardware multiplier instructions or floating-point operations. The environment manager and the NFC parameter configuration module form a low-frequency bypass pipeline, which runs in a 10Hz timer interrupt or background task, independent of the high-frequency control main pipeline. When a reconfiguration request is triggered by the environment manager or an external NFC write, the low-frequency bypass pipeline updates the scaling identifier in the global configuration register and relocks the configuration scaling factor, enabling the high-frequency control main pipeline to seamlessly and smoothly migrate to the new unified scaling domain in the next pulse width modulation control cycle.

[0016] As can be seen from the above technical solutions, the embodiments of this application have the following advantages: This invention constructs a unified scaling domain (USD) by strictly locking the configuration scaling factor within the configuration cycle. Regardless of how the sampled values ​​change within the high-frequency control cycle, the target configuration quantity and the sampled feedback quantity remain at the same fixed-point scale, ensuring the consistency of the control benchmark and solving the control inaccuracy problem caused by dynamic scaling.

[0017] This invention abandons the traditional proportional amplification error logic and introduces an attenuation factor, which is implemented by shifting the LED right by 2 bits in hardware. This not only compensates for the steady-state error caused by the temperature drift of the LED current-voltage characteristics without overshoot, but also weakens the influence of high-frequency sampling noise, ensuring the absolute stability of the control loop.

[0018] This invention explicitly applies the right-shift anti-overflow mechanism to the state accumulator register within the predictive control engine, rather than directly right-shifting the ADC sampling local variables. Combined with a 4-PWM cycle right-shift 1-bit decay mechanism, the upper limit boundary of the accumulator register is mathematically limited, ensuring the safety of fixed-point arithmetic operations.

[0019] This invention introduces a cost function that includes a configuration bias penalty term, and solves the problem of the algorithm formula being disconnected from the hardware implementation in existing patents by solving the minimum problem in the code logic through a 5-point loop around the current duty cycle. At the same time, it ensures that the system operates stably within the optimal working area of ​​the NFC configuration.

[0020] This invention decouples the verification of the NFC communication protocol layer to the first layer processing, and the fifth layer only retains pure physical register mapping and bus write operations. It removes redundant protocol calculations in the high-frequency control interrupt, and with the bypass running environment manager, it not only ensures the latency requirements of the high-frequency main control cycle, but also realizes adaptive rescaling of low-frequency environmental disturbances. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0022] Figure 1 A flowchart illustrating the architecture of an LED driver intelligent configuration platform supporting NFC parameter writing, provided in an embodiment of the present invention. Figure 2 This is a hardware data flow diagram of the discrete shift addition spectrum provided in an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] Furthermore, the technical features in the various embodiments or individual embodiments provided in this application can be arbitrarily combined with each other to form a feasible technical solution. Such combination is not constrained by the order of steps and / or the structural composition mode, but must be based on the ability of those skilled in the art to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0025] In the embodiments provided in this application, it should be understood that the disclosed methods and systems can be implemented in other ways. The system embodiments described below are merely illustrative. For example, the division of units and modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or modules can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling communication connection between the various components shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, and can be electrical, mechanical or other forms.

[0026] In addition, each functional unit in the various embodiments of this application can be integrated into a single processor, or each unit can be a separate device, or two or more units can be integrated into a single device; each functional unit in the various embodiments of this application can be implemented in hardware or in the form of hardware plus software functional units.

[0027] Those skilled in the art will understand that all or part of the steps of the following method embodiments can be implemented by program instructions and related hardware. The aforementioned program instructions can be stored in a computer-readable storage medium. When executed, the program instructions perform the steps of the following method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as mobile storage devices, read-only memory (ROM), magnetic disks, or optical disks. It should be understood that the use of terms such as "system," "device," "unit," and / or "module" in this application is merely to distinguish different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they can be replaced by other expressions.

[0028] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature marked "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" or "several" means two or more, unless otherwise explicitly specified. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes and to aid those skilled in the art, and are not intended to limit the implementation conditions of this application. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives of this application, should still fall within the scope of the technical content disclosed in this application.

[0029] If a flowchart is used in this application, it is used to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, the steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0030] It should also be noted that, in this document, terms such as “comprising,” “including,” or any other variations thereof are intended to cover a non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising one…” does not exclude the presence of other identical elements in the article or device that includes the aforementioned element.

[0031] Example 1, referring to Figure 1This embodiment provides an LED driver intelligent configuration platform that supports NFC parameter writing, including an NFC parameter configuration module (first layer), a scaling migration module (second layer), a hierarchical prediction module (third layer), a hardware scaling module (fourth layer), an encoding module (fifth layer), and an environment manager.

[0032] like Figure 1 As shown, an LED driver intelligent configuration platform that supports NFC parameter writing includes an NFC parameter configuration module, a scaling migration module, a hierarchical prediction module, a hardware scaling module, an encoding module, and an environment manager. The NFC parameter configuration module is used to receive NFC data exchange format messages, perform a sixteen-bit cyclic redundancy check calculation, and when the check passes, parse and extract the scaling identifier, the original target current value and the configuration reference duty cycle, and lock the configuration scaling factor. The scaling migration module retrieves the discrete shift addition spectrum of the hardware scaling module based on the scaling identifier, maps the original target current value and the original feedback current value sampled by the analog-to-digital converter to a unified scaling domain, and generates a unified scaling domain target current and a unified scaling domain feedback current. The hierarchical prediction module is used to calculate the compensated target current through the attenuation-type target error compensation algorithm, and iterate through the duty cycle search space to display the candidate duty cycle corresponding to the minimum value of the weighted cost as the optimal duty cycle. The hardware scaling module is used to store the discrete shift addition spectrum, and when the pulse width modulation control cycle count reaches the preset cycle value four times, it performs a bit width overflow prevention control operation on the state accumulation register inside the hierarchical prediction module. The encoding module is used to perform interval clamping restriction on the optimal duty cycle, generate corresponding register address mapping data, and send it to the duty cycle control register of the LED driver chip through the hardware physical bus. The environment manager is used to read LED temperature sensor data and input voltage sensor data at a low-frequency cycle independent of pulse width modulation control interruption. When the temperature change or voltage fluctuation exceeds the preset boundary, it sends a reconfiguration request to the NFC parameter configuration module.

[0033] This application provides an intelligent configuration platform for LED drivers that supports NFC parameter writing. By setting up an NFC parameter configuration module, a scaling migration module, a hierarchical prediction module, a hardware scaling module, an encoding module, and an environment manager, these modules work together to achieve collaborative processing of NFC configuration parameters and real-time feedback data within a unified scaling domain, thus completing the intelligent configuration and control of LED driver parameters. Specifically, the NFC parameter configuration module parses configuration parameters and locks scaling identifiers; the scaling migration module maps the target current and feedback current to the same numerical domain based on the scaling identifier, improving the consistency of control calculations; the hierarchical prediction module combines compensation calculations and duty cycle optimization to achieve real-time prediction and optimized control of LED driver output parameters; the hardware scaling module uses discrete shift addition to perform scaling calculations, combined with status register bit width control, reducing computational resource consumption and improving the reliability of fixed-point arithmetic; the encoding module quickly maps the optimized duty cycle to register control data and sends it to the LED driver chip, improving control response speed; and the environment manager operates independently of the high-frequency control loop, triggering reconfiguration when environmental changes are detected, enabling the system to automatically update configuration parameters based on environmental changes such as temperature and voltage.

[0034] Therefore, this application can realize the coordinated operation of NFC parameter writing and LED driver control, while ensuring the real-time performance of high-frequency control, improving the consistency of configuration parameters and feedback data, enhancing the system's adaptability to environmental changes, reducing control computation complexity, and improving the control stability, reliability and intelligence level of the LED driver system.

[0035] The specific logic for locking the configuration scaling factor in the NFC parameter configuration module includes: When the NFC parameter writing action is triggered or a reconfiguration request is received from the environment manager, the scaling identifier in the message is extracted and the configuration scaling factor in the current configuration period is locked. Within the same pulse width modulation high-frequency control cycle, the value of the configuration scaling factor is kept fixed so that the target current in the unified scaling domain and the feedback current in the unified scaling domain are consistent with the reference in the fixed-point Q12 format.

[0036] In one embodiment, the NFC parameter configuration module is used to receive NDEF format binary messages sent by an external configuration terminal. The length of the NDEF format binary message is 8 bytes, and the data structure is defined as follows: Byte 0 to Byte 1 are the CRC16 checksum for the communication layer; The second byte is the scaling identifier S, which has a value range of 0x00 to 0x04; Bytes 3 and 4 contain the original 16-bit unsigned target current value. Its value ranges from 0 to 65535, corresponding to a physical current of 0A to 5A; Bytes 5 and 6 configure the baseline duty cycle, in Q10 format, with a value range of 0 to 1023, corresponding to a duty cycle of 0% to 100%. The 7th byte is a reserved space.

[0037] The processing logic of the NFC parameter configuration module specifically includes: The CRC16 check function is invoked to perform data verification on the message. If the verification fails, the message is discarded. If the verification is successful, the configuration scaling factor S and the original target current value will be parsed and extracted. In conjunction with the baseline duty cycle, when this action is triggered, the scaling identifier S of the current configuration period is locked, and the corresponding theoretical configuration scaling ratio is determined based on the discrete shift addition graph corresponding to the scaling identifier S. In subsequent PWM control loops, the scaling factor is configured as long as no reconfiguration request is received. Maintain a constant and lock in the scale consistency of the uniform scaling domain (USD).

[0038] It should be noted that NFC is a short-range, high-frequency wireless communication technology; NDEF is the NFC data exchange format, a binary message structure. USD stands for Unified Scaling Domain, which refers to the unified fixed-point numerical space after the configuration target quantity and the real-time feedback quantity are mapped through the same scaling factor. Q12 format is a fixed-point number representation method, which means that in a 16-bit signed integer, the high 4 bits represent the integer part (including the sign bit) and the low 12 bits represent the fractional part. The scaling identifier S is used to select the index value of the internal shift map of the hardware scaling accelerator.

[0039] Theoretical scaling ratio S represents the theoretical scaling ratio corresponding to the scaling identifier S, and is used only to indicate the scaling relationship corresponding to the discrete shift addition spectrum. The actual scaling process is completed by calling the corresponding discrete shift addition graph based on the scaling identifier S.

[0040] The processing logic of the scaling and migration module includes: During the configuration period in which the scaling factor remains fixed, the discrete shift mapping function corresponding to the scaling identifier in the hardware scaling module is invoked to convert the original target current value in unsigned integer format into a unified scaling domain target current in fixed-point format. The target current in the uniform scaling domain is the Q12 format target current in the uniform scaling domain (USD). At the moment when the analog-to-digital converter completes sampling, the original feedback current value in unsigned integer format is converted into a uniform scaling domain feedback current in fixed-point Q12 format through the discrete shift mapping function.

[0041] The feedback current in the uniform scaling domain is the Q12 format feedback current in the uniform scaling domain (USD).

[0042] In one embodiment, under the Q12 fixed-point number format, the value 1.0 corresponds to the fixed-point integer 4096, i.e., 212212. The range of the 16-bit signed integer is [-32768, +32767]. The maximum physical current of the system is set to 5A, which corresponds to the base integer value 20480 under the Q12 format, i.e., 5×40965×4096.

[0043] When inputting raw data, it is normalized to the reference fixed-point number space in Q12 format for a 16-bit unsigned integer raw target current value. ∈[0,65535], corresponding to physical currents from 0A to 5A, Q12 reference conversion is completed through binary arithmetic shift and addition to generate the target reference fixed-point number. Its mathematical expression is: ; For the 12-bit unsigned integer raw feedback current value sampled by the analog-to-digital converter (ADC) The corresponding physical current ranges from 0A to 5A, generating a number of feedback reference fixed points. Its mathematical expression is: ; The above arithmetic multiplication by 5 is implemented in hardware through combinational logic (X << 2) + X without a multiplier, that is, the binary number is shifted left by two bits and then superimposed on itself; Based on the scaling identifier S, the corresponding discrete shift mapping function in the hardware scaling module is invoked to map the target reference fixed-point number and the feedback reference fixed-point number to a unified scaling domain USD. Its mathematical expression is: ; ; in, For the uniform scaling domain target current in Q12 format, Configure the scaling ratio for the uniform scaling domain feedback current in Q12 format. This is the equivalent gain designation for the scaling identifier S in the continuous number field, for example, when S=0x03. =0.750, and its discretized mapping entity in a fixed-point hardware pipeline is the discrete shift mapping function. Since the target value and the feedback value call the same S and the same shift pattern within the same PWM control cycle, absolute alignment of their scales in the fixed-point Q12 dimension is ensured.

[0044] The hierarchical prediction module includes a decaying target error compensator (TEC) and an explicit cost function minimization solver. The attenuation-type target error compensator (TEC) includes a target current calculated after compensation using an attenuation-type target error compensation algorithm. Its processing logic includes: The difference between the target current and the feedback current in the unified scaling domain under the current pulse width modulation period is calculated to obtain the unified scaling domain current error value. The unified scaling domain current error value is then arithmetically shifted right by two bits to introduce a quarter attenuation coefficient. The right-shifted uniform scaling domain current error value is superimposed on the uniform scaling domain target current to generate the compensated target current.

[0045] In one embodiment, the pulse width modulation period is the PWM period; To address the steady-state current deviation caused by the drift of the LED's current-voltage characteristics as the junction temperature increases, the current error under the current PWM period k can be calculated. To prevent overshoot and high-frequency oscillation caused by traditional proportional amplification, an attenuation factor of 0.25 is introduced. In hardware, this is achieved by right-shifting the binary arithmetic by 2 bits to generate the compensated target current. The attenuation-type target error compensator (TEC) is an error compensation algorithm that introduces an attenuation coefficient of less than 1 to prevent system overshoot. When the system has a positive error, that is, when the feedback value is lower than the target value, the target current is moderately increased after compensation to boost the system response. At the same time, the attenuation coefficient of 0.25 ensures that the high-frequency noise is reduced to 1 / 4 of the original value, thus avoiding control loop oscillation.

[0046] The explicit cost function minimization solver is used to solve for the optimal duty cycle, and its processing logic includes: Obtain the actual duty cycle output of the previous pulse width modulation cycle, and construct a duty cycle search space with the actual duty cycle as the center, including five consecutive integer candidate values; In one embodiment, the actual duty cycle of the output from the previous PWM cycle is obtained. Construct a duty cycle search space containing 5 candidate values, and the duty cycle search space includes candidate duty cycles. And candidate duty cycle It is an integer; Based on the 16-bit signed state accumulator register maintained by the hardware scaling module, the predicted current value corresponding to each candidate duty cycle is calculated using the discrete prediction function. The mathematical expression for the discrete prediction function is: ; in, Candidate duty cycle The corresponding predicted current value, For discrete prediction functions, The system fixed-point gain coefficient is set to 128 in the Q12 format, since 128 equals... Therefore, the hardware implementation uses a 7-bit left shift of the binary number, without calling a hardware multiplier. The 16-bit signed status accumulator register maintained for the fourth-layer hardware scaling module. This represents a right shift of 2 bits in binary arithmetic. A right shift of n bits in arithmetic arithmetic is equivalent to division by... And round down; Among them, the status accumulator register Used to record the cumulative amount of control state, and used as the state feedback term of the discrete prediction function to participate in the prediction of the next PWM cycle; This discrete prediction function is the first-order discrete difference state equation of the LED driver power electronic circuit (such as Buck / Boost topology) in the fixed-point number domain. Without needing to solve complex differential equations or perform matrix operations, it predicts the PWM duty cycle if it is adjusted to a candidate duty cycle in the next cycle using only a few integer additions, subtractions, and shifts. The value of the LED's output current.

[0047] For each candidate duty cycle in the duty cycle search space, the weighted sum of costs consisting of the current tracking error term, the duty cycle smoothing term, and the configuration bias penalty term that deviates from the NFC configuration baseline duty cycle is calculated by explicitly calculating the cost function. Explicitly compute the cost function The mathematical expression is: ; in, Candidate duty cycle The corresponding cost weighted sum, To compensate for the target current, To configure the baseline duty cycle, , and These are the weighting coefficients for the current tracking error term, the duty cycle smoothing term, and the configuration bias penalty term for deviation from the NFC configuration baseline duty cycle, respectively. The current tracking error term is... The duty cycle smoothing term is The configuration bias penalty term for deviation from the NFC configuration baseline duty cycle is: , This represents the absolute value operation; in, The preferred value is 4. Preferably 1, The preferred value is 2; It should be noted that in microcontrollers or digital signal processors, the execution time window for high-frequency (100kHz) PWM control interrupts is extremely narrow (only 10μs).

[0048] The weighting coefficients 4, 1, and 2 are all powers of 2. In embedded fixed-point arithmetic: Multiply =4 is equivalent to a left shift of 2 bits in binary arithmetic (<<2); Multiply =1 is equivalent to a direct output (no displacement); Multiply =2 is equivalent to a binary arithmetic left shift by 1 bit (<<1).

[0049] This preferred scheme enables an explicit cost function. The calculation is completely independent of the hardware multiplier instruction. It can complete the evaluation of 5 candidate duty cycles in a very short time by relying on only a single cycle of binary shift and addition. This greatly saves the computing power resources of the MCU and ensures the absolute real-time performance of the 100kHz high-frequency control main pipeline.

[0050] Iterate through and compare the weighted total cost corresponding to the five candidate duty cycles, extract the candidate duty cycle that minimizes the weighted total cost, and assign it to the optimal duty cycle.

[0051] It should be noted that the explicit cost function minimization solver can solve the problem of excessive computing power in traditional finite control set model predictive control FCS-MPC. It limits the prediction range to 5 integer points around the current duty cycle, without the need for complex discretization or continuous space differentiation. Minimization can be completed with only 5 very short for loops, making it extremely suitable for 100kHz MCUs. Traditional predictive control is prone to deviations due to sensor noise. This explicit cost function incorporates a baseline value configured with NFC. This allows the system to fine-tune the duty cycle according to temperature / voltage, while preventing excessive duty cycle drift from damaging the LED hardware. The TEC compensation is multiplied by 0.25 using >>2, with state accumulation feedback. The method uses >>2, and with the addition and subtraction of absolute values, the entire hierarchical prediction module does not call the hardware multiplier during execution. All operations involving the constant gain of 128 are implemented by binary left shift, so the entire execution process maintains zero hardware multiplier overhead.

[0052] The hardware scaling module is connected to the scaling migration module and the hierarchical prediction module respectively, and has a built-in discrete shift-add graph without multipliers; Reference Figure 2 This is a hardware data flow graph for a discrete shift addition pattern, which includes: The first mode is to directly output the input data; The second mode is the input data superimposed with the data itself after arithmetic right shift by one bit; The third mode is the input data superimposed with the data itself after arithmetic right shift by two bits; The fourth mode is the input data minus the data after arithmetic right shift by two bits; The fifth mode is to successively superimpose the input data with the data itself arithmetically shifted one position to the right and the data itself arithmetically shifted three positions to the right.

[0053] Referring to Table 1, which shows the discrete shift addition diagram, to achieve fast scaling without consuming hardware multiplier resources, the preset discrete shift mapping logic is as follows: Discrete Shift Addition Diagram: Table 1

[0054] Where X is the input 32-bit signed integer data, and ≫ represents the binary arithmetic right shift operator.

[0055] The logic for performing bit-width overflow prevention control on the status accumulator register includes: Define the status accumulator register as a 16-bit signed integer register; In each pulse width modulation cycle, the uniform scaling domain current error value is accumulated to the status accumulation register, and the pulse width modulation cycle counter is incremented once. When the pulse width modulation period counter reaches four times, the current accumulated value in the status accumulator register is shifted right by one bit using binary arithmetic, and the pulse width modulation period counter is cleared, so that the dynamic upper limit of the value in the status accumulator register is maintained within the boundary of the largest positive number of a 16-bit signed integer.

[0056] In one embodiment, a state accumulator register is defined. It is a 16-bit signed integer register, whose representable numerical boundary is [−32768, +32767]. In each PWM cycle k, with a main frequency of 100kHz, the current error is... Accumulated to status accumulator register In the Q12 fixed-point format, the maximum single-step error is [value missing]. And increment the PWM cycle counter by 1; To prevent the 16-bit register from overflowing due to continuous accumulation in the same direction, the state decay formula is executed when the PWM period counter reaches the preset period value of 4: ; Synchronously clear the PWM period counter to zero, and increment the state accumulator register corresponding to PWM period k+1. The dynamic upper limit is kept below 24575 to prevent fixed-point arithmetic overflow.

[0057] Exemplary proof of overflow prevention: Assuming the operating condition is such that the initial value of the state accumulator is at the maximum safety boundary... =24575, and the maximum single-step error accumulation occurred in the subsequent four consecutive cycles, that is... At this point, before the decay is performed, the maximum possible value of the temporary accumulated value is 24575 + 16384 = 40959. This intermediate process is temporarily stored using a 32-bit accumulator inside the microcontroller. When the counter reaches 4, an arithmetic right shift of 1 bit is performed, which is divided by 2. The new value of the status accumulator register is: ; Therefore, after 4 cycles of right shift by 1 bit and decay, The value always converges to below 24575, which mathematically guarantees that the 16-bit signed state accumulator register will not experience hardware arithmetic overflow.

[0058] It should be noted that, in the prediction function, To scale the value of the current state accumulator register in real time during the prediction calculation process, and to generate the predicted state feedback, the value in this state accumulator register... 1 is a state decay operation performed once every four PWM cycles to prevent bit width overflow of the state accumulation register. The two functions are different and do not replace each other.

[0059] The encoding module is connected to the hierarchical prediction module, and its processing logic includes: Receive the optimal duty cycle and determine the magnitude of the optimal duty cycle compared to the preset lower limit duty cycle and the preset upper limit duty cycle; When the optimal duty cycle is lower than the preset lower duty cycle value, the optimal duty cycle is corrected to the preset lower duty cycle value; When the optimal duty cycle is higher than the preset upper limit duty cycle value, the optimal duty cycle is corrected to the preset upper limit duty cycle value; The corrected optimal duty cycle is converted into 16-bit binary data, combined with the physical register address of the LED driver chip to generate a control frame, which is then written to the LED driver chip via the hardware bus.

[0060] In one embodiment, the encoding module is connected to the third-layer hierarchical prediction module. It does not include NFC communication protocol processing and application layer communication verification steps. It is only responsible for generating register writing data frames and sending them to the LED driver chip via the I2C bus or SPI bus.

[0061] In this embodiment, the preferred preset lower duty cycle value is 5, corresponding to a 0.5% duty cycle lower limit, and the preferred preset upper duty cycle value is 1018, corresponding to a 99.5% duty cycle upper limit, based on a 10-bit digital PWM counter. In the Q10 fixed-point format, the actual duty cycle corresponding to a value of 5 is approximately 5 / 1024 ≈ 0.488% ≈ 0.5%. The power MOSFETs in the LED driver circuit have inherent gate turn-on delay, rise time, and dead time. If the duty cycle is lower than 5, i.e., the pulse width is less than 0.5%, and at a 100kHz PWM frequency, the pulse width is less than 50ns. This conduction time will approach or even be less than the minimum physical response limit of the power device, easily causing severe heating due to the half-conduction state of the power switch, or causing the PWM drive pulse to be discarded by hardware physical filtering. To eliminate high-frequency flicker under deep dimming, setting 5 as a safety lower limit can ensure a stable minimum controllable effective current pulse output by the driver chip while providing an extremely wide dimming ratio (200:1). This avoids high-frequency current oscillation and LED light intensity flicker caused by inductor current discontinuity (DCM) at ultra-low duty cycles.

[0062] In the Q10 fixed-point format, the actual duty cycle corresponding to the value 1018 is 1018 / 1024≈99.41%≈99.5%. At this time, about 0.5% is retained in one PWM cycle, corresponding to 6 LSB counting units, and the turn-off time is about 60ns in a 100kHz cycle.

[0063] In Buck or Buck-Boost LED driver topologies, a high-side N-channel MOSFET driver circuit is used. The power required by the high-side MOSFET gate-floating driver chip relies on the bootstrap capacitor being charged via the low-side loop during the power switch's off-state. If the duty cycle reaches 100% (D=1023), the high-side switch remains continuously on, preventing the bootstrap capacitor from receiving a turn-off charge. This can cause the driver chip to erroneously turn off due to undervoltage protection (UVSO), leading to system failure. Setting an upper limit of 1018 forces the retention of a minimum turn-off time, ensuring that the bootstrap capacitor is accurately refreshed and charged in each PWM cycle.

[0064] A stable shutdown cycle provides the necessary potential reset time for the sampling resistor and the analog comparator / sample-and-hold circuit inside the microcontroller, preventing false tripping of the overcurrent protection caused by high-frequency saturation.

[0065] By limiting the optimal duty cycle safety clamp of the hierarchical prediction module output to a fixed-point closed interval of [5, 1018], the system ensures high dynamic response and extremely wide dimming range while eliminating the risks of power tube overheating, drive circuit power failure, and switch noise runaway caused by duty cycle extreme value saturation from a physical source. This ensures the hardware safety and steady-state reliable operation of the LED driver chip under various extreme control commands.

[0066] The optimal duty cycle value after clamp correction is converted into 16-bit binary register data, which is then combined with the physical address of the PWM duty cycle control register of the LED driver chip to generate a write data frame. This frame is then sent to the LED driver chip via the I2C bus and SPI bus. Since CRC calculation at the communication layer is not included, the real-time performance of the instruction write is guaranteed.

[0067] The environment manager is connected in bypass to the NFC parameter configuration module and connects the LED onboard temperature sensor and the input voltage sampling ADC. When the temperature change is detected to be greater than 15 degrees Celsius or the input voltage fluctuation exceeds the preset safety limit, the environment manager evaluates and determines the new scaling requirement, sends a reconfiguration request to the first-layer NFC parameter configuration module, updates the scaling identifier and remaps the target current of the unified scaling domain.

[0068] In one embodiment, the environment manager operates as a bypass low-frequency task within a 10Hz timer interrupt, without consuming the computing power of the 100kHz high-frequency PWM control main pipeline. The environment manager monitors the LED temperature and input voltage at a 10Hz sampling frequency, and initiates a reconfiguration request to the NFC parameter configuration module when the monitored values ​​exceed the limits. This enables the system to adapt to environmental changes while maintaining the stability of the high-frequency control loop.

[0069] In one embodiment, the specific execution logic of the environment manager includes: The trigger cycle is a 10Hz low-frequency timer independent of the pulse width modulation (PWM) control interrupt. When the low-frequency timer expires, the trigger environment manager executes the low-frequency cycle task: starts the microcontroller's low-speed analog-to-digital converter (ADC) channel, reads the onboard negative temperature coefficient (NTC) thermistor of the LED board to obtain the current temperature, and reads the voltage divider sampling circuit to obtain the current input voltage.

[0070] To prevent high-frequency noise interference, a 4-point moving average filter is applied to the raw data sampled by the ADC to eliminate occasional sampling spikes. The filter calculation formula is as follows: ; ; in, This is the filtered current temperature value. This is the current input voltage value after filtering. This is the raw temperature measurement data from the i-th sampling. The original input voltage measurement data of the i-th sampling is given, where i is the sampling point number within the sliding filter window, i=1, 2, 3, 4; The Environment Manager retrieves the temperature and voltage reference values ​​saved during the last reconfiguration, and calculates the temperature reference value and the filtered current temperature value, respectively. The absolute value of the difference, and the voltage reference value and the current input voltage value after filtering. The absolute value of the difference is used to obtain the current temperature change and the current voltage fluctuation.

[0071] The preset temperature boundary is set to 15℃. When the temperature rises or falls by more than 15℃, the LED's current-voltage characteristics and maximum safe current will change drastically. The preset voltage boundary is set to 10% of the bus nominal voltage. When the bus voltage fluctuates by more than ±10%, the system power supply status changes drastically.

[0072] If the current temperature change is less than or equal to the preset temperature boundary (ΔT≤15℃) and the current voltage fluctuation is less than or equal to the preset voltage boundary (ΔV≤10%), then the environment is determined to be within the safe range of slight drift. The environment manager clears the request flag and directly terminates this 10Hz low-frequency interrupt service. If the current temperature change exceeds the preset temperature boundary (ΔT>15℃) or the current voltage fluctuation exceeds the preset voltage boundary (ΔV>10%), the environment is deemed to be out of bounds, triggering the execution of the adaptive target scaling requirement assessment operation. The operation of assessing the adaptive target scaling requirement includes: The preset temperature rating and voltage compensation relationship is calculated using conditional threshold logic, and the environment manager uses the filtered current temperature value. With input voltage value , For the input rated voltage, the following step-wise decision logic is executed: During normal working hours, when and At that time, with the overall correction factor K=1.00, the new scaling identifier is locked. =0x00; During the first stage of heat reduction... At this time, a first-level derating is triggered, correcting the scaling factor K=0.75. This is achieved in hardware by subtracting the original target current by arithmetically shifting it two bits to the right, i.e., X−(X≫2), and matching and locking the new scaling identifier. =0x03; During the second-level deep reduction phase, when At this time, a secondary derating is triggered, correcting the scaling factor K to 0.50. This is achieved in hardware by performing a binary arithmetic right shift of the original target current by one bit (i.e., X ≫ 1), matching and locking the new scaling identifier. =0x00 and the target current is shifted to the right; During the voltage anomaly compensation phase, when or At that time, a voltage correction factor of 0.90 is further added on top of the current temperature derating factor.

[0073] The environment manager calculates the updated original target current value. and execute the configuration baseline duty cycle. The feedforward adaptive adjustment is calculated using the following formula: ; The calculation result, after clamping, is used as the new configuration baseline duty cycle. ; The Environment Manager will derive a new scaling identifier. Updated original target current value and the new configuration baseline duty cycle The data is packaged and encapsulated into a reconfiguration data structure RECFG_PACKET, and temporarily stored in the shared memory area by writing to the shadow register.

[0074] It should be noted that the above-described conditional threshold logic is only one implementation method. In other embodiments, lookup tables, continuous linear functions, or fitted curves can also be used to achieve adaptive correction of temperature and input voltage.

[0075] This transmission process is completed asynchronously via software interrupts and flags, without any blocking wait. The environment manager then exits this 10Hz low-frequency interrupt service.

[0076] When the NFC parameter configuration module polls or responds to the RECFG_REQ_FLAG flag, it recognizes a reconfiguration request from the environment manager. The NFC parameter configuration module calls the data validity verification function to perform a consistency check on the data passed by the environment manager. When the verification is successful: Update and latch the global configuration register CFG_SCALE_REG to the new scaling identifier. And relock the corresponding configuration scaling factor. .

[0077] Within the next 100kHz PWM high-frequency control cycle, the maximum response delay does not exceed 10μs, and the scaling migration module automatically reads the new scaling identifier. The corresponding discrete shift addition spectrum in the hardware scaling module is retrieved, and the original target current value and the sampled original feedback current value are remapped to the new unified scaling domain USD, thereby realizing the adaptive seamless and smooth migration of the control system to environmental changes.

[0078] In one embodiment of the present invention, a dual-rate collaborative operation architecture for the high-frequency control main pipeline and the low-frequency bypass pipeline is further included, the logic of which is as follows: The scaling migration module, hierarchical prediction module, hardware scaling module, and encoding module constitute the high-frequency control main pipeline, which runs in a 100kHz pulse width modulation control interrupt. The entire process uses fixed-point Q12 format for addition, subtraction, and binary shift operations, without hardware multiplier instructions or floating-point operations. The environment manager and the NFC parameter configuration module form a low-frequency bypass pipeline, which runs in a 10Hz timer interrupt or background task, independent of the high-frequency control main pipeline. When a reconfiguration request is triggered by the environment manager or an external NFC write, the low-frequency bypass pipeline updates the scaling identifier in the global configuration register and relocks the configuration scaling factor, enabling the high-frequency control main pipeline to seamlessly and smoothly migrate to the new unified scaling domain in the next pulse width modulation control cycle.

[0079] To prevent data contention between the 10Hz low-frequency bypass pipeline and the 100kHz high-frequency control main pipeline or to prevent interruptions in the PWM cycle when configuration parameters are modified, an atomic latch update mechanism based on the PWM counter periodic reset event is implemented: After the low-frequency bypass pipe (environment manager or NFC interrupt) completes the reconfiguration parameter calculation, it only writes the data to the global configuration shadow register and sets the global atomic request flag RECFG_PENDING = 1. At this time, it does not directly modify the current configuration register being used by the high-frequency control main pipe. The high-frequency control main pipeline running in the 100kHz PWM control interrupt prioritizes a one-time hardware-level polling check of the RECFG_PENDING flag only when the PWM counter count value returns to zero (i.e., the underscore lock point at the beginning of the PWM cycle). If RECFG_PENDING == 1 is detected, the high-frequency main pipe will configure the shadow register within one clock cycle. , and The atomic copy is made into the current running register, and then the RECFG_PENDING flag is cleared to 0. The scaling migration module then, at the beginning of the same PWM cycle, based on the latest locked... Recalculate for this period and .

[0080] This atomic latch mechanism ensures that any parameter update action only occurs at the beginning boundary of the PWM control cycle, completely eliminating the control quantity calculation disorder and output step spike caused by the sudden change of the scaling factor SS within a single 10μs control cycle, and realizing seamless and smooth migration of the unified scaling domain USD under high and low frequency cross-domain coordination.

[0081] This invention constructs a unified scaling domain (USD) by strictly locking the configuration scaling factor within the configuration cycle. Regardless of how the sampled values ​​change within the high-frequency control cycle, the target configuration quantity and the sampled feedback quantity remain at the same fixed-point scale, ensuring the consistency of the control benchmark and solving the control inaccuracy problem caused by dynamic scaling.

[0082] This invention abandons the traditional proportional amplification error logic and introduces an attenuation factor, which is implemented by shifting the LED right by 2 bits in hardware. This not only compensates for the steady-state error caused by the temperature drift of the LED current-voltage characteristics without overshoot, but also weakens the influence of high-frequency sampling noise, ensuring the absolute stability of the control loop.

[0083] This invention explicitly applies the right-shift anti-overflow mechanism to the state accumulator register within the predictive control engine, rather than directly right-shifting the ADC sampling local variables. Combined with a 4-PWM cycle right-shift 1-bit decay mechanism, the upper limit boundary of the accumulator register is mathematically limited, ensuring the safety of fixed-point arithmetic operations.

[0084] This invention introduces a cost function that includes a configuration bias penalty term, and solves the problem of the algorithm formula being disconnected from the hardware implementation in existing patents by solving the minimum problem in the code logic through a 5-point loop around the current duty cycle. At the same time, it ensures that the system operates stably within the optimal working area of ​​the NFC configuration.

[0085] This invention decouples the verification of the NFC communication protocol layer to the first layer processing, and the fifth layer only retains pure physical register mapping and bus write operations. It removes redundant protocol calculations in the high-frequency control interrupt, and with the bypass running environment manager, it not only ensures the latency requirements of the high-frequency main control cycle, but also realizes adaptive rescaling of low-frequency environmental disturbances.

[0086] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0087] In the above embodiments of this application, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0088] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An LED drive intelligent configuration platform supporting NFC parameter writing, characterized in that, It includes an NFC parameter configuration module, a scaling migration module, a hierarchical prediction module, a hardware scaling module, an encoding module, and an environment manager; The NFC parameter configuration module is used to receive NFC data exchange format messages, perform a sixteen-bit cyclic redundancy check calculation, and when the check passes, parse and extract the scaling identifier, the original target current value and the configuration reference duty cycle, and lock the configuration scaling factor. The scaling migration module retrieves the discrete shift addition spectrum of the hardware scaling module based on the scaling identifier, maps the original target current value and the original feedback current value sampled by the analog-to-digital converter to a unified scaling domain, and generates a unified scaling domain target current and a unified scaling domain feedback current. The hierarchical prediction module is used to calculate the compensated target current through the attenuation-type target error compensation algorithm, and iterate through the duty cycle search space to display the candidate duty cycle corresponding to the minimum value of the weighted cost as the optimal duty cycle. The hardware scaling module is used to store the discrete shift addition spectrum, and when the pulse width modulation control cycle count reaches the preset cycle value four times, it performs a bit width overflow prevention control operation on the state accumulation register inside the hierarchical prediction module. The encoding module is used to perform interval clamping restriction on the optimal duty cycle, generate corresponding register address mapping data, and send it to the duty cycle control register of the LED driver chip through the hardware physical bus. The environment manager is used to read LED temperature sensor data and input voltage sensor data at a low-frequency cycle independent of pulse width modulation control interruption. When the temperature change or voltage fluctuation exceeds the preset boundary, it sends a reconfiguration request to the NFC parameter configuration module.

2. The LED driving intelligent configuration platform supporting NFC parameter writing according to claim 1, characterized in that: The specific logic for locking the configuration scaling factor in the NFC parameter configuration module includes: When the NFC parameter writing action is triggered or a reconfiguration request is received from the environment manager, the scaling identifier in the message is extracted and the configuration scaling factor in the current configuration period is locked. Within the same pulse width modulation high-frequency control cycle, the value of the configuration scaling factor is kept fixed so that the target current in the unified scaling domain and the feedback current in the unified scaling domain are consistent with the reference in the fixed-point Q12 format.

3. The LED driving intelligent configuration platform supporting NFC parameter writing according to claim 1, characterized in that: The processing logic of the scaling and migration module includes: During the configuration period in which the scaling factor remains fixed, the discrete shift mapping function corresponding to the scaling identifier in the hardware scaling module is invoked to convert the original target current value in unsigned integer format into a unified scaling domain target current in fixed-point format. At the moment when the analog-to-digital converter completes sampling, the original feedback current value in unsigned integer format is converted into a uniform scaling domain feedback current in fixed-point Q12 format through the discrete shift mapping function.

4. The LED driving intelligent configuration platform supporting NFC parameter writing according to claim 1, characterized in that: The hierarchical prediction module includes a decaying target error compensator (TEC) and an explicit cost function minimization solver. The attenuation-type target error compensator (TEC) includes a target current calculated after compensation using an attenuation-type target error compensation algorithm. Its processing logic includes: The difference between the target current and the feedback current in the unified scaling domain under the current pulse width modulation period is calculated to obtain the unified scaling domain current error value. The unified scaling domain current error value is then arithmetically shifted right by two bits to introduce a quarter attenuation coefficient. The right-shifted uniform scaling domain current error value is superimposed on the uniform scaling domain target current to generate the compensated target current.

5. The LED driving intelligent configuration platform supporting NFC parameter writing according to claim 4, characterized in that: The explicit cost function minimization solver is used to solve for the optimal duty cycle, and its processing logic includes: Obtain the actual duty cycle output of the previous pulse width modulation cycle, and construct a duty cycle search space with the actual duty cycle as the center, including five consecutive integer candidate values; Based on the 16-bit signed state accumulator register maintained by the hardware scaling module, the predicted current value corresponding to each candidate duty cycle is calculated using the discrete prediction function. For each candidate duty cycle in the duty cycle search space, the weighted sum of costs consisting of the current tracking error term, the duty cycle smoothing term, and the configuration bias penalty term that deviates from the NFC configuration baseline duty cycle is calculated by explicitly calculating the cost function. Iterate through and compare the weighted total cost corresponding to the five candidate duty cycles, extract the candidate duty cycle that minimizes the weighted total cost, and assign it to the optimal duty cycle.

6. The LED driving intelligent configuration platform supporting NFC parameter writing according to claim 1, characterized in that: The hardware scaling module is connected to both the scaling-transfer module and the hierarchical prediction module, and incorporates a multiplier-free discrete shift-add graph, which includes: The first mode is to directly output the input data; The second mode is the input data superimposed with the data itself after arithmetic right shift by one bit; The third mode is the input data superimposed with the data itself after arithmetic right shift by two bits; The fourth mode is the input data minus the data after arithmetic right shift by two bits; The fifth mode is to successively superimpose the input data with the data itself arithmetically shifted one position to the right and the data itself arithmetically shifted three positions to the right.

7. The LED driving intelligent configuration platform supporting NFC parameter writing according to claim 6, characterized in that: The logic for performing bit-width overflow prevention control on the status accumulator register includes: Define the status accumulator register as a 16-bit signed integer register; In each pulse width modulation cycle, the uniform scaling domain current error value is accumulated to the status accumulation register, and the pulse width modulation cycle counter is incremented once. When the pulse width modulation period counter reaches four times, the current accumulated value in the status accumulator register is shifted right by one bit using binary arithmetic, and the pulse width modulation period counter is cleared, so that the dynamic upper limit of the value in the status accumulator register is maintained within the boundary of the largest positive number of a 16-bit signed integer.

8. The LED driving intelligent configuration platform supporting NFC parameter writing according to claim 1, characterized in that: The encoding module is connected to the hierarchical prediction module, and its processing logic includes: Receive the optimal duty cycle and determine the magnitude of the optimal duty cycle compared to the preset lower limit duty cycle and the preset upper limit duty cycle; When the optimal duty cycle is lower than the preset lower duty cycle value, the optimal duty cycle is corrected to the preset lower duty cycle value; When the optimal duty cycle is higher than the preset upper limit duty cycle value, the optimal duty cycle is corrected to the preset upper limit duty cycle value; The corrected optimal duty cycle is converted into 16-bit binary data, combined with the physical register address of the LED driver chip to generate a control frame, which is then written to the LED driver chip via the hardware bus.

9. The LED driver intelligent configuration platform supporting NFC parameter writing according to claim 1, characterized in that: The environment manager is connected in bypass to the NFC parameter configuration module and connects the LED onboard temperature sensor and the input voltage sampling ADC. When the temperature change is detected to be greater than 15 degrees Celsius or the input voltage fluctuation exceeds the preset safety limit, the environment manager evaluates and determines the new scaling requirement, sends a reconfiguration request to the first-layer NFC parameter configuration module, updates the scaling identifier and remaps the target current of the unified scaling domain.

10. The LED driver intelligent configuration platform supporting NFC parameter writing according to claim 1, characterized in that: It also includes a dual-rate collaborative operation architecture for the high-frequency control main pipeline and the low-frequency bypass pipeline, the logic of which is as follows: The scaling migration module, hierarchical prediction module, hardware scaling module, and encoding module constitute the high-frequency control main pipeline, which runs in a 100kHz pulse width modulation control interrupt. The entire process uses fixed-point Q12 format for addition, subtraction, and binary shift operations, without hardware multiplier instructions or floating-point operations. The environment manager and the NFC parameter configuration module form a low-frequency bypass pipeline, which runs in a 10Hz timer interrupt or background task, independent of the high-frequency control main pipeline. When a reconfiguration request is triggered by the environment manager or an external NFC write, the low-frequency bypass pipeline updates the scaling identifier in the global configuration register and relocks the configuration scaling factor, enabling the high-frequency control main pipeline to seamlessly and smoothly migrate to the new unified scaling domain in the next pulse width modulation control cycle.

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