Circuit board and method of manufacturing the same

Abstract

The application discloses a circuit board and a manufacturing method thereof. The circuit board comprises an inner circuit substrate, a first adhesive layer, a second adhesive layer, a first outer circuit substrate and a second outer circuit substrate. The inner circuit substrate comprises an inner circuit layer, a barrier, a first dielectric layer and a second dielectric layer. The inner circuit layer comprises a coplanar waveguide structure, the coplanar waveguide structure comprises a signal line and a ground line located on opposite sides of the signal line, the signal line and the ground line are separated by the barrier and are in contact with the barrier, the first dielectric layer is provided with a first through slot penetrating through the first dielectric layer, the coplanar waveguide structure is exposed from the first through slot, and the barrier protrudes from the surface of the coplanar waveguide structure. The first adhesive layer is provided with a first window penetrating through the first adhesive layer, the first window is in communication with the first through slot to form a first cavity, and the coplanar waveguide structure is exposed from the first cavity.

Description

Technical Field

[0001] This application relates to the field of circuit boards, and more particularly to a circuit board and a method for manufacturing the same. Background Technology

[0002] During the circuit board manufacturing process, adhesive overflow can easily occur during lamination. This overflow can flow onto and cover the signal lines of the coplanar waveguide structure, affecting the formation of air cavities on the surface of the coplanar waveguide structure. Summary of the Invention

[0003] In view of this, this application provides a circuit board and a method for manufacturing the same.

[0004] This application provides a circuit board including an inner circuit substrate, a first adhesive layer, a second adhesive layer, a first outer circuit substrate, and a second outer circuit substrate. The inner circuit substrate includes an inner circuit layer, a barrier, a first dielectric layer, and a second dielectric layer. The inner circuit layer includes a coplanar waveguide structure, which includes a signal line and a ground line located on opposite sides of the signal line. The barrier is embedded in the inner circuit layer, and the signal line and the ground line are separated by the barrier and are in contact with the barrier. The first dielectric layer and the second dielectric layer cover opposite surfaces of the inner circuit layer. The first dielectric layer has a first through-slot penetrating the first dielectric layer. The coplanar waveguide structure is exposed from the first through-slot. The barrier protrudes from the surface of the coplanar waveguide structure away from the second dielectric layer and is accommodated in the first through-slot. The barrier is surrounded by the first dielectric layer and the inner circuit layer to form a first adhesive overflow groove.

[0005] The first adhesive layer covers the inner circuit substrate. The first adhesive layer has a first window that penetrates the first adhesive layer. The first window communicates with the first through slot to form a first cavity. The coplanar waveguide structure is exposed from the first cavity.

[0006] The second adhesive layer covers the side of the internal circuit board opposite to the first adhesive layer;

[0007] The first outer circuit board covers the surface of the first adhesive layer away from the inner circuit board and is electrically connected to the inner circuit board.

[0008] The second outer circuit board covers the surface of the second adhesive layer away from the surface of the inner circuit board and is electrically connected to the inner circuit board.

[0009] A second aspect of this application provides a method for manufacturing a circuit board, comprising the following steps:

[0010] A first substrate is provided, the first substrate includes a first metal layer and a first dielectric layer, the first dielectric layer covers the surface of the first metal layer, a first through groove is formed on the surface of the first dielectric layer, and the first metal layer is exposed from the bottom of the first through groove.

[0011] A first photoresist layer is formed in the first through groove, and the first photoresist layer covers the surface of the first metal layer;

[0012] The first photoresist layer is exposed and developed to form multiple first openings in the first photoresist layer that expose the first metal layer.

[0013] The first metal layer is etched to form multiple slots to obtain an inner circuit layer including a coplanar waveguide structure. Each first opening is connected to each slot. The coplanar waveguide structure includes a signal line and a ground line located on opposite sides of the signal line. The signal line and the ground line are separated by the slots.

[0014] A blocking body is placed in the slot, and the blocking body protrudes from the opposite two surfaces of the inner circuit layer;

[0015] Remove the first photoresist layer and cover the surface of the inner circuit layer opposite to the first dielectric layer with a second dielectric layer to form an inner circuit substrate.

[0016] A second substrate and a first adhesive layer are provided, wherein the first adhesive layer has a first opening penetrating the first adhesive layer;

[0017] The second substrate, the first adhesive layer, and the inner circuit substrate are stacked and pressed together in sequence, wherein the second substrate covers the surface of the first adhesive layer away from the inner circuit substrate, the first adhesive layer covers the surface of the first dielectric layer away from the inner circuit layer, the first window corresponds to the position of the first through slot and the coplanar waveguide structure, and the first window communicates with the first through slot to form a first cavity; the space enclosed by the barrier, the inner circuit layer, and the first dielectric layer constitutes a first adhesive overflow groove.

[0018] In the circuit board provided in this application, a barrier is provided on the signal line and ground line of the coplanar waveguide structure. The barrier is used to block the excess glue generated during the circuit board manufacturing process, and to prevent the excess glue from flowing to the surface of the signal line and covering the signal line, so as to ensure that an effective cavity is formed on the surface of the signal line. Attached Figure Description

[0019] Figure 1 A cross-sectional schematic diagram of a first substrate provided in one embodiment of this application, wherein a first through groove is formed on the first substrate.

[0020] Figure 2 In order to be in Figure 1 The diagram shows a cross-sectional view of a first photoresist layer and a second photoresist layer formed on a first substrate, with a first opening and a second opening formed within the first and second photoresist layers.

[0021] Figure 3 In order to be in Figure 2 The diagram shows a cross-sectional view of the etched grooves on the first metal layer.

[0022] Figure 4 In order to be in Figure 3 The diagram shows a cross-sectional view of the slot filled with a barrier.

[0023] Figure 5 In order to be in Figure 4 A cross-sectional diagram showing the removal of the first and second photoresist layers.

[0024] Figure 6 This is a cross-sectional schematic diagram of a embodiment of the present application showing the stacking and pressing of a second substrate, a first adhesive layer, an internal circuit substrate, a second adhesive layer, and a third substrate.

[0025] Figure 7 This is a cross-sectional schematic diagram of a first cavity and a second cavity formed by pressing according to an embodiment of this application.

[0026] Figure 8 This is a cross-sectional schematic diagram of a circuit board provided in one embodiment of this application.

[0027] Explanation of main component symbols

[0028]

[0029]

[0030]

[0031] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0032] To better understand the above-mentioned objectives, features, and advantages of the embodiments of this application, the application will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the features in the embodiments of this application can be combined with each other.

[0033] The following description sets forth numerous specific details to provide a thorough understanding of the embodiments of this application. The described implementations are only a portion, not all, of the embodiments described herein. All other implementations obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of the embodiments of this application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application.

[0035] Please see Figures 1 to 8 This application provides a method for manufacturing a circuit board 100, including the following steps:

[0036] S1: Please refer to Figure 1 A first substrate 10 is provided. The first substrate 10 includes a first metal layer 11 and a first dielectric layer 12. The first dielectric layer 12 covers the surface of the first metal layer 11. The first dielectric layer 12 has a first through groove 12a that passes through the first dielectric layer 12. The first metal layer 11 is exposed from the bottom of the first through groove 12a.

[0037] In this embodiment, the first metal layer 11 can be made of copper foil. The first dielectric layer 12 includes a first substrate layer 121 and a second substrate layer 122. The first substrate layer 121 can be made of adhesive, and the second substrate layer 122 can be made of polyimide. This is just an example, and this application does not impose any special limitations on the material of the first dielectric layer 12. In this embodiment, the first metal layer 11 includes patterned lines.

[0038] S2: Please refer to Figure 1 and Figure 2 A first photoresist layer 13 is formed within the first through-groove 12a, and the first photoresist layer 13 covers the surface of the first metal layer 11. A second photoresist layer 14 is formed on the surface of the first metal layer 11 opposite to the first dielectric layer 12.

[0039] In this embodiment, the first photoresist layer 13 and the second photoresist layer 14 can be made of liquid photosensitive solder resist ink.

[0040] S3: Please refer to Figure 2 The first photoresist layer 13 and the second photoresist layer 14 are exposed and developed, so that the first photoresist layer 13 forms a plurality of first openings 13a exposing the first metal layer 11, and the second photoresist layer 14 forms a plurality of second openings 14a exposing the first metal layer 11, with the positions of the first openings 13a and the second openings 14a corresponding to each other. In this embodiment, there are two first openings 13a and two openings 14a.

[0041] S4: Please refer to Figure 2 and Figure 3The first metal layer 11 is etched to form multiple slots 15a. The multiple slots 15a space the first metal layer 11 to form signal lines 21 and ground lines 22, resulting in an inner circuit layer 15 including a coplanar waveguide structure 20. The first opening 13a and the second opening 14a are respectively connected to the multiple slots 15a. The coplanar waveguide structure 20 includes signal lines 21 and ground lines 22 located on opposite sides of the signal lines 21. The signal lines 21 and ground lines 22 are separated by the slots 15a.

[0042] S5: Please refer to Figure 4 A blocking body 30 is placed within the slot 15a. The blocking body 30 protrudes from the two opposite surfaces of the inner circuit layer 15. The space enclosed by the blocking body 30, the inner circuit layer 15, and the first dielectric layer 12 constitutes the first adhesive overflow groove 46. The blocking body 30 is used to block the adhesive overflow generated by the adhesive layer during the lamination process of the circuit board 100, so that the adhesive overflows into the first adhesive overflow groove 46 without covering the surface of the signal line 21.

[0043] In this embodiment, the barrier 30 fills the first opening 13a, the second opening 14a, and the slot 15a, and the two surfaces of the barrier 30 exposed on the first photoresist layer 13 and the second photoresist layer 14 are flush with the surfaces of the first photoresist layer 13 and the second photoresist layer 14 that are away from the inner circuit layer 15. The barrier 30 can be made of a highly elastic material, such as modified polymethyl methacrylate. This is just an example, and this application does not impose any special limitations on the material of the barrier 30.

[0044] S6: Please refer to Figure 4 , Figure 5 and Figure 6 The first photoresist layer 13 and the second photoresist layer 14 are removed. A second dielectric layer 41 is provided, and a second through-groove 41a is formed on the surface of the second dielectric layer 41. The second dielectric layer 41 covers the surface of the inner circuit layer 15 opposite to the first dielectric layer 12. The coplanar waveguide structure 20 and the barrier 30 are exposed in the second through-groove 41a, thereby forming the inner circuit substrate 50. The space enclosed by the barrier 30, the inner circuit layer 15, and the second dielectric layer 41 constitutes a second adhesive overflow groove 47, which is used to contain excess adhesive.

[0045] In this embodiment, the second dielectric layer 41 includes a third substrate layer 411 and a fourth substrate layer 412. The third substrate layer 411 can be made of an adhesive, and the fourth substrate layer 412 can be made of polyimide. This is just an example, and this application does not impose any special restrictions on the material of the second dielectric layer 41.

[0046] S7: Please refer to Figure 6 and Figure 7The system provides a second substrate 42, a first adhesive layer 44, a second adhesive layer 45, and a third substrate 43. The first adhesive layer 44 has a first window 44a that penetrates the first adhesive layer 44, and the first window 44a corresponds to the position of the first through groove 12a and the coplanar waveguide structure 20. The second adhesive layer 45 has a second window 45a that penetrates the second adhesive layer 45, and the position of the second window 45a corresponds to the position of the second through groove 41a and the coplanar waveguide structure 20.

[0047] The second substrate 42, the first adhesive layer 44, the inner circuit substrate 50, the second adhesive layer 45, and the third substrate 43 are stacked and pressed in sequence, such that the second substrate 42 covers the surface of the first adhesive layer 44 away from the inner circuit substrate 50, the first adhesive layer 44 covers the surface of the first dielectric layer 12 away from the inner circuit layer 15, the third substrate 43 covers the surface of the second adhesive layer 45 away from the inner circuit substrate 50, and the second adhesive layer 45 covers the surface of the inner circuit substrate 50. The first opening 44a is connected to the first through groove 12a to form a first cavity 51 on the surface of the coplanar waveguide structure 20, and the second opening 45a is connected to the second through groove 41a to form a second cavity 52 on the opposite surface of the coplanar waveguide structure 20.

[0048] During the pressing process, after the first adhesive layer 44 and the second adhesive layer 45 are heated and melted, they are prone to overflow under the action of external forces such as the press. If overflow occurs, the overflow will flow into the first overflow tank 46 and the second overflow tank 47, and the overflow will not easily flow to the signal line 21 and cover the surface of the signal line 21 due to the blocking effect of the blocking body 30.

[0049] Furthermore, during the pressing process, the second substrate 42 and / or the third substrate 43 at the location of the first cavity 51 and / or the second cavity 52 are prone to sinking due to the influence of external forces such as the press. When the material of the blocking body 30 is a highly elastic material, and the surface of the blocking body 30 protrudes from the surface of the first dielectric layer 12 and / or the second dielectric layer 41, the blocking body 30 protruding from the surface of the inner circuit layer 15 acts as a support buffer. It can buffer the pressure during the pressing process. When the pressing is completed and the external forces such as the press are removed, the blocking body 30 can rebound to prevent the cavity from collapsing and can form an effective cavity on the surface of the coplanar waveguide structure 20.

[0050] In this embodiment, the second substrate 42 includes a second metal layer 421 and a third dielectric layer 422, and the third substrate 43 includes a third metal layer 431 and a fourth dielectric layer 432. The second metal layer 421 and the third metal layer 431 can be made of copper foil. The third dielectric layer 422 and the fourth dielectric layer 432 can be made of epoxy resin board with a flame retardant rating of FR-4.

[0051] In this embodiment, the first adhesive layer 44 and the second adhesive layer 45 are made of polypropylene.

[0052] In this embodiment, the first cavity 51 and the second cavity 52 contain air or are in a vacuum.

[0053] S8: Please refer to Figure 8 A first through-hole 61 is formed on the second substrate 42, penetrating the second substrate 42, the first adhesive layer 44, and the first dielectric layer 12, with the inner circuit layer 15 exposed from the bottom of the first through-hole 61. A second through-hole 62 is formed on the third substrate 43, penetrating the third substrate 43, the second adhesive layer 45, and the second dielectric layer 41, with the inner circuit layer 15 exposed from the bottom of the second through-hole 62. A third through-hole 63 is formed on the surface of the second substrate 42, penetrating the second substrate 42, the first adhesive layer 44, the first dielectric layer 12, the inner circuit layer 15, the second dielectric layer 41, the second adhesive layer 45, and the third substrate 43.

[0054] S9: Please refer to Figure 8 A first conductive structure 64 is electroplated within the first through-hole 61, electrically connecting the inner circuit layer 15 and the second metal layer 421. A second conductive structure 65 is electroplated within the second through-hole 62, electrically connecting the inner circuit layer 15 and the third metal layer 431. A third conductive structure 66 is electroplated within the third through-hole 63, electrically connecting the inner circuit layer 15, the second metal layer 421, and the third metal layer 431.

[0055] In some embodiments, the method further includes electroplating a first electroplated layer 71 on the surface of the second metal layer 421 opposite to the third dielectric layer 422, and electroplating a second electroplated layer 72 on the surface of the third metal layer 431 opposite to the fourth dielectric layer 432. The first electroplated layer 71 is electrically connected to the second metal layer 421 and the third conductive structure 66. The second electroplated layer 72 is electrically connected to the third metal layer 431 and the third conductive structure 66.

[0056] S10: Please refer to Figure 8 The second metal layer 421 and the first electroplated layer 71 are fabricated to form a first outer circuit layer 67. The third metal layer 431 and the second electroplated layer 72 are fabricated to form a second outer circuit layer 68.

[0057] If there is no first electroplating layer 71 and second electroplating layer 72 in step S9, then in step S10, the second metal layer 421 is fabricated to form the first outer circuit layer 67; and the third metal layer 431 is fabricated to form the second outer circuit layer 68.

[0058] S11: Please refer to Figure 8A protective layer 80 is formed on the surfaces of the first outer circuit layer 67 and the second outer circuit layer 68. The protective layer 80 covers the surface of the first outer circuit layer 67 away from the third dielectric layer 422, the surface of the second outer circuit layer 68 away from the fourth dielectric layer 432, and the surface of the third conductive structure 66 exposed on the third via 63.

[0059] Please see Figure 8 This application also provides a circuit board 100, including an inner circuit substrate 50, a first adhesive layer 44, a second adhesive layer 45, a first outer circuit substrate 91, and a second outer circuit substrate 92. The inner circuit substrate 50 includes an inner circuit layer 15, a barrier 30, a first dielectric layer 12, and a second dielectric layer 41. The inner circuit layer 15 includes a coplanar waveguide structure 20, which includes a signal line 21 and a ground line 22 located on opposite sides of the signal line 21. The barrier 30 is embedded in the inner circuit layer 15, and the signal line 21 and the ground line 22 are separated by the barrier 30 and are in contact with the barrier 30. The first dielectric layer 12 and the second dielectric layer 41 cover the opposite surfaces of the inner circuit layer 15. The first dielectric layer 12 has a first through-slot 12a penetrating the first dielectric layer 12. The coplanar waveguide structure 20 is exposed from the first through-slot 12a. The blocking body 30 protrudes from the surface of the coplanar waveguide structure 20 away from the surface of the second dielectric layer 41 and is accommodated in the first through-slot 12a. The blocking body 30, the inner circuit layer 15, and the first dielectric layer 12 surround each other to form a first overflow groove 46. The first adhesive layer 44 covers the inner circuit substrate 50. The first adhesive layer 44 has a first opening 44a penetrating the first adhesive layer 44. The first opening 44a communicates with the first through-slot 12a to form a first cavity 51. The coplanar waveguide structure 20 is exposed from the first cavity 51. The second adhesive layer 45 covers the side of the inner circuit substrate 50 away from the first adhesive layer 44. The first outer circuit substrate 91 covers the surface of the first adhesive layer 44 away from the inner circuit substrate 50 and is electrically connected to the inner circuit substrate 50. The second outer circuit board 92 covers the second adhesive layer 45 away from the surface of the inner circuit board 50 and is electrically connected to the inner circuit board 50.

[0060] The first adhesive overflow groove 46 is used to collect adhesive overflow generated during the manufacturing process of the circuit board 100, and the block 30 prevents the adhesive overflow from covering the surface of the signal line 21. In this embodiment, the material of the block 30 can be a highly elastic material, such as modified polymethyl methacrylate or other elastic materials. This is just an example, and this application does not impose any special limitations on the material of the block 30.

[0061] In this embodiment, the inner circuit layer 15 is provided with a slot 15a, and the blocking body 30 is disposed in the slot 15a. The first overflow groove 46 is located in the first through groove 12a.

[0062] In this embodiment, the first cavity 51 is filled with air, and the coplanar waveguide structure 20 is in contact with the air. Using air as a medium can better reduce the skin effect of the coplanar waveguide structure 20, resulting in lower damage and a wider bandwidth, which meets the requirements of high-performance microwave integrated circuits for high frequency, high speed and low loss.

[0063] In some embodiments, the second dielectric layer 41 is provided with a second through groove 41a penetrating the second dielectric layer 41, and the second adhesive layer 45 is provided with a second window 45a penetrating the second adhesive layer 45. The second window 45a communicates with the second through groove 41a to form a second cavity 52. ​​The coplanar waveguide structure 20 is exposed from the second cavity 52. ​​The barrier 30 protrudes from the surface of the coplanar waveguide structure 20 away from the first dielectric layer 12 and is accommodated in the second cavity 52. ​​The barrier 30, the second dielectric layer 41 and the inner circuit layer 15 surround to form a second adhesive overflow groove 47.

[0064] In this embodiment, the second cavity 52 is filled with air. The addition of the second cavity 52 ensures that the coplanar waveguide structure 20, especially the signal line 21, is in contact with air on both sides, further reducing signal loss. The second adhesive overflow groove 47 is used to collect adhesive overflow generated during the fabrication of the circuit board 100.

[0065] In some embodiments, the barrier 30 includes a first surface 31 and a second surface 32 facing each other. The first surface 31 protrudes from the surface of the first dielectric layer 12 away from the inner circuit layer 15 and is separate from the first outer circuit substrate 91. Increasing the height of the barrier 30 can further improve its effect in preventing excess adhesive, and the barrier 30 can also provide support, reducing the risk of the first cavity 51 collapsing during the pressing process.

[0066] In some embodiments, the second surface 32 protrudes from the surface of the second dielectric layer 41 away from the inner circuit layer 15 and is separate from the second outer circuit substrate 92. Increasing the height of the barrier 30 can further improve its effect in preventing excess adhesive. Furthermore, the barrier 30 can act as a support, reducing the risk of the second cavity 52 collapsing during the lamination process.

[0067] In some embodiments, the first external circuit board 91 includes a first external circuit layer 67 and a third dielectric layer 422. The third dielectric layer 422 is located between the first external circuit layer 67 and the first adhesive layer 44. The third dielectric layer 422 covers the surface of the first adhesive layer 44 away from the surface of the inner circuit board 50, and a portion of the surface of the third dielectric layer 422 is exposed in the first cavity 51.

[0068] In some embodiments, the second external circuit board 92 includes a second external circuit layer 68 and a fourth dielectric layer 432. The fourth dielectric layer 432 is located between the second external circuit layer 68 and the second adhesive layer 45. The fourth dielectric layer 432 covers the surface of the second adhesive layer 45 away from the surface of the inner circuit board 50, and a portion of the surface of the fourth dielectric layer 432 is exposed in the second cavity 52.

[0069] In some embodiments, the circuit board 100 further includes a first conductive structure 64 that penetrates the first outer circuit board 91, the first adhesive layer 44 and the first dielectric layer 12 and is electrically connected to the inner circuit layer 15.

[0070] In some embodiments, the circuit board 100 further includes a second conductive structure 65, which penetrates the second outer circuit board 92, the second adhesive layer 45, and the second dielectric layer 41 and is electrically connected to the inner circuit layer 15.

[0071] In some embodiments, the circuit board 100 further includes a third conductive structure 66, which penetrates the circuit board 100 and electrically connects the inner circuit layer 15, the first outer circuit substrate 91, and the second outer circuit substrate 92. The third conductive structure 66 is used to enable circuit conduction between the circuit layers within the circuit board 100.

[0072] The above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application should not depart from the spirit and scope of the technical solutions of this application.

Claims

1. A circuit board, characterized in that, include: An internal circuit board includes an internal circuit layer, a barrier, a first dielectric layer, and a second dielectric layer. The internal circuit layer includes a coplanar waveguide structure, which includes a signal line and a ground line located on opposite sides of the signal line. The barrier is embedded in the internal circuit layer, and the signal line and the ground line are separated by the barrier and are in contact with the barrier. The first dielectric layer and the second dielectric layer cover opposite surfaces of the internal circuit layer. The first dielectric layer has a first through-slot penetrating the first dielectric layer. The coplanar waveguide structure is exposed from the first through-slot. The barrier protrudes from the surface of the coplanar waveguide structure away from the second dielectric layer and is accommodated in the first through-slot. The barrier, the first dielectric layer, and the internal circuit layer surround each other to form a first adhesive overflow groove. A first adhesive layer covers the inner circuit substrate. The first adhesive layer has a first window that penetrates the first adhesive layer. The first window communicates with the first through slot to form a first cavity. The coplanar waveguide structure is exposed from the first cavity. The second adhesive layer covers the side of the inner circuit board that is away from the first adhesive layer; A first outer circuit board covers the surface of the first adhesive layer that is away from the inner circuit board and is electrically connected to the inner circuit board. The second outer circuit board covers the surface of the second adhesive layer away from the inner circuit board and is electrically connected to the inner circuit board.

2. The circuit board as described in claim 1, characterized in that, The second dielectric layer has a second through groove penetrating the second dielectric layer, and the second adhesive layer has a second opening penetrating the second adhesive layer. The second opening and the second through groove communicate to form a second cavity. The coplanar waveguide structure is exposed from the second cavity. The blocking body protrudes from the surface of the coplanar waveguide structure away from the first dielectric layer and is accommodated in the second cavity. The blocking body, the second dielectric layer, and the inner circuit layer surround to form a second overflow groove.

3. The circuit board as described in claim 1, characterized in that, The barrier includes a first surface and a second surface opposite each other, the first surface protruding from the surface of the first dielectric layer away from the inner circuit layer and separate from the first outer circuit substrate.

4. The circuit board as described in claim 3, characterized in that, The second surface protrudes from the surface of the second dielectric layer away from the inner circuit layer and is separate from the second outer circuit substrate.

5. The circuit board as described in claim 1, characterized in that, The first external circuit board includes a first external circuit layer and a third dielectric layer. The third dielectric layer is located between the first external circuit layer and the first adhesive layer. The third dielectric layer covers the surface of the first adhesive layer away from the inner circuit board, and a portion of the surface of the third dielectric layer is exposed in the first cavity.

6. The circuit board as described in claim 2, characterized in that, The second external circuit board includes a second external circuit layer and a fourth dielectric layer. The fourth dielectric layer is located between the second external circuit layer and the second adhesive layer. The fourth dielectric layer covers the surface of the second adhesive layer away from the inner circuit board, and a portion of the surface of the fourth dielectric layer is exposed in the second cavity.

7. The circuit board as described in claim 1, characterized in that, The circuit board further includes a first conductive structure that penetrates the first outer circuit substrate, the first adhesive layer, and the first dielectric layer and is electrically connected to the inner circuit layer.

8. A method for manufacturing a circuit board, characterized in that, Includes the following steps: A first substrate is provided, the first substrate includes a first metal layer and a first dielectric layer, the first dielectric layer covers the surface of the first metal layer, a first through groove is formed on the surface of the first dielectric layer, and the first metal layer is exposed from the bottom of the first through groove. A first photoresist layer is formed in the first through groove, and the first photoresist layer covers the surface of the first metal layer; The first photoresist layer is exposed and developed to form multiple first openings in the first photoresist layer that expose the first metal layer. The first metal layer is etched to form multiple slots to obtain an inner circuit layer including a coplanar waveguide structure. Each first opening is connected to each slot. The coplanar waveguide structure includes a signal line and a ground line located on opposite sides of the signal line. The signal line and the ground line are separated by the slots. A blocking body is placed in the slot, and the blocking body protrudes from the opposite two surfaces of the inner circuit layer; Remove the first photoresist layer and cover the surface of the inner circuit layer opposite to the first dielectric layer with a second dielectric layer to form an inner circuit substrate. A second substrate and a first adhesive layer are provided, wherein the first adhesive layer has a first opening penetrating the first adhesive layer; The second substrate, the first adhesive layer, and the inner circuit substrate are stacked and pressed together in sequence, wherein the second substrate covers the surface of the first adhesive layer away from the inner circuit substrate, the first adhesive layer covers the surface of the first dielectric layer away from the inner circuit layer, the first window corresponds to the position of the first through slot and the coplanar waveguide structure, and the first window communicates with the first through slot to form a first cavity; the space enclosed by the barrier, the inner circuit layer, and the first dielectric layer constitutes a first adhesive overflow groove.

9. The method for manufacturing a circuit board as described in claim 8, characterized in that, The manufacturing method further includes: A second photoresist layer is formed on the surface of the first metal layer away from the first dielectric layer. The second photoresist layer is exposed and developed to form a plurality of second openings that expose the first metal layer. The positions of the second openings correspond to the positions of the first openings. The second openings are connected to the slots. The blocking part is located in the second opening. A second dielectric layer is provided, which covers the surface of the inner circuit layer opposite to the first dielectric layer. The second dielectric layer is provided with a second through slot, and the coplanar waveguide structure and the barrier are exposed in the second through slot. A second adhesive layer and a third substrate are provided, wherein the second adhesive layer has a second opening; The inner circuit substrate, the second adhesive layer, and the third substrate are stacked and pressed together in sequence, wherein the third substrate covers the surface of the second adhesive layer away from the inner circuit substrate, the second adhesive layer covers the surface of the inner circuit substrate, the second opening corresponds to the position of the second through slot and the coplanar waveguide structure, and the second opening communicates with the second through slot to form a second cavity; the space enclosed by the barrier, the inner circuit layer, and the second dielectric layer constitutes a second adhesive overflow groove.

10. The method for manufacturing a circuit board as described in claim 8, characterized in that, The blocking body protrudes from the surface of the inner circuit layer away from the first photoresist layer away from the inner circuit layer.

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