GaN chip embedded PCB integrated LC high-frequency power circuit structure and preparation method

Abstract

This invention discloses a GaN chip embedded PCB integrated LC high-frequency power circuit structure and fabrication method. The structure includes: a multilayer PCB substrate, a GaN bare chip, a PCB integrated equivalent capacitor assembly, and a PCB integrated equivalent inductor assembly. The multilayer PCB substrate has an inner cavity and inner layer circuitry. The GaN bare chip is embedded in the inner cavity and has power pads that are bonded to the inner layer circuitry. The PCB integrated equivalent capacitor assembly includes copper foil plates facing each other in the multilayer PCB substrate and an insulating dielectric layer sandwiched between the copper foil plates. The PCB integrated equivalent inductor assembly includes patterned conductive traces in the inner layer of the multilayer PCB substrate. By implementing this invention, a discrete, passive, low-parasitic, high-frequency, and high-efficiency integrated design of GaN power circuits is achieved, thus meeting the application requirements of embedded GaN high-frequency power circuits.

Description

Technical Field

[0001] This invention relates to the field of wide bandgap semiconductor power circuit technology, and in particular to the structure and fabrication method of GaN chip embedded PCB integrated LC high-frequency power circuit. Background Technology

[0002] Gallium nitride (GaN), as a third-generation wide-bandgap semiconductor material, has been widely used in power conversion scenarios such as high-frequency switching power supplies, new energy PFC circuits, high-frequency inverters, and wireless charging, as well as emerging fields such as joint motors for humanoid robots, thanks to its advantages such as fast switching speed, low conduction loss, and excellent high-frequency characteristics. GaN devices can achieve switching speeds of over 10 A / ns and operating frequencies exceeding tens of MHz. Compared to traditional silicon MOSFETs, its high-frequency operating capability has significant advantages, providing a core device foundation for the high-frequency, high-efficiency, and miniaturized power conversion circuits.

[0003] However, existing GaN power circuits generally employ a surface-mount packaged GaN device architecture paired with external discrete inductors and capacitors, which has several inherent drawbacks: external discrete LC devices occupy a large PCB area, resulting in low circuit integration and hindering device miniaturization; the pin and pad traces of discrete devices introduce additional parasitic inductance and resistance, which can easily cause severe voltage and current spikes and electromagnetic interference under high-speed GaN switching conditions, even damaging the devices; the large distance between discrete devices and the GaN chip leads to a lengthy power loop, significantly increasing high-frequency switching losses and limiting the high-frequency performance of GaN; at the same time, the large number of discrete passive components and complex assembly processes increase production costs and reduce overall reliability. Currently, the industry only offers scattered designs for PCB-based decoupling capacitors or single-planar inductors, lacking a complete solution that deeply integrates embedded GaN bare chips with an integrated PCB LC equivalent passive structure, making it difficult to simultaneously achieve multiple effects such as loop parasitic suppression, passive component integration, and high-frequency loss optimization.

[0004] Therefore, it is necessary to design a new structure to solve the technical problems of existing GaN high-frequency power circuits, such as numerous discrete passive components, large parasitic parameters, significant switching spikes, low integration, and high high-frequency losses, so as to realize the discrete passive, low parasitic, high-frequency and high-efficiency integrated design of GaN power circuits, thereby adapting to the application requirements of embedded GaN high-frequency power circuits. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a GaN chip embedded PCB integrated LC high-frequency power circuit structure and fabrication method.

[0006] To solve the above-mentioned technical problems, the objective of this invention is achieved through the following technical solution: providing a GaN chip embedded PCB integrated LC high-frequency power circuit structure, including: a multilayer PCB substrate, a GaN bare chip, a PCB integrated equivalent capacitor assembly, and a PCB integrated equivalent inductor assembly; The multilayer PCB substrate has an inner cavity and an inner circuit. The GaN bare chip is buried in the inner cavity. The GaN bare chip has a power pad, and the power pad is bonded and connected to the inner circuit. The PCB integrated equivalent capacitor assembly includes copper foil plates facing each other in the multilayer PCB substrate and an insulating dielectric layer sandwiched between the copper foil plates. The PCB integrated equivalent inductor component includes patterned conductive traces on the inner layer of the multilayer PCB substrate. The PCB integrated equivalent capacitor component, the PCB integrated equivalent inductor component, and the GaN bare chip constitute an integrated high-frequency power circuit.

[0007] The further technical solution is as follows: the power pad includes a drain power pad and a source power pad, and the copper foil plate covers the area where the drain power pad is located and the area where the source power pad is located, forming an embedded equivalent capacitor in situ. The embedded equivalent capacitor is used to realize high-frequency decoupling, resonant energy storage or voltage regulation functions.

[0008] The further technical solution is as follows: the insulating dielectric layer is made of FR4 board or high dielectric constant resin film; the capacitance value of the PCB integrated equivalent capacitor assembly is controlled by adjusting the overlapping area of ​​the mutually facing copper foil plates and / or the thickness of the insulating dielectric layer.

[0009] The further technical solution is as follows: the PCB integrated equivalent inductor component includes at least one of a single-turn wide copper foil straight trace structure and a multi-layer unidirectional spiral stacked trace structure. By adjusting the trace enclosure area, inter-layer stacking height, copper foil width and the number of trace coils, an equivalent inductance value with a preset inductance value is formed.

[0010] The further technical solution is as follows: the single-turn wide copper foil straight trace structure is formed by forming a wide and thick copper foil straight trace in the inner layer of the multilayer PCB substrate to form a single-turn planar power inductor; The multi-layer co-directional spiral stacked trace structure consists of multiple inner layers of co-directional spiral copper foil traces connected in series through metal vias, forming a multi-layer spiral resonant inductor.

[0011] The further technical solution is that the integrated high-frequency power circuit is entirely enclosed within the multilayer PCB substrate.

[0012] A further technical solution is as follows: the PCB integrated equivalent capacitor component is connected between the drain power pad and the source power pad to form a high-frequency decoupling path.

[0013] The further technical solution is as follows: the parameters of the multilayer spiral resonant inductor and the PCB integrated equivalent capacitor component are matched to form an integrated LC resonant cavity.

[0014] In addition, to overcome the shortcomings of the prior art, this invention also provides a method for fabricating a GaN chip embedded PCB integrated LC high-frequency power circuit structure, which includes the following steps: A multilayer PCB substrate is fabricated and an inner cavity is reserved. The copper foil for capacitor plates and copper foil for inductor traces are patterned in the inner layer of the multilayer PCB substrate. The GaN bare chip is implanted into the inner cavity, and the power pads of the GaN bare chip are bonded and connected to the inner circuit. The medium layer is pressed and cured to form an integrated structure.

[0015] A further technical solution includes: before fabricating the multilayer PCB substrate, the following steps are also included: Based on the target circuit parameters, simulation is used to determine the plate area and dielectric thickness of the equivalent capacitor, as well as the trace length, number of turns, and enclosed area of ​​the equivalent inductor.

[0016] The beneficial effects of this invention compared to existing technologies are as follows: This invention directly embeds the GaN bare chip in the inner cavity of a multilayer PCB substrate, bonding its power pads to the inner layer circuitry of the substrate. It utilizes the opposing copper foil plates and the insulating dielectric layer sandwiched between them to form an integrated equivalent capacitor assembly, and the patterned conductive traces on the inner layer of the substrate to form an integrated equivalent inductor assembly. This allows the equivalent capacitance, equivalent inductance, and the GaN bare chip to form an integrated high-frequency power circuit within the PCB. Thus, the native characteristics of the PCB's copper foil and dielectric layer replace external discrete LC devices in situ, eliminating parasitic inductance and resistance introduced by discrete device pins and pad traces. This avoids voltage and current spikes, electromagnetic interference, and device breakdown risks under high-speed switching conditions, significantly shortening the power circuit and reducing high-frequency switching losses. It achieves a discrete, passive, low-parasitic, high-frequency, and high-efficiency integrated design for GaN power circuits, thereby adapting to the application requirements of embedded GaN high-frequency power circuits.

[0017] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A layered cross-sectional view of the GaN chip embedded PCB integrated LC high-frequency power circuit structure provided in an embodiment of the present invention. Figure 2 This is a cross-sectional structural diagram of a PCB integrated equivalent capacitor assembly provided in an embodiment of the present invention; Figure 3 A cross-sectional view of the PCB integrated equivalent inductor assembly provided in an embodiment of the present invention; Figure 4 This is an overall layout diagram of the integrated high-frequency power circuit provided in an embodiment of the present invention; Figure 5 A circuit schematic diagram of an integrated high-frequency power circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of an LLC high-frequency resonant circuit provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the integrated PFC circuit for totem poles provided in an embodiment of the present invention. Explanation of the markings in the image: 1. Multilayer PCB substrate; 2. Inner cavity; 3. GaN bare chip; 4. Power pad; 5. Upper copper foil electrode; 6. Lower copper foil electrode; 7. Insulating dielectric layer; 8. Equivalent capacitance circuit; 9. Inner spiral copper foil trace; 10. Metal via; 11. Multilayer magnetic field superposition area; 12. Equivalent inductance circuit; 13. Integrated power main circuit; 14. High-frequency decoupling branch; 15. Resonant filter branch; 16. Input power supply; 17. Embedded main switch GaN transistor; 18. Embedded freewheeling GaN transistor; 19. PCB embedded flat... 20. Power inductor; 21. PCB-embedded parallel plate decoupling capacitor; 22. Load resistor; 23. Half-bridge input power supply; 24. Upper embedded GaN transistor; 25. Lower embedded GaN transistor; 26. PCB-embedded spiral resonant inductor; 27. PCB-embedded resonant capacitor; 28. High-frequency transformer primary side; 29. ​​AC input source; 30. PCB-embedded input filter inductor; 31. First embedded GaN switch; 32. Second embedded GaN switch; 33. PCB-embedded output decoupling capacitor; 34. DC output load; Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0022] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0023] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] Gallium nitride (GaN), as a third-generation wide-bandgap semiconductor material, boasts fast switching speeds, low conduction losses, and excellent high-frequency characteristics. It is widely used in high-frequency switching power supplies, new energy PFC, high-frequency inverters, wireless charging, and humanoid robot joint motors, with switching speeds exceeding 10A / ns and operating frequencies exceeding tens of MHz, demonstrating significant high-frequency advantages. However, existing GaN power circuits generally employ surface-mount packaged devices paired with external discrete inductors and capacitors, resulting in drawbacks such as large PCB area occupation, low integration density, parasitic parameters introduced by pins and traces leading to switching spikes and electromagnetic interference, even device breakdown, lengthy power loops increasing high-frequency losses, and numerous components, complex assembly, high cost, and low reliability. Furthermore, the industry only offers scattered designs such as PCB local decoupling capacitors or single planar inductors, lacking a complete solution that deeply integrates embedded GaN bare chips with PCB-integrated LC equivalent passive structures, making it difficult to simultaneously address parasitic suppression, passive integration, and high-frequency loss optimization.

[0025] To address these issues, this invention provides a GaN chip embedded PCB integrated LC high-frequency power circuit structure and fabrication method, solving the technical problems of existing GaN high-frequency power circuits such as numerous discrete passive components, large parasitic parameters, significant switching spikes, low integration density, and high high-frequency losses. This achieves a discrete, passive, low-parasitic, high-frequency, and high-efficiency integrated design for GaN power circuits, thereby adapting to the application requirements of embedded GaN high-frequency power circuits.

[0026] Specifically, by directly embedding the GaN bare chip in the inner cavity of a multilayer PCB substrate and bonding it to the inner layer circuitry via power pads, an integrated equivalent capacitor is constructed within the PCB inner layer using opposing copper foil plates to hold an insulating dielectric layer (FR4 substrate or high dielectric constant resin film; the capacitance value can be adjusted by changing the overlap area of ​​the plates and the dielectric thickness). An integrated equivalent inductor is constructed using patterned conductive traces (single-turn wide copper foil straight traces forming a single-turn planar power inductor, or multi-layer co-directional spiral stacked traces connected in series via metal vias to form a multi-layer spiral resonant inductor; the inductance value can be adjusted by the trace enclosure area, interlayer stacking height, copper foil width, and number of turns). Furthermore, the capacitor plates can in situ cover the drain and source power pad areas to form an embedded equivalent capacitor, which is then connected between the drain and source to achieve high-frequency decoupling, resonant energy storage, or voltage regulation. The parameters of the inductor and capacitor are matched to form an integrated LC resonant cavity, so that the equivalent capacitance, equivalent inductance and GaN bare chip are together enclosed in the PCB to form an integrated high-frequency power circuit. With the support of the manufacturing process of "first simulating to determine the capacitor plate area, dielectric thickness and inductor trace length, number of turns and enclosed area, then fabricating the inner cavity and patterned copper foil, implanting GaN bare chip for bonding and conduction, and pressing and solidifying the dielectric layer", the original characteristics of the PCB's own copper foil and dielectric layer are used to replace the external discrete LC devices. This eliminates the parasitic inductance and resistance introduced by the pin pads of discrete devices, shortens the power circuit, suppresses switching spikes and electromagnetic interference, and reduces high-frequency switching losses. It realizes the discrete passive, low parasitic, high-frequency and high-efficiency integrated design of GaN power circuit, and thus adapts to the application requirements of embedded GaN high-frequency power circuit.

[0027] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0028] Reference Figures 1 to 4 This embodiment provides a GaN chip embedded PCB integrated LC high-frequency power circuit structure, including a multilayer PCB substrate 1, a GaN bare chip 3, a PCB integrated equivalent capacitor component and a PCB integrated equivalent inductor component.

[0029] Among them, GaN bare chip refers to gallium nitride power semiconductor die without plastic encapsulation, ceramic packaging or other packaging processes. It does not have package pins and the power pads are directly exposed on the chip surface; embedded type refers to the mounting method in which the chip is placed inside the PCB substrate and does not protrude from the outer surface of the PCB substrate; PCB integrated equivalent capacitor assembly refers to a PCB body structure that can achieve the target capacitance function by using the copper foil layer of the PCB substrate itself as the electrode and the dielectric layer as the dielectric layer, without using independently packaged capacitor components; PCB integrated equivalent inductor assembly refers to a PCB body structure that can achieve the target inductance function by using the patterned conductive traces in the inner layer of the PCB substrate, without using independently packaged inductor devices.

[0030] like Figure 1 As shown, the multilayer PCB substrate 1 has an inner cavity 2 and inner layer circuitry. The inner cavity refers to a cavity formed in the inner layer region of the multilayer PCB substrate 1 to accommodate the GaN bare chip 3. The GaN bare chip 3 is embedded in the inner cavity 2 and has power pads 4, which are bonded and connected to the inner layer circuitry. Specifically, the inner cavity 2 can be formed by processes such as controlled-depth milling, laser ablation, or dielectric layer window lamination. It can be a closed cavity with both top and bottom closed, or a semi-closed cavity with openings at the top or bottom. The cavity size should be just large enough to accommodate the GaN bare chip 3 and its bonding space to minimize the PCB area occupied. The bonding and connection can be achieved using gold wire bonding or copper wire bonding. As alternative solutions, it can also be achieved by sintering silver chips followed by wire bonding, copper pillar flip-chip interconnection, or solder flip-chip interconnection. This invention does not limit the cavity forming process or the specific form of bonding and connection.

[0031] Since the GaN bare chip 3 is directly embedded in the inner layer of the PCB without traditional packaging, the parasitic inductance and parasitic resistance introduced by the package pins and package bonding wires are eliminated. The voltage and current spikes of GaN devices under high-speed switching conditions are effectively suppressed, and the circuit operation stability is significantly improved.

[0032] like Figure 2 As shown, the PCB integrated equivalent capacitor assembly includes copper foil plates facing each other in a multilayer PCB substrate 1 and an insulating dielectric layer 7 sandwiched between the two sets of copper foil plates. The facing copper foil plates are the upper copper foil plate 5 and the lower copper foil plate 6, which together form a parallel plate capacitor structure, forming an equivalent capacitor circuit 8. Figure 3 As shown, the PCB integrated equivalent inductor component includes patterned conductive traces in the inner layer of the multilayer PCB substrate 1, that is, a trace structure with the target inductance function is formed by patterning and etching the inner layer copper foil.

[0033] like Figure 4As shown, the PCB-integrated equivalent capacitance component, PCB-integrated equivalent inductance component, and GaN bare chip 3 constitute an integrated high-frequency power circuit. This integrated high-frequency power circuit refers to a power current loop formed by the GaN bare chip 3, the PCB-integrated equivalent capacitance component, and the PCB-integrated equivalent inductance component directly connected through the inner layer circuitry of the PCB. This loop does not contain any external discrete inductors or capacitors. Specifically, the integrated high-frequency power circuit includes an integrated power main circuit 13, a high-frequency decoupling branch 14, and a resonant filter branch 15. Thus, the GaN power circuit achieves a discrete, passive design, significantly reducing circuit size and significantly improving integration.

[0034] Furthermore, the multilayer PCB substrate 1 can adopt a symmetrical stacking design, that is, copper foil layers and dielectric layers are symmetrically arranged above and below the layer where the GaN bare chip 3 is located, in order to balance the lamination stress and prevent board warping; the surface layer of the multilayer PCB substrate 1 can also be provided with a grounded copper shielding layer, which encloses the integrated high-frequency power circuit between the shielding layers, further suppressing the outward radiation of high-frequency switching noise and reducing electromagnetic interference.

[0035] Further reference Figure 1 and Figure 2 The power pad 4 includes a drain power pad and a source power pad. The copper foil plate covers the areas where the drain power pad and the source power pad are located. That is, in the direction perpendicular to the PCB board, the projection of the copper foil plate covers the drain power pad area and the source power pad area of ​​the GaN bare chip 3, thereby forming an embedded equivalent capacitor in situ. This embedded equivalent capacitor is used to realize high-frequency decoupling, resonant energy storage, or voltage regulation. Since the equivalent capacitor is formed in situ close to the power pad 4 of the GaN bare chip 3, the decoupling path is the shortest, and there are no additional parasitic parameters introduced by leads and pad traces. Its high-frequency decoupling effect is far superior to that of external surface-mount capacitors.

[0036] Specifically, the upper copper foil electrode 5 and the lower copper foil electrode 6 can be respectively set to correspond one-to-one with the drain power pad and the source power pad, or a whole board arrangement can be adopted in which one copper foil electrode covers both the drain power pad area and the source power pad area at the same time; when the GaN bare chip 3 has multiple sets of drain and source power pads, multiple copper foil electrodes can also be set in corresponding partitions to achieve partition decoupling and further shorten the decoupling path of each pad.

[0037] In one embodiment, the insulating dielectric layer 7 is made of FR4 substrate or a high-dielectric-constant resin film; wherein, the high-dielectric-constant resin film refers to a special dielectric material for embedded capacitors with a relative permittivity higher than that of conventional FR4 substrate. The capacitance value of the PCB-integrated equivalent capacitor assembly can be controlled by adjusting the overlap area of ​​the opposing copper foil plates and / or the thickness of the insulating dielectric layer 7. In one specific implementation, the thickness of the insulating dielectric layer 7 can be selected within the range of 20μm-100μm, and the relative permittivity of the dielectric can be selected within the range of 4.2-40, so that the capacitance value covers the pF to nF level to adapt to different operating conditions such as high-frequency decoupling and resonant circuits. Since the capacitor parameters are precisely calibrated by the PCB layout and stack-up parameters, the consistency is good, and no debugging is required, avoiding parameter dispersion caused by the tolerance of discrete capacitors and soldering deviations.

[0038] In terms of capacitance design, the capacitance of a parallel-plate capacitor structure is positively correlated with the relative permittivity of the dielectric and the overlap area of ​​the copper foil plates, and negatively correlated with the thickness of the insulating dielectric layer 7. Therefore, during layout design, the target capacitance value can be obtained by first adjusting the overlap area for coarse adjustment, and then by selecting the dielectric thickness or changing the dielectric material. Under high-frequency operating conditions, it is advisable to select a dielectric material with a lower dielectric loss factor (Df) to reduce the high-frequency dielectric loss of the equivalent capacitor itself, ensuring that its loss in the MHz to tens of MHz frequency band is lower than that of traditional discrete devices.

[0039] As an alternative, the high dielectric constant resin film can be an epoxy resin film doped with ceramic filler, and the insulating dielectric layer 7 can also be replaced with low-loss dielectric materials such as ceramic-filled polytetrafluoroethylene (PTFE) sheets and liquid crystal polymer (LCP) films. In addition to adjusting the overlap area and dielectric thickness, the capacitance value can also be adjusted by replacing the dielectric material with a different dielectric constant.

[0040] As an alternative structure to the equivalent capacitor, the PCB integrated equivalent capacitor assembly can also adopt a same-layer interdigitated capacitor structure, that is, interdigitated electrodes are patterned on the same copper foil layer, and the edge electric field between adjacent interdigitated electrodes is used to form a capacitor; the interdigitated capacitor structure can be used alone or in parallel with the above-mentioned parallel plate capacitor structure to obtain a larger capacitance value in the same area.

[0041] Further reference Figure 3 The PCB integrated equivalent inductor component includes at least one of a single-turn wide copper foil straight trace structure and a multi-layer unidirectional spiral stacked trace structure. By adjusting the trace enclosure area, inter-layer stacking height, copper foil width, and number of trace coils, an equivalent inductance value with a preset inductance value is formed, constituting an equivalent inductance loop 12. As an alternative, the patterned conductive traces can also adopt a serpentine (bent) trace structure. This invention does not limit the specific pattern form of the traces.

[0042] In terms of inductance design, the inductance of the equivalent inductance mainly depends on the magnetic flux area enclosed by the traces: the larger the trace area, the higher the interlayer stacking height (i.e., the longer the magnetic field coupling path between traces), and the more coils, the greater the inductance. The copper foil width is mainly used to balance the current carrying capacity and parasitic capacitance. Under high-frequency operating conditions, due to the skin effect, the current concentrates on the surface of the copper foil. Using wide and thick copper foil traces can effectively reduce AC resistance and reduce the high-frequency loss of the inductor.

[0043] In one embodiment, the single-turn wide copper foil straight trace structure is formed by straight traces of wide, thick copper foil in the inner layer of a multilayer PCB substrate 1, constituting a single-turn planar power inductor. This single-turn planar power inductor has no magnetic core structure, eliminating high-frequency core loss and magnetic saturation issues. Furthermore, the wide, thick copper foil has a large cross-sectional area and strong current-carrying capacity, making it suitable for low-voltage, high-current power filtering scenarios. To further enhance the current-carrying capacity, two or more inner layers of wide copper foil straight traces can be connected in parallel through metal vias, significantly reducing trace resistance and temperature rise without increasing the board area.

[0044] The multi-layer unidirectional spiral stacked trace structure consists of multiple inner-layer spiral copper foil traces 9 connected in series through metal vias 10, forming a multi-layer spiral resonant inductor. These metal vias are through-holes that penetrate the PCB dielectric layer and form interlayer conductive connections through metallization plating, including mechanically drilled plated vias, as well as laser-drilled blind vias and buried vias. The spiral copper foil traces 9 are wound in the same direction, and the magnetic fields generated by the coils in each layer are superimposed within the multi-layer magnetic field superposition region 11, thus significantly increasing the overall inductance within a limited planar area, suitable for high-frequency resonant scenarios. Since the equivalent inductance is formed based on the inner-layer copper foil of the PCB, there are no parasitic pins or mounting height issues associated with discrete inductors, reducing high-frequency losses, shrinking circuit size, and improving integration.

[0045] To improve the quality factor (Q value) of a multilayer spiral resonant inductor, the following measures can be taken: increase the copper thickness of the spiral traces to reduce series resistance; increase the spacing between adjacent turns to reduce inter-turn parasitic capacitance; maintain sufficient dielectric spacing between the spiral traces and the ground plane to reduce parasitic capacitance to ground; align the spiral traces of each layer vertically to maximize the efficiency of magnetic flux superposition in the same direction. These measures can be used individually or in combination.

[0046] In one embodiment, the integrated high-frequency power circuit is entirely enclosed within the multilayer PCB substrate 1. All power connections between the GaN bare chip 3, the copper foil electrode, and the patterned conductive traces are completed through the inner layer circuitry of the PCB, and the power current does not pass through discrete devices on the outer surface of the PCB. In a specific implementation, the power pads 4 of the GaN bare chip 3 are directly connected to the copper foil electrode and the patterned conductive traces via the inner layer circuitry, with a straight-line distance of no more than 1 mm. The enclosed area of ​​the integrated high-frequency power circuit is less than 10 mm², and the inherent parasitic inductance of the circuit can be stably controlled within the 10 pH-100 pH range (below the 100 pH level). This effectively suppresses voltage and current spikes and high-frequency oscillations caused by switching rates above 10 A / ns of GaN devices, reducing electromagnetic interference. Simultaneously, since the power devices and passive structures are all built into the PCB, heat can be quickly conducted to the outer layer of the PCB through the large-area copper foil and metal vias 10 for dissipation. The short heat dissipation path and low thermal resistance contribute to improved overall lifespan and reliability.

[0047] To further optimize heat dissipation, a thermal via array can be set below and around the GaN bare chip 3. The thermal vias connect the inner heat dissipation copper foil to the heat dissipation pads or heat sinks on the PCB surface, forming a low thermal resistance heat conduction channel that runs through the thickness of the board. The thermal via array can be manufactured using the same process as the metal vias 10 mentioned above, without adding any additional processes.

[0048] In terms of layout, the high-frequency decoupling branch 14 should be arranged close to the GaN bare chip 3 on the nearest side of the integrated power main circuit 13, and the resonant filter branch 15 should be arranged along the power current flow direction so that the current loops of each branch are closed and do not overlap with each other, thus avoiding the introduction of additional parasitic parameters by magnetic field coupling between branches.

[0049] In one embodiment, an equivalent capacitor component integrated on the PCB is connected between the drain power pad and the source power pad to form a high-frequency decoupling path. This high-frequency decoupling path can quickly dissipate the energy of transient disturbances during switching, offset the voltage and current spikes caused by high di / dt and dv / dt during GaN high-speed switching, and suppress high-frequency oscillations in the circuit.

[0050] When the GaN bare chip 3 contains multiple sets of drain and source power pads, multiple sets of parallel plate equivalent capacitors can be set accordingly. The capacitance values ​​of each set of equivalent capacitors can be the same or can be configured differently according to the switching current of each pad group, so that the decoupling impedance remains low in each switching frequency band.

[0051] In one embodiment, the parameters of the multilayer spiral resonant inductor and the PCB integrated equivalent capacitance component are matched. That is, the inductance value of the spiral resonant inductor and the capacitance value of the equivalent capacitance are designed in tandem according to the target resonant frequency, thereby forming an integrated LC resonant cavity in situ without the need for any external surface-mount resonant components. In a specific implementation, this integrated LC resonant cavity is suitable for GaN high-frequency soft-switching operating scenarios of 10MHz-50MHz, enabling the circuit to operate stably under soft-switching conditions and significantly reducing switching losses.

[0052] The specific design method for resonant parameter matching is as follows: First, determine the product and proportional relationship between the resonant inductance and resonant capacitance values ​​based on the target resonant frequency and power level. Then, determine the inductance value by adjusting the number of turns and layers of the spiral trace, and determine the capacitance value by adjusting the overlapping area of ​​the copper foil plates and the dielectric thickness. Finally, verify the resonant point through electromagnetic field simulation and iteratively correct the layout parameters to ensure that the resonant frequency of the resonant cavity is precisely matched with the switching frequency of the GaN device, thereby achieving soft switching conditions of zero voltage turn-on (ZVS) or zero current turn-off (ZCS).

[0053] For example, a GaN Buck step-down circuit integrated structure adapted to switching frequencies up to 20MHz is disclosed. (See reference...) Figure 1 , Figure 2 and Figure 5 The multilayer PCB substrate 1 adopts a 4-layer stacked structure. The insulating dielectric layer 7 uses conventional FR4 material with a relative permittivity of 4.2 and a single-layer dielectric thickness of 50μm. The GaN bare chip 3 is embedded in the cavity 2 of the second inner layer of the PCB. The drain power pad and source power pad of the GaN bare chip 3 are directly opposite the copper foil plates of the first and third layers, respectively, forming a parallel plate integrated equivalent decoupling capacitor. The overlap area of ​​the copper foil plates is 8mm², with an equivalent capacitance of approximately 5.9pF, which can effectively filter out high-frequency switching noise.

[0054] In this embodiment, the circuit output terminal uses a 3oz thick inner copper foil to create a single-turn planar equivalent inductor. The trace length is 12mm, the width is 2mm, and the trace height from the ground plane is 0.1mm. Simulation results show an equivalent inductance value of 4.8nH. This single-turn planar power inductor has no magnetic core structure and no high-frequency magnetic loss, and can carry a large current of 20A, completely replacing traditional surface-mount power inductors and suitable for low-voltage, high-current, high-frequency step-down scenarios. As an alternative, the copper thickness of the thick copper foil can be selected in the range of 1oz-6oz, and the number of PCB layers can be stacked in 5, 6, or 8 layers. When the output current requirement is higher, two or more GaN bare chips can be connected in parallel and buried in the same inner cavity or adjacent inner cavity to improve the current carrying capacity.

[0055] like Figure 5As shown, the high-frequency Buck step-down topology of this embodiment includes an input power supply 16, an embedded main switch GaN transistor 17, an embedded freewheeling GaN transistor 18, a PCB-embedded planar power inductor 19, a PCB-embedded parallel-plate decoupling capacitor 20, and a load resistor 21. Its electrical connections are as follows: the positive terminal of the input power supply 16 is connected to the drain of the embedded main switch GaN transistor 17; the source of the main switch GaN transistor 17 is directly connected to the copper foil at the input terminal of the PCB-embedded planar power inductor 19; the output terminal of the planar power inductor 19 is connected to the positive terminal of the load resistor 21 and the upper plate of the PCB-embedded parallel-plate decoupling capacitor 20; the lower plate of the decoupling capacitor 20 is connected to system ground and simultaneously connected to the source of the embedded freewheeling GaN transistor 18; the drain of the freewheeling GaN transistor 18 is connected back to the source terminal of the main switch GaN transistor 17. This topology utilizes the native structure of the PCB to implement the output LC filter network, eliminating the need for traditional surface-mount power inductors and output capacitors; the power loop is completely embedded within the multi-layer structure of the PCB. Tests showed that the overall power loop area of ​​this embodiment is only 8mm², the parasitic inductance of the loop is as low as 35pH, and the peak voltage amplitude of the switching is reduced by more than 40% compared with the discrete device solution.

[0056] The design process of this embodiment is as follows: First, determine the target inductance value according to the output current ripple requirements, and then deduce the layout parameters such as trace length, width and ground clearance from the target inductance value. After simulation verification, the layout is finalized. The driving circuit of the GaN bare chip also uses short traces on the inner layer of the PCB to connect to the driving pad as close as possible to avoid the introduction of additional parasitic inductance in the driving circuit, which may lead to false turn-on.

[0057] Another example is an adaptation to a 30MHz GaN LLC resonant soft-switching circuit. (See reference...) Figures 1 to 4 and Figure 6 The multilayer PCB substrate 1 adopts a 6-layer stacked structure. The insulating dielectric layer 7 uses a high dielectric constant buried capacitor special dielectric with a relative dielectric constant of 18 and a dielectric thickness of 30μm. The GaN bare chip 3 is buried in the third inner layer. Large-area copper foil plates are arranged on its upper and lower layers respectively. The overlapping area of ​​the copper foil plates is 15mm², and the equivalent resonant capacitance is about 79.5pF, which meets the capacitance parameter requirements of LLC resonant cavity.

[0058] In this embodiment, the resonant inductor employs four layers of unidirectional spiral copper foil traces 9, with interlayer conduction via metal vias 10. The spiral has six turns, resulting in an overall equivalent inductance of 1.2 μH. This precisely matches the aforementioned embedded equivalent resonant capacitor, forming a passive LC resonant cavity. As an alternative, the number of spiral turns and spiral layers can be increased or decreased according to the target resonant frequency. The dielectric can also be replaced with other high-dielectric-constant materials to adjust the resonant capacitor value, thereby covering different resonant operating points within the 10MHz-50MHz range.

[0059] like Figure 6As shown, the LLC resonant converter topology in this embodiment includes a half-bridge input power supply 22, an upper embedded GaN transistor 23, a lower embedded GaN transistor 24, a PCB-embedded spiral resonant inductor 25, a PCB-embedded resonant capacitor 26, and the primary side of a high-frequency transformer 27. Its electrical connection is as follows: the upper embedded GaN transistor 23 and the lower embedded GaN transistor 24 form a half-bridge; the output terminal at the midpoint of the half-bridge is connected in series with the PCB-embedded spiral resonant inductor 25 and the PCB-embedded resonant capacitor 26 to form an LC resonant cavity; the entire resonant cavity is connected in series to the circuit of the primary side of the high-frequency transformer 27. Both the resonant inductor and resonant capacitor are equivalent passive structures formed by PCB layout, without any external components. The resonant parameters are precisely calibrated by the PCB stack-up, copper foil area, and number of coils. Testing shows that the entire resonant circuit has no external discrete components, the circuit parasitic parameters are extremely small, soft-switching operation is stable, the circuit conversion efficiency is improved by 3.5% compared to traditional discrete solutions, and electromagnetic interference is significantly reduced.

[0060] In this embodiment, the resonant cavity parameters and the dead time of the GaN switch are designed in synergy, so that the switch can complete the switching near the zero crossing of the resonant current, achieving zero voltage turn-on (ZVS); the primary side 27 of the transformer can also be implemented using a planar winding on the inner layer of the PCB, so that both the transformer and the resonant cavity are embedded in the PCB, further improving the overall power density.

[0061] Another example: applied to high-frequency totem-pole PFC circuits. (See reference...) Figure 1 , Figure 2 , Figure 4 and Figure 7 The multilayer PCB substrate 1 adopts a 5-layer structure, with the GaN bare chip 3 embedded in the inner layer. Embedded decoupling capacitors are placed adjacent to the power circuit to quickly absorb switching spikes and suppress high-frequency oscillations. A wide copper foil planar inductor is used as the power frequency filter inductor at the input end, which balances high current carrying capacity and low high-frequency loss, and is compatible with the high-frequency PFC operating characteristics of GaN. As an alternative, this wide copper foil planar inductor can also be replaced with a multilayer spiral stacked inductor or a serpentine trace inductor to adapt to different input filter inductance requirements. When the electromagnetic compatibility requirements on the input side are high, a common-mode choke structure can also be added to the AC input side. This common-mode choke structure can also be implemented using a double-wire spiral trace wound in parallel on the inner layer of the PCB.

[0062] like Figure 7As shown, the totem pole PFC topology of this embodiment includes an AC input source 28, a PCB-embedded input filter inductor 29, a first embedded GaN switch 30, a second embedded GaN switch 31, a PCB-embedded output decoupling capacitor 32, and a DC output load 33. Its electrical connection is as follows: the AC input source 28 is connected to the midpoint of the totem pole bridge arm via the PCB-embedded input filter inductor 29. The bridge arm is symmetrically composed of the first embedded GaN switch 30 and the second embedded GaN switch 31. The DC output terminal is connected in parallel to the PCB-embedded large-capacity parallel-plate output decoupling capacitor 32, achieving high-frequency ripple filtering and voltage regulation, completely eliminating the need for external filter inductors and high-voltage decoupling capacitors in traditional PFC circuits. Testing shows that the circuit integration of this embodiment is more than 60% higher than that of discrete device solutions.

[0063] The aforementioned GaN chip embedded PCB integrated LC high-frequency power circuit structure directly embeds the GaN bare chip in the inner cavity of a multilayer PCB substrate, bonding its power pads to the inner layer circuitry of the substrate. The PCB integrates an equivalent capacitor assembly using the opposing copper foil plates and the insulating dielectric layer sandwiched between them, and an equivalent inductor assembly using the patterned conductive traces on the inner layer of the substrate. This allows the equivalent capacitance, equivalent inductance, and the GaN bare chip to form an integrated high-frequency power circuit within the PCB. By replacing external discrete LC devices with the native characteristics of the PCB's copper foil and dielectric layer, the parasitic inductance and resistance introduced by the discrete device pins and pad traces are eliminated. This avoids voltage and current spikes, electromagnetic interference, and device breakdown risks under high-speed switching conditions, significantly shortening the power circuit and reducing high-frequency switching losses. This achieves a discrete, passive, low-parasitic, high-frequency, and high-efficiency integrated design for GaN power circuits, thus meeting the application requirements of embedded GaN high-frequency power circuits.

[0064] In one embodiment, a method for fabricating a GaN chip embedded PCB integrated LC high-frequency power circuit structure is also provided, for fabricating the high-frequency power circuit structure described in any of the above embodiments, comprising the following steps performed sequentially: S2. Fabricate a multilayer PCB substrate and reserve inner layer cavities. Pattern the capacitor plate copper foil and inductor trace copper foil in the inner layer of the multilayer PCB substrate. The inner layer cavity can be formed by controlled depth milling or laser ablation. As an alternative, the cavity can also be formed by laminating after opening windows in the dielectric layer. The patterning can be done using conventional acid etching process, and the line width and line spacing are controlled according to the target inductance and capacitance parameters.

[0065] S3. Implant the GaN bare chip into the inner cavity and bond the power pads of the GaN bare chip to the inner circuitry for connection. The bonding method can be gold wire bonding, copper wire bonding, or copper pillar flip-chip or solder flip-chip interconnect. Before implantation, adhesive can be applied to the bottom of the cavity to fix it and prevent the GaN bare chip from shifting during bonding and subsequent lamination.

[0066] S4. The dielectric layer is pressed and cured to form an integrated structure, completing the integrated packaging of the equivalent LC passive device and GaN chip built into the PCB. The pressing and curing can employ a stepped temperature curing process to reduce internal stress and prevent dielectric cracking at the cavity edges. Alternatively, partial lamination can be completed first, followed by die bonding, and finally secondary lamination to seal the cavity. This invention does not restrict the order of lamination and die bonding.

[0067] Using the above-described fabrication method, the parameters of capacitors and inductors are precisely calibrated by the PCB layout and layer stack-up, eliminating the need for surface mount component procurement, mounting, and soldering processes. This significantly reduces assembly defect rates, lowers production costs, and significantly improves overall consistency and reliability. After curing, random sampling tests of the inductance and capacitance values ​​of the integrated structure can be performed, and the test data can be fed back to the layout parameters for closed-loop correction, further converging the consistency of LC parameters in batch products.

[0068] Furthermore, before fabricating the multilayer PCB substrate, the above-mentioned preparation method also includes step S1: based on the target circuit parameters, the plate area and dielectric thickness of the equivalent capacitor, as well as the trace length, number of turns, and enclosed area of ​​the equivalent inductor, are determined by simulation. Specifically, electromagnetic field simulation software can be used to establish a PCB stack-up and layout model, and the layout parameters can be iteratively optimized with the target capacitance and inductance values ​​as constraints. The simulation content can include electrostatic capacitance extraction, magnetic quasi-static inductance extraction, and loop parasitic parameter extraction. As an alternative, the above parameters can also be determined by combining analytical calculation and simulation verification.

[0069] In other embodiments, the GaN bare chip can be an enhancement-type GaN HEMT die, a cascode GaN die, or a GaN power stage die with integrated drive and protection functions. The present invention does not limit the specific device form of the GaN bare chip. The number of GaN bare chips can be one, two or more. Multiple GaN bare chips can be embedded in the same inner cavity or disposed in different inner cavities to form a half-bridge, full-bridge or parallel switching structure.

[0070] The high-frequency power circuit structure of this embodiment can be widely used in GaN power conversion scenarios in the MHz to tens of MHz frequency band, such as high-frequency switching power supplies, PFC power factor correction circuits, LLC resonant converters, high-frequency inverter circuits, wireless charging, and humanoid robot joint motor drives, and has strong versatility.

[0071] In summary, this embodiment embeds the GaN bare chip into the inner cavity of the PCB. Relying on the PCB's multi-layer copper foil stacking structure, dielectric layer insulation characteristics, and trace enclosure structure, embedded equivalent capacitance and equivalent inductance are constructed in situ, completely replacing traditional external discrete inductors and capacitors. On the one hand, the power loop is shortened to an extreme degree, and parasitic inductance is reduced to below the pH level, effectively suppressing voltage and current spikes and high-frequency losses caused by GaN high-speed switching. On the other hand, passive components are completely built into the PCB, eliminating the need for additional surface mount technology (SMT) processes. This significantly improves circuit integration, heat dissipation performance, and operational reliability. Furthermore, the LC parameters can be precisely customized through PCB layout parameters to adapt to various application scenarios.

[0072] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A GaN chip embedded PCB integrated LC high-frequency power circuit structure, characterized in that, include: Multilayer PCB substrate, GaN bare chip, PCB integrated equivalent capacitor assembly and PCB integrated equivalent inductor assembly; The multilayer PCB substrate has an inner cavity and an inner circuit. The GaN bare chip is buried in the inner cavity. The GaN bare chip has a power pad, and the power pad is bonded and connected to the inner circuit. The PCB integrated equivalent capacitor assembly includes copper foil plates facing each other in the multilayer PCB substrate and an insulating dielectric layer sandwiched between the copper foil plates. The PCB integrated equivalent inductor component includes patterned conductive traces on the inner layer of the multilayer PCB substrate. The PCB integrated equivalent capacitor component, the PCB integrated equivalent inductor component, and the GaN bare chip constitute an integrated high-frequency power circuit.

2. The GaN chip embedded PCB integrated LC high-frequency power circuit structure according to claim 1, characterized in that, The power pads include drain power pads and source power pads. The copper foil plates cover the areas where the drain power pads and the source power pads are located, forming an embedded equivalent capacitor in situ. The embedded equivalent capacitor is used to realize high-frequency decoupling, resonant energy storage, or voltage regulation functions.

3. The GaN chip embedded PCB integrated LC high-frequency power circuit structure according to claim 1, characterized in that, The insulating dielectric layer is made of FR4 substrate or high dielectric constant resin film; the capacitance value of the PCB integrated equivalent capacitor assembly is controlled by adjusting the overlap area of ​​the mutually facing copper foil plates and / or the thickness of the insulating dielectric layer.

4. The GaN chip embedded PCB integrated LC high-frequency power circuit structure according to claim 1, characterized in that, The PCB integrated equivalent inductor component includes at least one of a single-turn wide copper foil straight trace structure and a multi-layer unidirectional spiral stacked trace structure. By adjusting the trace enclosure area, inter-layer stacking height, copper foil width and number of trace coils, an equivalent inductance value with a preset inductance value is formed.

5. The GaN chip embedded PCB integrated LC high-frequency power circuit structure according to claim 4, characterized in that, The single-turn wide copper foil straight trace structure is formed by straight traces of wide and thick copper foil in the inner layer of the multilayer PCB substrate, forming a single-turn planar power inductor. The multi-layer co-directional spiral stacked trace structure consists of multiple inner layers of co-directional spiral copper foil traces connected in series through metal vias, forming a multi-layer spiral resonant inductor.

6. The GaN chip embedded PCB integrated LC high-frequency power circuit structure according to claim 1, characterized in that, The integrated high-frequency power circuit is entirely enclosed within the multilayer PCB substrate.

7. The GaN chip embedded PCB integrated LC high-frequency power circuit structure according to claim 2, characterized in that, The PCB integrated equivalent capacitor assembly is connected between the drain power pad and the source power pad to form a high-frequency decoupling path.

8. The GaN chip embedded PCB integrated LC high-frequency power circuit structure according to claim 5, characterized in that, The multilayer spiral resonant inductor and the PCB integrated equivalent capacitor assembly are matched in parameters to form an integrated LC resonant cavity.

9. A method for fabricating a GaN chip embedded PCB integrated LC high-frequency power circuit structure, characterized in that, The method for fabricating a GaN chip embedded PCB integrated LC high-frequency power circuit structure as described in any one of claims 1 to 8 includes the following steps: A multilayer PCB substrate is fabricated and an inner cavity is reserved. The copper foil for capacitor plates and copper foil for inductor traces are patterned in the inner layer of the multilayer PCB substrate. The GaN bare chip is implanted into the inner cavity, and the power pads of the GaN bare chip are bonded and connected to the inner circuit. The medium layer is pressed and cured to form an integrated structure.

10. The method for fabricating a GaN chip embedded PCB integrated LC high-frequency power circuit structure according to claim 9, characterized in that, Before fabricating the multilayer PCB substrate, the following steps are also included: Based on the target circuit parameters, simulation is used to determine the plate area and dielectric thickness of the equivalent capacitor, as well as the trace length, number of turns, and enclosed area of ​​the equivalent inductor.

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