Semiconductor structure, method for manufacturing the same and electronic device

Abstract

This application provides a semiconductor structure, its fabrication method, and an electronic device. The semiconductor structure includes at least one stacked structure; the stacked structure, formed on the same substrate, includes: a memory array circuit layer and a control circuit layer that are alternately stacked in a vertical direction. The memory array circuit layer is configured to store data at least once. The control circuit layer is configured to control the read / write operations and data processing of the memory array circuit. By providing multiple memory array circuit layers on the same substrate, with each memory array circuit layer corresponding to an independent control circuit layer, this application can significantly shorten the physical transmission distance between the memory array circuit layer and the corresponding control circuit layer.

Description

Cross-references to related applications

[0001] This disclosure is based on and claims priority to Chinese Patent Application No. 202611054683.8, filed on July 15, 2026, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure, its fabrication method, and an electronic device. Background Technology

[0003] Dynamic Random Access Memory (DRAM) devices contain memory array circuitry and Complementary Metal-Oxide-Semiconductor (CMOS) circuitry. The CMOS circuitry primarily consists of core circuitry and peripheral circuitry. Existing CMOS-Bonded Array (CBA) architectures typically employ a two-wafer discrete fabrication approach, where the CMOS circuitry and memory array circuitry are fabricated on two separate wafers, with subsequent interlayer interconnection achieved through bonding processes. Furthermore, in this architecture, the core circuitry and peripheral circuitry are coplanarly arranged.

[0004] However, as the number of stacked layers of the storage array circuitry increases in the vertical direction, the physical distance between the upper storage cells and the bottom control circuitry increases, leading to an increase in parasitic parameters such as interconnect resistance and capacitance. This causes the sensing signal to attenuate more during transmission, thus affecting read reliability and performance. Summary of the Invention

[0005] This application provides a semiconductor structure, its fabrication method, and an electronic device. By providing multiple memory array circuit layers on the same substrate, with each memory array circuit layer corresponding to an independent control circuit layer, the physical transmission distance between the memory array circuit layer and the corresponding control circuit layer can be significantly shortened.

[0006] The technical solution of this application embodiment is implemented as follows: This application provides a semiconductor structure, which includes at least one stacked structure. The stacked structure is formed on the same substrate and includes a memory array circuit layer and a control circuit layer that are stacked alternately in a vertical direction. The memory array circuit layer is configured to store data. The control circuit layer is configured to control the read and write operations and data processing of the memory array circuit.

[0007] In some embodiments of this disclosure, the stacked structure includes multiple sets of stacked structures; wherein, one set of the stacked structures includes: a memory array circuit layer and a control circuit layer stacked along the vertical direction, the memory array circuit layer being located below the control circuit layer; in the stacked structure, the transistor channel material in the bottommost memory array circuit layer includes a first material or a second material, the transistor channel material in the remaining memory array circuit layers includes the first material, and the transistor channel material in all the control circuit layers includes a third material, wherein the first material, the second material, and the third material are different semiconductor materials.

[0008] In some embodiments of this disclosure, the stacked structure includes multiple sets of stacked structures; wherein, one set of the stacked structures includes: a memory array circuit layer and a control circuit layer stacked along the vertical direction, the memory array circuit layer being located above the control circuit layer; in the stacked structure, the transistor channel material in the bottommost control circuit layer includes a second material or a third material, the transistor channel material in the remaining control circuit layers includes the third material, and the transistor channel material in all the memory array circuit layers includes a first material, wherein the first material, the second material, and the third material are different semiconductor materials.

[0009] In some embodiments of this disclosure, the first material includes a metal oxide semiconductor material, the second material includes a silicon-based semiconductor material, and the third material includes a transition metal sulfide or a transition metal selenide.

[0010] In some embodiments of this disclosure, the storage array circuit layer is divided into a first part and a second part along the vertical direction; wherein the first part is controlled by the control circuit layer above it, and the second part is controlled by the control circuit layer below it.

[0011] In some embodiments of this disclosure, the control circuit layer includes a core circuit layer and a peripheral circuit layer; the core circuit layer is at least used to control the read and write operations of the memory array circuit; the peripheral circuit layer is at least used to control the data communication, address decoding and timing management of the memory array circuit; in a set of the stacked structures, the core circuit layer and the peripheral circuit layer are stacked along the vertical direction.

[0012] In some embodiments of this disclosure, in a set of stacked structures, the memory array circuit layer is located below the core circuit layer and the peripheral circuit layer is located above the core circuit layer; or, in a set of stacked structures, the peripheral circuit layer is located below the core circuit layer and the memory array circuit layer is located above the core circuit layer.

[0013] In some embodiments of this disclosure, the semiconductor structure further includes: a plurality of the stacked structures; the plurality of stacked structures are respectively formed on different substrates and bonded to each other along the vertical direction.

[0014] In some embodiments of this disclosure, the semiconductor structure further includes: in-memory computing circuitry; The in-memory computing circuit is located in at least one of the control circuit layer, the core circuit layer, and the peripheral circuit layer; The in-memory computing circuit is configured to perform computational processing on the data read from or written to the memory array circuit layer.

[0015] This disclosure also provides a method for fabricating a semiconductor structure, the method comprising: providing at least one substrate; forming a stacked structure on the substrate; wherein the stacked structure comprises: a memory array circuit layer and a control circuit layer that are alternately stacked in a vertical direction; the memory array circuit layer is configured to store data; and the control circuit layer is configured to control the read and write operations and data processing of the memory array circuit.

[0016] In some embodiments of this disclosure, the stacked structure includes multiple sets of stacked structures; wherein, one set of the stacked structures includes: a memory array circuit layer and a control circuit layer stacked along the vertical direction; the memory array circuit layer is located below the control circuit layer, or the memory array circuit layer is located above the control circuit layer.

[0017] In some embodiments of this disclosure, the control circuit layer includes a core circuit layer and a peripheral circuit layer; wherein the core circuit layer is at least used to control the read and write operations of the memory array circuit; the peripheral circuit layer is at least used to control the data communication, address decoding and timing management of the memory array circuit; the core circuit layer and the peripheral circuit layer are stacked along the vertical direction; or, the core circuit layer and the peripheral circuit layer are located on the same layer along the vertical direction.

[0018] In some embodiments of this disclosure, the method for fabricating the semiconductor structure further includes: providing a plurality of substrates, each of which has the stacked structure formed on it; and bonding the plurality of substrates along the vertical direction using a hybrid bonding process.

[0019] This disclosure also provides an electronic device, including a semiconductor structure as described in any of the above embodiments, or a semiconductor structure manufactured according to the method for preparing the semiconductor structure as described in any of the above embodiments.

[0020] The embodiments of this application have the following beneficial effects: By providing multiple memory array circuit layers on the same substrate, with each memory array circuit layer corresponding to an independent control circuit layer, compared to the traditional architecture where a single control circuit layer drives multiple memory arrays, the physical transmission distance between the memory array circuit layer and the corresponding control circuit layer can be significantly shortened. Furthermore, this effectively reduces parasitic parameters such as resistance and capacitance generated by interconnect lines, mitigating problems such as amplitude attenuation and noise rise of the sensing signal in long-distance transmission paths. Thus, the signal readout reliability and performance of the memory chip are improved. In addition, compared to the traditional architecture where the memory array circuit layer 10 and the control circuit layer 20 are fabricated on two separate substrates and then bonded together, this integrated manufacturing method eliminates the need for complex bonding processes, resulting in a simpler process flow and lower mass production costs. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application. Figure 1 ; Figure 2 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application. Figure 2 ; Figure 3 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application. Figure 3 ; Figure 4 This is a schematic diagram of the semiconductor structure provided in the embodiments of this application. Figure 4 ; Figure 5 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 5 ; Figure 6 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 6 ; Figure 7 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 7 ; Figure 8 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 8 ; Figure 9 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 9 ; Figure 10 Schematic diagram of the semiconductor structure provided in the embodiments of this application Figure 10 ; Figure 11 This is a schematic flowchart illustrating the method for fabricating a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of the invention will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate the embodiments of this application, but are not intended to limit the scope of the embodiments of this application.

[0023] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0024] In the following description, the terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0025] In this document, when a layer / component is referred to as being "above" another layer / component, the layer / component may be directly above the other layer / component, or there may be an intermediate layer / component between them. Furthermore, in one orientation, a layer / component is "above" another layer / component; when the orientation is reversed, the layer / component may be "below" the other layer / component.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of embodiments of this application.

[0027] Complementary Metal-Oxide-Semiconductor (CMOS) in Dynamic Random Access Memory (DRAM) devices is the most fundamental and core manufacturing technology in integrated circuits. In a CMOS bonded array (CBA) architecture, the CMOS circuitry and the memory array circuitry are typically fabricated on two separate wafers and then connected via bonding. This allows the CMOS circuitry to control the read / write operations and data processing of the entire memory array. However, as the number of stacked layers in the vertical direction of the memory array increases, the physical distance between the higher-level memory cells and the lower-level control circuitry increases, leading to a rise in parasitic parameters such as interconnect resistance and capacitance. This causes accelerated attenuation of the sensing signal during transmission, thus affecting read reliability and performance.

[0028] Based on this, embodiments of this disclosure provide a semiconductor structure. Figure 1 and Figure 2 These represent two stacking methods for semiconductor structures. (Refer to...) Figure 1 and Figure 2 As shown, the semiconductor structure includes: at least one stacked structure 100; the stacked structure 100, formed on the same substrate, includes: a memory array circuit layer 10 and a control circuit layer 20 that are stacked alternately in a vertical direction; the memory array circuit layer 10 is configured to store data; the control circuit layer 20 is configured to control the read and write operations and data processing of the memory array circuit.

[0029] It should be noted that, referring to Figure 1 and Figure 2 As shown, the control circuit layer 20 integrates the decoding, amplification, timing control, and signal processing transistors required for memory read / write operations. Leveraging the advantages of single-crystal silicon channel devices—high carrier mobility, fast switching speed, and low static power consumption—it can perform core logic operations and signal processing tasks such as memory array addressing, weak read signal amplification, and read / write timing control. It provides stable and reliable drive and detection circuits for the memory array, ensuring normal read / write operations of the memory cells. The memory array circuit layer 10 is the core functional layer in the semiconductor memory chip used for actual data storage. It consists of a large number of repeating memory cells (such as transistors or capacitors) arranged in a matrix of rows (word lines) and columns (bit lines), responsible for storing binary information in a high-density manner.

[0030] Understandably, referring to Figure 1 and Figure 2As shown, by providing multiple layers of memory array circuitry 10 on the same substrate, with each layer of memory array circuitry 10 corresponding to an independent control circuitry 20, compared to the traditional architecture where a single control circuitry 20 drives multiple memory arrays, the physical transmission distance between the memory array circuitry 10 and the corresponding control circuitry 20 can be significantly shortened. Furthermore, this effectively reduces parasitic parameters such as resistance and capacitance generated by interconnect lines, mitigating problems such as amplitude attenuation and noise rise of the sensing signal in long-distance transmission paths. This improves the signal readout reliability and performance of the memory chip. In addition, compared to the traditional architecture where the memory array circuitry 10 and control circuitry 20 are fabricated on two separate substrates and then bonded together, this integrated manufacturing method eliminates the need for complex bonding processes, resulting in a simpler process flow and lower mass production costs. The substrate can include a silicon-based substrate, such as a wafer, or a substrate formed from other semiconductor materials.

[0031] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2 As shown, the stacked structure includes multiple sets of stacked structures; wherein, one set of the stacked structures includes: a memory array circuit layer and a control circuit layer stacked along the vertical direction, the memory array circuit layer being located below the control circuit layer; in the stacked structure, the transistor channel material in the bottommost memory array circuit layer includes a first material or a second material, the transistor channel material in the remaining memory array circuit layers includes the first material, and the transistor channel material in all the control circuit layers includes a third material, wherein the first material, the second material, and the third material are different semiconductor materials.

[0032] It should be noted that, referring to Figure 1 and Figure 2 As shown, in a set of stacked structures 30, when the memory array circuit layer 10 is located below the control circuit layer 20; in the stacked structure 100, the transistor channel material in the bottommost memory array circuit layer 10 is a first material or a second material, the transistor channel material in the remaining memory array circuit layers 10 is a first material, and the transistor channel material in all control circuit layers includes a third material.

[0033] In some embodiments of this disclosure, the stacked structure includes multiple sets of stacked structures; wherein, one set of the stacked structures includes: a memory array circuit layer and a control circuit layer stacked along the vertical direction, the memory array circuit layer being located above the control circuit layer; in the stacked structure, the transistor channel material in the bottommost control circuit layer includes a second material or a third material, the transistor channel material in the remaining control circuit layers includes the third material, and the transistor channel material in all the memory array circuit layers includes a first material, wherein the first material, the second material, and the third material are different semiconductor materials.

[0034] It should be noted that in a stacked structure 30, when the memory array circuit layer 10 is located above the control circuit layer 20; in the stacked structure 100, the transistor channel material in the bottommost control circuit layer 20 is a second material or a third material, the transistor channel material in the remaining control circuit layers includes the third material, and the transistor channel material in all memory array circuit layers includes a first material; wherein, the preparation temperature of the first material is not higher than 450°C.

[0035] In some embodiments of this disclosure, the first material includes a metal oxide semiconductor material, the second material includes a silicon-based semiconductor material, and the third material includes a transition metal sulfide or a transition metal selenide.

[0036] It should be noted that the first material can specifically be indium gallium zinc oxide (IGZO). The second material can specifically be single-crystal silicon. The third material is a new material, specifically: molybdenum disulfide (MoS2), bismuth oxyselenide (Bi2O2Se), indium selenide (InSe), and tungsten diselenide (WSe2). It should also be noted that when using single-crystal silicon as the transistor channel material, the accompanying ion implantation, high-temperature activation annealing, and other complete process technologies are mature and standardized, offering strong process controllability, fewer process fluctuations and defects, and consistently achieving high device production yields.

[0037] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2 As shown, the memory array circuit layer 10 can be vertically divided into a first part and a second part; the first part is controlled by the control circuit layer 20 adjacent to it above, and the second part is controlled by the control circuit layer 20 adjacent to it below. This minimizes the physical transmission distance between the memory array circuit layer and the corresponding control circuit layer 20, thereby reducing parasitic parameters such as resistance and capacitance generated by the interconnect lines. This improves the signal read reliability and performance of the memory chip.

[0038] In some embodiments of this disclosure, reference is made to Figures 3 to 6As shown, the control circuit layer 20 includes a core circuit layer 21 and a peripheral circuit layer 22; the core circuit layer 21 is used at least to control the read and write operations of the memory array circuit; the peripheral circuit layer 22 is used at least to control the data communication, address decoding and timing management of the memory array circuit.

[0039] It should be noted that, referring to Figures 3 to 6 As shown, the core circuit layer 21 includes core circuitry, which mainly comprises modules such as bit line sense amplifiers (BLSA) and word line drivers (SWD). The BLSA senses and amplifies the weak charge signals in the memory cells, converting them into clear logic levels; the SWD selects and drives specific word lines to open the corresponding memory cell rows. Through these circuits closely integrated with the memory array, the core circuitry enables fast and precise access to the memory cells, making it the most critical front-end control component in the data read / write process.

[0040] It should also be noted that, referring to Figures 3 to 6 As shown, the peripheral circuit layer 22 includes peripheral circuits, which mainly include modules such as an address decoder, a data buffer, a clock generator, a voltage pump (charge pump), and command control logic. The decoder converts externally input addresses into row / column selection signals; the buffer temporarily stores data to be read or written and matches the external bus speed; the clock generator provides synchronization timing for the internal modules; the voltage pump generates the high voltage required for read, write, and erase operations (especially in flash memory); and the command control logic parses instructions from the host and coordinates the core circuitry, memory array, and other modules to operate sequentially. The peripheral circuits ensure that the memory chip can interact correctly with the external system and guarantee the orderly execution of internal operations.

[0041] In this embodiment of the disclosure, reference is made to Figure 3 and Figure 4 As shown, in a set of stacked structures 30, the core circuit layer 21 and the peripheral circuit layer 22 are stacked vertically; or, referring to... Figure 5 and Figure 6 As shown, in a set of stacked structures 30, the core circuit layer 21 and the peripheral circuit layer 22 are located on the same layer in the vertical direction.

[0042] It should be noted that, referring to Figures 3 to 6 As shown, the control circuit layer 20 can stack the core circuit layer 21 and the peripheral circuit layer 22 in the vertical direction according to application requirements, that is, manufacture them separately; at the same time, the core circuit layer 21 and the peripheral circuit layer 22 can also be set in the same layer, that is, manufacture them simultaneously.

[0043] In some embodiments of this disclosure, reference is made to Figure 3 and Figure 4 As shown, in a set of stacked structures 30, the storage array circuit layer 10 is located below the core circuit layer 21, and the peripheral circuit layer 22 is located above the core circuit layer 21; or, in a set of stacked structures 30, the peripheral circuit layer 22 is located below the core circuit layer 21, and the storage array circuit layer 10 is located above the core circuit layer 21.

[0044] It should be noted that, referring to Figure 3 As shown, in a stacked structure 30, when the memory array circuit layer 10 is located below the core circuit layer 21 and the peripheral circuit layer 22 is located above the core circuit layer 21; in the stacked structure 100, the transistor channel material in the bottommost memory array circuit layer 10 is a first material or a second material, and the transistor channel materials in the remaining memory array circuit layer 10, core circuit layer 21, and peripheral circuit layer 22 are a first material or a third material. The first material can be indium gallium zinc oxide (IGZO). The second material can be single-crystal silicon. The third material is a new material, specifically: molybdenum disulfide (MoS2), bismuth oxyselenide (Bi2O2Se), indium selenide (InSe), and tungsten diselenide (WSe2).

[0045] It should also be noted that, referring to Figure 4 As shown, in a set of stacked structures 30, when the peripheral circuit layer 22 is located below the core circuit layer 21 and the memory array circuit layer 10 is located above the core circuit layer 21; in the stacked structure 100, the transistor channel material in the bottommost peripheral circuit layer 22 is a first material or a second material, and the transistor channel material in the remaining memory array circuit layer 10, core circuit layer 21 and peripheral circuit layer 22 is the first material; wherein, the preparation temperature of the first material is not higher than 450°C.

[0046] In some embodiments of this disclosure, reference is made to Figure 7 As shown, the semiconductor structure also includes: a plurality of stacked structures 100; the plurality of stacked structures 100 are formed on different substrates and bonded to each other in the vertical direction.

[0047] It should be noted that, referring to Figure 7 As shown, by bonding multiple stacked structures 100 sequentially along the vertical direction, multi-layer functional array units can be integrated in the vertical dimension, avoiding process thermal budget conflicts and process interference caused by simultaneously fabricating multiple devices on a single substrate. At the same time, it effectively improves the integration density and total storage capacity of the array devices without increasing the chip planar area.

[0048] In some embodiments of this disclosure, reference is made to Figures 8 to 10As shown, the semiconductor structure also includes: in-memory computing (PIM) circuit 40; the in-memory computing circuit 40 is located in at least one of the control circuit layer 20, the core circuit layer 21, and the peripheral circuit layer 22, or simultaneously in the core circuit layer 21 and the peripheral circuit layer 22; the in-memory computing circuit 40 is configured to perform computational processing on data read from or written to the memory array circuit layer 10.

[0049] It should be noted that, referring to Figures 8 to 10 As shown, by introducing the in-memory computing circuit 40, the computing operation can be completed directly inside the control circuit layer 20, which greatly reduces the round-trip data transfer between the processor and the memory array circuit, thereby significantly reducing access latency and data path power consumption.

[0050] This disclosure also provides a method for fabricating a semiconductor structure, referring to... Figure 11 As shown, the method for fabricating the semiconductor structure includes steps S101-S102.

[0051] Step S101: Provide at least one substrate.

[0052] In this embodiment of the disclosure, reference is made to Figure 11 As shown, at least one substrate is provided. There is no specific limitation on the material of the substrate. As an example, the substrate can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure.

[0053] Step S102: Form a stacked structure 100 on the substrate; wherein the stacked structure 100 includes: a memory array circuit layer and a control circuit layer that are stacked alternately in a vertical direction.

[0054] In this embodiment of the disclosure, reference is made to Figure 1 , Figure 2 and Figure 11As shown, the memory array circuit layer 10 is configured to store data; the control circuit layer 20 is configured to control the read / write operations and data processing of the memory array circuit. By providing multiple memory array circuit layers 10 on the same substrate, each memory array circuit layer 10 is configured with an independent control circuit layer 20. Compared to the traditional architecture where a single control circuit layer 20 drives multiple memory arrays, this significantly shortens the physical transmission distance between the memory array circuit layer 10 and the corresponding control circuit layer 20. Furthermore, it effectively reduces parasitic parameters such as resistance and capacitance generated by interconnect lines, mitigating problems such as amplitude attenuation and noise rise of the sensing signal in long-distance transmission paths. This improves the signal read reliability and performance of the memory chip. In addition, compared to the traditional architecture where the memory array circuit layer 10 and control circuit layer 20 are fabricated on two separate substrates and then bonded together, this integrated manufacturing method eliminates the need for complex substrate bonding processes, resulting in a simpler process flow and lower mass production costs.

[0055] In some embodiments of this disclosure, reference is made to Figure 1 and Figure 2 As shown, the stacked structure 100 includes multiple stacked structures 30; wherein, one stacked structure 30 includes a memory array circuit layer 10 and a control circuit layer 20 stacked in the vertical direction. Figure 11 The specific steps of step S102 shown may include step S201.

[0056] Step S201: Form a stacked structure 100 on a substrate; wherein, in a set of stacked structures 30, the memory array circuit layer 10 is located below the control circuit layer 20; or, in a set of stacked structures 30, the memory array circuit layer 10 is located above the control circuit layer 20.

[0057] In this embodiment of the disclosure, reference is made to Figure 1 and Figure 2As shown, a stacked structure 100 is formed on a substrate. In a set of stacked structures 30, when the memory array circuit layer 10 is below the control circuit layer 20, the transistor channel material in the bottommost memory array circuit layer 10 is a first material or a second material, and the transistor channel material in the remaining memory array circuit layers 10 and control circuit layers 20 is the first material. In a set of stacked structures 30, when the memory array circuit layer 10 is above the control circuit layer 20, the transistor channel material in the bottommost control circuit layer 20 is a first material or a second material, and the transistor channel material in the remaining memory array circuit layers 10 and control circuit layers 20 is the first material; wherein, the fabrication temperature of the first material is not higher than 450°C. The first material can be indium gallium zinc oxide (IGZO). Specifically, the new material can be: molybdenum disulfide (MoS2), bismuth oxyselenide (Bi2O2Se), indium selenide (InSe), and tungsten diselenide (WSe2). The second material can be single-crystal silicon. It should also be noted that when using monocrystalline silicon as the transistor channel material, the complete set of processes such as ion implantation and high-temperature activation annealing are mature and standardized, with strong process controllability, few process fluctuation defects, and a stable high device production yield.

[0058] In some embodiments of this disclosure, reference is made to Figures 3 to 6 As shown, the control circuit layer 20 includes a core circuit layer 21 and a peripheral circuit layer 22; wherein, the core circuit layer 21 is used at least to control the read and write operations of the memory array circuit; and the peripheral circuit layer 22 is used at least to control the data communication, address decoding and timing management of the memory array circuit. Figure 11 The specific steps of step S102 shown may include step S301.

[0059] Step S301: Form a stacked structure 100 on a substrate; wherein, in a set of stacked structures 30, the core circuit layer 21 and the peripheral circuit layer 22 are stacked in the vertical direction; or, in a set of stacked structures 30, the core circuit layer 21 and the peripheral circuit layer 22 are located on the same layer in the vertical direction.

[0060] In this embodiment of the disclosure, reference is made to Figure 1 and Figure 2 As shown, a stacked structure 100 is formed on the substrate. The control circuit layer 20 can be configured within a set of stacked structures 30, as required by the application. Figure 3 and Figure 4 As shown, the core circuit layer 21 and the peripheral circuit layer 22 are stacked vertically, meaning they are manufactured separately; alternatively, they can also be manufactured in a set of stacked structures 30, referring to... Figure 5 and Figure 6 As shown, the core circuit layer 21 and the peripheral circuit layer 22 are set on the same layer, that is, they are manufactured at the same time.

[0061] In some embodiments of this disclosure, Figure 11 The specific steps of step S102 shown may include step S401.

[0062] Step S401: Form a stacked structure 100 on a substrate; wherein, in a set of stacked structures 30, the memory array circuit layer 10 is located below the core circuit layer 21 and the peripheral circuit layer 22 is located above the core circuit layer 21; or, in a set of stacked structures 30, the peripheral circuit layer 22 is located below the core circuit layer 21 and the memory array circuit layer 10 is located above the core circuit layer 21.

[0063] In this embodiment of the disclosure, reference is made to Figures 1 to 4 As shown, a stacked structure 100 is formed on a substrate. In one set of stacked structures 30, when the memory array circuit layer 10 is below the core circuit layer 21 and the peripheral circuit layer 22 is above the core circuit layer 21; in the stacked structure 100, the transistor channel material in the bottommost memory array circuit layer 10 is a first material or a second material, and the transistor channel materials in the remaining memory array circuit layer 10, core circuit layer 21, and peripheral circuit layer 22 are the first material (e.g., thin-film single-crystal silicon, MoS2, Bi2O2Se, InSe, WSe2). The first material can be indium gallium zinc oxide (IGZO). The second material can be single-crystal silicon. In a stacked structure 30, when the peripheral circuit layer 22 is located below the core circuit layer 21 and the memory array circuit layer 10 is located above the core circuit layer 21; in the stacked structure 100, the transistor channel material in the bottommost peripheral circuit layer 22 is a first material or a second material, and the transistor channel material in the remaining memory array circuit layer 10, core circuit layer 21 and peripheral circuit layer 22 is the first material; wherein, the preparation temperature of the first material is not higher than 450°C.

[0064] In some embodiments of this disclosure, in Figure 11 Following step S102, the semiconductor structure fabrication method further includes steps S501-S502.

[0065] Step S501: Provide multiple substrates.

[0066] In this embodiment of the disclosure, reference is made to Figure 1 and Figure 2 As shown, multiple substrates are provided; wherein a stacked structure 100 is formed on each substrate.

[0067] Step S502: Bond multiple substrates along the vertical direction using a hybrid bonding process.

[0068] In this embodiment of the disclosure, reference is made to Figure 7As shown, multiple substrates are bonded vertically using a hybrid bonding process, resulting in multiple stacked structures 100. Hybrid bonding is a bumpless bonding process. Two substrates are used to fabricate dielectric layers and embedded copper pads, respectively. After planarization and activation, they are aligned, bonded, and subjected to low-temperature annealing. The dielectric and copper pads are bonded simultaneously, achieving mechanical fixation and electrical interconnection at the same interface, realizing high-density vertical interconnection. By sequentially bonding multiple stacked structures 100 vertically, multi-layer functional array units can be integrated in the vertical dimension, avoiding process thermal budget conflicts and process interference caused by simultaneously fabricating multiple devices on a single substrate. Simultaneously, without increasing the chip planar area, the integration density and total storage capacity of the array devices are effectively improved.

[0069] Based on the same inventive concept, this disclosure also provides an electronic device, which includes a semiconductor structure as described in any of the above embodiments, or a semiconductor structure manufactured according to the preparation method of the semiconductor structure in any of the above embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0070] It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments of this application are merely for description and do not represent the superiority or inferiority of the embodiments. It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0071] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0072] The above are merely specific implementations of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes: at least one stacked structure; The stacked structure, formed on the same substrate, includes: a memory array circuit layer and a control circuit layer that are stacked alternately in a vertical direction; The storage array circuit layer is configured to store data at least; The control circuit layer is configured at least to control the read and write operations and data processing of the storage array circuit.

2. The semiconductor structure according to claim 1, characterized in that, The stacked structure includes multiple sets of stacked structures; wherein each set of stacked structures includes: a memory array circuit layer and a control circuit layer stacked along the vertical direction, with the memory array circuit layer located below the control circuit layer; In the stacked structure, the transistor channel material in the bottommost memory array circuit layer includes a first material or a second material, the transistor channel material in the remaining memory array circuit layers includes the first material, and the transistor channel material in all the control circuit layers includes a third material. The first material, the second material, and the third material are different semiconductor materials.

3. The semiconductor structure according to claim 1, characterized in that, The stacked structure includes multiple sets of stacked structures; wherein each set of stacked structures includes: a memory array circuit layer and a control circuit layer stacked along the vertical direction, with the memory array circuit layer located above the control circuit layer; In the stacked structure, the transistor channel material in the bottommost control circuit layer includes a second material or a third material, the transistor channel material in the remaining control circuit layers includes the third material, and the transistor channel material in all the memory array circuit layers includes a first material. The first material, the second material, and the third material are different semiconductor materials.

4. The semiconductor structure according to claim 2 or 3, characterized in that, The first material includes a metal oxide semiconductor material, the second material includes a silicon-based semiconductor material, and the third material includes a transition metal sulfide or a transition metal selenide.

5. The semiconductor structure according to claim 1, characterized in that, The storage array circuit layer is divided into a first part and a second part along the vertical direction; The first part is controlled by the control circuit layer above it, and the second part is controlled by the control circuit layer below it.

6. The semiconductor structure according to claim 2 or 3, characterized in that, The control circuit layer includes: a core circuit layer and a peripheral circuit layer; The core circuit layer is used at least to control the read and write operations of the storage array circuit. The peripheral circuit layer is at least used to control the data communication, address decoding and timing management of the memory array circuit. In each set of the stacked structures, the core circuit layer and the peripheral circuit layer are stacked along the vertical direction.

7. The semiconductor structure according to claim 6, characterized in that, In each of the aforementioned stacked structures, the memory array circuit layer is located below the core circuit layer, and the peripheral circuit layer is located above the core circuit layer; or... In each of the aforementioned stacked structures, the peripheral circuit layer is located below the core circuit layer, and the memory array circuit layer is located above the core circuit layer.

8. The semiconductor structure according to claim 2 or 3, characterized in that, The semiconductor structure further includes: a plurality of stacked structures; the plurality of stacked structures are formed on different substrates and bonded to each other along the vertical direction.

9. The semiconductor structure according to claim 6, characterized in that, The semiconductor structure also includes: in-memory computing circuitry; The in-memory computing circuit is located in at least one of the control circuit layer, the core circuit layer, and the peripheral circuit layer; The in-memory computing circuit is configured to perform computational processing on the data read from or written to the memory array circuit layer.

10. A method for fabricating a semiconductor structure, characterized in that, The method for preparing the semiconductor structure includes: Provide at least one substrate; A stacked structure is formed on the substrate; wherein the stacked structure includes: a memory array circuit layer and a control circuit layer that are stacked alternately in a vertical direction; the memory array circuit layer is configured at least to store data; and the control circuit layer is configured at least to control the read and write operations and data processing of the memory array circuit.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The stacked structure includes multiple sets of stacked structures; wherein each set of stacked structures includes: a memory array circuit layer and a control circuit layer stacked along the vertical direction; the memory array circuit layer is located below the control circuit layer, or the memory array circuit layer is located above the control circuit layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The control circuit layer includes a core circuit layer and a peripheral circuit layer; wherein, the core circuit layer is used at least to control the read and write operations of the memory array circuit; and the peripheral circuit layer is used at least to control the data communication, address decoding, and timing management of the memory array circuit. The core circuit layer and the peripheral circuit layer are stacked along the vertical direction; or, the core circuit layer and the peripheral circuit layer are located on the same layer along the vertical direction.

13. The method for preparing a semiconductor structure according to any one of claims 10-12, characterized in that, The method for preparing the semiconductor structure further includes: A plurality of said substrates are provided, and the stacked structure is formed on each said substrate; Multiple substrates are bonded along the vertical direction using a hybrid bonding process.

14. An electronic device, characterized in that, It includes the semiconductor structure as described in any one of claims 1 to 9, or the semiconductor structure formed by the method of preparing the semiconductor structure according to any one of claims 10 to 13.

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