Floating gate resistance structure in NAND flash memory

Abstract

This invention discloses a floating gate resistor structure in NAND flash memory, comprising two or more parallel floating gate polysilicon strands on the top surface of first active regions with aligned length edges. A control gate dielectric layer and first and second lead-out regions (with the control gate dielectric layer removed) are formed on the top surface of each floating gate polysilicon strand. The resistance of the floating gate polysilicon strand between the first and second lead-out regions serves as a floating gate sub-resistor. A control gate conductive material layer covers all first active regions within the region where the floating gate resistor is formed. Between each first active region, the control gate conductive material layer has lateral control gate cut-off regions that laterally divide the control gate conductive material layer. At least one longitudinal control gate cut-off region is formed in the region between the first and second lead-out regions, and the control gate conductive material layers contacting the first and second lead-out regions respectively form the first and second control gate leads. The floating gate sub-resistors are connected in series to form the floating gate resistor. This invention saves chip area.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a floating gate resistor structure in NAND flash memory. Background Technology

[0002] NAND flash memory, as the most mainstream type of memory, accounts for over 90% of the non-volatile memory market. NAND flash memory primarily uses a serial structure to perform NAND calculations, enabling a more compact storage structure. Due to its high storage density and low cost, it is widely used in USB flash drives, SD cards, SSDs, mobile devices, embedded systems, and more. In recent years, with the rise and development of the mobile internet, big data, and cloud storage markets, as well as the robust development of technologies such as AI, VR, and 5G, the NAND flash memory market has experienced rapid growth.

[0003] In NAND flash memory circuits, cells are organized into pages, blocks, and planes. A page is the unit for simultaneous programming and reading operations, while a block is the smallest erasable unit composed of multiple pages. Because a single etching scheme is used when entering small NAND cells, the ONO layer, which serves as the control gate dielectric layer, needs to be removed using an ONO etching process to bring out the ground select (GSL) and string select (SSL) transistors, thus connecting the control gate to the polysilicon of the floating gate.

[0004] Meanwhile, since the control gate uses self-align double patterning (SADP) technology, it needs to be truncated at the top and bottom after formation. Currently, the control gate truncation (POC) layer is used, which can stop at the top of the dielectric layer (ONO) to cut off the control gate and retain the floating gate.

[0005] like Figure 1 The diagram shown is a schematic diagram of the planar structure of existing NAND flash memory; Figure 2 It is along Figure 1 A cross-sectional structural diagram of the dashed line AA; existing NAND flash memory includes: storage cells 114a and a storage array formed by arranging the storage cells 114a.

[0006] The first gate structure 102a of the memory cell 114a includes a tunneling dielectric layer 104, a floating gate polysilicon 105, a control gate dielectric layer 106, and a control gate polysilicon 107 formed on a semiconductor substrate 101.

[0007] Typically, the control gate dielectric layer 106 is an ONO layer, which includes a first oxide layer, a second nitride layer, and a third oxide layer. The second nitride layer is formed on the top surface of the first oxide layer, and the third oxide layer is formed on the top surface of the second nitride layer.

[0008] The storage array includes a storage cell string 115 consisting of multiple storage cells connected in series.

[0009] Each memory cell 114a of the memory cell string 115 is located between an N-type heavily doped first source region 103a and an N-type heavily doped first drain region 103b. The first source region 103a is connected to an N-type heavily doped common source region 103c via a first select transistor 114b, i.e., a ground select transistor. An active contact hole 111a is formed on the top of the common source region 103c and connected to the source line SL composed of the front metal layer 112. The first drain region 103b is connected to an N-type heavily doped common drain region 103d via a second select transistor 114c, i.e., a series select transistor. The common drain region 103d is connected to the bit line BL composed of the front metal layer 112 via a top drain contact hole 111b.

[0010] The second gate structure 102b of the first selector 114b includes the tunneling dielectric layer 104, the floating gate polysilicon 105, the control gate dielectric layer 106, and the control gate polysilicon 107 formed on the semiconductor substrate 101; the second gate structure 102b also has a first gate connection region 106a, in which the control gate dielectric layer 106 is removed and the floating gate polysilicon 105 and the control gate polysilicon 107 are in contact.

[0011] The third gate structure 102c of the second selector 114c has the same structure as the second gate structure 102b.

[0012] In the storage array, the storage cell strings 115 on the same row are aligned and arranged; the storage cell strings 115 on the same column are aligned and arranged to form storage pages 116.

[0013] In the column direction, the storage cells 114a on the same column are aligned and the first selection tubes 114b are aligned.

[0014] The control gate polysilicon 107 reserved by each of the first select transistors 114b are connected together to form the first select transistor gate line SGs. Figure 1The top view, i.e., the planar structure, of the first gate structure 102a, the second gate structure 102b, and the third gate structure 102c shown is the top view structure of the control gate polysilicon 107. The first gate connection region 106a extends along the column direction and is strip-shaped, and the source contact hole 111a extends along the column direction and is strip-shaped.

[0015] The control gate polysilicon 107 of each of the second select transistors 114c are connected together to form a second select transistor gate line SGd. The first select transistor gate line SGs is led out through the front metal layer 112 to form a ground select line. The second select transistor gate line SGd is led out through the front metal layer 112 to form a series select line.

[0016] Figure 2 The top view structure corresponding to the shared source line SL shown in the figure and Figure 1 The source contact hole 111a is parallel to and located at the top of the source contact hole 111a.

[0017] The storage array includes multiple rows of bit lines BL. The shared drain area 103d is shared by two adjacent storage cell strings 115, and the bit lines BL in the same row are connected to the multiple shared drain areas 103d. Figure 1 In the process, each row of memory cell strings 115 is formed in an active region formed by the semiconductor substrate 101, each active region having a strip structure, and the bit line BL is parallel to the active region corresponding to each memory cell string 115.

[0018] In the column direction, the control gate polysilicon 107 of each of the aligned memory cells 114a is connected together to form a cell control gate line and the cell control gate line extends along the column direction to the outside of the memory array. On both sides of the extension of each cell control gate line to the outside of the memory array, there are control gate cut-off regions 113. The control gate polysilicon 107 in the control gate cut-off region 113 is removed and stops on the control gate dielectric layer 106.

[0019] At both ends of each of the memory pages 116 in the column direction, the control gate cut-off regions 113 corresponding to each of the cell control gate lines are connected together and form a strip parallel to the row direction. After being cut off, each of the cell control gate lines is connected to the corresponding word line, i.e., WL, through the corresponding front metal layer 112 at the top.

[0020] like Figure 2As shown, in each of the memory cell strings 115, N-type heavily doped cell connection regions 103 are self-aligned and formed in the semiconductor substrate 101 between each of the first gate structures 102a. For each memory cell 114, the cell connection regions 103 on both sides of the first gate structure 102a serve as the source or drain regions of the memory cell 114. The first source region 103a and the first drain region 103b also belong to the cell connection regions 103, but are marked separately.

[0021] Sidewalls 108 are formed on the side surfaces of each of the first gate structures 102a and the second gate structures 102b, and the sidewalls 108 completely fill the gap between each of the first gate structures 102a and the gap between the first gate structure 102a and the second gate structure 102b.

[0022] The dielectric layer 109a in the spacer region between the second gate structures 102c at the top of the common source region 103c and the dielectric layer 109b in the spacer region between the third gate structures 102c at the top of the common drain region 103d are composed of the interlayer film 110. Both the source contact via 111a and the drain contact via 111b pass through the interlayer film 110.

[0023] NAND circuits require different voltages, necessitating stable resistors to regulate these voltages. Currently, the primary method uses resistors with floating gate polysilicon. These resistors are formed by removing the ONO layer, creating a connection to the upper control gate and facilitating the connection of contact holes. However, the distance between the two resistors in this structure is currently limited by the design rules of the control gate (CG), resulting in a significant increase in chip area when using this type of resistor. Further explanation follows: like Figure 3 The diagram shown is a planar structural schematic of the floating gate resistor structure in existing NAND flash memory. Figure 4 yes Figure 3 A schematic diagram of the three-dimensional structure at point 207 within the dashed box; Figure 5 It is along Figure 3 A cross-sectional view of line AA in the diagram; In the existing NAND flash memory floating gate resistor structure, the formation region of the floating gate resistor includes two or more parallel first active regions (not shown).

[0024] A tunneling dielectric layer (not shown) and a floating gate polysilicon 201 are sequentially formed on the top surface of the first active region. The length side of the floating gate polysilicon 201 is aligned with the length side of the first active region. That is, in the planar structure, the floating gate polysilicon 201 is located directly above the first active region. Along the width direction of the floating gate polysilicon 201, the formation region of the floating gate resistor is located between the dashed lines corresponding to the two ends of the width d105. It can be seen that the formation region of the floating gate resistor includes two floating gate polysilicon 201s, and therefore also includes two of the first active regions. The following description will use the example of the formation region of the floating gate resistor including two floating gate polysilicon 201s.

[0025] The first active region consists of a semiconductor substrate (not shown) surrounded by shallow trench isolation (not shown).

[0026] A control gate dielectric layer 208 is formed on the top surface of each of the floating gate polysilicon 201. A first lead-out region 202a and a second lead-out region 202b are also provided on the top surface of each of the floating gate polysilicon 201. The control gate dielectric layer 208 in the first lead-out region 202a and the second lead-out region 202b are removed. The resistance of the floating gate polysilicon 201 in the region 202c between the first lead-out region 202a and the second lead-out region 202b is used as a floating gate sub-resistor.

[0027] The control gate dielectric layer 208 is an ONO layer, which includes a first oxide layer 208a, a second nitride layer 208b, and a third oxide layer 208c stacked sequentially.

[0028] A strip-shaped control gate conductive material layer 203 is formed on top of each of the first active regions. The strip-shaped structure of the control gate conductive material layer 203 is formed by patterned etching. The length direction of the control gate conductive material layer 203 is along the length direction of the first active region. In the first lead-out region 202a and the second lead-out region 202b, the control gate conductive material layer 203 is in contact with the floating gate polysilicon 201; outside the first lead-out region 202a and the second lead-out region 202b, the control gate conductive material layer 203 is located on the top surface of the control gate dielectric layer 208. The structure of the control gate dielectric layer 208 is shown in [reference needed]. Figure 5 As shown.

[0029] Two longitudinal control gate truncated regions 204 are formed in the region between the first lead-out region 202a and the second lead-out region 202b to truncate the strip-shaped control gate conductive material layer 203. The control gate conductive material layer 203 in the longitudinal control gate truncated regions 204 is removed, and the control gate conductive material layer 203 is divided along its length. The control gate conductive material layer 203 in contact with the corresponding first lead-out region 202a forms the first control gate lead-out end, and the control gate conductive material layer 203 in contact with the corresponding second lead-out region 202b forms the second control gate lead-out end.

[0030] The tops of each of the first control gate leads and each of the second control gate leads are connected to a metal interconnect structure composed of a front metal layer 206 through contact holes 205. The metal interconnect structure connects each of the floating gate resistors in series to form the floating gate resistor. Figure 5 In the process, the second control gate leads of the two floating gate resistors are connected through the metal wire, and the first control gate leads of the two floating gate resistors are respectively led out to the first resistor terminal and the second resistor terminal. Figure 5 Only the front metal layer 206 corresponding to the metal interconnect is shown in the image.

[0031] The material of the control gate conductive material layer 203 includes polycrystalline silicon.

[0032] like Figure 3 As shown, the spacing d101 between the conductive material layers 203 of the control gate is greater than or equal to the minimum distance of the control gate specified by the design rules.

[0033] The distance d102 between the outer length side of each of the first active regions and the corresponding length side in the control gate conductive material layer 203 is greater than or equal to the minimum distance of the control gate surrounding the active region as specified by the design rules.

[0034] Figure 3 The width d103 of the floating gate polysilicon 201 is also shown.

[0035] It can be seen that the width d105 of the region where the floating gate resistor is formed is d101 + 4 * d102 + 2 * d103.

[0036] The spacing between the floating gate polysilicon 201 is d104, where d104 is d101 + 2 * d102.

[0037] Figure 5 The floating gate resistor structure shown can and Figure 2The NAND flash memory cells shown are integrated together to form the structure. The tunneling dielectric layer, the floating gate polysilicon 201, the control gate dielectric layer 208, and the control gate conductive material layer 203 corresponding to the floating gate resistor structure can be combined with... Figure 2 The tunneling dielectric layer 104, floating gate polysilicon 105, control gate dielectric layer 106, and control gate conductive material layer 107 shown are formed simultaneously using the same process. In existing processes, Figure 2 The control gate conductive material layer 107 shown and Figure 5 The control gate conductive material layer 203 shown is simultaneously etched to form a strip structure, and then the strip structure is truncated by the control gate. However, in the patterned etching of the strip structure of the control gate conductive material layer 203, d101 needs to be constrained by design rules, which ultimately makes d105 larger, and the area of ​​the floating gate resistor formation region will be larger. Figure 5 The width W101 of the floating gate resistor corresponding to region 202c is also shown. Summary of the Invention

[0038] The technical problem to be solved by the present invention is to provide a floating gate resistor structure in NAND flash memory that can eliminate the limitation of control gate design rules on the size reduction of floating gate resistor, thereby reducing the space occupied by the floating gate resistor, saving chip area, and without the need to add new process structures and masks.

[0039] To solve the above-mentioned technical problems, the floating gate resistor structure in the NAND flash memory provided by the present invention includes two or more parallel-arranged first active regions in the formation region of the floating gate resistor.

[0040] A tunneling dielectric layer and a floating gate polysilicon are sequentially formed on the top surface of the first active region, and the long side of the floating gate polysilicon is aligned with the long side of the first active region.

[0041] A control gate dielectric layer is formed on the top surface of each of the floating gate polysilicon. A first lead-out region and a second lead-out region are also provided on the top surface of each of the floating gate polysilicon. The control gate dielectric layer in the first lead-out region and the second lead-out region are removed. The resistance of the floating gate polysilicon between the first lead-out region and the second lead-out region is a floating gate sub-resistor.

[0042] The control gate conductive material layer covers all the first active regions in the formation region of the floating gate resistor; the length direction of the control gate conductive material layer is along the length direction of the first active regions, and the control gate conductive material layer is in contact with the floating gate polysilicon in the first lead-out region and the second lead-out region; outside the first lead-out region and the second lead-out region, the control gate conductive material layer is located on the top surface of the control gate dielectric layer.

[0043] Between each of the first active regions, the control gate conductive material layer has a lateral control gate cut-off region, in which the control gate conductive material layer is removed, such that the control gate conductive material layer remaining on both sides of the lateral control gate cut-off region is divided into multiple strips in the width direction.

[0044] At least one longitudinal control gate cut-off region is formed in the region between the first lead-out region and the second lead-out region. The control gate conductive material layer in the longitudinal control gate cut-off region is removed and the control gate conductive material layer is divided in the length direction. The control gate conductive material layer that contacts the corresponding first lead-out region forms the first control gate lead-out end, and the control gate conductive material layer that contacts the corresponding second lead-out region forms the second control gate lead-out end.

[0045] The tops of each of the first control gate leads and each of the second control gate leads are connected to a metal interconnect structure composed of a front metal layer through contact holes. The metal interconnect structure connects each of the floating gate resistors in series to form the floating gate resistor.

[0046] A further improvement is that the first active region is composed of a semiconductor substrate with shallow trench isolation surrounding its periphery.

[0047] A further improvement is that the semiconductor substrate is made of silicon.

[0048] A further improvement is that the material of the control gate conductive material layer includes polycrystalline silicon.

[0049] A further improvement is that the spacing between the first active regions is greater than or equal to the minimum distance between active regions specified in the design rules.

[0050] In the formation region of the floating gate resistor, the distance between the outermost two outer length sides of the first active regions and the corresponding length side in the control gate conductive material layer is greater than or equal to the minimum distance of the control gate surrounding the active region as specified by the design rules.

[0051] A further improvement is that the metal interconnect structure connecting the floating gate resistors in series includes: a first resistor terminal, a second resistor terminal, and a metal wire located between the first resistor terminal and the second resistor terminal to connect adjacent floating gate resistors in series.

[0052] The first control gate leads of each of the two outermost floating gate resistors located between the two outermost floating gate resistors are connected to the first control gate leads of the floating gate resistors on one side via the metal wire, and the second control gate leads of each of the floating gate resistors are connected to the second control gate leads of the floating gate resistors on the other side via the metal wire, forming a serpentine connection structure.

[0053] One of the two outermost floating gate resistors that is not connected to the metal wire is connected to the first resistor terminal and the other is connected to the second resistor terminal.

[0054] A further improvement is that the material of the tunneling medium layer includes an oxide layer.

[0055] A further improvement is that the control gate dielectric layer is an ONO layer, which includes a first oxide layer, a second nitride layer and a third oxide layer stacked sequentially.

[0056] A further improvement is that the gate structure of the NAND flash memory cell includes the tunneling dielectric layer, the floating gate polysilicon, the control gate dielectric layer and the control gate conductive material layer stacked in sequence, wherein the floating gate polysilicon and the control gate conductive material layer are isolated by the control gate dielectric layer.

[0057] The process structures of the tunneling dielectric layer, the floating gate polysilicon, the control gate dielectric layer, and the control gate conductive material layer of the gate structure are the same as those of the tunneling dielectric layer, the floating gate polysilicon, the control gate dielectric layer, and the control gate conductive material layer corresponding to the floating gate resistor, and are formed simultaneously.

[0058] A further improvement is that, in the NAND flash memory storage array, the control gate conductive material layers of the storage cells in the same column are connected together to form a control gate strip.

[0059] The control gate strip has a third control gate cutoff region at both ends, in which the control gate conductive material layer is removed.

[0060] The third control gate cutoff region, the lateral control gate cutoff region, and the longitudinal control gate cutoff region are defined using the same mask and share the same control gate cutoff process.

[0061] Along the strip-shaped extension direction of the floating gate resistors composed of polysilicon floating gates, the top control gate conductive material layer does not need to initially form a strip structure corresponding one-to-one with the strips of the floating gate resistors. Instead, based on forming all the first active regions covering the formation area of ​​the floating gate resistors, a transverse control gate cutoff region is set between each of the first active regions to achieve the segmentation of the control gate conductive material layer in the width direction, thereby achieving a strip structure corresponding one-to-one with the strips of the floating gate resistors. At the same time, a longitudinal control gate cutoff region is retained to longitudinally segment the strip structure of each control gate conductive material layer, wherein the transverse control gate cutoff region is set... This design allows the width dimension of the floating gate resistor formation area to be unrestricted by the control gate design rules corresponding to the spacing between the strip structures of the control gate conductive material layer. Only the design rules for the active region spacing need to be met. Therefore, the width dimension of the floating gate resistor formation area can be reduced, thereby reducing the space occupied by the floating gate resistor and saving chip area. Furthermore, in this invention, the added lateral control gate cutoff region can be formed simultaneously with the longitudinal control gate cutoff region using the same mask and the same process, such as etching. Therefore, this invention does not require additional process structures or masks, and it also has the advantage of low process cost. Attached Figure Description

[0062] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments: Figure 1 This is a schematic diagram of the planar structure of existing NAND flash memory; Figure 2 It is along Figure 1 A schematic diagram of the cross-sectional structure of the dashed line AA; Figure 3 This is a schematic diagram of the planar structure of the floating gate resistor in existing NAND flash memory; Figure 4 yes Figure 3 A schematic diagram of the three-dimensional structure at point 207 within the dashed box; Figure 5 It is along Figure 3 A schematic diagram of the cross-sectional structure at line AA in the middle; Figure 6 This is a schematic diagram of the planar structure of the floating gate resistor structure in the NAND flash memory according to an embodiment of the present invention; Figure 7 yes Figure 6 A schematic diagram of the three-dimensional structure at point 307 within the dashed box; Figure 8 It is along Figure 6 A schematic diagram of the cross-sectional structure at line AA in the diagram. Detailed Implementation

[0063] like Figure 6The diagram shown is a planar structural schematic of the floating gate resistor structure in a NAND flash memory according to an embodiment of the present invention. Figure 7 yes Figure 6 A schematic diagram of the three-dimensional structure at point 307 within the dashed box; Figure 8 It is along Figure 6 A cross-sectional structural diagram at line AA in the figure; In the floating gate resistor structure of the NAND flash memory in this embodiment of the invention, the formation region of the floating gate resistor includes two or more parallel first active regions (not shown).

[0064] A tunneling dielectric layer (not shown) and a floating gate polysilicon 301 are sequentially formed on the top surface of the first active region. The length side of the floating gate polysilicon 301 is aligned with the length side of the first active region. That is, in the planar structure, the floating gate polysilicon 301 is located directly above the first active region. Along the width direction of the floating gate polysilicon 301, the formation region of the floating gate resistor is located between the dashed lines corresponding to the two ends of the width d204. It can be seen that the formation region of the floating gate resistor includes two floating gate polysilicon 301s, and therefore also includes two of the first active regions. In the embodiments of the present invention, the example of the formation region of the floating gate resistor including two floating gate polysilicon 301s is used for illustration.

[0065] In this embodiment of the invention, the first active region is composed of a semiconductor substrate (not shown) surrounded by shallow trench isolation (not shown) on its periphery.

[0066] The semiconductor substrate is made of silicon.

[0067] The material of the tunneling medium layer includes an oxide layer.

[0068] A control gate dielectric layer 208 is formed on the top surface of each of the floating gate polysilicon 301. A first lead-out region 302a and a second lead-out region 302b are also provided on the top surface of each of the floating gate polysilicon 301. The control gate dielectric layer 208 in the first lead-out region 302a and the second lead-out region 302b are removed. The resistance of the floating gate polysilicon 301 in the region 302c between the first lead-out region 302a and the second lead-out region 302b is used as a floating gate sub-resistor.

[0069] In this embodiment of the invention, the control gate dielectric layer 208 is an ONO layer, which includes a first oxide layer 208a, a second nitride layer 208b, and a third oxide layer 208c stacked sequentially.

[0070] The control gate conductive material layer 303 covers all the first active regions in the formation region of the floating gate resistor; the length direction of the control gate conductive material layer 303 is along the length direction of the first active regions, and in the first lead-out region 302a and the second lead-out region 302b, the control gate conductive material layer 303 is in contact with the floating gate polysilicon 301; outside the first lead-out region 302a and the second lead-out region 302b, the control gate conductive material layer 303 is located on the top surface of the control gate dielectric layer 208. The structure of the control gate dielectric layer 208 is shown in [reference needed]. Figure 8 As shown.

[0071] Between each of the first active regions, the control gate conductive material layer 303 has a lateral control gate cut-off region 304b, in which the control gate conductive material layer 303 in the lateral control gate cut-off region 304b is removed, such that the control gate conductive material layer 303 remaining on both sides of the lateral control gate cut-off region 304b is divided into multiple strips in the width direction.

[0072] At least one longitudinal control gate cut-off region 304a is formed in the region between the first lead-out region 302a and the second lead-out region 302b. The control gate conductive material layer 303 in the longitudinal control gate cut-off region 304a is removed and the control gate conductive material layer 303 is divided in the length direction. The control gate conductive material layer 303 that contacts the corresponding first lead-out region 302a forms the first control gate lead-out end, and the control gate conductive material layer 303 that contacts the corresponding second lead-out region 302b forms the second control gate lead-out end.

[0073] The tops of each of the first control gate leads and each of the second control gate leads are connected to a metal interconnect structure composed of a front metal layer 306 through contact holes 305. The metal interconnect structure connects each of the floating gate resistors in series to form the floating gate resistor.

[0074] In this embodiment of the invention, the material of the control gate conductive material layer 303 includes polycrystalline silicon.

[0075] like Figure 6 As shown, the spacing d201 between the first active regions is greater than or equal to the minimum distance between active regions specified by the design rules.

[0076] In the formation region of the floating gate resistor, the distance d203 between the outermost two outer length sides of the first active regions and the corresponding length sides in the control gate conductive material layer 303 is greater than or equal to the minimum distance of the control gate surrounding the active region as specified by the design rules.

[0077] Figure 6The width d202 of the floating gate polysilicon 301 is also shown.

[0078] It can be seen that the width d204 of the region where the floating gate resistor is formed is d201+2*d202+2*d203.

[0079] and Figure 3 Compared to the width d105, d102 is equal to d203, d103 is equal to d202, and d104 corresponds to d201 in the embodiment of the present invention. However, d104 is d101+2*d102, which is greater than d101. Therefore, d204 in the embodiment of the present invention is reduced.

[0080] The following uses specific parameters as an example to further illustrate the size reduction in an embodiment of the present invention: The distances between the control gate and the active region, i.e., d102 and d203, are the same, such as 0.294 micrometers; The resistor widths, d103 and d202, are the same, for example, 0.350 micrometers; The control gate distance is d101. Figure 6 There is no control gate distance; d101 is, for example, 0.3 micrometers; The active region distances are d104 and d201, which are different. d104 is d101 + 2 * d102, and can be calculated to be 0.888 micrometers; d201 is, for example, 0.25 micrometers.

[0081] The total width of the resistors, d105 and d204, are different. Calculations show that d105 is 2.176 micrometers and d204 is 1.798 micrometers.

[0082] As can be seen, the embodiments of the present invention improve upon the existing control gate distance limitation by using a whole-piece control gate, thereby reducing the total resistor width by 17%. Additionally, it should be noted that the lateral control gate cutoff region 304b of the gate cut layer, i.e., the distance from the ONO layer, meets the rules.

[0083] In embodiments of the present invention, such as Figure 8 As shown, the metal interconnect structure connecting the floating gate resistors in series includes: a first resistor terminal (not shown), a second resistor terminal (not shown), and a metal wire located between the first resistor terminal and the second resistor terminal, connecting adjacent floating gate resistors in series. Figure 8 Only the front metal layer 206 corresponding to the metal interconnect is shown in the image.

[0084] The first control gate leads of each of the two outermost floating gate resistors located between the two outermost floating gate resistors are connected to the first control gate leads of the floating gate resistors on one side via the metal wire, and the second control gate leads of each of the floating gate resistors are connected to the second control gate leads of the floating gate resistors on the other side via the metal wire, forming a serpentine connection structure.

[0085] One of the two outermost floating gate resistors, which is not connected to the metal connection, is connected to the first resistor terminal and the other is connected to the second resistor terminal. Because... Figure 6 Only two of the first active regions are shown. It can be seen that the second control gate leads of the two floating gate resistors are connected through the metal wire, and the first control gate leads of the two floating gate resistors are respectively led out to the first resistor terminal and the second resistor terminal.

[0086] In this embodiment of the invention, the gate structure of the NAND flash memory cell includes the tunneling dielectric layer, the floating gate polysilicon 301, the control gate dielectric layer 208, and the control gate conductive material layer 303 stacked sequentially. The floating gate polysilicon 301 and the control gate conductive material layer 303 are isolated by the control gate dielectric layer 208. In this application, the structure of the NAND flash memory can adopt... Figure 1 and Figure 2 The existing structure is implemented, for example: the tunneling dielectric layer, the floating gate polysilicon 301, the control gate dielectric layer 208, and the control gate conductive material layer 303 included in the gate structure of the NAND flash memory in the embodiments of the present invention can be respectively adopted Figure 2 The tunneling dielectric layer 104, floating gate polysilicon 105, control gate dielectric layer 106, and control gate conductive material layer 107 shown are implemented.

[0087] The process structures of the tunneling dielectric layer, the floating gate polysilicon 301, the control gate dielectric layer 208, and the control gate conductive material layer 303 of the gate structure are the same as those of the tunneling dielectric layer, the floating gate polysilicon 301, the control gate dielectric layer 208, and the control gate conductive material layer 303 corresponding to the floating gate resistor, and are formed simultaneously.

[0088] In this embodiment of the invention, in the NAND flash memory storage array, the control gate conductive material layers 303 of the storage cells in the same column are connected together to form a control gate strip. Please refer to [reference needed for the planar structure of the control gate strip]. Figure 1 The first gate structure 102a in the planar structure.

[0089] The control gate strip has third control gate cut-off regions at both ends, in which the control gate conductive material layer 303 is removed. Please refer to [reference needed] for the third control gate cut-off region. Figure 1 As can be seen from the control gate cutoff region 113, the control gate cutoff region 113 is also a longitudinal cutoff of the strip structure, i.e., the control gate strip. There is no structure in the existing process that laterally cuts off the control gate strip.

[0090] The third control gate cutoff region, the lateral control gate cutoff region 304b, and the longitudinal control gate cutoff region 304a are defined using the same mask and share the same control gate cutoff process. Therefore, in this embodiment of the invention, the lateral control gate cutoff region 304b does not increase the cost, but it can effectively reduce the chip width and ultimately reduce the chip area.

[0091] Along the strip-shaped extension direction of the floating gate resistors composed of each floating gate polysilicon 301, the top control gate conductive material layer 303 does not need to initially form a strip structure corresponding one-to-one with the strips of the floating gate resistors. Instead, based on forming all the first active regions covering the formation area of ​​the floating gate resistors, by setting transverse control gate cut-off regions 304b between each first active region, the control gate conductive material layer 303 can be divided in the width direction, thereby achieving a strip structure corresponding one-to-one with the strips of the floating gate resistors; at the same time, the longitudinal control gate cut-off region 304a, which longitudinally divides the strip structure of each control gate conductive material layer 303, is retained, wherein the transverse control gate cut-off region 304b The configuration ensures that the width dimension of the floating gate resistor formation area is not limited by the control gate design rules corresponding to the spacing between the strip structures of the control gate conductive material layer 303. Only the design rules for the active region spacing need to be met. Therefore, the width dimension of the floating gate resistor formation area can be reduced, thereby reducing the space occupied by the floating gate resistor and saving chip area. Furthermore, in this embodiment, the added lateral control gate cutoff region 304b can be formed simultaneously with the longitudinal control gate cutoff region 304a using the same mask and the same process, such as etching. Therefore, this embodiment does not require additional process structures or masks, and it also has the advantage of low process cost.

[0092] In this embodiment of the invention, each of the first active regions of the formation region of the floating gate resistor is separated by using a whole control gate to cover the active region. Then, the horizontal control gate is separated by the horizontal gate cutoff (POC), i.e., the horizontal control gate cutoff region 304b. Combined with the vertical gate cutoff, i.e., the vertical control gate cutoff region 304a, the separated control gate is achieved, thus realizing an effective floating gate resistor, removing the original restrictions imposed by the control gate design rules, reducing the space occupied by the resistor, and saving chip area.

[0093] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A floating gate resistor structure in NAND flash memory, characterized in that, The formation region of the floating gate resistor includes two or more parallel-arranged first active regions; A tunneling dielectric layer and a floating gate polysilicon are sequentially formed on the top surface of the first active region, and the long side of the floating gate polysilicon is aligned with the long side of the first active region. A control gate dielectric layer is formed on the top surface of each of the floating gate polysilicon. A first lead-out region and a second lead-out region are also provided on the top surface of each of the floating gate polysilicon. The control gate dielectric layer in the first lead-out region and the second lead-out region are removed. The resistance of the floating gate polysilicon between the first lead-out region and the second lead-out region is a floating gate sub-resistor. The control gate conductive material layer covers all the first active regions in the formation region of the floating gate resistor; the length direction of the control gate conductive material layer is along the length direction of the first active regions, and the control gate conductive material layer is in contact with the floating gate polysilicon in the first lead-out region and the second lead-out region; outside the first lead-out region and the second lead-out region, the control gate conductive material layer is located on the top surface of the control gate dielectric layer; Between each of the first active regions, the control gate conductive material layer has a lateral control gate cut-off region, and the control gate conductive material layer in the lateral control gate cut-off region is removed, so that the control gate conductive material layer remaining on both sides of the lateral control gate cut-off region is divided into multiple strips in the width direction. At least one longitudinal control gate cut-off region is formed in the region between the first lead-out region and the second lead-out region. The control gate conductive material layer in the longitudinal control gate cut-off region is removed and the control gate conductive material layer is divided in the length direction. The control gate conductive material layer that contacts the corresponding first lead-out region forms the first control gate lead-out end, and the control gate conductive material layer that contacts the corresponding second lead-out region forms the second control gate lead-out end. The tops of each of the first control gate leads and each of the second control gate leads are connected to a metal interconnect structure composed of a front metal layer through contact holes. The metal interconnect structure connects each of the floating gate resistors in series to form the floating gate resistor.

2. The floating gate resistor structure in NAND flash memory as described in claim 1, characterized in that: The first active region consists of a semiconductor substrate with shallow trench isolation surrounding its periphery.

3. The floating gate resistor structure in NAND flash memory as described in claim 2, characterized in that: The semiconductor substrate is made of silicon.

4. The floating gate resistor structure in NAND flash memory as described in claim 1, characterized in that: The material of the control gate conductive material layer includes polycrystalline silicon.

5. The floating gate resistor structure in NAND flash memory as described in claim 1, characterized in that: The spacing between the first active regions is greater than or equal to the minimum distance between active regions specified in the design rules; In the formation region of the floating gate resistor, the distance between the outermost two outer length sides of the first active regions and the corresponding length side in the control gate conductive material layer is greater than or equal to the minimum distance of the control gate surrounding the active region as specified by the design rules.

6. The floating gate resistor structure in NAND flash memory as described in claim 1, characterized in that: The metal interconnect structure that connects the floating gate resistors in series includes: a first resistor terminal, a second resistor terminal, and a metal wire located between the first resistor terminal and the second resistor terminal that connects the adjacent floating gate resistors in series. The first control gate lead of each of the two outermost floating gate resistors located between the two outermost floating gate resistors and the first control gate lead of the floating gate resistor on one side are connected by the metal wire, and the second control gate lead of each of the floating gate resistors and the second control gate lead of the floating gate resistor on the other side are connected by the metal wire, forming a serpentine connection structure. One of the two outermost floating gate resistors that is not connected to the metal wire is connected to the first resistor terminal and the other is connected to the second resistor terminal.

7. The floating gate resistor structure in NAND flash memory as described in claim 1, characterized in that: The material of the tunneling medium layer includes an oxide layer.

8. The floating gate resistor structure in NAND flash memory as described in claim 1, characterized in that: The control gate dielectric layer is an ONO layer, which includes a first oxide layer, a second nitride layer, and a third oxide layer stacked sequentially.

9. The floating gate resistor structure in NAND flash memory as described in claim 1, characterized in that: The gate structure of the NAND flash memory cell includes the tunneling dielectric layer, the floating gate polysilicon, the control gate dielectric layer and the control gate conductive material layer stacked in sequence, wherein the floating gate polysilicon and the control gate conductive material layer are isolated by the control gate dielectric layer; The process structures of the tunneling dielectric layer, the floating gate polysilicon, the control gate dielectric layer, and the control gate conductive material layer of the gate structure are the same as those of the tunneling dielectric layer, the floating gate polysilicon, the control gate dielectric layer, and the control gate conductive material layer corresponding to the floating gate resistor, and are formed simultaneously.

10. The floating gate resistor structure in NAND flash memory as described in claim 9, characterized in that: In the NAND flash memory storage array, the control gate conductive material layers of the storage cells in the same column are connected together to form a control gate strip; The control gate strip has a third control gate cutoff region at both ends, and the control gate conductive material layer in the third control gate cutoff region is removed; The third control gate cutoff region, the lateral control gate cutoff region, and the longitudinal control gate cutoff region are defined using the same mask and share the same control gate cutoff process.

Images