Metal-insulator-metal capacitor and method of fabrication

Abstract

This invention discloses a metal-insulator-metal capacitor and its fabrication method, belonging to the field of semiconductor device fabrication. The method includes: obtaining a wafer; forming an isolation layer on the wafer surface; after forming the isolation layer, forming a TiN sacrificial layer at least at the wafer edge and on the surface away from the isolation layer; adsorbing an aniline-based material onto the surface of the TiN sacrificial layer to form an atomic layer deposition (ALD) growth inhibition layer; sequentially forming a lower electrode plate, a dielectric layer, and an upper electrode plate on the surface of the isolation layer using an ALD process; and removing the ALD growth inhibition layer and the TiN sacrificial layer to complete the fabrication of the metal-insulator-metal capacitor. By depositing a TiN sacrificial layer on the back side and edge of the wafer and adsorbing an aniline-based material, only the initial TiN sacrificial layer is retained on the back side of the wafer during subsequent ALD deposition. During subsequent removal, only the TiN sacrificial layer on the back side of the wafer needs to be removed in a shorter time, significantly reducing chemical damage to the back side of the wafer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication, and in particular to a metal-insulator-metal capacitor and its fabrication method. Background Technology

[0002] Metal-Insulator-Metal (MIM) capacitors are crucial passive components in integrated circuits, playing a key role in analog / RF circuits, mixed-signal circuits, and system-on-a-chip (SoC). Their performance directly affects the chip's operating frequency, noise characteristics, and overall functional stability. MIM capacitors typically employ a sandwich structure, consisting of a bottom metal layer, an intermediate insulating dielectric layer, and a top metal layer stacked sequentially.

[0003] Two different MIM structures exist in the current technology. Traditional planar MIM capacitors consist of two electrode layers and one dielectric layer, with a relatively simple structure, but the capacitance density per unit area is limited by the electrode area and the dielectric constant of the dielectric material. The multilayer stacked three-dimensional structure is formed by etching trenches on the substrate surface and then sequentially depositing multiple layers of electrode and dielectric materials within the trenches. On the one hand, the introduction of the trench structure effectively increases the effective electrode area per unit projected area, thus significantly improving the capacitance density; on the other hand, the multilayer MIM structure allows for flexible adjustment of the capacitance value through series or parallel connection of different capacitor layers, thereby achieving more precise capacitance control.

[0004] In the fabrication of three-dimensional MIM capacitors, the high aspect ratio trenches place stringent demands on thin film deposition technology. Atomic Layer Deposition (ALD) technology, with its excellent step coverage, atomic-level thickness control precision, and good conformal properties, has become the preferred technology for depositing multilayer thin films within the trenches. ALD can sequentially deposit electrode materials (such as TiN) and dielectric materials (such as ZrO2 / Al2O3 / ZrO2 stacks, referred to as ZAZ structures, or other high-k dielectrics) to ensure that the film layers within the trench are continuous, uniform, and have controllable thickness.

[0005] The conformal deposition characteristics of atomic layer deposition (ALD) technology dictate that while depositing a thin film on the front side of the wafer, it inevitably deposits multiple layers of the same thickness and composition on the back side. These back-side deposited layers must be completely removed before downstream processes; otherwise, they will affect subsequent photolithography alignment, back-side contact, and equipment transfer processes, and may introduce particulate contamination. Currently, the removal of ALD films on the back side of the wafer is typically achieved using wet etching methods, such as step-by-step or one-step etching using different acid combinations. To ensure complete removal of all layers, a very high over-etching rate must be applied during the process. This not only prolongs the etching time but also causes the etching solution to be in contact with the wafer back-side substrate (silicon or silicon oxide) for an extended period, resulting in severe damage to the wafer back-side surface, such as pits, increased roughness, and stress introduction. This leads to an increase in the defect density on the wafer back side, affecting subsequent back-side inspection, thickness measurement, and shipment quality inspection, ultimately reducing device yield and reliability.

[0006] Therefore, how to efficiently and uniformly remove the thin film deposited on the back side of the wafer without damaging the back side has become a key technical challenge that urgently needs to be solved in the manufacturing of 3D MIM capacitors. Summary of the Invention

[0007] The purpose of this invention is to provide a metal-insulator-metal capacitor and its preparation method, which can effectively remove the thin film formed on the back side of the wafer during atomic layer deposition without damaging the back side of the wafer, thereby solving the above-mentioned problems.

[0008] To solve the above-mentioned technical problems, the present invention provides a method for preparing a metal-insulator-metal capacitor, comprising:

[0009] Obtain wafers;

[0010] An isolation layer is formed on the surface of the wafer;

[0011] After the isolation layer is formed, a TiN sacrificial layer is formed at least at the wafer edge and on the surface away from the isolation layer;

[0012] After forming the TiN sacrificial layer, aniline-based materials are adsorbed onto the surface of the TiN sacrificial layer to form an atomic layer deposition growth inhibition layer.

[0013] A lower electrode plate, a dielectric layer, and an upper electrode plate are sequentially formed on the surface of the isolation layer using an atomic layer deposition process.

[0014] The atomic layer deposition growth inhibition layer and the TiN sacrificial layer are removed to complete the fabrication of the metal-insulator-metal capacitor.

[0015] Optionally, after forming the isolation layer, forming a TiN sacrificial layer at least at the wafer edge and on the surface away from the isolation layer includes:

[0016] After the isolation layer is formed, a TiN sacrificial layer is formed on the wafer edge and the surface away from the isolation layer using a chemical vapor deposition process.

[0017] Optionally, the thickness of the TiN sacrificial layer ranges from 30 Å to 70 Å.

[0018] Optionally, after forming the isolation layer, forming a TiN sacrificial layer at least at the wafer edge and on the surface away from the isolation layer includes:

[0019] TiN material is deposited on the surface of a wafer with the isolation layer based on an atomic layer deposition process to form the TiN sacrificial layer at the wafer edge and on the surface away from the isolation layer.

[0020] Optionally, the thickness of the TiN sacrificial layer ranges from 5 Å to 15 Å.

[0021] Optionally, after forming the TiN sacrificial layer, adsorbing aniline-based materials onto the surface of the TiN sacrificial layer to form an atomic layer deposition growth inhibition layer includes:

[0022] After the TiN sacrificial layer is formed, aniline is adsorbed on the surface of the TiN sacrificial layer to form an atomic layer deposition growth inhibition layer.

[0023] Optionally, the atomic layer deposition growth inhibitor layer is formed on the surface of the TiN sacrificial layer on the wafer away from the isolation layer using a spin coating process.

[0024] Optionally, removing the atomic layer deposition growth inhibition layer and the TiN sacrificial layer includes:

[0025] The atomic layer deposition growth inhibition layer and the TiN sacrificial layer are removed using a wet etching process.

[0026] Optionally, the etching solution for the wet etching process includes one of the following: HF:HNO3 mixture, NH4OH + H2O2 + H2O mixture, HF:H2O2 mixture, and H2SO4 + H2O2 mixture.

[0027] The present invention also provides a metal-insulator-metal capacitor, which is prepared based on the preparation method of the metal-insulator-metal capacitor described in any one of the above embodiments.

[0028] The method for fabricating a metal-insulator-metal capacitor provided by this invention pre-deposits a TiN sacrificial layer on the back side and edge of the wafer and introduces a growth inhibitor for ALD onto it. This ensures that when the electrode layer and dielectric layer are subsequently deposited using ALD technology, only the initial TiN sacrificial layer is retained on the back side of the wafer due to the presence of the inhibitor. During subsequent removal, only the TiN sacrificial layer on the back side of the wafer needs to be removed. Therefore, it can be completely removed in a short time without applying excessive over-etching, thereby significantly reducing chemical damage to the silicon substrate or oxide layer on the back side of the wafer and effectively reducing the defect density on the back side. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 An image of the back side of a wafer according to a method for fabricating a metal-insulator-metal capacitor according to the prior art;

[0031] Figure 2 This is a flowchart illustrating the method for preparing a metal-insulator-metal capacitor according to the present invention.

[0032] Figure 3 A graph comparing the adsorption capacity of aniline for different materials;

[0033] Figures 4a to 4f This is a schematic flowchart of an embodiment of the method for preparing a metal-insulator-metal capacitor according to the present invention;

[0034] Figures 5a to 5f This is a schematic flowchart of a second embodiment of the method for preparing a metal-insulator-metal capacitor according to the present invention.

[0035] In the figure, 1: wafer; 2: isolation layer; 3: TiN sacrificial layer; 4: atomic layer deposition growth inhibition layer; 5: lower electrode plate; 6: dielectric layer; 7: upper electrode plate. Detailed Implementation

[0036] The core of this invention is to provide a method for fabricating a metal-insulator-metal capacitor that effectively mitigates the problem of wafer backside damage caused by the removal of thin films deposited on the wafer backside during atomic layer deposition (MIM) processes. In the prior art, during the fabrication of 3D MIM capacitors, atomic layer deposition (MID) technology, with its excellent step coverage, atomic-level thickness control precision, and good conformal properties, can sequentially deposit electrode and dielectric materials. However, while depositing thin films on the wafer front side, it is inevitable that multiple layers of the same thickness and composition will be deposited on the wafer backside. The deposited layers on the wafer backside must be completely removed before downstream processes; otherwise, it will affect subsequent photolithography alignment, backside contact, and equipment transfer processes, and may introduce particulate contamination. To ensure complete removal of all layers, a very high over-etching rate must be applied, which not only prolongs the etching time but also causes the etching solution to be in contact with the wafer backside for an extended period, resulting in severe damage to the wafer backside surface, such as pits, increased roughness, and stress introduction, thereby leading to an increase in the defect density on the wafer backside. For example, when depositing TiN via ALD, a thickness of 200 Å to 400 Å is typically required, during which an ALD TiN layer of the same thickness is also grown on the back side of the wafer. When etching with HFN solution, the etching rate uniformity for ALD TiN is poor and low; for example, the etching rate in the central region is 44.5 Å / min, while the etching rate in the edge region is approximately 84.2 Å / min. Therefore, 200 Å of ALD TiN requires approximately 4.5 minutes of etching to ensure removal, but by this time, the edges have already exceeded 100% over-etching, leading to chemical damage to the silicon substrate, especially the back side of the wafer. Figure 1 As shown.

[0037] In the technical solution of this application, a TiN sacrificial layer is pre-deposited on the back side and edge of the wafer, and growth inhibitors for ALD are introduced on the surface of the TiN sacrificial layer by adsorbing aniline-based materials. This prevents the deposition of corresponding electrode and dielectric layers on the back side of the wafer due to the presence of the inhibitors, so that only the initial TiN sacrificial layer is retained on the back side of the wafer. During subsequent removal, only the TiN sacrificial layer on the back side of the wafer needs to be removed. Therefore, it can be completely removed in a short time without applying excessive over-etching, thereby significantly reducing chemical damage to the silicon substrate or oxide layer on the back side of the wafer and effectively reducing the defect density on the back side.

[0038] To enable those skilled in the art to better understand the present invention, the invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] The preparation method of the metal-insulator-metal capacitor and the metal-insulator-metal capacitor provided in the embodiments of the present invention will be described below with reference to the accompanying drawings.

[0040] Reference Figure 2 As shown in Figure 5, the fabrication method of a metal-insulator-metal capacitor may include:

[0041] S1: Obtain the wafer.

[0042] In this step, refer to Figure 4a and Figure 5a Wafer 1 is a wafer with some front-end processes completed, which is used as the carrier base for a metal-insulator-metal capacitor. In this embodiment, there are no particular restrictions on the structure on the surface of wafer 1, and those skilled in the art can choose the structure to be formed according to actual needs.

[0043] In one feasible implementation, wafer 1 includes at least one of the following structures on its surface:

[0044] A semiconductor substrate in which active and / or passive devices, as well as doped well structures, are formed.

[0045] An interlayer dielectric layer is disposed on the semiconductor substrate, and the material of the interlayer dielectric layer is a low-k dielectric material, an ultra-low-k dielectric material, or silicon oxide. Contact holes are formed in the interlayer dielectric layer to achieve electrical connections between the metal-insulator-metal capacitor and the underlying metal structure. Optionally, the substrate also includes an etch stop layer disposed between the semiconductor substrate and the interlayer dielectric layer. Interconnect structures are also disposed on the substrate, located on the semiconductor substrate.

[0046] In this embodiment, wafer 1 includes two surfaces: a front surface and a back surface. The front surface of wafer 1 refers to the surface on wafer 1 where the aforementioned structures, such as semiconductor active devices, are formed. The back surface of wafer 1 refers to the surface on wafer 1 that is opposite to the front surface.

[0047] S2: An isolation layer is formed on the wafer surface.

[0048] In this step, refer to Figure 4b and Figure 5b An isolation layer 2 is formed on the front side of the wafer to isolate the subsequently fabricated metal-insulator-metal capacitor from the underlying structure in the wafer 1, in order to prevent adverse phenomena such as interlayer metal diffusion, leakage or short circuit.

[0049] In this embodiment, there are no particular limitations on the isolation layer 2, and its material and formation process are techniques known to those skilled in the art. In one feasible implementation, the material of the isolation layer 2 is silicon nitride or silicon oxide. The thickness of the isolation layer 2 can be set according to actual process requirements; for example, the thickness of the isolation layer 2 can be set between 50 Å and 2000 Å. The isolation layer 2 can be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition processes to ensure that it has good coverage and density.

[0050] For example, the isolation layer 2 can be a silicon oxide thin film formed on the front side of the wafer by a plasma-enhanced chemical vapor deposition process.

[0051] S3: After the isolation layer is formed, a TiN sacrificial layer is formed at least at the wafer edge and on the surface away from the isolation layer.

[0052] In this step, refer to Figure 4c and Figure 5c At least a TiN sacrificial layer 3 needs to be formed on the wafer edge and the back side of the wafer. The TiN sacrificial layer 3 can be formed only on the wafer edge and the back side of the wafer, or it can be formed on both the wafer edge and the front and back surfaces of the wafer. That is to say, a TiN sacrificial layer 3 must be formed on the wafer edge and the back side of the wafer for subsequent adsorption of aniline-based materials to form an atomic layer deposition growth inhibition layer 4.

[0053] In one feasible implementation, step S3 may include:

[0054] S3': After the isolation layer is formed, a TiN sacrificial layer is formed at the wafer edge and on the surface away from the isolation layer.

[0055] In this step, refer to Figure 4c The surface of wafer 1 furthest from the isolation layer refers to the back side of the wafer. Since the TiN sacrificial layer 3 is formed only at the wafer edge and on the back side, a process capable of achieving this growth is required. For example, the TiN sacrificial layer 3 can be formed at the wafer edge and on the back side using chemical vapor deposition (CVD). CVD allows for selective deposition, ensuring the TiN sacrificial layer 3 is grown only at the wafer edge and on the back side, while it is not grown on the front side of the wafer because it is placed on a chuck. In the case of CVD, the thickness of the TiN sacrificial layer 3 can range from 30 Å to 70 Å. Within this thickness range, the TiN sacrificial layer 3 can effectively cover the back side and wafer edge without affecting subsequent removal.

[0056] In another feasible implementation, step S3 may include:

[0057] S3'': After the isolation layer is formed, a TiN sacrificial layer is formed at the wafer edge, as well as on the front and back sides of the wafer.

[0058] In this step, refer to Figure 5c A TiN sacrificial layer 3 is formed at the wafer edge, as well as on the front and back sides of the wafer using atomic layer deposition (ALD) technology. As previously mentioned, the conformal deposition characteristics of ALD allow for the simultaneous formation of the TiN sacrificial layer 3 across the entire wafer 1. To ensure that the TiN sacrificial layer 3 on the front side of the wafer does not affect the functionality of subsequent TiN layers and the overall structure of the MIM, the thickness of the TiN sacrificial layer 3 is in the range of 5 Å to 15 Å using ALD. The TiN sacrificial layer 3 on the front side of the wafer can subsequently be retained on wafer 1 as part of the TiN in the lower electrode plate 5.

[0059] S4: After forming the TiN sacrificial layer, aniline-based materials are adsorbed on the surface of the TiN sacrificial layer to form an atomic layer deposition growth inhibition layer.

[0060] In this step, refer to Figure 4d and Figure 5d By selectively modifying the surface, the TiN sacrificial layer 3 on the back side and edge of the wafer is treated to precisely control the selectivity of subsequent ALD growth.

[0061] In this embodiment, aniline-based materials are used as ALD growth inhibitors to form an atomic layer deposition growth inhibition layer 4. Aniline-based materials selectively adsorb onto the TiN sacrificial layer 3. The core mechanism is that the amino group (-NH2) and the large π-bond on the benzene ring in the aniline-based material molecule can undergo strong coordination bonding and π-π conjugation stacking effects with the dangling bonds and unsaturated metal active sites on the TiN surface, forming a dense and highly ordered self-assembled monolayer, ultimately achieving ultra-high selective chemisorption of TiN material. Figure 3 As shown, among different materials, aniline-based materials have the largest adsorption capacity for TiN.

[0062] Due to the strong π-bond conjugated chemisorption of aniline-based materials on the TiN surface, their desorption activation energy is extremely high. Under the typical temperature window (usually 150℃ to 350℃) and high vacuum environment of the subsequent ALD deposition process, the saturated vapor pressure of this atomic layer deposition growth inhibition layer 4 is extremely low, preventing thermally induced volatilization or gas-phase diffusion. Simultaneously, the strong bonding inhibits lateral surface migration of molecules on the solid-phase surface. Therefore, this atomic layer deposition growth inhibition layer 4 exhibits extremely high spatial stability, preventing migration across the wafer edge to the effective chip area on the front side, and also preventing desorption within the ALD chamber causing cross-contamination. This completely eliminates the possibility of negatively impacting the core electrical performance of the front-side MIM device (such as leakage current Jg, breakdown voltage Vbd, and capacitance density uniformity).

[0063] In this embodiment, the spatial distribution of aniline materials on wafer 1 is controlled based on a spin-coating process. Specifically, centrifugal force and edge wetting effect are used to selectively coat and retain the aniline solution on the surface of the TiN sacrificial layer 3 on the back side of the wafer and on the surface of the TiN sacrificial layer 3 in the edge region of the wafer.

[0064] Due to the presence of the atomic layer deposition growth inhibition layer 4 on the back side and edge of the wafer, the dense atomic layer deposition growth inhibition layer 4 effectively blocks the chemical adsorption sites of ALD titanium precursors such as TiCl4 and TDMAT on the TiN seed layer on the back side of the wafer during subsequent ALD deposition of TiN. This completely "poisons" the ALD nucleation process, thereby avoiding the growth of unnecessary TiN films in the non-effective areas of wafer 1, namely the back side and edge of the wafer.

[0065] Similarly, due to the presence of atomic layer deposition growth inhibition layer 4, the precursor cannot be deposited on the back side and edge of the wafer when forming the high-k dielectric stack of the MIM capacitor via ALD, because of the lack of nucleation substrate.

[0066] Therefore, for the back side and edge of the wafer, only the deposited TiN sacrificial layer 3 exists, while the thickness of the subsequent electrode and dielectric layers remains unchanged, which facilitates subsequent removal and effectively reduces the amount of etching. It should be noted that for the above step S3'', although a TiN sacrificial layer 3 is also formed on the front side of the wafer, in this step, it is neither necessary nor possible to form an atomic layer deposition growth inhibition layer 4 on the front side of the wafer. That is to say, regardless of the method used in step S3, in step S4, the atomic layer deposition growth inhibition layer 4 is only formed on the back side and edge of the wafer.

[0067] S5: Based on atomic layer deposition process, a lower electrode plate, a dielectric layer and an upper electrode plate are sequentially formed on the surface of the isolation layer.

[0068] In this step, refer to Figure 4e and Figure 5e Using atomic layer deposition (ALD) technology, on the surface of wafer 1 after the growth inhibition layer 4 is modified by ALD in step S4, a sandwich stack structure of a MIM capacitor—lower electrode plate 5, dielectric layer 6, and upper electrode plate 7—is sequentially constructed. In this embodiment, the lower electrode plate 5, dielectric layer 6, and upper electrode plate 7 can all be formed using conventional techniques known in the art.

[0069] In one feasible implementation, step S5 includes the following steps:

[0070] S501: A lower electrode plate is formed on the front side of the wafer after step S4.

[0071] In this step, the lower electrode plate 5 can be formed using any of the following processes: physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Taking ALD as an example, the formation of the lower electrode plate 5 includes: placing the wafer 1, after completing step S4, in the ALD reaction chamber; the precursor can be tetrakis(dimethylamino)titanium. In a typical ALD growth cycle, the titanium precursor and reactive gas (such as NH3 or N2 / H2 plasma) are sequentially pulsed, with approximately one atomic layer of TiN film deposited per cycle. By repeating the growth cycle, the thickness of the lower electrode plate 5 is precisely controlled to the target value. The process temperature is typically set at around 250°C.

[0072] S502: After the lower electrode plate is formed, a dielectric layer is deposited on the surface of the lower electrode plate.

[0073] In this step, the dielectric layer 5 can have a conventional dielectric layer structure known in the art, such as a high-k dielectric material stack structure, to achieve high capacitance density with a relatively thin physical thickness. For example, the dielectric layer 5 may include stack structures such as ZAZ (ZrO2 / Al2O3 / ZrO2), ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3), AZAZA (Al2O3 / ZrO2 / Al2O3 / ZrO2 / Al2O3), and AZAZAZA (Al2O3 / ZrO2 / Al2O3 / ZrO2 / Al2O3). Taking the ZAZ (ZrO2 / Al2O3 / ZrO2) structure as an example, step S502 includes:

[0074] Bottom ZrO2 layer: Deposited using thermal atomic layer deposition (TILD), with tetrakis(dimethylamino)zirconium (Zr[N(CH3)2]4) and water vapor (H2O) as precursors. ZrO2 has a high dielectric constant and is the main contributing layer for capacitance density.

[0075] Intermediate Al2O3 layer: Trimethylaluminum (TMA, Al(CH3)3) and water vapor are used as precursors. Al2O3 has a large band gap and mainly plays a role in reducing leakage current in the ZAZ structure. TMA gas can be introduced for surface pretreatment before deposition to optimize nucleation quality.

[0076] Top ZrO2 layer: The process is the same as the bottom ZrO2 layer, and together with the bottom ZrO2 layer, they form a symmetrical ZAZ structure.

[0077] After the lower electrode plate 5 is formed, the dielectric layer 6 is continuously deposited in the same atomic layer deposition reaction chamber without breaking the vacuum. This in-situ integration method effectively avoids interface contamination between the lower electrode plate 5 and the dielectric layer 6, which is crucial for ensuring the leakage current characteristics and reliability of the MIM capacitor.

[0078] S503: After the dielectric layer is formed, an upper electrode plate is formed on the surface of the dielectric layer.

[0079] In this step, the upper electrode plate 7 is also made of TiN, and the same ALD process and precursor are used as for the lower electrode plate 5. The thickness of the upper electrode plate 7 is precisely controlled by repeating the ALD growth cycle.

[0080] In step S5, the thickness of each film layer can be independently controlled by precisely controlling the number of ALD growth cycles for each layer. The thickness of each layer is typically in the nanometer range (e.g., about 7 nm for ZrO2 and about 1 nm for Al2O3). The lower electrode plate 5, dielectric layer 6, and upper electrode plate 7 can be deposited in the same ALD reaction chamber without disrupting the vacuum during deposition, thus ensuring that the entire MIM stack (lower electrode-dielectric layer-upper electrode) is completed continuously in a single ALD operation.

[0081] In this embodiment, since aniline materials are selectively adsorbed onto the surface of the TiN sacrificial layer 3 on the back side and edge of the wafer in step S4 to form a dense atomic layer deposition growth inhibition layer 4, during the ALD deposition of the lower electrode plate 5, dielectric layer 6 and upper electrode plate 7, the corresponding lower electrode plate 5, dielectric layer 6 and upper electrode plate 7 are only deposited on the front side of the wafer, and cannot be deposited on the back side and edge of the wafer. The atomic layer deposition growth inhibition layer 4 effectively blocks the nucleation and growth of precursors in the non-effective areas during the subsequent ALD process, so that only a thin TiN sacrificial layer 3 and atomic layer deposition growth inhibition layer 4 exist on the back side and edge of the wafer, which is beneficial for subsequent removal.

[0082] It should be noted that the preparation process described in step S5 is merely an example and does not limit the scope of the present invention. Those skilled in the art can adjust the preparation process of this step according to actual needs, and such adjustments are also within the protection scope of the present invention.

[0083] S6: Remove the atomic layer deposition growth inhibition layer and TiN sacrificial layer to complete the fabrication of the metal-insulator-metal capacitor.

[0084] In this step, refer to Figure 4f and Figure 5f By using a wet etching process, the atomic layer deposition growth inhibition layer 4 and the TiN sacrificial layer 3 remaining on the back side and edge of the wafer after the MIM stack (lower electrode / dielectric layer / upper electrode) deposition are removed together, so as to avoid the residue from having an adverse effect on subsequent processes and device reliability.

[0085] In this embodiment, wet etching is the main process for removing the TiN film. Its core mechanism is as follows: the oxidant in the etching solution first oxidizes TiN into soluble or readily reactant products such as TiO2, and then removes the products from the surface through complexation or dissolution reactions. The atomic layer deposition growth inhibition layer 4 is also decomposed and removed in a strongly oxidizing or acidic / alkaline etching environment, achieving simultaneous stripping of the dual-layer structure in a single wet etching process.

[0086] The etching solution used in the wet etching process can be a conventional etching solution known in the art. It is important to note that the etching solution needs to have a high etching rate for TiN and aniline-based materials, while maintaining a sufficiently low etching rate for exposed MIM capacitor structures such as TiN electrode plates, dielectric layers, and the effective areas on the front side of the wafer, to avoid damaging the completed functional device. For example, the etching solution can include a mixture of HF:HNO3, a mixture of NH4OH + H2O2 + H2O, a mixture of HF:H2O2, or a mixture of H2SO4 + H2O2.

[0087] In one feasible implementation, an HF:HNO3 mixture can be used as the etching solution. In this etching solution, HNO3 acts as a strong oxidant to oxidize TiN, while HF dissolves the generated titanium oxide; the two work synergistically to achieve efficient etching. It should be noted that due to the presence of HF, this system is somewhat corrosive to the silicon substrate, therefore the etching time needs to be precisely controlled. The etching time needs to ensure that the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4 are completely removed while avoiding over-etching that could damage the underlying wafer 1 or adjacent structures. In this embodiment, the etching time ranges from 3 s to 10 s.

[0088] In this embodiment, due to the presence of an atomic layer deposition growth inhibition layer 4 containing aniline-based materials, when forming the lower electrode plate 5, dielectric layer 6, and upper electrode plate 7 by atomic layer deposition in step S5, deposition is only performed on the front side of the wafer, and cannot be performed on the front side and edge of the wafer. Therefore, only a very thin atomic layer deposition growth inhibition layer 4 and TiN sacrificial layer 3 exist on the front side and edge of the wafer, so the removal step can be completed in a very short time during the removal process.

[0089] For example, if the TiN sacrificial layer 3 is formed by chemical vapor deposition in step S3', removing the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4 requires only a short time, resulting in minimal damage to the back side of the wafer. In this case, the removal of the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4 can be performed after each subsequent layer is deposited, and then the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4 can be deposited again before the next layer is deposited. For example, before depositing the top electrode, the TiN sacrificial layer 3 is deposited on the back side of the wafer and the wafer edge, and aniline-based materials are adsorbed. After the top electrode is deposited, the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4 are removed by a wet etching process. Before depositing the dielectric layer, the TiN sacrificial layer 3 is deposited again on the back side of the wafer and the wafer edge, and aniline-based materials are adsorbed. Furthermore, the removal of the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4 can also be performed after all layers of the MIM structure have been deposited.

[0090] In step S3'', when atomic layer deposition is used to form the TiN sacrificial layer 3, the TiN sacrificial layer 3 is thinner, and the removal of the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4 is also shorter. At this time, the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4 can be removed after all layers of the MIM structure have been deposited. Meanwhile, the TiN sacrificial layer 3 on the front side of the wafer can exist as part of the lower electrode plate 5 in the MIM capacitor.

[0091] After wet etching and subsequent cleaning and drying, the atomic layer deposition growth inhibition layer 4 and TiN sacrificial layer 3 on the back side and edge of the wafer were completely removed, while the MIM capacitor structure in the effective area on the front side of the wafer was completely preserved. At this point, the fabrication process of the metal-insulator-metal capacitor was completed, and wafer 1 could proceed to subsequent photolithography patterning, rapid thermal annealing, and electrical performance testing.

[0092] In summary, the method for fabricating the metal-insulator-metal capacitor of the present invention deposits a TiN sacrificial layer 3 on the back side and edge of the wafer, and adsorbs aniline-based materials on the TiN sacrificial layer 3 to form an atomic layer deposition growth inhibition layer 4. In the subsequent process of fabricating the lower electrode plate 5 / dielectric layer 6 / upper electrode plate 7 structure by atomic layer deposition, it is impossible to deposit corresponding thin films on the back side and edge of the wafer. This results in only a thin TiN sacrificial layer 3 and atomic layer deposition growth inhibition layer 4 existing on the back side and edge of the wafer. As a result, the removal process can be completed in a very short time without damaging the back side of the wafer.

[0093] The preparation method of the metal-insulator-metal capacitor of the present invention will be described in detail below with reference to specific embodiments.

[0094] Example 1

[0095] Reference Figures 4a to 4f A method for preparing a metal-insulator-metal capacitor, comprising:

[0096] S1: Obtain the wafer; the wafer includes the front and back sides;

[0097] S2: A silicon oxide thin film is formed on the front side of the wafer as an isolation layer using a plasma-enhanced chemical vapor deposition process;

[0098] S3: After the isolation layer is formed, a TiN sacrificial layer is formed on the wafer edge and the back of the wafer using a chemical vapor deposition process. The thickness of the TiN sacrificial layer is approximately 50 Å.

[0099] S4: After forming the TiN sacrificial layer, aniline is adsorbed on the surface of the TiN sacrificial layer to form an atomic layer deposition growth inhibition layer;

[0100] S5: A lower electrode plate, a dielectric layer, and an upper electrode plate are sequentially formed on the surface of the isolation layer based on atomic layer deposition (ALD) technology; the lower electrode plate includes TiN, the dielectric layer includes a ZAZ stacked structure, and the upper electrode plate includes TiN.

[0101] S6: The metal-insulator-metal capacitor is fabricated by using a wet etching process with an HF:HNO3 mixture as the etching solution to remove the atomic layer deposition growth inhibition layer and the TiN sacrificial layer.

[0102] In this embodiment, the time required to remove the TiN sacrificial layer is significantly shorter compared to existing preparation methods.

[0103] Example 2

[0104] Reference Figures 5a to 5f A method for preparing a metal-insulator-metal capacitor, comprising:

[0105] S1: Obtain the wafer; the wafer includes the front and back sides;

[0106] S2: A silicon oxide thin film is formed on the front side of the wafer as an isolation layer using a plasma-enhanced chemical vapor deposition process;

[0107] S3: After the isolation layer is formed, a TiN sacrificial layer is formed at the wafer edge, the back side of the wafer, and the front side of the wafer based on the atomic layer deposition process. The thickness of the TiN sacrificial layer is about 10 Å.

[0108] S4: After forming the TiN sacrificial layer, aniline is adsorbed on the surface of the TiN sacrificial layer at the wafer edge and on the back side of the wafer to form an atomic layer deposition growth inhibition layer;

[0109] S5: A lower electrode plate is formed on the surface of the isolation layer using physical vapor deposition, and a dielectric layer and an upper electrode plate are formed sequentially on the surface of the lower electrode plate using atomic layer deposition; the lower electrode plate includes TiN, the dielectric layer includes a ZAZ stacked structure, and the upper electrode plate includes TiN.

[0110] S6: The atomic layer deposition growth inhibition layer and TiN sacrificial layer on the wafer edge and back side are removed by using a wet etching process with an HF:HNO3 mixture as the etching solution, thus completing the fabrication of the metal-insulator-metal capacitor.

[0111] In this embodiment, since the TiN sacrificial layer 3 is formed by atomic layer deposition, the TiN sacrificial layer 3 is thinner, and it only takes about 6 seconds to remove the TiN sacrificial layer 3 and the atomic layer deposition growth inhibition layer 4. Compared with about 52 seconds in the prior art, the time is reduced by about 80%, and it causes almost no damage to the back side of the wafer.

[0112] This invention also provides a metal-insulator-metal capacitor, which is prepared based on the metal-insulator-metal capacitor preparation method described in the above embodiments. Since the back side of the wafer is not damaged during the wafer backside cleaning process, the metal-insulator-metal capacitor according to this invention has excellent structural integrity and process stability, and the overall yield and batch-to-batch consistency of the product are significantly improved.

[0113] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0114] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0115] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0116] The metal-insulator-metal capacitor and its preparation method provided by this invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make several improvements and modifications to this invention without departing from the principles of this invention, and these improvements and modifications also fall within the protection scope of the claims of this invention.

Claims

1. A method for preparing a metal-insulator-metal capacitor, characterized in that, include: Obtain wafers; An isolation layer is formed on the surface of the wafer; After the isolation layer is formed, a TiN sacrificial layer is formed at least at the wafer edge and on the surface away from the isolation layer; After forming the TiN sacrificial layer, aniline-based materials are adsorbed onto the surface of the TiN sacrificial layer to form an atomic layer deposition growth inhibition layer. A lower electrode plate, a dielectric layer, and an upper electrode plate are sequentially formed on the surface of the isolation layer using an atomic layer deposition process. The atomic layer deposition growth inhibition layer and the TiN sacrificial layer are removed to complete the fabrication of the metal-insulator-metal capacitor.

2. The method for preparing a metal-insulator-metal capacitor according to claim 1, characterized in that, After forming the isolation layer, forming a TiN sacrificial layer at least at the wafer edge and on the surface away from the isolation layer includes: After the isolation layer is formed, a TiN sacrificial layer is formed on the wafer edge and the surface away from the isolation layer using a chemical vapor deposition process.

3. The method for preparing a metal-insulator-metal capacitor according to claim 2, characterized in that, The thickness of the TiN sacrificial layer ranges from 30 Å to 70 Å.

4. The method for preparing a metal-insulator-metal capacitor according to claim 1, characterized in that, After forming the isolation layer, forming a TiN sacrificial layer at least at the wafer edge and on the surface away from the isolation layer includes: TiN material is deposited on the surface of a wafer with the isolation layer based on an atomic layer deposition process to form the TiN sacrificial layer at the wafer edge and on the surface away from the isolation layer.

5. The method for preparing a metal-insulator-metal capacitor according to claim 4, characterized in that, The thickness of the TiN sacrificial layer ranges from 5 Å to 15 Å.

6. The method for preparing a metal-insulator-metal capacitor according to claim 1, characterized in that, After forming the TiN sacrificial layer, adsorbing aniline-based materials on the surface of the TiN sacrificial layer to form an atomic layer deposition growth inhibition layer includes: After the TiN sacrificial layer is formed, aniline is adsorbed on the surface of the TiN sacrificial layer to form an atomic layer deposition growth inhibition layer.

7. The method for preparing a metal-insulator-metal capacitor according to claim 6, characterized in that, The atomic layer deposition growth inhibitor layer is formed on the surface of the TiN sacrificial layer on the wafer away from the isolation layer using a spin coating process.

8. The method for preparing a metal-insulator-metal capacitor according to claim 1, characterized in that, Removing the atomic layer deposition growth inhibition layer and the TiN sacrificial layer includes: The atomic layer deposition growth inhibition layer and the TiN sacrificial layer are removed using a wet etching process.

9. The method for preparing a metal-insulator-metal capacitor according to claim 1, characterized in that, The etching solution used in wet etching processes includes one of the following: HF:HNO3 mixture, NH4OH + H2O2 + H2O mixture, HF:H2O2 mixture, and H2SO4 +H2O2 mixture.

10. A metal-insulator-metal capacitor, characterized in that, It is prepared according to the method for preparing a metal-insulator-metal capacitor as described in any one of claims 1 to 9.

Images