A gallium oxide insulated gate bipolar transistor with a p-type AlN-based hetero-collector

Abstract

The application relates to the field of transistors, in particular to a gallium oxide insulated gate bipolar transistor with a p-type AlN-based hetero collector. The gallium oxide lacks p-type doping, and a traditional gallium oxide device is difficult to realize bipolar conduction of an insulated gate bipolar transistor. The gallium oxide insulated gate bipolar transistor with the p-type AlN-based hetero collector is provided with a new structure, the AlN / Ga2O3 hetero interface is used to realize collector hole injection and drift region conductance modulation, so that the limitation of the single-pole conduction mechanism of the gallium oxide device on the conduction resistance is broken, and the quality of the collector junction interface and the reliability of the device are improved.

Description

Technical Field

[0001] This invention relates to the field of transistor technology, and more particularly to a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector. Background Technology

[0002] Currently, β-gallium oxide (β-Ga2O3) has attracted much attention among next-generation power semiconductor materials due to its ultra-wide bandgap and extremely high theoretical critical breakdown electric field strength. Compared with gallium nitride (GaN) and silicon carbide (SiC), gallium oxide has greater theoretical advantages in the drift layer design of high-voltage power devices, and its n-type doping process is mature, allowing for low-cost, large-size fabrication of single-crystal substrates via melt processing. However, gallium oxide has an extremely large effective hole mass and is highly prone to self-trapping, making p-type doping impossible to achieve to date. This intrinsic limitation has kept gallium oxide power devices in unipolar forms such as Schottky diodes and metal-oxide-semiconductor field-effect transistors (MOSFETs) for a long time, unable to overcome the fundamental bottleneck of the drift layer resistance increasing sharply with increasing voltage rating through conductance modulation.

[0003] An insulated-gate bipolar transistor (IGBT) is a composite power device that combines the gate control characteristics of a metal-oxide-semiconductor field-effect transistor (MOSFET) with the minority carrier injection characteristics of a bipolar transistor. Its core working mechanism lies in the p-carrier injection during conduction. + collector to n - The drift region is injected with a large number of holes, creating a high-concentration electron-hole plasma. This significantly reduces the equivalent resistance of the drift region through conductivity modulation, thereby achieving conduction losses far lower than those of unipolar devices while maintaining high voltage withstand capability. This mechanism of the insulated-gate bipolar transistor (IGBT) determines its widespread application in high-voltage, high-current power conversion fields.

[0004] To circumvent the barrier of p-type gallium oxide deficiency, researchers have explored constructing heterojunctions by directly bonding or epitaxially growing external p-type materials with n-type gallium oxide, injecting holes into the gallium oxide drift region using a hetero collector. For example, a hetero collector junction is formed by depositing p-type material on the back side of the n-Ga2O3 drift region, while the front side is treated with p-type material (p-NiO2O3). x The p-NiO material (p-Cu2O or p-diamond, etc.) forms the bulk region and the channel of the metal-oxide-semiconductor field-effect transistor. Channel conduction is controlled by the gate voltage. During forward conduction, holes are injected into the drift region from the collector-side p-type material to trigger conductance modulation. There are two implementation forms: vertical and lateral. Existing research shows that p-NiO... x / n-Ga2O3 heterojunctions have achieved effective bipolar conductance modulation in diode structures, verifying the physical feasibility of the heterojunction implantation approach. This has driven the proposal of the concept of gallium oxide insulated-gate bipolar transistors based on heterojunction collectors. There are also reports on p-NiO... xThe n-Ga2O3 heterojunction power diode, constructed using a heterojunction pn junction of NiO and gallium oxide, allows for hole injection into the drift region under forward bias, triggering conductance modulation within the gallium oxide and achieving a combination of ultra-high breakdown voltage and low specific on-resistance. Additionally, an n-β-Ga2O3 / p-GaN / n-GaN heterojunction bipolar transistor (HBT) structure has been reported, with β-Ga2O3 as the emitter, p-GaN as the base, and n-GaN as the collector; simulation results show a certain current gain.

[0005] However, the above-mentioned solutions also have inherent drawbacks. For example, the main drawback of using p-type materials as heterocollectors in gallium oxide insulated-gate bipolar transistors (GaO) is the large valence band shift between the p-type material and β-Ga₂O₃. Hole injection requires overcoming a high interface barrier and necessitates a high forward bias or interface-assisted tunneling to effectively inject into the drift region, which is detrimental to achieving low on-state voltage drop collector junction designs. Furthermore, p-type materials and β-Ga₂O₃ have shortcomings in thermal stability and interfacial chemical compatibility, posing process challenges to the long-term reliability of the devices. p-NiO x While the / n-Ga2O3 heterojunction power diode verified the physical feasibility of heterohole injection, this approach is a gateless two-terminal device and lacks voltage-controllable switching capability, making it unsuitable for direct application in power switching applications requiring active control of conduction and turn-off. The n-β-Ga2O3 / p-GaN / n-GaN heterojunction bipolar transistor employs a current-controlled topology rather than a voltage-controlled insulated-gate bipolar transistor, lacking insulated-gate drive characteristics; gallium oxide serves only as the emitter rather than the drift region, failing to realize its ultra-high voltage withstand potential; the p-type region is GaN, with a relatively narrow bandgap, limiting the stability of the collector junction under ultra-high voltage operating conditions.

[0006] Therefore, developing a gallium oxide insulated-gate bipolar transistor with better performance is of great significance to the development of insulated-gate bipolar transistors. Summary of the Invention

[0007] In view of this, the present invention provides a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterojunction collector. The gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterojunction provided by the present invention achieves collector hole injection and drift region conductance modulation through an aluminum nitride / gallium oxide (AlN / Ga2O3) heterojunction, thereby breaking through the limitation of on-resistance on the unipolar conduction mechanism of gallium oxide devices and improving the collector junction interface quality and device reliability.

[0008] This invention provides a gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector, wherein the gate structure is a trench gate or a planar gate; the trench gate structure includes: a periodic unit structure along the lateral direction, and, from top to bottom along the longitudinal direction, an emitter metal layer, an n-type insulated-gate bipolar transistor, and an insulated-gate bipolar transistor. + Source region and p + Body contact area, p-type body area, n - Gallium oxide drift region, p-type AlN-based heterocollector layer and collector metal; also includes the emitter metal layer, n + Source region and p + A trench gate structure with a body contact region and a p-type body region arranged side-by-side at the center. From top to bottom, the trench gate structure includes a gate, an insulating layer covering the bottom and sides of the gate, and the insulating layer and the p-type body region together cover the n-type body region. - Gallium oxide drift region, the side of the insulating layer is connected to the emitter metal layer and n from top to bottom. + Source region, p-type body region and part of n - Gallium oxide drift region contact; the planar gate structure includes: a periodic unit structure along the lateral direction, and sequentially, from top to bottom, an emitter metal layer and a planar gate structure, n + Source region and p + Body contact area, p-type body area, n - Gallium oxide drift region, p-type AlN-based heterocollector layer, and collector metal; the planar gate structure, from top to bottom, includes a gate, an insulating layer enclosing the bottom and sides of the gate, and the insulating layer and the p-type body region together cover the n-type gate. - Gallium oxide drift region, inner surface of p-type body region and n - Partial lateral contact of the gallium oxide drift region.

[0009] Preferably, in a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector, the valence band offset ranges from -0.2 to -2 eV; and the conduction band offset ranges from -1.0 to -3.0 eV.

[0010] Preferred, n + The source region is n + GaN source region or n + AlGaN source region; p + The bulk contact region is heavily doped with Mg p + GaN region or p + AlGaN region.

[0011] Preferably, the p-type body region is p-GaN or p-AlGaN.

[0012] Preferred, n - An n-type AlN-based heterocollector layer is also provided between the gallium oxide drift region and the p-type AlN-based heterocollector layer. + Gallium oxide field stop layer.

[0013] Preferably, the p-type AlN-based heterocurrent collector layer and the n-type AlN-based heterocurrent collector layer are preferred. - An AlN ultrathin layer is disposed between the gallium oxide drift regions; the thickness of the AlN ultrathin layer is 1~3nm.

[0014] Preferably, the p-type AlN-based heterocollector layer includes one or more of the following: Mg-doped p-AlN monolayer, Mg-doped p-AlGaN layer, p-AlInN ternary alloy, δ-doped AlN, p-AlN / AlGaN superlattice, AlN / GaN superlattice, p-AlN / p-GaN composite layer, p-AlGaN / AlN composite layer, p-GaN ohmic contact cap layer, and p-AlGaN ohmic contact cap layer; the δ-doped AlN is periodic Mg δ-doped AlN.

[0015] Preferably, the groove geometry of the groove grid is a standard rectangular groove grid, an oblique groove grid, a rounded corner groove grid, or a circular arc groove grid.

[0016] Preferably, the trench grid further includes a shielding electrode, which is disposed at the lower part of the trench and short-circuited to the collector electrode.

[0017] The present invention also provides a method for fabricating a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector according to the above scheme, which can be a forward epitaxial method, a back-side integration method, a surface activated bonding method (SAB), an atomic layer deposition method (ALD), or a magnetron sputtering method.

[0018] Preferably, the forward epitaxial method includes the following steps: growing a p-type AlN-based heterocollector layer on a substrate, and then epitaxially growing n-type AlN-based heterocollector layer on the p-type AlN-based heterocollector layer. - Gallium oxide drift region, n - Selective epitaxy or deposition of p-type bulk regions above gallium oxide drift regions, forming n-type bulk regions. + Source region and p + The body contact region is dry-etched into trenches, and gate dielectric and gate conductor are deposited. The emitter and gate are metallized, and the growth substrate is thinned or removed on the back side. A collector metal ohmic contact is made on the back side of the exposed p-type AlN-based hetero collector layer to obtain a gallium oxide insulated gate bipolar transistor with a p-type AlN-based hetero collector.

[0019] Preferably, the backside integration method includes the following steps: preparing n - Epitaxial wafers in gallium oxide drift regions are selectively grown with p-type bulk regions, and n-type bulk regions are formed on the p-type bulk regions. + Source region and p + In the body contact region, dry etching forms trenches, depositing the gate dielectric and gate conductor, and metallizing the emitter and gate. -After thinning the back side of the gallium oxide drift region, a p-type AlN-based hetero collector layer is integrated, and the collector is metallized to obtain a gallium oxide insulated gate bipolar transistor with a p-type AlN-based hetero collector.

[0020] Preferably, the preparation method of the surface-activated bonding method is the same as that of the forward epitaxial method, except that n is epitaxially grown on the p-type AlN-based heterocurrent collector layer. - The gallium oxide drift region is replaced by: an epitaxial wafer with a separately fabricated p-type AlN-based heterocollector layer and an n-type AlN-based heterocollector layer. - Direct bonding of epitaxial wafers in gallium oxide drift regions.

[0021] Preferably, the preparation method of atomic layer deposition is the same as that of forward epitaxy, except that the growth of p-type AlN-based heterocurrent collector layer on the substrate is replaced by: AlN deposition by atomic layer deposition, Mg ion implantation on the back side, and annealing activation.

[0022] Preferably, the preparation method of magnetron sputtering is the same as that of forward epitaxy, except that the growth of a p-type AlN-based heterocurrent collector layer on the substrate is replaced by: using a magnetron sputtering Mg-Al alloy target on an n-type AlN-based heterocurrent collector layer. - Mg-doped AlN is deposited on the back side of the gallium oxide drift region, followed by annealing.

[0023] The present invention also provides the application of the gallium oxide insulated gate bipolar transistor with p-type AlN-based heterocollector in the field of high voltage and high power electronics.

[0024] This invention also provides the application of p-AlN / n-Ga2O3 heterojunction in the field of two-terminal power diodes.

[0025] Compared with the prior art, the present invention has achieved the following beneficial effects: This invention addresses the problem of insufficient p-type doping in gallium oxide and the difficulty in achieving bipolar conduction in insulated-gate bipolar transistors (IGBTs) using traditional gallium oxide devices. It proposes a novel structure for a gallium oxide IGBT with a p-type AlN-based heterocollector. By using the AlN / Ga2O3 heterointerface, hole injection and drift region conductance modulation are achieved, thereby overcoming the limitation of on-resistance imposed by the unipolar conduction mechanism of gallium oxide devices and improving the quality of the collector junction interface and the reliability of the device.

[0026] This invention utilizes the lower interface valence band barrier corresponding to the type II band arrangement that can be formed in AlN / Ga2O3 heterojunctions under specific preparation and interface conditions. Under a reasonable forward bias, it achieves collector hole injection and drift region conductance modulation, overcoming the shortcomings of existing heterojunction collector schemes such as high injection barriers and insufficient material compatibility. At the same time, it uses the large interface conduction band shift brought about by the ultra-wide bandgap of AlN to suppress electron reverse injection and improve the high voltage stability of the collector junction. Furthermore, it solves the practical problems of low p-type AlN doping efficiency and ohmic contact difficulties through composite layer engineering methods such as superlattice, delta doping, polarization enhancement, and p-GaN contact cap layers, combining band advantages with engineering feasibility. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of this invention, the accompanying drawings used in the embodiments of this invention or in the prior art are briefly described below. For those skilled in the art, other drawings can be derived from the following drawings without creative effort, and all such drawings are within the protection scope of this invention.

[0028] Figure 1 A schematic diagram of the device structure of a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector provided by the present invention (taking a trench gate as an example). Figure 2 In this invention, the p-type AlN-based heterocurrent collector layer and the n - Equilibrium band diagram of heterojunction in gallium oxide drift region (Simulation results of computer-aided design for process and device). Figure 3 Two-dimensional hole concentration distribution of a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector provided for this invention in the forward conduction state (Vg=8V, Vce=10V) (Simulation results of computer-aided design for process and device). Figure 4 Output characteristic curves of gallium oxide insulated gate bipolar transistor with p-type AlN-based heterocollector provided for this invention (process and device computer-aided design simulation results). Figure 5 The longitudinal electric field distribution of the gallium oxide insulated gate bipolar transistor with p-type AlN-based heterocollector provided by the present invention in the off state (Vce=2000V) (TCAD simulation results of process and device computer-aided design). Figure 6 A schematic diagram of the process flow for fabricating a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector according to the present invention (taking forward epitaxy and back-side integration as examples). Figure 7The geometric morphology of the trench gate of the gallium oxide insulated gate bipolar transistor with p-type AlN-based heterocollector provided by the present invention is shown in the following figure: where a is a standard rectangular trench gate, b is a beveled trench gate, c is a rounded trench gate, and d is a circular arc trench gate. Figure 8 A deformation diagram of the shielding gate geometry of the trench gate of a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector provided by the present invention. Figure 9 A schematic diagram of the device structure of a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector provided by the present invention (taking a planar gate as an example). Figure reference numerals: 1 is the current collector, 2 is the p-type AlN-based heterocurrent collector layer, 3 is the n-type current collector layer. + Gallium oxide field-stop layer, 4 is n - Gallium oxide drift region, 5 is the insulating layer, 6 is the gate, 7 is the p-type body region, 8 is the p-type... + Body contact area, 9 is n + In the source region, 10 is the emitter metal layer, and 11 is the shielding electrode. Detailed Implementation

[0029] This invention provides a gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector, wherein the gate structure is a trench gate or a planar gate; the structure of the trench gate (e.g.) Figure 1 (As shown) includes: a periodic unit structure along the horizontal direction, and sequentially includes an emitter metal layer, n... + Source region and p + Body contact area, p-type body area, n - Gallium oxide drift region, p-type AlN-based heterocollector layer and collector metal; also includes the emitter metal layer, n + Source region and p + A trench gate structure with a body contact region and a p-type body region arranged side-by-side at the center. From top to bottom, the trench gate structure includes a gate, an insulating layer covering the bottom and sides of the gate, and the insulating layer and the p-type body region together cover the n-type body region. - Gallium oxide drift region, the side of the insulating layer is connected to the emitter metal layer and n from top to bottom. + Source region, p-type body region and part of n - Gallium oxide drift region contact; planar gate structure (e.g.) Figure 9 (As shown) includes: a periodic unit structure along the horizontal direction, and sequentially includes an emitter metal layer and a planar gate structure from top to bottom along the vertical direction, n + Source region and p + Body contact area, p-type body area, n -Gallium oxide drift region, p-type AlN-based heterocollector layer, and collector metal; the planar gate structure, from top to bottom, includes a gate, an insulating layer enclosing the bottom and sides of the gate, and the insulating layer and the p-type body region together cover the n-type gate. - Gallium oxide drift region, inner surface of p-type body region and n - Partial lateral contact of the gallium oxide drift region.

[0030] In this invention, the definition and calculation formula of band offset are as follows: Valence band shift (VBO): VBO = Ev(Ga2O3) - Ev(p-type AlN-based heterocurrent collector layer); Conduction band shift (CBO): CBO = Ec(Ga2O3) - Ec(p-type AlN-based hetero collector layer).

[0031] The experimental evidence for the band shift comes from two independent measurements: H. Sun et al. (APL, 2017) first determined the VBO of the β-Ga₂O₃ / AlN heterojunction to be approximately -0.55 ± 0.05 eV and the CBO to be approximately -1.75 ± 0.05 eV using high-resolution XPS, confirming a type II staggered band arrangement. In 2025, a polarity-dependent study further revealed that the VBO and CBO for Al-polarized and N-polarized AlN were approximately -0.64 eV and -1.84 eV, respectively, indicating consistent band types. Both sets of data jointly show that the AlN valence band top is approximately 0.55–0.64 eV higher than the gallium oxide valence band top, forming a relatively moderate valence band step at the heterojunction; the absolute value of the conduction band shift is approximately 1.75–1.84 eV, creating a higher potential barrier for electrons at the collector junction. Compared with the previously reported NiO / Ga2O3 system (VBO absolute value on the order of approximately 1.6 eV), AlN / Ga2O3 has a lower hole injection barrier and a larger conduction band shift absolute value, forming a better combination in terms of both hole injection efficiency and electron blocking capability.

[0032] In terms of device physics, VBO < 0 means that during forward conduction, collector holes must overcome an interface valence band barrier on the order of |VBO| to enter the gallium oxide drift region. This barrier can be overcome under actual forward bias through thermal emission or interface-assisted injection mechanisms. The smaller the barrier, the lower the required forward bias, which is more conducive to low on-state voltage drop design. A larger |CBO| effectively suppresses reverse leakage of electrons from the drift region to the collector side in the off-state, helping to maintain the off-state blocking performance.

[0033] As a specific embodiment of the present invention Figure 2 In this invention, the p-type AlN-based heterocurrent collector layer and the n -The equilibrium band diagram of the heterojunction in the gallium oxide drift region shows that in a gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterojunction, the valence band offset can range from -0.2 to -2 eV, and the conduction band offset can range from -1.0 to -3.0 eV.

[0034] The gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector provided by this invention has a trench gate structure: As a specific embodiment of the present invention, the emitter metal layer and n + Source region, p + The body contact region can employ ohmic contacts, and the ohmic contact electrode can be a metal combination of Ti / Al / Ni / Cu or a metal combination of Ti / Al / Pt / Cu; the n at the top of the p-type body region + Source region and p + The body contact area is shorted by the emitter metal layer to prevent parasitic conduction caused by the floating potential of the p-type body region.

[0035] As a specific embodiment of the present invention, n + The source region can be n + GaN source region or n + AlGaN source region; p + The bulk contact region can be Mg heavily doped p + GaN region or p + AlGaN region.

[0036] In a specific embodiment of the present invention, the p-type body region can be p-GaN or p-AlGaN. The p-type body region is located on both sides of the trench gate and serves to establish the gate-controlled inversion channel and the depletion channel during turn-off. The present invention employs the aforementioned p-type body region to utilize its mature p-type doping process and excellent gate control performance.

[0037] As a specific embodiment of the present invention, n - An n-type heterocollector layer can also be provided between the gallium oxide drift region and the p-type AlN-based heterocollector layer. + Gallium oxide field-stop layer. - The gallium oxide drift region, located beneath the p-type body region, is responsible for the device's main breakdown voltage function. Its thickness and doping concentration are designed according to the target breakdown voltage. - n can be set below the gallium oxide drift region + Gallium oxide field-stop layer, with a doping concentration higher than n - Gallium oxide drift regions are used to adjust the longitudinal electric field distribution and together with the p-type AlN-based heterojunction form a heterojunction; if n is not specified... + Gallium oxide field-stop layer, p-type AlN-based heterocollector layer can be directly connected with n - Gallium oxide drift region contact.

[0038] n + Gallium oxide field-stop layers are used to adjust the longitudinal electric field distribution and turn-off characteristics, with or without n + Both structures of the gallium oxide field stop layer are within the protection range.

[0039] As a specific embodiment of the present invention, a p-type AlN-based heterocurrent collector layer and an n - An AlN ultrathin layer can be deposited between the gallium oxide drift regions; the thickness of the AlN ultrathin layer can be 1~3 nm, specifically 2 nm. This is achieved between the p-type AlN-based heterocollector layer and the n-type AlN-based heterocollector layer. - The tunnel junction structure, in which an ultrathin AlN layer is inserted between gallium oxide drift regions, enables hole injection by crossing the valence band barrier through quantum tunneling.

[0040] As a specific embodiment of the present invention, the p-type AlN-based heterocollector layer may include one or more of the following: Mg-doped p-AlN monolayer, Mg-doped p-AlGaN layer, p-AlInN ternary alloy, δ-doped AlN, p-AlN / AlGaN superlattice, AlN / GaN superlattice, p-AlN / p-GaN composite layer, p-AlGaN / AlN composite layer, p-GaN ohmic contact cap layer, and p-AlGaN ohmic contact cap layer; the δ-doped AlN may be periodic Mg δ-doped AlN. The p-type AlN-based heterocollector layer is defined as an engineerable tunable composite material system located at the bottom of the device, serving as both the hole supply region and the p-type region on the collector side.

[0041] As a specific embodiment of the present invention, the content of Al component in the Mg-doped p-AlGaN layer can be 30~100%, specifically 50% or 75%.

[0042] As a specific embodiment of the present invention, the AlN / GaN superlattice can be an AlN / GaN polarization-enhanced superlattice.

[0043] Mg-doped p-AlN monolayers serve as the core interface layer, directly forming heterojunctions with gallium oxide; δ-doped AlN improves the equivalent activation concentration through periodic Mg δ-doped layers; Mg-doped p-AlGaN, by adjusting the Al composition, can flexibly balance |VBO|, Mg activation rate, and processing difficulty, making it the most direct and approximately equivalent substitute for Mg-doped p-AlN monolayers; p-AlInN ternary alloys can further reduce the lattice mismatch with Ga2O3 through In composition; p-AlN / AlGaN superlattices utilize the piezoelectric polarization field at the heterojunction to assist Mg ionization, thereby increasing the effective hole concentration; AlN / GaN superlattices utilize polarization-induced... Hole injection enhances the overall hole supply; a p-AlN / p-GaN composite layer, with a thin layer of p-AlN directly contacting gallium oxide to retain the bandgap advantage, and a thick layer of p-GaN stacked on top to provide an efficient hole source and low bulk resistivity; a p-AlGaN / AlN composite layer, with AlGaN of medium Al composition replacing pure AlN to balance the difficulty of p-type doping and bandgap adjustment; a p-GaN or p-AlGaN ohmic contact cap layer, disposed at the bottom of the p-type AlN-based hetero collector layer to reduce the collector metal contact resistance. The engineering design of the p-type AlN-based hetero collector layer composite layer is one of the key aspects of this invention. The above embodiments are all technically equivalent solutions to achieve the same hole injection function, and the above embodiments can be used individually or in combination.

[0044] As a specific embodiment of the present invention, the p-type body region (gate control function) and the p-type AlN-based heterocollector layer (hole injection function) are relatively independent in terms of functional positioning and material selection. They can be optimized separately, and there is generally no hard relationship between them that determines each other.

[0045] As a specific embodiment of the present invention, the collector and the p-type AlN-based hetero collector layer can be in ohmic contact, and the ohmic contact electrode can be a metal combination of Ti / Al / Ni / Cu or a metal combination of Ti / Al / Pt / Cu.

[0046] As a specific embodiment of the present invention, such as Figure 7 As shown, the trench geometry of the trench grid can be a standard rectangular trench grid, an angled trench grid, a rounded trench grid, or a circular arc trench grid. This invention does not impose special requirements on the trench geometry of the trench grid. Based on the standard rectangular trench grid, various modifications can be made to the trench geometry: angled or rounded trenches can smooth out electric field concentration at the bottom and corners of the trench, reducing the risk of localized breakdown of the grid dielectric.

[0047] As a specific embodiment of the present invention, such as Figure 8As shown, the trench gate may also include a shielding electrode, which can be disposed in the lower part of the trench and short-circuited to the collector. The shielding electrode, short-circuited to the source, forms a split-gate structure in the lower part of the trench, transferring the high electric field region below the shielding electrode and further protecting the gate oxide layer.

[0048] The morphological deformation of the trench gate described above in this invention does not affect the overall longitudinal structure of the p-AlN-based collector layer and the device. The sidewall angle, bottom radius of curvature, and shielding electrode depth are all structural parameters that can be independently optimized.

[0049] The gallium oxide insulated gate bipolar transistor (GaO) with a p-type AlN-based heterocollector provided by this invention has a gate structure and device topology that are not limited to the above-described schemes. For example, a planar gate can replace a trench gate, which can reduce the process requirements for the aspect ratio of gallium oxide etching. The device topology can be a vertical power device or a lateral power device, with the collector and emitter located on the same side of the device surface. The p-type AlN-based heterocollector layer is locally embedded near the surface of the gallium oxide epitaxial layer, which is suitable for low-voltage monolithic integration applications.

[0050] The gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector provided by the present invention, when the gate structure is a planar gate, can have the same parameters as the trench gate except for the difference in the gate structure mentioned above, and will not be repeated here.

[0051] The gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector provided by this invention has the following output characteristics: Figure 4 As shown, the working principle is as follows: 1) As Figure 5 As shown, in the off state, the gate is at zero bias or negative bias, and the p-type body region depletes the trench sidewalls. + Source region to n - The electron channels in the gallium oxide drift region are pinched off. A reverse-biased heterojunction is formed between the p-type AlN-based heterocollector layer on the collector side and the n-type gallium oxide, and the depletion region shifts towards the less doped n-type... - Gallium oxide drift region extends longitudinally, n - The gallium oxide drift region bears the main blocking voltage. Due to the large absolute value of CBO, a high potential barrier is formed on the conduction band side of the collector junction in the reverse bias state, effectively suppressing leakage current and ensuring blocking performance in the off state. 2) For example Figure 3 As shown, in the forward conduction state, when a positive bias voltage exceeding the threshold is applied to the gate, an n-type inversion channel is formed in the p-type body region of the trench sidewall, allowing electrons to flow from the n-type gate. + The source region enters n via the channel - Gallium oxide drift regions are transported towards the collector. As the collector forward bias increases, the p-type AlN-based hetero collector layer and the n-type gallium oxide hetero collector junction are forward biased. Holes on the collector side overcome the interface valence band barrier and are injected into the n-type hetero collector junction under the forward bias.- Gallium oxide drift region. Injected holes and n - In the gallium oxide drift region, electrons collectively form a high-concentration plasma, enabling n - Conductivity modulation occurs in the gallium oxide drift region, significantly reducing the equivalent resistance and enabling the device to operate with a low on-state voltage drop. The conductivity modulation effect is jointly determined by the magnitude of the valence band barrier at the collector junction interface, the effective hole concentration of the p-type AlN-based heterocollector layer, and the forward bias voltage of the collector.

[0052] The present invention also provides a method for fabricating a gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector according to the above scheme, which can be a forward epitaxial method, a back-side integration method, a surface activated bonding method (SAB), an atomic layer deposition method (ALD), or a magnetron sputtering method.

[0053] As a specific embodiment of the present invention, such as Figure 6 As shown, the forward epitaxial method for fabricating a gallium oxide insulated-gate bipolar transistor with a trench gate structure and a p-type AlN-based heterocollector may include the following steps: growing a p-type AlN-based heterocollector layer on a substrate, and then epitaxially growing no on the p-type AlN-based heterocollector layer. - Gallium oxide drift region, n - Selective epitaxy or deposition of p-type bulk regions above gallium oxide drift regions, forming n-type bulk regions. + Source region and p + The body contact region is dry-etched into trenches, and gate dielectric and gate conductor are deposited. The emitter and gate are metallized, and the growth substrate is thinned or removed on the back side. A collector metal ohmic contact is made on the back side of the exposed p-type AlN-based hetero collector layer to obtain a gallium oxide insulated gate bipolar transistor with a p-type AlN-based hetero collector.

[0054] As a specific embodiment of the present invention, in the forward epitaxy method, the substrate can be a sapphire substrate, a Si substrate, a GaN substrate, a SiC substrate, or an AlN substrate; the thickness of the substrate can be 100nm~1000μm, specifically 200nm, 500nm, 1μm, 10μm, 100μm, or 500μm.

[0055] As a specific embodiment of the present invention, in the forward epitaxy method, the epitaxy n - The methods for gallium oxide drift regions can be metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0056] As a specific embodiment of the present invention, in the forward epitaxy method, when an n-type AlN-based heterocollector is provided in a gallium oxide insulated-gate bipolar transistor having an n-type AlN-based heterocollector... + Gallium oxide field-stop layer, epitaxial n +The methods for creating gallium oxide field cutoff layers can be metal-organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), or molecular beam epitaxy (MBE).

[0057] The forward epitaxial path starts with a p-type AlN-based heterocollector layer as the substrate and gradually completes the device fabrication from bottom to top.

[0058] As a specific embodiment of the present invention, such as Figure 6 As shown, the fabrication of a gallium oxide insulated-gate bipolar transistor with a trench gate structure and a p-type AlN-based heterocollector using the back-side integration method may include the following steps: fabricating n - Epitaxial wafers in gallium oxide drift regions are selectively grown with p-type bulk regions, and n-type bulk regions are formed on the p-type bulk regions. + Source region and p + In the body contact region, dry etching forms trenches, depositing the gate dielectric and gate conductor, and metallizing the emitter and gate. - After thinning the back side of the gallium oxide drift region, a p-type AlN-based hetero collector layer is integrated, and the collector is metallized to obtain a gallium oxide insulated gate bipolar transistor with a p-type AlN-based hetero collector.

[0059] As a specific embodiment of the present invention, in the back-side integration method, when an n-type AlN-based heterocollector is provided in a gallium oxide insulated-gate bipolar transistor having a p-type AlN-based heterocollector... + Gallium oxide field-stop layer, fabrication of n - During the epitaxial fabrication of gallium oxide drift regions, n-type epitaxial wafers can also be fabricated simultaneously. + An epitaxial wafer with a gallium oxide field-stop layer. This invention addresses n... - Gallium oxide drift region or n + There are no special requirements for the fabrication method of the epitaxial wafer with the gallium oxide field stop layer; conventional processes in the field are used to complete the n... - / n + Devices can be fabricated on the front side of a Ga2O3 epitaxial wafer.

[0060] As a specific embodiment of the present invention, in the back-side integration method, the p-type AlN-based heterocurrent collector layer can be integrated by surface activation bonding or back-side deposition; the back-side deposition method can be magnetron sputtering, molecular beam epitaxy (MBE) or pulsed laser deposition (PLD).

[0061] Backside integration is compatible with existing gallium oxide frontside processes, but it has high requirements for bonding interface quality and backside process temperature window control.

[0062] As a specific embodiment of the present invention, a gallium oxide insulated-gate bipolar transistor with a trench gate structure and a p-type AlN-based heterocollector is prepared by surface activation bonding method. The preparation method is the same as that of forward epitaxy, except that n is epitaxially grown on the p-type AlN-based heterocollector layer. - The gallium oxide drift region is replaced by: an epitaxial wafer with a separately fabricated p-type AlN-based heterocollector layer and an n-type AlN-based heterocollector layer. - Epitaxial wafers in the gallium oxide drift region are directly bonded. This invention bypasses the process challenges of epitaxial AlN on gallium oxide through surface activation bonding.

[0063] As a specific embodiment of the present invention, in the surface-activated bonding method, when an n-type AlN-based heterocollector is provided in a gallium oxide insulated-gate bipolar transistor having a p-type AlN-based heterocollector electrode... + Gallium oxide field-stop layer, n + The fabrication method of gallium oxide field cutoff layer can be compared with n - The gallium oxide drift region is the same.

[0064] As a specific embodiment of the present invention, a gallium oxide insulated-gate bipolar transistor with a trench gate structure and a p-type AlN-based heterocollector is fabricated using atomic layer deposition (ALD). The fabrication method is the same as that of forward epitaxy, except that instead of growing a p-type AlN-based heterocollector layer on the substrate, AlN is deposited using ALD, followed by backside Mg ion implantation and annealing activation. ALD allows for precise control of interface quality and the thickness of the p-type AlN-based heterocollector layer.

[0065] As a specific embodiment of the present invention, a gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector and a trench gate structure is fabricated by magnetron sputtering. The fabrication method is the same as that of forward epitaxy, except that the p-type AlN-based heterocollector layer is grown on the substrate instead of the substrate by magnetron sputtering a Mg-Al alloy target on the n-type AlN-based heterocollector layer. - Mg-doped AlN is deposited on the back side of the gallium oxide drift region, followed by annealing.

[0066] In magnetron sputtering, p-type conductivity is achieved by combining magnetron sputtering with high-temperature annealing. This approach is highly compatible with existing back-side processes and has strong engineering practical value.

[0067] In this invention, the gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector and a planar gate structure is fabricated in the same way as the gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector and a trench gate structure, except for the position of the gate structure, which will not be described in detail here.

[0068] The present invention also provides the application of the gallium oxide insulated gate bipolar transistor with p-type AlN-based heterocollector in the field of high voltage and high power electronics.

[0069] This invention provides a gallium oxide insulated-gate bipolar transistor (IGBT) with a p-type AlN-based heterocollector. It constructs the heterocollector of a β-Ga₂O₃ IGBT using a p-type AlN-based material, thus forming a novel structure for an IGBT with a p-type AlN-based heterocollector. This provides a new technical path for realizing IGBT devices in the gallium oxide material system. The physical basis lies in the type II band arrangement of the AlN / β-Ga₂O₃ heterojunction, where VBO is approximately -0.55 to -0.64 eV and CBO is approximately -1.75 to -1.84 eV, which is beneficial for achieving collector hole injection at a lower potential barrier. Meanwhile, |CBO| is approximately 1.75 to 1.84 eV, which can form a higher potential barrier for electrons, suppressing reverse leakage in the off-state. Therefore, the asymmetric barrier combination of a smaller hole barrier and a larger conduction band barrier formed by the AlN / β-Ga2O3 heterocell is the key and core of this invention, which distinguishes it from existing gallium oxide power device structures.

[0070] This invention also provides the application of p-AlN / n-Ga2O3 heterojunction in the field of two-terminal power diodes.

[0071] The p-AlN / n-Ga2O3 heterojunction constructed by this invention, and its extended application in the field of power diodes at both ends, also fall within the scope of protection of this invention.

[0072] In summary, this invention utilizes a p-type AlN-based heterocollector layer to realize a novel β-Ga₂O₃ insulated-gate bipolar transistor, overcoming the technical limitation of not being able to realize bipolar conducting devices due to the lack of p-type β-Ga₂O₃ material. Compared with previously reported solutions, this invention has the following advantages in terms of hole injection, electron blocking, material stability, and engineering implementation: (1) The hole injection barrier is significantly reduced, and the on-state voltage drop is even lower. High-resolution XPS measurements of the β-Ga2O3 / AlN heterojunction show a VBO of approximately -0.55±0.05 eV and a CBO of approximately -1.75±0.05 eV, indicating a type II staggered arrangement. Polarity-dependent studies further show a VBO of approximately -0.64±0.5 eV and a CBO of approximately -1.84±0.3 eV, both confirming a type II arrangement. In contrast, the VBO of NiO / β-Ga2O3 varies between 2.12 and 2.66 eV under different orientations. The AlN collector exhibits significantly improved injection efficiency under the same forward bias, resulting in a lower forward voltage drop at the collector junction, which is more conducive to achieving effective conductance modulation at ultra-high voltage levels.

[0073] (2) The electron blocking capability in the off-state is significantly stronger. The conduction band shift of NiO / Ga2O3 is only about 0.3 eV, which is almost ineffective in blocking electrons from leaking to the collector side in the off-state; while the present invention has |CBO|≈1.75~1.84 eV, and the large conduction band shift (|CBO|≥1.50 eV) strongly confines the charge carriers and effectively suppresses leakage current, resulting in superior turn-off blocking characteristics. These two advantages together achieve a performance trade-off that is superior to the NiO scheme in both the on and off states.

[0074] (3) It has comprehensive advantages in terms of band gap, thermal conductivity and lattice matching. AlN has a band gap of about 6.2 eV and a thermal conductivity of over 300 W / (m·K). Its lattice mismatch with the β-Ga2O3(-201) plane is only about 2.4%, which is far superior to the previously reported p-type oxides such as NiO (band gap of about 3.7 eV and thermal conductivity of about 6 W / (m·K)). The smaller lattice mismatch leads to a lower interface defect state density. AlN's high melting point and chemical stability ensure the long-term reliability of the device. The wider band gap also results in a lower intrinsic carrier concentration at the collector at high temperatures, which further ensures the blocking capability.

[0075] (4) The engineered design of the composite layer provides a feasible path to alleviate the problems of low doping efficiency and difficulty in ohmic contact of p-type AlN. Through superlattice, delta doping, polarization enhancement and p-GaN ohmic contact cap layer, the effective hole concentration can be adjusted by the Mg doping concentration, and the collector ohmic contact problem can also be alleviated by the p-GaN cap layer, making the present invention not only advantageous in bandgap design but also engineering feasible. In addition, compared with gallium oxide monopole devices, bipolar conductivity modulation, through minority carrier injection and conductivity modulation, is expected to reduce the on-resistance determined by the monopole drift region at the same voltage level, with particularly significant advantages in conduction loss in ultra-high voltage applications above 10kV.

[0076] The embodiments of the present invention have been described above; however, these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. All other embodiments obtained by those skilled in the art based on the above embodiments of the present invention without inventive effort are within the protection scope of the present invention.

Claims

1. A gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector, characterized in that, The gate structure can be a trench gate or a planar gate; the trench gate structure includes: a periodic unit structure along the lateral direction, and, from top to bottom along the longitudinal direction, an emitter metal layer, n... + Source region and p + Body contact area, p-type body area, n - Gallium oxide drift region, p-type AlN-based heterocollector layer and collector metal; also includes the emitter metal layer, n + Source region and p + A trench gate structure with a body contact region and a p-type body region arranged side-by-side at the center. From top to bottom, the trench gate structure includes a gate, an insulating layer covering the bottom and sides of the gate, and the insulating layer and the p-type body region together cover the n-type body region. - Gallium oxide drift region, the side of the insulating layer is connected to the emitter metal layer and n from top to bottom. + Source region, p-type body region and part of n - Gallium oxide drift region contact; the planar gate structure includes: a periodic unit structure along the lateral direction, and sequentially, from top to bottom, an emitter metal layer and a planar gate structure, n + Source region and p + Body contact area, p-type body area, n - Gallium oxide drift region, p-type AlN-based heterocollector layer, and collector metal; the planar gate structure, from top to bottom, includes a gate, an insulating layer enclosing the bottom and sides of the gate, and the insulating layer and the p-type body region together cover the n-type gate. - Gallium oxide drift region, inner surface of p-type body region and n - Partial lateral contact of the gallium oxide drift region.

2. The gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector according to claim 1, characterized in that, n + The source region is n + GaN source region or n + AlGaN source region; p + The bulk contact region is heavily doped with Mg p + GaN region or p + AlGaN region.

3. The gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector according to claim 2, characterized in that, The p-type bulk region is p-GaN or p-AlGaN.

4. The gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector according to claim 1, characterized in that, n - An n-type AlN-based heterocollector layer is also provided between the gallium oxide drift region and the p-type AlN-based heterocollector layer. + Gallium oxide field stop layer.

5. The gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector according to claim 1, characterized in that, p-type AlN-based heterocurrent collector layer and n - An AlN ultrathin layer is disposed between the gallium oxide drift regions; the thickness of the AlN ultrathin layer is 1~3nm.

6. The gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector according to claim 1, characterized in that, p-type AlN-based heterocollector layers include one or more of the following: Mg-doped p-AlN monolayer, Mg-doped p-AlGaN layer, p-AlInN ternary alloy, δ-doped AlN, p-AlN / AlGaN superlattice, AlN / GaN superlattice, p-AlN / p-GaN composite layer, p-AlGaN / AlN composite layer, p-GaN ohmic contact cap layer, and p-AlGaN ohmic contact cap layer; δ-doped AlN is periodic Mg δ-doped AlN.

7. The gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector according to claim 1, characterized in that, The trench geometry of the trench grid can be a standard rectangular trench grid, a beveled trench grid, a rounded corner trench grid, or a circular arc trench grid; the trench grid also includes a shielding electrode, which is located at the bottom of the trench and short-circuited to the collector electrode.

8. A method for fabricating a gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector, characterized in that, The gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector is the gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector as claimed in any one of claims 1 to 7, and is obtained by forward epitaxy, back-side integration, surface activation bonding, atomic layer deposition, or magnetron sputtering.

9. An application of a gallium oxide insulated-gate bipolar transistor with a p-type AlN-based heterocollector in the field of high-voltage, high-power electronics, characterized in that... The gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector is the gallium oxide insulated gate bipolar transistor with a p-type AlN-based heterocollector as claimed in any one of claims 1 to 7.

10. An application of a p-AlN / n-Ga2O3 heterojunction in the field of two-terminal power diodes, characterized in that, The p-AlN / n-Ga2O3 heterojunction is the p-AlN / n-Ga2O3 heterojunction in the gallium oxide insulated gate bipolar transistor having a p-type AlN-based hetero collector as described in any one of claims 1 to 7.

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