An LDMOS based on multi-gradient recombination doped drain and its fabrication method

Abstract

This application discloses an LDMOS based on a multi-gradient composite doped drain and its fabrication method. The LDMOS includes a P-type well region and an N-type drift region fabricated in a substrate. The source region, drain region, and gate region of the LDMOS are sequentially disposed on the P-type well region, the N-type drift region, and the upper surface of the substrate. The gate region is isolated between the P-type well region and the N-type drift region by a gate oxide region. The N-type drift region is a three-segment gradient lightly doped drain region, consisting of a first, second, and third lightly doped drain region sequentially from the substrate to the upper surface of the LDMOS. The junction depth decreases sequentially and the doping concentration increases sequentially from the gate region to the drain region. Because the N-type drift region has a three-dimensional gradient buffer field and a bottom-layer electrostatic shield, it can solve the defects of short-channel electric field penetration and tunneling leakage, thereby physically suppressing DIBL and channel punch-through, significantly reducing GIDL and BTBT tunneling leakage, and solving the short-channel effect and leakage bottleneck of small-size LDMOS.

Description

Technical Field

[0001] This application relates to the field of semiconductor fabrication technology, specifically to an LDMOS based on a multi-gradient composite doped drain and its fabrication method. Background Technology

[0002] DMOS stands for Double-Diffused Metal-Oxide-Semiconductor Field-Effect Transistor, primarily consisting of two types: VDMOS and LDMOS (Laterally Diffused MOSFET). LDMOS, with its advantages of high voltage withstand capability, high transconductance, and high gain, is widely used as a high-voltage power device in radio frequency power integrated circuits. An LDMOS device is composed of hundreds or thousands of single-structure LDMOS cells. In the BCD (Bipolar-CMOS-DMOS) process platform, the LDMOS device is the core component for achieving "high-voltage / high-current power switching capability," working in conjunction with on-chip low-voltage CMOS control and logic, as well as BJTs, ESD protection devices, and isolation devices to complete power conversion and intelligent control on a single chip.

[0003] LDMOS devices belong to the laterally diffused metal-oxide-semiconductor (LDMOS) category. They are widely used in power management, automotive electronics, and power conversion due to their advantages such as low on-resistance, adjustable breakdown voltage, and good process compatibility. For advanced small-size BCD processes, to achieve high chip integration and miniaturization, it is necessary to simultaneously shrink the gate length, drift region length, and cell pitch of LDMOS devices. However, traditional planar LDD-LDMOS suffers from inherent, unavoidable defects at the short-channel scale, severely limiting the performance and yield of high-voltage devices on the nanoscale BCD platform.

[0004] (1) Severe short-channel effect: Traditional monolayer uniform LDD has a single doping profile, and the drain electric field can easily penetrate laterally into the short-channel region, causing significant drain-induced barrier reduction (DIBL), threshold voltage roll-off, and subthreshold characteristic degradation. The short-channel punch-through effect is prominent, and the turn-off stability of small-size devices is extremely poor.

[0005] (2) High reverse leakage current and tunneling leakage current: The electric field is concentrated in the gate-drain overlap region, LDD and P-body junction region, which generates strong gate-induced drain leakage current (GIDL) and interband tunneling (BTBT), resulting in a significant increase in off-state leakage current and substrate reverse leakage current, resulting in high static power consumption and poor reliability of the device.

[0006] (3) Existing improvement schemes have obvious shortcomings: conventional segmented LDD only achieves lateral doping partitioning without vertical gradient, and the diffusion controllability is poor under the nano-shallow junction process; the traditional Halo / Pocket structure is independent of LDD injection, requires additional photolithography mask, increases process cost, and will increase junction capacitance, deteriorate on resistance and device frequency characteristics, and cannot meet the mass production requirements of high density, high performance and small size BCD.

[0007] (4) Poor process compatibility: Most existing multi-step LDD and multi-layer shielding structures are designed for large-size processes of 0.18μm and above. The structure size is too large and the process steps are complicated, which cannot be compatible with small-size nanoscale shallow junction, short trench and high-precision self-alignment process. Summary of the Invention

[0008] The main technical problem addressed by this invention is how to improve the electrical properties of LDMOS devices with small-size multi-stage LDDs.

[0009] According to a first aspect, one embodiment provides an LDMOS based on a multi-gradient composite doped drain, characterized in that it includes a P-type well region and an N-type drift region fabricated in an N-type substrate; the source region of the LDMOS is disposed in the P-type well region; the drain region of the LDMOS is disposed in the N-type drift region; and the gate region of the LDMOS is disposed on the upper surface of the N-type substrate and isolated between the P-type well region and the N-type drift region by a gate oxide region.

[0010] The source connection terminal of the LDMOS is disposed on the source region, the gate connection terminal of the LDMOS is disposed on the gate region, and the drain connection terminal of the LDMOS is disposed on the drain region.

[0011] The N-type drift region is a three-segment gradient lightly doped drain region, which includes a first lightly doped drain region, a second lightly doped drain region, and a third lightly doped drain region sequentially from the substrate to the upper surface of the LDMOS. The first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region exhibit a gradient distribution with decreasing junction depth and increasing doping concentration from the gate region to the drain region.

[0012] The drain region penetrates the third lightly doped drain region and extends into the second lightly doped drain region;

[0013] The first lightly doped drain region is also located below the bottom of the gate region. The junction depth of the first lightly doped drain region is the largest among the three lightly doped drain regions, and the doping concentration is the lowest among the three gradient lightly doped drain regions. This is used to smooth out the electric field spike in the overlapping region of the gate region and the drain region.

[0014] The second lightly doped drain region is adjacent to the first lightly doped drain region. The junction depth of the second lightly doped drain region is smaller than that of the first lightly doped drain region, and the doping concentration is greater than that of the first lightly doped drain region. The lateral doping concentration gradually changes along the direction from the gate region to the drain region to smooth the electric field transition between the gate region and the drain region.

[0015] The third lightly doped drain region is adjacent to the second lightly doped drain region. The junction depth of the third lightly doped drain region is the smallest among the three gradient lightly doped drain regions, and the doping concentration is greater than that of the second lightly doped drain region. It is used as the main current conduction path of the LDMOS.

[0016] In one embodiment, a P-type pocket region is further provided in the first lightly doped drain region. The P-type pocket region is attached to the contact surface between the first lightly doped drain region and the N-type substrate to form the built-in electrostatic shielding barrier of the LDMOS.

[0017] In one embodiment, the P-type well region and the N-type drift region are isolated by the N-type substrate, and the isolation region is disposed below the gate region;

[0018] The P-type pocket region is attached to the N-type substrate side contact surface that isolates the P-type well region and the N-type drift region, and is also attached to the lower contact surface between the first lightly doped drain region and the N-type substrate.

[0019] In one embodiment, the sidewalls of the gate region and the gate oxide region are covered by the insulating layer, which is formed on the source region and the second lightly doped drain region; the insulating layer serves as a sidewall for self-aligned ion implantation.

[0020] In one embodiment, the P-type pocket region covers only the gate region and the first lightly doped drain region under the insulating layer.

[0021] In one embodiment, the insulating layer is made of silicon nitride; the gate region is made of polysilicon.

[0022] According to a second aspect, one embodiment provides a method for fabricating an LDMOS based on a multi-gradient composite doped drain, characterized in that it is used to fabricate an LDMOS as described in the first aspect, the LDMOS fabrication method comprising:

[0023] Complete shallow trench isolation, P-body region implantation and channel threshold adjustment implantation, grow gate oxide region, deposit polysilicon, and form gate region structure by photolithography and etching.

[0024] A gate sidewall dielectric layer is deposited, and an insulating layer is formed on both sides of the gate region by anisotropic etching. The insulating layer is used as a self-aligned mask for subsequent full doping implantation.

[0025] The first N-type oblique ion implantation is performed using a large tilt angle rotation implantation method, so that the ions obliquely penetrate into the region below the bottom of the gate region, forming the first lightly doped drain region with the largest junction depth and the lowest doping concentration below the bottom of the gate region.

[0026] A second N-type oblique ion implantation is performed, using a medium tilt angle rotation implantation method to form a second lightly doped drain region with a lateral doping gradient directly below the vertical projection of the insulating layer. The junction depth of the second lightly doped drain region is smaller than that of the first lightly doped drain region, and the doping concentration is greater than that of the first lightly doped drain region.

[0027] A third N-type near-vertical ion implantation is performed to form a third lightly doped drain region with the smallest junction depth and the highest doping concentration in the N-type drift region outside the insulating layer. The third lightly doped drain region constitutes the main current conduction path of the LDMOS.

[0028] P-type tilt ion implantation is performed, and a P-type pocket region is formed at the bottom of the first lightly doped drain region and the second lightly doped drain region by self-alignment. The outer boundary of the P-type pocket region ends at the outer edge of the insulating layer and does not extend to the third lightly doped drain region and the drain region.

[0029] Annealing activation doping is performed to complete source / drain N-type heavy doping implantation, metallization, and back-end processes, resulting in a lateral double-diffused metal-oxide semiconductor device.

[0030] In one embodiment, the deposition gate sidewall dielectric layer comprises:

[0031] The insulating layer is made of silicon nitride and is deposited using low-pressure chemical vapor deposition with a thickness of 30 nm to 80 nm.

[0032] In one embodiment, the implantation energy of the first N-type oblique ion implantation is 50 keV to 100 keV, the implantation tilt angle is 22° to 28°, and a rotational implantation method is used;

[0033] The second N-type oblique ion implantation has an implantation energy of 15 keV to 30 keV and an implantation tilt angle of 10° to 15°, and adopts a rotational implantation method.

[0034] The third N-type near-vertical ion implantation has an implantation energy of 3keV to 8keV and an implantation tilt angle of 0° to 5°.

[0035] In one embodiment, the dopant element of the P-type tilt ion implantation is boron, the implantation tilt angle of the P-type tilt ion implantation is greater than the implantation tilt angle of the second N-type oblique ion implantation, and the implantation depth of the P-type pocket region is greater than the junction depth of the first lightly doped drain region and the second lightly doped drain region.

[0036] The annealing activation doping adopts a millisecond peak annealing process with an annealing temperature higher than 1000℃ and an annealing time not exceeding 10ms, in order to suppress lateral diffusion of doping and ensure the steep gradient doping profile of the three-segment lightly doped drain region and the P-type pocket region.

[0037] According to the LDMOS of the above embodiment, since the N-type drift region has a three-dimensional gradient buffer field and a bottom electrostatic shield, it can solve the defects of short-channel electric field penetration and tunneling leakage, thereby suppressing DIBL and channel punch-through from a physical level, greatly reducing GIDL and BTBT tunneling leakage, and solving the short-channel effect and leakage bottleneck of small-size LDMOS. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the cross-sectional structure of an LDMOS transistor.

[0039] Figure 2 This is a schematic cross-sectional view of an LDMOS structure in one embodiment;

[0040] Figure 3 This is a schematic flowchart of an LDMOS fabrication method in one embodiment. Detailed Implementation

[0041] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0042] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0043] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0044] Please refer to Figure 1 This is a schematic diagram of the cross-sectional structure of an LDMOS. Planar LDMOS typically uses a gate-N-type drift region (N-drift) for lateral voltage withstand to achieve high-voltage turn-off support. The P-body region of the LDMOS is usually short-circuited to the source. Its core functions are to form a conductive channel, constitute the main breakdown voltage PN junction with the N-drift, and suppress parasitic BJT effects and prevent latch-up by shorting to the source. The functions of shallow trench isolation (STI) include:

[0045] 1) Although the body electrode and the source electrode are shorted in the circuit, the STI between them can physically isolate the direct contact between the source N⁺ and the body P-type silicon, thus avoiding the formation of parasitic PN junctions and additional leakage current.

[0046] 2) STI can block the carrier injection path of parasitic NPN transistors, effectively suppress latch-up effect and device mis-conduction, and improve the reliability of high voltage operation.

[0047] 3) It can smooth the peak value of the source electric field and reduce the body parasitic capacitance, while taking into account the voltage withstand capability and high frequency and switching performance of LDMOS.

[0048] The source, as the current input terminal of an LDMOS (for N-LDMOS), is characterized by a key structural feature: the internal N+ region (providing charge carriers) and the P+ contact region (connecting the body) are shorted in a metal layer, forming a "source-body short." Polysilicon serves as the polysilicon gate, acting as the gate electrode (above the gate oxide, applying voltage to control the opening and closing of the channel below) and extending as a field plate (often extending to cover part of the drift region, becoming a "gate field plate" to smooth the surface electric field). Silicon nitride (Si3N4), as a dielectric material, is used in the process for etching hard masks / stop layers (due to its higher etching selectivity compared to silicon dioxide), passivation protection layers, and stress layers (to improve CMOS performance). In LDMOS, it is usually part of the process, not the active region of the device. The drain is the current output terminal / high voltage withstand terminal of the LDMOS, located at the end of the N-drift region, led out through a metal contact, and withstands a high voltage when the LDMOS is turned off. The P-well and body regions are usually the same area. From a manufacturing perspective, "P-well" emphasizes that it is a P-type doped region formed by ion implantation, used to form the body region of the MOSFET and the necessary PN junction. The N-drift region is the core region for achieving high-voltage capability in LDMOS. Its functions are voltage withstand (lightly doped, sufficient to withstand high voltage during turn-off) and conductivity (providing a path for current from the channel to the drain during turn-on). Its length and doping distribution are key considerations in the trade-off design of breakdown voltage (BV) and specific on-resistance (Ron, sp). The substrate is the mechanical base and common electrical ground of the chip. Its functions are to support all devices, provide electrical isolation (forming a PN junction with the N-type region above), and be connected to the lowest potential (e.g., grounding, providing a path for parasitic currents). The gate region has a gate connection terminal, and the gate oxide region is used to isolate the gate region from the substrate.

[0049] Laterally diffused metal-oxide-semiconductor (LDMOS) devices are widely used in BCD integrated circuit process platforms. As chip integration density continues to increase, the gate length, drift region length, and cell pitch of devices are continuously shrunk to the deep submicron level. Traditional planar lightly doped drain LDMOS devices have the following problems at the short-channel scale: the doping profile of the single-layer uniform lightly doped drain is uniform, and the drain electric field can easily penetrate the short-channel region laterally, causing drain-induced barrier reduction (DIBL), threshold voltage roll-off, and channel punch-through, resulting in a decrease in device turn-off stability; the electric field is concentrated in the gate-drain overlap region and the junction region between the lightly doped drain and the P-type body region, generating gate-induced drain leakage current (GIDL) and interband tunneling (BTBT), leading to an increase in off-state leakage current.

[0050] To address these issues, existing technologies employ segmented lightly doped drains or Halo / Pocket implantation. However, conventional segmented lightly doped drains only achieve lateral doping partitioning, lacking a vertical depth gradient. This results in poor diffusion controllability under shallow nanojunction processes, failing to effectively suppress short-channel punch-through and reverse leakage. Traditional Halo / Pocket structures operate independently of the lightly doped drain implantation process, requiring additional photolithography masks, increasing process costs, and causing increased junction capacitance and deteriorated on-resistance, making them incompatible with small-size, high-density BCD mass production processes. Existing multi-step lightly doped drains and multi-layer shielding structures are mostly designed for processes of 0.18 μm and above, and their structural dimensions and process steps are unsuitable for the requirements of nanoscale shallow junction, short-channel, and high-precision self-aligned processes.

[0051] To address the issues of significant short-channel effect, high reverse leakage current, poor process compatibility, and severe performance trade-offs in existing small-size LDD-LDMOS, this application proposes a three-segment longitudinal and transverse gradient LDD + gate sidewall self-aligned embedded P-type shielding pocket composite structure. Without adding photolithography masks, process steps, or sacrificing on-resistance, it physically suppresses DIBL and channel punch-through, significantly reduces GIDL and BTBT tunneling leakage, and solves the short-channel effect and leakage bottleneck of small-size LDMOS.

[0052] Example 1:

[0053] Please refer to Figure 2 This is a cross-sectional structural diagram of an LDMOS in one embodiment. The LDMOS disclosed in this application is based on a BCD process platform and includes a P-type well region 20 and an N-type drift region fabricated in an N-type substrate 1. The source region 21 of the LDMOS is disposed in the P-type well region 20, the drain region 31 of the LDMOS is disposed in the N-type drift region, and the gate region 2 of the LDMOS is disposed on the upper surface of the N-type substrate 1 and isolated between the P-type well region 20 and the N-type drift region 30 by a gate oxide region. The source terminal of the LDMOS is disposed on the source region 21, the gate terminal of the LDMOS is disposed on the gate region 11, and the drain terminal of the LDMOS is disposed on the drain region 31. The N-type drift region is a three-segment gradient lightly doped drain region, which includes a first lightly doped drain region 32, a second lightly doped drain region 33, and a third lightly doped drain region 34 sequentially from the substrate to the upper surface of the LDMOS. The first lightly doped drain region 32, the second lightly doped drain region 33, and the third lightly doped drain region 34 exhibit a gradient distribution with decreasing junction depth and increasing doping concentration from the gate region 2 to the drain region 31. The drain region 31 penetrates the third lightly doped drain region 34 and extends into the second lightly doped drain region 33.

[0054] The first lightly doped drain region 32 is also located below the bottom of the gate region 2. The junction depth of the first lightly doped drain region 32 is the largest among the three gradient lightly doped drain regions, and the doping concentration is the lowest among the three gradient lightly doped drain regions. It is used to smooth the electric field peak in the overlap region of the gate region 2 and the drain region 31. In one embodiment, the first lightly doped drain region 32 is located below the bottom of the gate and the inner projection of the insulating layer. It is formed by high-energy, large-angle oblique self-aligned implantation. It has the largest junction depth and the lowest doping concentration among the three regions. This region does not bear the main current conduction. It is used to smooth the electric field peak in the gate-drain overlap region, suppress GIDL tunneling, block the drain field from directly entering the channel, and weaken the DIBL effect from the source.

[0055] The second lightly doped drain region 33 is adjacent to the first lightly doped drain region 32. The junction depth of the second lightly doped drain region 33 is smaller than that of the first lightly doped drain region 32, and the doping concentration is greater than that of the first lightly doped drain region 32. The lateral doping concentration gradually changes along the direction from the gate region to the drain region to smooth the electric field transition between the gate region and the drain region. In one embodiment, the second lightly doped drain region 33 is located directly below the vertical projection of the insulating layer and is formed by medium-energy, medium-angle injection. The lateral doping concentration gradually changes to resolve abrupt electric field changes, smooth potential drops, reduce impact ionization and hot carrier degradation, and achieve a smooth electric field transition between the gate and drain regions.

[0056] The third lightly doped drain region 34 is adjacent to the second lightly doped drain region 33. The junction depth of the third lightly doped drain region 34 is the smallest among the three gradient lightly doped drain regions, and its doping concentration is greater than that of the second lightly doped drain region 33. It is used as the main current conduction path of the LDMOS. In one embodiment, the third lightly doped drain region 34 is located in the drift region outside the insulating layer and is formed by low-energy near-vertical injection. It has the smallest vertical junction depth and the highest doping concentration among the three gradient lightly doped drain regions, forming the main current conduction path of the LDMOS device. While maintaining the breakdown voltage characteristics of the drift region, it significantly reduces the series resistance and avoids the on-resistance degradation caused by the multi-segment lightly doped structure. The third lightly doped drain region 34 is used to widen the drain depletion region, weaken the electrostatic coupling of the drain to the channel, and completely suppress the short-channel punch-through effect.

[0057] In one embodiment, a P-type pocket region 35 is further provided within the first lightly doped drain region 32. The P-type pocket region 35 is attached to the contact surface between the first lightly doped drain region 32 and the N-type substrate 1, serving to form the built-in electrostatic shielding barrier of the LDMOS. In another embodiment, the P-type well region 20 and the N-type drift region are isolated by the N-type substrate 1, with the isolation region located below the gate region 2. The P-type pocket region 35 is attached to both the N-type substrate 1 side contact surface that isolates the P-type well region 20 and the N-type drift region, and the lower contact surface between the first lightly doped drain region 32 and the N-type substrate 1.

[0058] In one embodiment, the sides of the gate region 2 and the gate oxide region 11 are covered by an insulating layer 14, which is fabricated above the source region 21 and the second lightly doped drain region 33. The insulating layer 14 serves as a sidewall for self-aligned ion implantation. In one embodiment, the P-type pocket region 35 covers only the gate region 2 and the first lightly doped drain region 32 under the insulating layer 14. In one embodiment, the P-type pocket region forms a continuous P-type shielding layer at the bottom of the first and second lightly doped drain regions through tilt-angle self-aligned implantation. This pocket strictly terminates at the outer edge of the insulating layer and does not extend to the third lightly doped drain region and the drain region. An internal electrostatic shielding barrier is formed between the N-type drift region and the P-type well region, which constrains the depletion region expansion downwards, shields the drain electric field upwards, and blocks the PN junction tunneling path, significantly reducing reverse leakage current.

[0059] In one embodiment, the insulating layer 14 is made of silicon nitride, and the gate region 2 is made of polysilicon.

[0060] The LDMOS disclosed in this application uses the same insulating layer (SiN sidewall) as a self-aligned mask. It forms a three-stage gradient LDD through N-type injection with three different energies and tilt angles. Then, it embeds a P-type shielding pocket in the bottom layer of the LDD through tilt angle self-aligned injection to form a three-dimensional electric field modulation composite structure, which is fully compatible with standard small-size BCD process.

[0061] Please refer to Figure 3 This is a schematic flowchart of an LDMOS fabrication method in one embodiment. This LDMOS fabrication method is used to fabricate the LDMOS described above, and includes:

[0062] Step 101: Prepare the gate.

[0063] The process involves shallow trench isolation, P-body region implantation, and channel threshold adjustment implantation. The gate oxide region is then grown, polysilicon is deposited, and the gate region structure is formed by photolithography and etching.

[0064] Step 102: Prepare the insulating layer.

[0065] A dielectric layer is deposited on the gate sidewalls, and an insulating layer is formed on both sides of the gate region by anisotropic etching. The insulating layer serves as a self-aligned mask for subsequent full doping implantation. In one embodiment, the insulating layer is made of silicon nitride and is deposited using low-pressure chemical vapor deposition with a thickness of 30 nm to 80 nm.

[0066] Step 103: Prepare the first lightly doped drain region.

[0067] The first N-type oblique ion implantation is performed using a large-angle rotational implantation method, allowing ions to penetrate obliquely into the region below the bottom of the gate region, forming the first lightly doped drain region with the largest junction depth and lowest doping concentration below the bottom of the gate region. In one embodiment, the implantation energy of the first N-type oblique ion implantation is 50keV to 100keV, the implantation angle is 22° to 28°, and a rotational implantation method is used.

[0068] Step 104: Prepare the second lightly doped drain region.

[0069] A second N-type oblique ion implantation is performed using a moderate tilt angle rotation implantation method to form a second lightly doped drain region with a laterally doped gradient directly below the vertical projection of the insulating layer. The junction depth of the second lightly doped drain region is smaller than that of the first lightly doped drain region, and the doping concentration is greater than that of the first lightly doped drain region. In one embodiment, the implantation energy of the second N-type oblique ion implantation is 15keV to 30keV, the implantation tilt angle is 10° to 15°, and a rotation implantation method is used.

[0070] Step 105: Prepare the third lightly doped drain region.

[0071] A third N-type near-vertical ion implantation is performed to form a third lightly doped drain region with the smallest junction depth and the highest doping concentration in the N-type drift region outside the insulating layer. This third lightly doped drain region constitutes the main current conduction path of the LDMOS. In one embodiment, the implantation energy of the third N-type near-vertical ion implantation is 3keV to 8keV, and the implantation tilt angle is 0° to 5°.

[0072] Step 106: Prepare the P-type pocket region.

[0073] P-type tilt ion implantation is performed, and a P-type pocket region is formed at the bottom of the first and second lightly doped drain regions through self-alignment. The outer boundary of the P-type pocket region ends at the outer edge of the insulating layer and does not extend into the third lightly doped drain region and the drain electrode region. In one embodiment, the dopant element for P-type tilt ion implantation is boron, the implantation tilt angle of P-type tilt ion implantation is greater than the implantation tilt angle of the second N-type oblique ion implantation, and the implantation depth of the P-type pocket region is greater than the junction depth of the first and second lightly doped drain regions.

[0074] Step 107: Prepare the drain electrode.

[0075] Annealing activation doping is performed to complete source / drain N-type heavy doping implantation, metallization, and back-end processes, resulting in a laterally double-diffused metal-oxide-semiconductor device. In one embodiment, annealing activation doping employs a millisecond spike annealing process with an annealing temperature higher than 1000°C and an annealing time not exceeding 10ms, in order to suppress lateral doping diffusion and ensure a steep gradient doping profile for the three-segment lightly doped drain region and P-type pocket region.

[0076] In this embodiment, all lightly doped drain implantations and P-pocket implantations share the same one-time-formed insulating layer sidewall as a self-aligned mask, requiring no additional photolithography. Therefore, the core step of the above LDMOS fabrication method is:

[0077] 1) The side walls are formed first.

[0078] After the gate etching is completed, a fixed-thickness SiN monolayer (insulating layer) sidewall is deposited and etched to form a rigid shielding boundary for all subsequent doping.

[0079] 2) High-energy injection at large tilt angles.

[0080] The oblique trajectory enters the gate bottom overlap region, forming the deep first lightly doped drain region.

[0081] 3) Energy injection at medium tilt angle.

[0082] The area directly below the sidewall is covered to form a gradient second lightly doped drain region.

[0083] 4) Near-vertical low-energy injection.

[0084] Only the exposed area outside the sidewall of the insulation layer is doped, forming a shallow third lightly doped drain region.

[0085] 5) Injection at tilt angle P.

[0086] A shielding pocket is formed only at the bottom of the first lightly doped drain region and the second lightly doped drain region.

[0087] All doping boundaries are determined entirely by the physical contours of the gate and insulating layers, with no overlay error, making it suitable for the miniaturization requirements of nanoscale high-precision devices.

[0088] The N-type drift region in this embodiment is composed of a three-segment vertically and horizontally gradient integrated lightly doped drain region. Unlike traditional single-layer or ordinary horizontally segmented LDDs, it achieves a three-segment gradient doping of "lightly doped at the gate, gradually increasing doping in the middle section, and relatively high doping at the drain end" through a combination of energy and tilt angle. This forms a concentration-increasing gradient within a unified lightly doped region of the LDD, balancing low leakage current and low on-resistance, decoupling the electric fields at the gate, middle section, and drain end, and adapting to the differentiated electric field control requirements of multiple regions in short-channel devices. Furthermore, a dedicated self-aligned P-type shielding pocket is set at the bottom of the LDD. Unlike traditional channel Halo implantation (located at both ends of the channel, increasing capacitance, and requiring additional photolithography), the P-type pocket region in this application is embedded in the bottom of the LDD and is formed with the LDD through self-alignment. It does not occupy the channel, does not increase the junction capacitance, and does not require additional masks. It is dedicated to shielding the leakage field and blocking tunneling leakage. Furthermore, the insulating layer, acting as a sidewall for multiple injections, eliminates the need for new process flows. The three N-type gradient injections and one P-type shielded injection reuse the same sidewall mask, ensuring full compatibility with the standard BCD process with no cost increase and no process compatibility risks. Moreover, it achieves a fundamental solution to both short-channel and leakage problems. A three-dimensional electric field shield combined with a gradient buffer field simultaneously addresses four major leakage and short-channel failure mechanisms: DIBL, punch-through, GIDL, and BTBT, achieving performance optimization without compromise.

[0089] The principle of LDMOS suppression of DIBL disclosed in the embodiments of this application is as follows:

[0090] Shallow LDD under the gate reduces the gate-drain overlap field strength, and the bottom P-type pocket region forms an electrostatic shielding wall, cutting off the penetration of the drain electric field lines into the short channel. The source barrier is not modulated by the drain voltage, and the threshold roll-off is significantly improved.

[0091] The principle of LDMOS channel punch-through suppression disclosed in this application embodiment is as follows:

[0092] The deep drain-end LDD widens the depletion region, the mid-section has a gentle potential gradient, and the bottom P-type pocket region raises the potential barrier at the bottom of the channel, preventing the source and drain depletion regions from docking and completely eliminating short-channel crossover.

[0093] The principle of LDMOS for GIDL tunneling suppression disclosed in this application embodiment is as follows:

[0094] Shallow doping under the gate eliminates the electric field spike at the gate oxide edge, significantly reducing the interband tunneling probability.

[0095] The principle of LDMOS interrupting the junction drain resistance of BBT disclosed in the embodiments of this application is as follows:

[0096] The bottom P-type shielding layer of the LDD forms a composite potential barrier, constraining the width of the depletion region and cutting off minority carrier tunneling and recombination paths.

[0097] The principle of reducing hot carrier leakage current using LDMOS disclosed in this application is as follows:

[0098] The peak electric field is dispersed by three gradients, which reduces collision ionization, decreases the generation of interface state traps, and improves long-term reliability.

[0099] The LDMOS fabrication method disclosed in this application involves only a slight increase in on-resistance, an improved breakdown voltage, no increase in device area, and no need for additional masks. The mass production cost is completely consistent with existing processes, making it suitable for small-size, high-density BCD mass production, automotive-grade applications, power management, high-voltage I / O, and other scenarios. The LDMOS disclosed in this application is applicable to high-density LDMOS on small-size BCD process platforms, automotive-grade power devices, power management chips, high-voltage I / O devices, RF driver devices, and low-leakage, high-reliability integrated circuits.

[0100] This application discloses an LDMOS based on a multi-gradient composite doped drain, comprising a P-type well region and an N-type drift region fabricated in a substrate. The source region, drain region, and gate region of the LDMOS are sequentially disposed on the P-type well region, the N-type drift region, and the upper surface of the substrate. The gate region is isolated between the P-type well region and the N-type drift region by a gate oxide region. The N-type drift region is a three-segment gradient lightly doped drain region, consisting of a first, second, and third lightly doped drain region sequentially from the substrate to the upper surface of the LDMOS. The junction depth decreases sequentially and the doping concentration increases sequentially from the gate region to the drain region. Because the N-type drift region possesses a three-dimensional gradient buffer field and underlying electrostatic shielding, it can solve the short-channel electric field penetration and tunneling leakage defects, thereby physically suppressing DIBL and channel punch-through, significantly reducing GIDL and BTBT tunneling leakage, and solving the short-channel effect and leakage bottleneck of small-size LDMOS.

[0101] The above examples illustrate this application only to aid understanding and are not intended to limit its scope. Those skilled in the art to which this application pertains can make various simple deductions, modifications, or substitutions based on the ideas presented.

Claims

1. An LDMOS based on a multi-gradient recombination doped drain, characterized in that, It includes a P-type well region and an N-type drift region fabricated in an N-type substrate; the source region of the LDMOS is disposed in the P-type well region; the drain region of the LDMOS is disposed in the N-type drift region; the gate region of the LDMOS is disposed on the upper surface of the N-type substrate and is isolated between the P-type well region and the N-type drift region by a gate oxide region. The source connection terminal of the LDMOS is disposed on the source region, the gate connection terminal of the LDMOS is disposed on the gate region, and the drain connection terminal of the LDMOS is disposed on the drain region. The N-type drift region is a three-segment gradient lightly doped drain region, which includes a first lightly doped drain region, a second lightly doped drain region, and a third lightly doped drain region sequentially from the substrate to the upper surface of the LDMOS. The first lightly doped drain region, the second lightly doped drain region, and the third lightly doped drain region exhibit a gradient distribution with decreasing junction depth and increasing doping concentration from the gate region to the drain region. The drain region penetrates the third lightly doped drain region and extends into the second lightly doped drain region; The first lightly doped drain region is also located below the bottom of the gate region. The junction depth of the first lightly doped drain region is the largest among the three lightly doped drain regions, and the doping concentration is the lowest among the three gradient lightly doped drain regions. This is used to smooth out the electric field spike in the overlapping region of the gate region and the drain region. The second lightly doped drain region is adjacent to the first lightly doped drain region. The junction depth of the second lightly doped drain region is smaller than that of the first lightly doped drain region, and the doping concentration is greater than that of the first lightly doped drain region. The lateral doping concentration gradually changes along the direction from the gate region to the drain region to smooth the electric field transition between the gate region and the drain region. The third lightly doped drain region is adjacent to the second lightly doped drain region. The junction depth of the third lightly doped drain region is the smallest among the three gradient lightly doped drain regions, and the doping concentration is greater than that of the second lightly doped drain region. It is used as the main current conduction path of the LDMOS.

2. The LDMOS as described in claim 1, characterized in that, A P-type pocket region is also provided in the first lightly doped drain region. The P-type pocket region is attached to the contact surface between the first lightly doped drain region and the N-type substrate to form the built-in electrostatic shielding barrier of the LDMOS.

3. The LDMOS as described in claim 2, characterized in that, The P-type well region and the N-type drift region are isolated by the N-type substrate, and the isolation region is disposed below the gate region; The P-type pocket region is attached to the N-type substrate side contact surface that isolates the P-type well region and the N-type drift region, and is also attached to the lower contact surface between the first lightly doped drain region and the N-type substrate.

4. The LDMOS as described in claim 2, characterized in that, The sidewalls of the gate region and the gate oxide region are covered by the insulating layer, which is formed on the source region and the second lightly doped drain region; the insulating layer serves as a sidewall for self-aligned ion implantation.

5. The LDMOS as described in claim 4, characterized in that, The P-type pocket region covers only the gate region and the first lightly doped drain region under the insulating layer.

6. The LDMOS as described in claim 4, characterized in that, The insulating layer is made of silicon nitride; the gate region is made of polysilicon.

7. A method for fabricating LDMOS based on multi-gradient recombination doped drain, characterized in that, The method for preparing the LDMOS as described in any one of claims 1 to 6 comprises: Complete shallow trench isolation, P-body region implantation and channel threshold adjustment implantation, grow gate oxide region, deposit polysilicon, and form gate region structure by photolithography and etching. A gate sidewall dielectric layer is deposited, and an insulating layer is formed on both sides of the gate region by anisotropic etching. The insulating layer is used as a self-aligned mask for subsequent full doping implantation. The first N-type oblique ion implantation is performed using a large tilt angle rotation implantation method, so that the ions obliquely penetrate into the region below the bottom of the gate region, forming the first lightly doped drain region with the largest junction depth and the lowest doping concentration below the bottom of the gate region. A second N-type oblique ion implantation is performed, using a medium tilt angle rotation implantation method to form a second lightly doped drain region with a lateral doping gradient directly below the vertical projection of the insulating layer. The junction depth of the second lightly doped drain region is smaller than that of the first lightly doped drain region, and the doping concentration is greater than that of the first lightly doped drain region. A third N-type near-vertical ion implantation is performed to form a third lightly doped drain region with the smallest junction depth and the highest doping concentration in the N-type drift region outside the insulating layer. The third lightly doped drain region constitutes the main current conduction path of the LDMOS. P-type tilt ion implantation is performed, and a P-type pocket region is formed at the bottom of the first lightly doped drain region and the second lightly doped drain region by self-alignment. The outer boundary of the P-type pocket region ends at the outer edge of the insulating layer and does not extend to the third lightly doped drain region and the drain region. Annealing activation doping is performed to complete source / drain N-type heavy doping implantation, metallization, and back-end processes, resulting in a lateral double-diffused metal-oxide semiconductor device.

8. The LDMOS fabrication method according to claim 7, characterized in that, The deposition gate sidewall dielectric layer includes: The insulating layer is made of silicon nitride and is deposited using low-pressure chemical vapor deposition with a thickness of 30 nm to 80 nm.

9. The LDMOS fabrication method according to claim 7, characterized in that, The first N-type oblique ion implantation has an implantation energy of 50 keV to 100 keV, an implantation tilt angle of 22° to 28°, and adopts a rotational implantation method; The second N-type oblique ion implantation has an implantation energy of 15 keV to 30 keV and an implantation tilt angle of 10° to 15°, and adopts a rotational implantation method; The third N-type near-vertical ion implantation has an implantation energy of 3keV to 8keV and an implantation tilt angle of 0° to 5°.

10. The LDMOS fabrication method according to claim 7, characterized in that, The doping element in the P-type tilt ion implantation is boron. The implantation tilt angle of the P-type tilt ion implantation is greater than the implantation tilt angle of the second N-type oblique ion implantation. The implantation depth of the P-type pocket region is greater than the junction depth between the first lightly doped drain region and the second lightly doped drain region. The annealing activation doping adopts a millisecond peak annealing process with an annealing temperature higher than 1000℃ and an annealing time not exceeding 10ms, in order to suppress lateral diffusion of doping and ensure the steep gradient doping profile of the three-segment lightly doped drain region and the P-type pocket region.

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