DMOS field plate biasing

Abstract

Embodiments of this disclosure relate to DMOS field plate biasing. The semiconductor device includes a drift layer of a first conductivity type disposed on a semiconductor substrate, and a gate electrode disposed above the drift layer via a first insulating film. At least one field plate is disposed above the drift layer and adjacent to the gate electrode via a second insulating film. A drain region of the first conductivity type is positioned in the drift layer at the end of the field plate opposite to the side of the gate electrode. A P-type body region of a second conductivity type, opposite to the first conductivity type, is positioned in the drift layer at the end of the gate electrode opposite to the side of the field plate. A source region of the first conductivity type is positioned in the P-type body region, and the gate electrode and the field plate are spaced apart from each other.

Description

Cross Reference to Related Applications

[0001] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 790,930, filed April 18, 2025, entitled “RESURF AND MULTI-GATE TECHNIQUES FOR LDMOS DEVICES,” filed under 35 USC §119(e), the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure generally relates to the field of semiconductor device manufacturing, and more specifically to drain extended metal-oxide-semiconductor (DMOS) transistors and associated field plate bias structures. Background Technology

[0003] DMOS transistors, with their combination of high voltage withstand capability, high current capability, fast switching characteristics, and robust performance, have become the preferred choice for many power electronics applications. Bipolar-CMOS-DMOS (BCD) technology has become the mainstream process for power management integrated circuits (PMICs), in which DMOS transistors act as primary power processing devices.

[0004] Power devices represent some of the largest contributors to die size and total cost in a PMIC. Specific on-resistance Rsp (typically expressed in mΩ) ·mm 2 Rsp (expressed in units) is one of the main performance metrics for DMOS power devices used in the linear operating region. Rsp reflects the die area utilization efficiency of the device for a given on-state resistance RDSON.

[0005] Compact power devices with low Rsp are highly desirable, and much design effort is dedicated to minimizing this parameter. However, reducing Rsp typically introduces competing trade-offs. For example, reducing on-resistance often requires increasing channel width or reducing drift region resistance, both of which can undesirably increase parasitic capacitance, reduce breakdown voltage, or complicate field plate optimization. Similarly, aggressively reducing drift region or field oxide thickness to decrease resistance can lead to high electric field congestion, adversely affecting device reliability and long-term performance. Summary of the Invention

[0006] According to one embodiment of this disclosure, a semiconductor device includes: a drift layer of a first conductivity type disposed on a semiconductor substrate; a gate electrode disposed above the drift layer via a first insulating film; at least one field plate disposed above the drift layer and adjacent to the gate electrode via a second insulating film; a drain region of a first conductivity type located in the drift layer at an end of the field plate opposite to the side of the gate electrode; a P-type body region of a second conductivity type located in the drift layer at an end of the field plate opposite to the side of the gate electrode, the second conductivity type being opposite to the first conductivity type; and a source region of a first conductivity type located in the P-type body region, the gate electrode and the field plate being spaced apart from each other. Attached Figure Description

[0007] The following detailed description will be best understood in conjunction with the accompanying drawings, which are given by way of example and are not intended to limit the embodiments described herein, in which:

[0008] Figure 1A This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, the semiconductor device including a field plate structure spaced apart from a gate electrode;

[0009] Figure 1B According to one embodiment of this disclosure Figure 1A A top view of a semiconductor device;

[0010] Figure 2 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, the semiconductor device including a field plate structure spaced apart from a gate electrode and a gate oxide formed by an alternative manufacturing process;

[0011] Figure 3 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, the semiconductor device including a plurality of field plates spaced apart from each other and separated from a gate electrode; and

[0012] Figure 4 This is a flowchart depicting the steps of a method for forming a semiconductor device having at least one field plate spaced apart from a gate electrode, according to an embodiment of the present disclosure.

[0013] The accompanying drawings are not necessarily drawn to scale. They are schematic representations only and are not intended to depict specific parameters of the embodiments in this disclosure. The drawings are intended to depict typical embodiments of this disclosure. In the drawings, the same reference numerals denote the same elements. Detailed Implementation

[0014] This document discloses detailed embodiments of the claimed structures and methods; however, it is to be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, which may be embodied in various forms. The claimed structures and methods may be embodied in many different forms and should not be construed as limited to the exemplary embodiments described herein. Details of various conventional features and techniques may be omitted in the description to avoid unnecessarily obscuring the presented embodiments.

[0015] For the purposes described below, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall be used in relation to the disclosed structures and methods oriented as shown in the accompanying drawings. Terms such as “above,” “cover,” “on top,” “on top,” “positioned on,” or “positioned at the top” mean that a first element (such as a first structure) is present on a second element (such as a second structure), wherein an intermediate element (such as an interface structure) may exist between the first and second elements. The term “direct contact” means that the first element (such as a first structure) and the second element (such as a second structure) are connected at the interface between the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0016] To avoid obscuring the presentation of embodiments of this disclosure, in the following detailed description, some processing steps or operations that are conventional in the art may have been combined for presentation and illustration purposes, and in some cases may not have been described in detail. In other cases, some processing steps or operations that are conventional in the art may not be described at all. It should be understood that the following description focuses more on the unique features or elements of the various embodiments of this disclosure.

[0017] Compact DMOS power devices are designed to minimize a specific on-resistance Rsp to achieve high current capability and efficient die utilization. In standard DMOS devices, the half-pitch (defined as the distance between the center of the body region and the center of the drain region) plays a crucial role in determining Rsp. Smaller pitch generally results in lower Rsp. However, aggressive pitch scaling can adversely affect breakdown voltage (BVDSS) and hot carrier injection (HCI) performance due to increased electric field congestion and non-uniform potential distribution in the drift region. Therefore, there is a fundamental trade-off between minimizing Rsp and BVDSS / HCI performance.

[0018] To address this tradeoff, embodiments of this disclosure provide a DMOS device comprising one or more independently biased field plates. In a first variation, a separate field plate structure is provided in addition to the gate electrode. The separate field plate structure is configured to optimize the electric field distribution across the drift region, thereby maximizing breakdown voltage and HCI performance, while enabling a reduced device pitch and lower Rsp. In another variation, the DMOS device comprises multiple (N) field plate structures disposed over the drift region. The biasing or driving techniques described herein can be extended to such multi-field plate configurations, where each field plate structure can be biased to a different potential to achieve finer control of the electric field gradient and further balance the tradeoffs between Rsp, BVDSS, and reliability. These approaches enable scalable and flexible field plate control architectures suitable for integration into advanced BCD and power management processes.

[0019] The following is a reference Figures 1A to 4 The accompanying drawings are used to describe in detail embodiments of DMOS devices that can be formed with single-field plate structures and multi-field plate structures.

[0020] Now for reference Figure 1A A cross-sectional view of a semiconductor device 100, including a field plate structure (hereinafter referred to as "field plate") 130 spaced apart from a gate electrode 126, is shown according to an embodiment of the present disclosure. The semiconductor device 100 is formed on a semiconductor substrate (hereinafter referred to as "substrate") 102, which may be a silicon, silicon-on-insulator (SOI), or silicon carbide (SiC) substrate. The substrate 102 may have a thickness suitable for mechanical support and for isolating high-voltage regions from the bulk.

[0021] A drift layer 106 of a first conductivity type is disposed on the substrate 102. For example, when the semiconductor device 100 is an n-channel DMOS transistor, the first conductivity type of the drift layer 106 is n-type. The drift layer 106 can be epitaxially grown to a desired thickness and doping concentration to establish a predetermined breakdown voltage (BVDSS). The drift layer 106 extends laterally between a body region (or body) 114 on one side and a drain region (or drain) 118 on the opposite side, thereby defining a... Figure 1A The device shown has a half-pitch.

[0022] A p-body region (also referred to as the p-body) 108 of a second conductivity type (e.g., p-type) opposite to that of drift layer 106 is typically formed in the upper portion of drift layer 106 by thermal activation following ion implantation. The p-body region 108 serves to form a pn junction with drift layer 106 to support high-voltage operation. Within the p-body region 108, a source region (or source) 116 of a first conductivity type is formed, for example, by shallow implantation and annealing. The source region 116 provides a low-resistance contact for carrier injection during device turn-on. A heavily doped p+ contact region may optionally be provided within the body region 114 to ensure reliable body contact and suppress parasitic bipolar effects.

[0023] Covering the drift layer 106 and the p-body region 108 is a first insulating film, referred to as gate oxide 124. Gate oxide 124 may be thermally grown silicon dioxide (SiO2) or a stacked oxide / nitride / oxide (ONO) structure having a first thickness h1 varying between approximately 1 nm and approximately 100 nm. Gate electrode 126 is disposed above gate oxide 124 and positioned above the channel region 110 formed in the p-body region 108. Gate electrode 126 may comprise polysilicon, a metal gate material (such as TiN, W, or Al), or a combination thereof, and may be patterned using conventional photolithography and etching techniques.

[0024] Adjacent to the gate electrode 126 is a field plate 130, which is disposed above the drift layer 106 and spaced apart from the gate electrode 126 by a distance d1. The distance d1 can range from approximately 5 nm to approximately 50 µm. The field plate 130 is electrically isolated from the drift layer 106 by a second insulating film, which can be the same material as the gate oxide 124 or a different material. In the embodiment of FIG. 1, the second insulating film corresponds to an extension of the gate oxide 124 having a second thickness h2, which is greater than the thickness h1 of the first insulating film. The second thickness h2 of the second insulating film (the thicker portion of the gate oxide 124) can vary between approximately 1 nm and approximately 5 µm or less. The field plate 130 can be formed of the same conductive material as the gate electrode 126 and can be patterned in separate or simultaneous masking steps.

[0025] A drain region 118 of a first conductivity type is located within the drift layer 106, at the end of the field plate 130 opposite the gate electrode 126. The drain region 118 can be formed by ion implantation followed by annealing to achieve the desired junction depth. The gate electrode 126 and the field plate 130 can be activated simultaneously or independently, depending on the desired device performance. The field plate 130 can be biased to a fixed potential, dynamically driven, or connected via a resistive or capacitive coupling network to customize the electric field distribution across the drift layer 106.

[0026] The spatial separation between the gate electrode 126 and the field plate 130 allows the electric field in the drift layer 106 to be redistributed, thereby reducing the field peak and improving BVDSS and HCI performance without significantly increasing Rsp.

[0027] Figure 1B This is a top (plan) view of a semiconductor device 100 according to an embodiment of the present disclosure, illustrating the relative arrangement of a gate electrode 126, a field plate 130, a source region 116, and a drain region 118. In this view, the gate electrode 126 covers at least a portion of the p-body region 108, while the field plate 130 is positioned adjacent to the gate electrode 126 and does not overlap with it. The field plate 130 extends laterally toward the drain region 118 and covers a portion of the drift layer 106.

[0028] Now for reference Figure 2 This illustration shows a cross-sectional view of a semiconductor device 200 including a field plate 130 spaced apart from a gate electrode 126, according to another embodiment of the present disclosure. In this embodiment, the gate oxide 124 (second insulating film) is formed by an alternative manufacturing process such as local silicon oxidation (LOCOS) or shallow trench isolation (STI). Figure 2 In this document, the same reference numerals are used to identify parts that are the same as or similar to those in Figure 1, and detailed descriptions of such parts are omitted to avoid unnecessary repetition.

[0029] In the LOCOS process, a silicon nitride (SiN) oxide mask is patterned to expose the desired field region, and thermal oxidation is performed to grow a thick field oxide that electrically isolates the field plate 130 from the drift layer 106. Alternatively, in the STI process, trenches are etched into the silicon surface and filled with oxide or high-density plasma (HDP) dielectric material, followed by surface planarization via chemical mechanical polishing (CMP). The insulating film based on STI or LOCOS can have a third thickness h3, which is greater than the first thickness h1 of the gate oxide 124 (the first insulating film), thereby providing enhanced field isolation and improved breakdown characteristics. For example, the third thickness h3 of the second insulating film (i.e., the thicker portion of the gate oxide 124) can vary between approximately 10 nm and approximately 5 µm.

[0030] like Figure 2 The semiconductor device 200 described herein enables flexible process integration while allowing for the use of thicker oxide or trench dielectric regions under the field plate 130 to withstand higher electric fields or optimize parasitic capacitance characteristics.

[0031] Now for reference Figure 3 A cross-sectional view of a semiconductor device 300, comprising a plurality of field plates 130 spaced apart from each other and separated from the gate electrode 126, according to another embodiment of the present disclosure, is illustrated. Figure 3 In this document, the same reference numerals are used to identify parts that are the same as or similar to those in Figure 1, and detailed descriptions of such parts are omitted to avoid unnecessary repetition.

[0032] In this embodiment, a first field plate 130a and a second field plate 130b are disposed on the drift layer 106 and separated by a distance d2. The distance d2 between the first field plate 130a and the second field plate 130b can vary between approximately 1 nm and approximately 10 µm, and includes all values ​​within this range. Each field plate can be independently biased or driven to a different potential to establish a multi-step electric field gradient across the drift layer 106.

[0033] The use of multiple field plates 130 provides finer control over the electric field distribution, thereby further improving breakdown voltage, on-resistance tradeoff, and hot carrier reliability. It should be noted that, although in Figure 3Only two field plates 130 are depicted (e.g., field plates 130a and 130b), but any number of field plates 130 can be provided, depending on the desired device design, voltage rating, and performance requirements. Multiple field plates 130 can be activated simultaneously, biased independently, or driven sequentially from the field plate 130 closest to the gate electrode 126 (e.g., field plate 130a) to the field plate closest to the drain region 118 (e.g., field plate 130b). Such an activation sequence provides additional flexibility in managing the dynamic electric field distribution during high-speed switching events.

[0034] Figure 4 This is a flowchart depicting the steps of a method 400 for forming a semiconductor device including at least one field plate spaced apart from a gate electrode according to an embodiment of the present disclosure. Method 400 can be applied to the fabrication of a reference device. Figures 1A to 3 The semiconductor device described is any semiconductor device, and is applicable to both single-field-board and multi-field-board implementations.

[0035] At step 402, a drift layer of a first conductivity type (e.g., n-type) is formed on the substrate. The drift layer can be epitaxially grown on a silicon, SOI, or SiC substrate to a predetermined thickness and doping concentration selected to achieve the desired breakdown voltage (BVDSS). The substrate can be fabricated using standard cleaning and heat treatment processes to ensure low defect density and uniform epitaxial quality.

[0036] At step 404, a gate electrode is formed over the drift layer via a first insulating film (such as thermally grown silicon dioxide or a high-k dielectric). The first insulating film acts as the gate dielectric and defines the channel control region. The gate electrode may comprise doped polysilicon, a metal gate material, or a metal stack, and is patterned using conventional photolithography and etching techniques.

[0037] At step 406, at least one field plate is formed above the drift layer and adjacent to the gate electrode via a second insulating film. The second insulating film may be an extension of the gate oxide or a separately deposited dielectric layer. In some embodiments, the second insulating film may be formed using a LOCOS process or an STI process, thereby creating a thicker oxide region under the field plate, which is configured to withstand a higher electric field and reduce parasitic capacitance. The field plate is spaced apart from the gate electrode by a predetermined distance and may be patterned from the same or different conductive layers as the gate electrode. When multiple field plates are used, each field plate may be formed and patterned sequentially or defined in a single process, followed by selective electrical interconnection.

[0038] At step 408, a drain region of the first conductivity type is formed in the drift layer at the end of the field plate opposite to the side of the gate electrode. The drain region can be achieved by ion implantation, diffusion, or epitaxial regrowth followed by annealing to obtain the desired junction depth and resistivity.

[0039] At step 410, a P-type body region of a second conductivity type (e.g., p-type), opposite to the conductivity type of the drift layer, is formed in the drift layer at the end of the gate electrode opposite to the side of the field plate. The body region can be implanted and activated to define a channel region below the gate.

[0040] At step 412, a source region of the first conductivity type is formed in the P-type body region, such that the gate electrode and the field plate are spaced apart from each other. The source region provides a low-resistance conductive path during device operation and can be formed using shallow implantation followed by activation annealing.

[0041] The above sequence of steps provides a general manufacturing framework for forming DMOS or LDMOS devices with one or more field plates spaced apart from the gate electrode. Additional process steps such as interlayer dielectric deposition, contact formation, and metallization can then be performed according to typical power device manufacturing techniques. Although Figure 4 The examples illustrate a specific sequence of steps, but those skilled in the art will understand that these steps may be performed in different orders or combined without departing from the scope of this disclosure.

[0042] Example Example 1. A semiconductor device, comprising: A drift layer of a first conductivity type is disposed on a semiconductor substrate; A gate electrode, which is disposed above the drift layer via a first insulating film; At least one field plate is disposed above the drift layer and adjacent to the gate electrode via a second insulating film; The drain region of the first conductivity type is located in the drift layer at one end of the field plate opposite to the side of the gate electrode. A second conductivity type P-type main body region, the P-type main body region being positioned in the drift layer at the end of the gate electrode opposite to the side of the field plate, the second conductivity type being the opposite of the first conductivity type; and The source region of the first conductivity type is located in the P-type body region, wherein the gate electrode and the field plate are spaced apart from each other. Example 2. The semiconductor device according to Example 1, wherein the distance between the gate electrode and the field plate is 5 nm or more and 50 µm or less. Example 3. A semiconductor device according to any one of Examples 1 to 2, wherein The gate electrode does not overlap with the field plate. Example 4. A semiconductor device according to any one of Examples 1 to 3, wherein The second thickness of the second insulating film is greater than the first thickness of the first insulating film. Example 5. The semiconductor device according to Example 4, wherein: The first thickness of the first insulating film is 1 nm or more and 100 nm or less, and The second thickness of the second insulating film is 1 nm or more and 5 µm or less. Example 6. A semiconductor device according to any one of Examples 1 to 5, The first insulating film and the second insulating film are integrally formed into a continuous dielectric structure. Example 7. A semiconductor device according to any one of Examples 1 to 6, The gate electrode covers at least a portion of the P-type body region in a plan view. Example 8. A semiconductor device according to any one of Examples 1 to 7, The gate electrode and the field plate are activated simultaneously. Example 9. A semiconductor device according to any one of Examples 1 to 8, The gate electrode and the field plate are activated independently. Example 10. A semiconductor device according to any one of Examples 1 to 9, The field plate is activated after the gate electrode is activated. Example 11. A semiconductor device according to any one of Examples 1 to 10, The gate electrode and the field plate are each supplied with different voltages. Example 12. A semiconductor device according to any one of Examples 1 to 11, The voltage supplied to the field plate is higher than the voltage supplied to the gate electrode. Example 13. A semiconductor device according to any one of Examples 1 to 12, The second insulating film is formed by localized silicon oxidation (LOCOS) or shallow trench isolation (STI). Example 14. A semiconductor device according to any one of Examples 1 to 13, The field plate is divided into multiple field plates, which are disposed above the drift layer and spaced apart from each other. Example 15. The semiconductor device according to Example 14, The distance between each of the plurality of field plates is 1 nm or more and 10 µm or less. Example 16. A semiconductor device according to any one of Examples 14 or 15, The multiple field plates are activated simultaneously. Example 17. A semiconductor device according to any one of Examples 14 or 15, The multiple field plates are activated independently. Example 18. A semiconductor device according to any one of Examples 14 or 17, The plurality of field plates are activated sequentially, starting from the field plate closest to the gate electrode and ending at the field plate closest to the drain region. Example 19. A semiconductor device according to any one of Examples 14 to 18, The gate electrode and each of the plurality of field plates are each supplied with a different voltage. Example 20. A semiconductor device according to any one of Examples 14 to 19, The voltage supplied to the plurality of field plates is higher than the voltage supplied to the gate electrode. Example 21. A method of forming a semiconductor device, comprising: A drift layer of the first conductivity type is formed on a semiconductor substrate; A gate electrode is formed above the drift layer via a first insulating film; At least one field plate is formed above and adjacent to the gate electrode via a second insulating film; In the drift layer, a drain region of the first conductivity type is formed at one end of the field plate opposite to the side of the gate electrode; In the drift layer, a P-type main region of a second conductivity type is formed at one end of the gate electrode opposite to the side of the field plate, the second conductivity type being the opposite of the first conductivity type; and A source region of the first conductivity type is formed in the P-type body region. The gate electrode is spaced apart from the field plate. Example 22. The method according to Example 21 further includes: The second insulating film is formed using a localized silicon oxidation (LOCOS) process or a shallow trench isolation (STI) process to provide electrical isolation between the field plate and the drift layer. The second insulating film has a thickness greater than that of the first insulating film. Example 23. The method according to any one of Examples 21 to 22, wherein forming the at least one field plate further comprises: The conductive layer is patterned and deposited simultaneously with or independently of the formation of the gate electrode. Example 24. The method according to any one of Examples 21 to 23 further includes: Multiple field plates are formed above the drift layer, spaced apart from each other. Each of the multiple field plates is independently, simultaneously, or sequentially biased or driven to control the electric field distribution across the drift layer. Example 25. The method according to any one of Examples 21 to 24 further includes: The gate electrode and the at least one field plate are activated or biased under static or dynamic driving conditions to maintain the desired electric field distribution and breakdown voltage, wherein the voltage supplied to the field plate is higher than the voltage supplied to the gate electrode.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as used herein. It should also be understood that the terms “comprising” and / or “including”, when used in this specification, designate the presence of said features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” or “optionally” means that an event or condition subsequently described may or may not occur, and the description includes both cases where the event occurs and cases where the event does not occur.

[0044] For ease of description, spatial relative terms such as “inside,” “outside,” “below,” “under,” “lower,” “above,” “upper,” “top,” “bottom,” etc., may be used herein to describe the relationship between one element or feature and another, as shown in the figures. Spatial relative terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the figures. For example, if the device in the figure is flipped, an element described as “below” or “under” other elements or features will be oriented “above” other elements or features. Therefore, the example term “below” can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0045] As used herein and throughout the claims, approximate language may be applied to modify any quantitative expression, which may vary permissibly without altering its underlying function. Therefore, values ​​modified by terms such as “about,” “approximately,” and “substantially” are not limited to the specified exact values. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Here and throughout the description and claims, range limitations may be combined and / or interchanged, and unless otherwise indicated by context or language, such ranges are identified and include all subranges contained therein. “About” applied to a specific value of a range applies to two values, and unless otherwise dependent on the precision of the instrument measuring that value, “about” may indicate + / - 10% of said values(s).

[0046] The description of various embodiments of this disclosure has been presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements relative to technologies found on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor device, comprising: A drift layer of a first conductivity type is disposed on a semiconductor substrate; A gate electrode, which is disposed above the drift layer via a first insulating film; At least one field plate is disposed above the drift layer and adjacent to the gate electrode via a second insulating film; The drain region of the first conductivity type is located in the drift layer at one end of the field plate opposite to the side of the gate electrode. A second conductivity type P-type main body region, the P-type main body region being positioned in the drift layer at the end of the gate electrode opposite to the side of the field plate, the second conductivity type being the opposite of the first conductivity type; and The source region of the first conductivity type is located within the P-type body region. The gate electrode is spaced apart from the field plate.

2. The semiconductor device according to claim 1, The distance between the gate electrode and the field plate is 5 nm or more and 50 µm or less.

3. The semiconductor device according to claim 1, The gate electrode does not overlap with the field plate.

4. The semiconductor device according to claim 1, The second thickness of the second insulating film is greater than the first thickness of the first insulating film.

5. The semiconductor device according to claim 4, wherein: The first thickness of the first insulating film is 1 nm or more and 100 nm or less, and The second thickness of the second insulating film is 1 nm or more and 5 µm or less.

6. The semiconductor device according to claim 1, The first insulating film and the second insulating film are integrally formed.

7. The semiconductor device according to claim 1, The gate electrode, in a plan view, covers part or all of the P-type body region.

8. The semiconductor device according to claim 1, The gate electrode and the field plate are activated simultaneously.

9. The semiconductor device according to claim 1, The gate electrode and the field plate are activated independently.

10. The semiconductor device according to claim 1, The field plate is activated after the gate electrode is activated.

11. The semiconductor device according to claim 1, The gate electrode and the field plate are each supplied with different voltages.

12. The semiconductor device according to claim 11, The voltage supplied to the field plate is higher than the voltage supplied to the gate electrode.

13. The semiconductor device according to claim 1, The second insulating film is formed by localized silicon oxide (LOCOS) or shallow trench isolation (STI).

14. The semiconductor device according to claim 1, The field plate is divided into multiple field plates.

15. The semiconductor device according to claim 14, The distance between each of the plurality of field plates is 1 nm or more and 10 µm or less.

16. The semiconductor device according to claim 14, The multiple field plates are activated simultaneously.

17. The semiconductor device according to claim 14, The multiple field plates are activated independently.

18. The semiconductor device according to claim 14, The plurality of field plates are activated sequentially, starting from the field plate closest to the gate electrode and ending at the field plate closest to the drain region.

19. The semiconductor device according to claim 14, The gate electrode and each of the plurality of field plates are each supplied with a different voltage.

20. The semiconductor device according to claim 14, The voltage supplied to the plurality of field plates is higher than the voltage supplied to the gate electrode.

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