A method for manufacturing a semiconductor structure

Abstract

This application discloses a method for fabricating a semiconductor structure, comprising: providing an initial structure including a substrate, a gate structure, and gate sidewalls; conformally depositing a silicon nitride protective layer on the initial structure; forming a patterned first photoresist layer on the protective layer; subjecting the exposed protective layer to hydrogen plasma treatment and oxidation treatment sequentially to convert the exposed protective layer into a silicon oxide layer; removing the silicon oxide layer by a wet etching process; etching the gate sidewalls and the protective layer by a dry etching process; conformally depositing a contact etch stop layer on the initial structure, and forming a dielectric layer on the contact etch stop layer; patterning the dielectric layer and the contact etch stop layer to form a first contact hole exposing a first metal silicide layer, a second contact hole exposing a second metal silicide layer, and a third contact hole exposing a third metal silicide layer. This application can prevent the metal silicide layer from being etched through.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a method for fabricating a semiconductor structure. Background Technology

[0002] Starting with the 90nm technology node, various stress-inducing techniques to enhance carrier mobility have gradually appeared in CMOS (Complementary Metal-Oxide-Semiconductor) manufacturing. For NMOS, Stress Memorization Technique (SMT) has been used to improve electron mobility. SMT is characterized by its ability to significantly accelerate electron mobility in NMOS devices through tensile stress, thereby increasing the drive current. For PMOS, the method of embedding germanium-silicon (SiGe) in the source / drain regions introduces local compressive strain or Stress Proximity Technology (SPT). This technique, which involves sidewall removal before the formation of the contact etch stop layer (CESL) after self-aligned silicide formation, has demonstrated enhanced CESL proximity and maximized stress transfer from the CESL to the channel. In addition to improved mobility, Stress Proximity Technology also expands the process window for subsequent interlayer dielectric filling.

[0003] Currently, SPT technology generally employs dry etching, using polymer gas plasma to etch silicon nitride sidewalls. The polymer gases mainly include CH2F2 and CH3F. However, due to the limited selectivity between silicon nitride and metal silicides in the etching process, excessive loss of metal silicides can occur, leading to the metal silicides being etched through in subsequent contact hole etching processes.

[0004] Therefore, improvements are needed to at least partially address the aforementioned problems. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To at least partially solve the above problems, according to a first aspect of the present invention, a method for fabricating a semiconductor structure is provided, comprising: An initial structure is provided, the initial structure including a substrate, a gate structure and a gate sidewall, wherein a source region and a drain region are formed on the upper part of the substrate, a first metal silicide layer and a second metal silicide layer are formed on the upper part of the source region and the upper part of the drain region respectively, the gate structure is located above the substrate between the source region and the drain region, the upper part of the gate structure has a third metal silicide layer, and the gate sidewall is located on both sides of the gate structure, the gate sidewall being made of silicon nitride; A protective layer is deposited conformally on the initial structure, wherein the material of the protective layer is silicon nitride; A patterned first photoresist layer is formed on the protective layer, wherein the patterned first photoresist layer exposes the protective layer located on the gate sidewall; The exposed protective layer is subjected to hydrogen plasma treatment and oxidation treatment in sequence to convert the exposed protective layer into a silicon oxide layer and remove the first photoresist layer. The silicon oxide layer is removed by a wet etching process; The gate sidewall and the protective layer are etched using a dry etching process to thin the gate sidewall and remove the protective layer. A conformal deposition of a contact etch stop layer is performed on the initial structure, and a dielectric layer is formed on the contact etch stop layer; The dielectric layer and the contact etch stop layer are patterned to form a first contact hole exposing the first metal silicide layer, a second contact hole exposing the second metal silicide layer, and a third contact hole exposing the third metal silicide layer.

[0007] For example, the oxidation process includes oxygen plasma treatment.

[0008] For example, the oxidation treatment includes performing a thermal oxidation process.

[0009] For example, the oxidation process includes maintaining the sample in an oxygen-containing environment for a predetermined time.

[0010] For example, patterning the etching of the dielectric layer and the contact etch stop layer includes: A patterned second photoresist layer is formed on the dielectric layer; Using the second photoresist layer as a mask, the dielectric layer and the contact etch stop layer are etched by an anisotropic dry etching process to form the first contact hole, the second contact hole and the third contact hole; The patterned first photoresist layer and the patterned second photoresist layer are patterned using the same photomask. The first photoresist layer is a negative photoresist layer, and the second photoresist layer is a positive photoresist layer, or the first photoresist layer is a positive photoresist layer and the second photoresist layer is a negative photoresist layer.

[0011] For example, the gate sidewall includes a first sidewall layer and a second sidewall layer, a first portion of the second sidewall layer is located between the first sidewall layer and the gate structure, and a second portion of the second sidewall layer is located between the first sidewall layer and the substrate; The first sidewall layer is a silicon nitride layer, and the second sidewall layer is a silicon oxide layer.

[0012] According to a second aspect of the present invention, a method for fabricating a semiconductor structure is provided, comprising: An initial structure is provided, the initial structure including a substrate, a gate structure and a gate sidewall, wherein a source region and a drain region are formed on the upper part of the substrate, a first metal silicide layer and a second metal silicide layer are formed on the upper part of the source region and the upper part of the drain region respectively, the gate structure is located above the substrate between the source region and the drain region, the upper part of the gate structure has a third metal silicide layer, and the gate sidewall is located on both sides of the gate structure, the gate sidewall being made of silicon nitride; A patterned first photoresist layer is formed on the initial structure, wherein the patterned first photoresist layer exposes the gate sidewall; The exposed gate sidewall is subjected to hydrogen plasma treatment and oxidation treatment in sequence to form a silicon oxide layer on the surface of the gate sidewall and remove the first photoresist layer. The silicon oxide layer is removed by a wet etching process; A conformal deposition of a contact etch stop layer is performed on the initial structure, and a dielectric layer is formed on the contact etch stop layer; The dielectric layer and the contact etch stop layer are patterned to form a first contact hole exposing the first metal silicide layer, a second contact hole exposing the second metal silicide layer, and a third contact hole exposing the third metal silicide layer.

[0013] For example, the oxidation process includes oxygen plasma treatment.

[0014] For example, the oxidation treatment includes performing a thermal oxidation process.

[0015] For example, the oxidation process includes maintaining the sample in an oxygen-containing environment for a predetermined time.

[0016] According to the semiconductor structure fabrication method of the present invention, damage to the first metal silicide layer, the second metal silicide layer and the third metal silicide layer can be significantly reduced when the gate sidewall is thinned, effectively preventing them from being etched through during subsequent contact hole formation. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions, thereby explaining the apparatus and principles of the invention. In the drawings, Figures 1A-1D These are cross-sectional schematic diagrams of the structures corresponding to each step of the semiconductor structure fabrication method in related technologies; Figure 2 This is a schematic flowchart of a method for fabricating a semiconductor structure according to the first embodiment of this application; Figures 3A-3I This is a cross-sectional schematic diagram of the structure corresponding to each step of the semiconductor structure fabrication method according to the first embodiment of this application; Figure 4 This is a schematic flowchart of a method for fabricating a semiconductor structure according to a second embodiment of this application; Figures 5A-5G This is a cross-sectional schematic diagram of the structure corresponding to each step of the semiconductor structure fabrication method according to the second embodiment of this application.

[0018] Explanation of reference numerals in the attached figures: 10-Substrate, 11-Source region, 12-Drain region, 13-First metal silicide layer, 14-Second metal silicide layer, 20-Gate structure, 21-Third metal silicide layer, 30-Gate sidewall, 40-Contact etch stop layer, 50-Dielectric layer, 61-First contact hole, 62-Second contact hole, 63-Third contact hole; 100 - Substrate, 110 - Source region, 111 - First metal silicide layer, 120 - Drain region, 121 - Second metal silicide layer, 200 - Gate structure, 210 - Third metal silicide layer, 220 - Gate dielectric layer, 230 - Gate layer, 300 - Gate sidewall, 310 - First sidewall layer, 311 - Silicon oxide layer, 320 - Second sidewall layer, 400 - Protective layer, 410 - Silicon oxide layer, 500 - First photoresist layer, 500' - First photoresist layer, 600 - Contact etch stop layer, 700 - Dielectric layer, 800 - Second photoresist layer, 910 - First contact hole, 920 - Second contact hole, 930 - Third contact hole. Detailed Implementation

[0019] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0020] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0021] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part.

[0022] Spatial relation terms such as "below," "under," "below," "under," "above," and "above" are used here for convenience to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of devices in use and operation.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0024] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of this application. Thus, variations in the shown shape are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of this application should not be limited to the specific shapes shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the figures are substantially schematic, and their shapes are not intended to show the actual shape of the device and are not intended to limit the scope of this application.

[0025] See attached document Figures 1A-1D An exemplary method for fabricating semiconductor structures in related technologies is provided, which includes the following steps: Please refer to the appendix first. Figure 1A This provides an initial structure, which includes a substrate 10, a gate structure 20, and gate sidewalls 30. A source region 11 and a drain region 12 are formed on the upper part of the substrate 10, spaced apart. A first metal silicide layer 13 and a second metal silicide layer 14 are formed on the upper parts of the source region 11 and the drain region 12, respectively. The gate structure 20 is located above the substrate 10 between the source region 11 and the drain region 12, and a third metal silicide layer 21 is formed on the upper part of the gate structure 20. Gate sidewalls 30 are located on both sides of the gate structure 20, and the gate sidewalls 30 are made of silicon nitride. The gate sidewalls 30 can be made entirely of silicon nitride, or the gate sidewalls 30 can include multiple sidewall layers, with the outermost sidewall layer (the sidewall layer furthest from the gate structure 20) being a silicon nitride layer.

[0026] Then, see appendix. Figure 1B The gate sidewall 30 made of silicon nitride is etched using a dry etching process to thin it. In the dry etching process, a heavy polymer gas plasma is typically used to etch the gate sidewall 30. The heavy polymer gases mainly include CH2F2 and CH3F. Due to the limited selectivity between silicon nitride and metal silicides, significant losses occur in the first metal silicide layer 13, the second metal silicide layer 14, and the third metal silicide layer 21 during the dry etching process.

[0027] Then, see appendix. Figure 1C A contact etch stop layer 40 is deposited conformally on the initial structure, and a dielectric layer 50 is formed on the contact etch stop layer 40.

[0028] Then, see appendix. Figure 1DThe dielectric layer 50 and the contact etch stop layer 40 are patterned and etched to form a first contact hole exposing the first metal silicide layer 13, a second contact hole exposing the second metal silicide layer 14, and a third contact hole exposing the third metal silicide layer 21. Because the first metal silicide layer 13, the second metal silicide layer 14, and the third metal silicide layer 21 suffer significant losses during the dry etching process, it is easy for the metal silicide layers to be etched through during the formation of the first, second, and third contact holes, leading to high resistance issues later on.

[0029] The following is a reference to the appendix. Figure 2 An exemplary description will be given of a method for fabricating a semiconductor structure according to the first embodiment of this application, which includes the following steps: S10: Provide an initial structure, wherein the initial structure includes a substrate, a gate structure and a gate sidewall, a source region and a drain region are formed on the upper part of the substrate, a first metal silicide layer and a second metal silicide layer are formed on the upper part of the source region and the upper part of the drain region respectively, the gate structure is located above the substrate between the source region and the drain region, the upper part of the gate structure has a third metal silicide layer, the gate sidewall is located on both sides of the gate structure, and the material of the gate sidewall includes silicon nitride.

[0030] S11: A protective layer is deposited conformally on the initial structure, wherein the material of the protective layer is silicon nitride.

[0031] S12: A patterned first photoresist layer is formed on the protective layer, wherein the patterned first photoresist layer exposes the protective layer located on the gate sidewall.

[0032] S13: The exposed protective layer is subjected to hydrogen plasma treatment and oxidation treatment in sequence to convert the exposed protective layer into a silicon oxide layer and remove the first photoresist layer.

[0033] S14: Remove the silicon oxide layer using a wet etching process.

[0034] S15: The gate sidewall and protective layer are etched by a dry etching process to thin the gate sidewall and remove the protective layer.

[0035] S16: A contact etch stop layer is deposited conformally on the initial structure, and a dielectric layer is formed on the contact etch stop layer.

[0036] S17: Pattern the etching dielectric layer and the contact etching stop layer to form a first contact hole exposing the first metal silicide layer, a second contact hole exposing the second metal silicide layer, and a third contact hole exposing the third metal silicide layer.

[0037] According to the semiconductor structure fabrication method of the first embodiment of this application, a protective layer of silicon nitride is first deposited conformally, and then the protective layer on the gate sidewall is successively subjected to hydrogen plasma treatment and oxidation treatment to convert it into a silicon oxide layer, which is then removed by a wet etching process. The gate sidewall is then thinned by a dry etching process, and the remaining protective layer located on the metal silicide layers (first metal silicide layer, second metal silicide layer and third metal silicide layer) is removed. The protective layer located on the metal silicide layer can protect the metal silicide layer during the dry etching process, and can significantly reduce the damage to the first metal silicide layer, the second metal silicide layer and the third metal silicide layer when thinning the gate sidewall, effectively preventing them from being etched through when forming contact holes in the future.

[0038] See attached document Figures 3A-3I The method for preparing a semiconductor structure according to the first embodiment of this application (including the above steps S10-S17) will be described in detail.

[0039] In step S10, see Appendix Figure 3A The initial structure is provided. The initial structure includes a substrate 100, a gate structure 200, and a gate sidewall 300.

[0040] For example, the substrate 100 may include a silicon substrate or other suitable semiconductor substrate, and an N-well or P-well may be fabricated in the substrate 100 as needed. A source region 110 and a drain region 120 are formed on the upper part of the substrate 100, which are spaced apart, and the source region 110 and the drain region 120 are the source region and drain region of the transistor, respectively. A first metal silicide layer 111 and a second metal silicide layer 121 are formed on the upper part of the source region 110 and the upper part of the drain region 120, respectively.

[0041] The gate structure 200 is located above the substrate 100 between the source region 110 and the drain region 120, and the upper part of the gate structure 200 has a third metal silicide layer 210. In this embodiment, the gate structure 200 includes a gate dielectric layer 220, a gate layer 230 located on the gate dielectric layer 220, and a third metal silicide layer 210 located on the gate layer 230. For example, the gate dielectric layer 220 may be a silicon oxide layer, and the gate layer 230 may be a polysilicon layer.

[0042] For example, the materials of the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210 may include at least one of cobalt silicide, nickel silicide, and titanium silicide. The metal silicides can be formed by depositing metal and performing an annealing process.

[0043] Gate sidewalls 300 are located on both sides of the gate structure 200, and the material of the gate sidewalls 300 includes silicon nitride. In this embodiment, the gate sidewalls 300 include a first sidewall layer 310 and a second sidewall layer 320. A first portion of the second sidewall layer 320 is located between the first sidewall layer 310 and the gate structure 200, and a second portion of the second sidewall layer 320 is located between the first sidewall layer 310 and the substrate 100. The first sidewall layer 310 is a silicon nitride layer, and the second sidewall layer 320 is a silicon oxide layer. By setting the second sidewall layer 320 made of silicon oxide between the first sidewall layer 310 made of silicon nitride and the gate structure 200 and the substrate 100, on the one hand, the stress influence of the second sidewall layer 320 can be alleviated; on the other hand, the second sidewall layer 320 can act as an etching stop layer when the first sidewall layer 310 is etched to prevent damage to the substrate 100 and the gate structure 200 during the etching process. In some embodiments, the gate sidewall 300 may be made entirely of silicon nitride, that is, the gate sidewall 300 may consist of only a single layer of silicon nitride. In some embodiments, the gate sidewall 300 may include multiple sidewall layers, wherein the outermost sidewall layer (the sidewall layer furthest from the gate structure 200) is made of silicon nitride.

[0044] In step S11, see Appendix Figure 3B A protective layer 400 is deposited conformally on the initial structure, wherein the protective layer 400 is made of silicon nitride. The protective layer 400 covers the upper surfaces of the first metal silicide layer 111, the second metal silicide layer 121 and the third metal silicide layer 210, and also covers the surface of the gate sidewall 300.

[0045] For example, the protective layer 400 can be deposited using an ALD (Atomic Layer Deposition) process. ALD is a high-precision vapor-phase thin film deposition technology based on surface-constrained chemical reactions. It is a core process for achieving atomic-level precision thin film preparation in advanced semiconductor manufacturing and micro / nano fabrication fields. Its core value lies in its ability to achieve extreme conformal coverage and sub-nanometer thickness control on complex three-dimensional morphologies. In some embodiments, the protective layer 400 can also be deposited using a PECVD (Plasma-Enhanced Chemical Vapor Deposition) process.

[0046] In step S12, see Appendix Figure 3C A patterned first photoresist layer 500 is formed on the protective layer 400, wherein the patterned first photoresist layer 500 exposes the protective layer 400 located on the gate sidewall 300. It should be noted that the patterned first photoresist layer 500 covers the protective layer 400 on the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210.

[0047] For example, the first photoresist layer 500 can be formed on the protective layer 400 by spin coating and patterned by photolithography.

[0048] In step S13, see Appendix Figures 3D-3E The exposed protective layer 400 is subjected to hydrogen plasma treatment and oxidation treatment successively to transform the exposed protective layer 400 into a silicon oxide layer 410 and remove the first photoresist layer 500. Specifically, the exposed silicon nitride protective layer 400 becomes a highly active modified layer after hydrogen plasma treatment, and this modified layer is transformed into a silicon oxide layer 410 after oxidation treatment.

[0049] In this embodiment, please refer to the appendix first. Figure 3D The exposed protective layer 400 is then treated with hydrogen plasma. This treatment involves ionizing hydrogen gas (or other suitable hydrogen-containing gases) to generate a large amount of hydrogen plasma, which acts on the exposed protective layer 400 (silicon nitride layer) through a combination of chemical reaction and physical bombardment, transforming it into a modified layer. On one hand, the electronegativity difference between silicon and nitrogen causes polarization in the silicon nitride layer, allowing positively charged hydrogen ions to combine with negatively charged nitrogen atoms in the silicon nitride. On the other hand, ion bombardment forms NH4+ bonds, while hydrogen free radicals in the plasma passivate the dangling bonds in silicon, forming Si-H4+ bonds, thus increasing the hydrogen content of the hydrogen-plasma-treated silicon nitride layer (i.e., the modified layer). In other words, after hydrogen plasma treatment, the nitrogen atom concentration in the modified layer decreases, and nitrogen atoms mainly exist as volatile NH4+. X The modified layer is lost in the form of oxygen, while Si-H bonds are formed. These Si-H bonds can react with oxygen during subsequent oxidation treatment, transforming the modified layer into a silicon oxide layer 410. The depth of the hydrogen plasma treatment can be greater than or equal to the thickness of the protective layer 400.

[0050] Then, see appendix. Figure 3E The protective layer 400 (i.e. the modified layer formed after hydrogen plasma treatment) is oxidized to transform it into a silicon oxide layer 410.

[0051] For example, the oxidation process may include oxygen plasma treatment, that is, generating a large amount of oxygen plasma by ionizing oxygen (or other suitable oxygen-containing gas, such as ozone), which acts on the hydrogen plasma-treated protective layer 400 (i.e., the modified layer) in a combination of chemical reaction and physical bombardment. This plasma reacts with the Si-H bonds in the modified layer, ultimately forming a silicon oxide layer 410. After the silicon oxide layer 410 is formed, the first photoresist layer 500 is removed.

[0052] For example, the oxidation process may include a thermal oxidation process, in which the protective layer 400 (i.e., the modified layer) after hydrogen plasma treatment is placed in a high-temperature environment, causing the modified layer to react with an oxidant (oxygen or water vapor) to form a silicon oxide layer 410. After the silicon oxide layer 410 is formed, the first photoresist layer 500 is removed. In some embodiments, the first photoresist layer 500 may be removed first, followed by the thermal oxidation process.

[0053] For example, the oxidation process may include maintaining the layer in an oxygen-containing environment for a preset time. Specifically, the protective layer 400 (i.e., the modified layer) after hydrogen plasma treatment may be placed in an oxygen atmosphere, an ozone atmosphere, or air for a preset time to allow the modified layer to undergo an oxidation reaction with oxygen or ozone to form a silicon oxide layer 410. After the silicon oxide layer 410 is formed, the first photoresist layer 500 is removed. In some embodiments, the first photoresist layer 500 may be removed first, followed by maintaining the layer in an oxygen-containing environment for a preset time.

[0054] For example, the oxidation process may include an ashing process, through which the first photoresist layer 500 is removed. The ashing process is a dry process that uses plasma to remove photoresist from the surface of a semiconductor wafer. It decomposes the photoresist into volatile byproducts through an oxidation reaction. Simultaneously, it oxidizes the protective layer 400 (i.e., the modified layer) after hydrogen plasma treatment, transforming it into a silicon oxide layer 410. In other words, the ashing process simultaneously removes the first photoresist layer 500 and transforms the modified layer into the silicon oxide layer 410, thereby effectively simplifying the fabrication process.

[0055] In step S14, see Appendix Figure 3F The silicon oxide layer 410 is removed using a wet etching process. After the silicon oxide layer 410 is removed, the gate sidewall 300 made of silicon nitride is exposed, that is, the first sidewall layer 310 is exposed. It should be noted that the protective layers 400 on the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210 are not removed during this process.

[0056] For example, the silicon oxide layer 410 can be removed by a wet etching solution containing hydrofluoric acid (HF).

[0057] In step S15, see Appendix Figure 3G The gate sidewall 300 and the protective layer 400 are etched by a dry etching process to thin the gate sidewall 300 and remove the protective layer 400.

[0058] For example, in a dry etching process, a polymer gas plasma (primarily CH2F2 and CH3F) can be used to etch the gate sidewall 300 (first sidewall layer 310) and the protective layer 400 of silicon nitride to thin the gate sidewall 300 to the required width and completely remove the protective layer 400. During this process, the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210 are protected by the protective layer 400, thus significantly reducing the damage suffered by these layers during the dry etching process.

[0059] In step S16, see Appendix Figure 3H A contact etch stop layer 600 is deposited conformally on the initial structure, and a dielectric layer 700 is formed on the contact etch stop layer 600.

[0060] For example, in step S16, a contact etch stop layer 600 (CESL) can be conformally deposited on the initial structure (the initial structure after thinning the gate sidewall 300) using a PECVD or ALD process. The material of the contact etch stop layer 600 can be silicon nitride. Then, a dielectric layer 700 is deposited on the contact etch stop layer 600 using a deposition process such as PECVD, and the upper surface of the dielectric layer 700 is planarized using a CMP (Chemical Mechanical Polishing) process. After planarization, the upper surface of the dielectric layer 700 is higher than the upper surface of the contact etch stop layer 600 on the gate structure 200. For example, the material of the dielectric layer 700 can be silicon oxide.

[0061] In step S17, see Appendix Figures 3H-3I The dielectric layer 700 and the contact etch stop layer 600 are patterned and etched to form a first contact hole 910 exposing the first metal silicide layer 111, a second contact hole 920 exposing the second metal silicide layer 121, and a third contact hole 930 exposing the third metal silicide layer 210. Since the damage to the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210 is significantly reduced when the gate sidewall 300 is thinned, it is effectively prevented that they are etched through during the formation of the first contact hole 910, the second contact hole 920, and the third contact hole 930.

[0062] Specifically, in step S17, please refer to the appendix. Figure 3HA patterned second photoresist layer 800 is formed on the dielectric layer 700. The opening pattern in the second photoresist layer 800 corresponds to the positions of the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210. For example, the second photoresist layer 800 can be formed on the dielectric layer 700 by spin coating and patterned by photolithography.

[0063] Then, see appendix. Figure 3H Using the second photoresist layer 800 as a mask, an anisotropic dry etching process is used to etch the dielectric layer 700 and the contact etch stop layer 600 until the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210 are exposed to form the first contact hole 910, the second contact hole 920, and the third contact hole 930. Afterward, the second photoresist layer 800 is removed.

[0064] For example, the patterned first photoresist layer 500 and the patterned second photoresist layer 800 are patterned using the same photomask. That is, after the first photoresist layer 500 and the second photoresist layer 800 are formed by spin coating, the same photomask is used for exposure in the photolithography process, followed by development to achieve patterning. Here, the first photoresist layer 500 is a negative photoresist layer, and the second photoresist layer 800 is a positive photoresist layer, or the first photoresist layer 500 is a positive photoresist layer, and the second photoresist layer 800 is a negative photoresist layer. Thus, the opening patterns in the patterned first photoresist layer 500 and the patterned second photoresist layer 800 are complementary in position and do not overlap. Patterning the first photoresist layer 500 and the patterned second photoresist layer 800 using the same photomask can effectively reduce production costs.

[0065] For example, after step S17, the preparation method further includes filling the first contact hole 910, the second contact hole 920 and the third contact hole 930 with conductive metal to form a first contact plug, a second contact plug and a third contact plug respectively connected to the first metal silicide layer 111, the second metal silicide layer 121 and the third metal silicide layer 210.

[0066] The following is a reference to the appendix. Figure 4 An exemplary description will be given of a method for fabricating a semiconductor structure according to a second embodiment of this application, the method comprising the following steps: S20: Provides an initial structure, which includes a substrate, a gate structure, and a gate sidewall. A source region and a drain region are formed on the upper part of the substrate, and a first metal silicide layer and a second metal silicide layer are formed on the upper part of the source region and the upper part of the drain region, respectively. The gate structure is located above the substrate between the source region and the drain region. A third metal silicide layer is located on the upper part of the gate structure. The gate sidewall is located on both sides of the gate structure. The material of the gate sidewall includes silicon nitride.

[0067] S21: A patterned first photoresist layer is formed on the initial structure, wherein the patterned first photoresist layer exposes the gate sidewall.

[0068] S22: The exposed gate sidewall is subjected to hydrogen plasma treatment and oxidation treatment in sequence to form a silicon oxide layer on the surface of the gate sidewall and remove the first photoresist layer.

[0069] S23: Remove the silicon oxide layer using a wet etching process.

[0070] S24: A contact etch stop layer is deposited conformally on the initial structure, and a dielectric layer is formed on the contact etch stop layer.

[0071] S25: Pattern the etching dielectric layer and the contact etching stop layer to form a first contact hole exposing the first metal silicide layer, a second contact hole exposing the second metal silicide layer, and a third contact hole exposing the third metal silicide layer.

[0072] According to the semiconductor structure fabrication method of the second embodiment of this application, the gate sidewall of silicon nitride is subjected to hydrogen plasma treatment and oxidation treatment in sequence to convert its surface into a silicon oxide layer, and then removed by wet etching process to thin the gate sidewall. This eliminates the need for dry etching process to etch the gate sidewall, which can significantly reduce the damage to the first metal silicide layer, the second metal silicide layer and the third metal silicide layer when thinning the gate sidewall, and effectively prevent them from being etched through when forming contact holes in the future.

[0073] See attached document Figures 5A-5G The method for preparing a semiconductor structure according to the second embodiment of this application (including the steps S20-S25 described above) will be described in detail.

[0074] In step S20, see Appendix Figure 5A The initial structure is provided. The initial structure includes a substrate 100, a gate structure 200, and a gate sidewall 300.

[0075] For example, the substrate 100 may include a silicon substrate or other suitable semiconductor substrate, and an N-well or P-well may be fabricated in the substrate 100 as needed. A source region 110 and a drain region 120 are formed on the upper part of the substrate 100, which are spaced apart, and the source region 110 and the drain region 120 are the source region and drain region of the transistor, respectively. A first metal silicide layer 111 and a second metal silicide layer 121 are formed on the upper part of the source region 110 and the upper part of the drain region 120, respectively.

[0076] The gate structure 200 is located above the substrate 100 between the source region 110 and the drain region 120, and the upper part of the gate structure 200 has a third metal silicide layer 210. In this embodiment, the gate structure 200 includes a gate dielectric layer 220, a gate layer 230 located on the gate dielectric layer 220, and a third metal silicide layer 210 located on the gate layer 230. For example, the gate dielectric layer 220 may be a silicon oxide layer, and the gate layer 230 may be a polysilicon layer.

[0077] For example, the materials of the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210 may include at least one of cobalt silicide, nickel silicide, and titanium silicide. The metal silicide layers can be formed by depositing metal and performing an annealing process.

[0078] Gate sidewalls 300 are located on both sides of the gate structure 200, and the gate sidewalls 300 are made of silicon nitride. In this embodiment, the gate sidewalls 300 include a first sidewall layer 310 and a second sidewall layer 320. A first portion of the second sidewall layer 320 is located between the first sidewall layer 310 and the gate structure 200, and a second portion of the second sidewall layer 320 is located between the first sidewall layer 310 and the substrate 100. The first sidewall layer 310 is a silicon nitride layer, and the second sidewall layer 320 is a silicon oxide layer. By providing a second sidewall layer 320 made of silicon oxide between the first sidewall layer 310 made of silicon nitride and the gate structure 200 and the substrate 100, on the one hand, the stress effect of the second sidewall layer 320 can be alleviated; on the other hand, the second sidewall layer 320 can act as an etching stop layer when the first sidewall layer 310 is etched to prevent damage to the substrate 100 and the gate structure 200 during the etching process. In some embodiments, the gate sidewall 300 may be made entirely of silicon nitride, that is, the gate sidewall 300 may consist of only a single layer of silicon nitride. In some embodiments, the gate sidewall 300 may include multiple sidewall layers, wherein the outermost sidewall layer (the sidewall layer furthest from the gate structure 200) is made of silicon nitride.

[0079] In step S21, see Appendix Figure 5BA patterned first photoresist layer 500' is formed on the initial structure, wherein the patterned first photoresist layer 500' exposes the gate sidewall 300 of silicon nitride material, that is, exposes the first sidewall layer 310. It should be noted that the patterned first photoresist layer 500' covers the first metal silicide layer 111, the second metal silicide layer 121 and the third metal silicide layer 210.

[0080] For example, the first photoresist layer 500' can be formed on the initial structure by spin coating and patterned by photolithography.

[0081] In step S22, see Appendix Figures 5C-5D The exposed gate sidewall 300 is subjected to hydrogen plasma treatment and oxidation treatment in sequence to form a silicon oxide layer 311 on the surface of the gate sidewall 300 and remove the first photoresist layer 500'.

[0082] In this embodiment, please refer to the appendix first. Figure 5C The exposed gate sidewall 300 (i.e., the first sidewall layer 310) is subjected to hydrogen plasma treatment. Hydrogen plasma treatment of the exposed gate sidewall 300 involves ionizing hydrogen gas (or other suitable hydrogen-containing gas) to generate a large amount of hydrogen plasma, which acts on the exposed gate sidewall 300 (silicon nitride layer) through a combination of chemical reaction and physical bombardment, forming a modified layer on its surface. On one hand, the electronegativity difference between silicon and nitrogen causes the silicon nitride layer to polarize, allowing positively charged hydrogen ions to combine with negatively charged nitrogen in silicon nitride. On the other hand, ion bombardment forms NH4+ bonds, while hydrogen free radicals in the plasma passivate the dangling bonds in silicon, forming Si-H4+ bonds, increasing the hydrogen content of the hydrogen plasma-treated silicon nitride layer (i.e., the modified layer). In other words, after hydrogen plasma treatment, the nitrogen atom concentration in the modified layer decreases, and nitrogen atoms mainly exist as volatile NH4+. X The form of loss occurs simultaneously, forming Si-H bonds. These Si-H bonds can react with oxygen during subsequent oxidation processes, transforming the modified layer into a silicon oxide layer 311.

[0083] Then, see appendix. Figure 5D The gate sidewall 300 (i.e. the modified layer formed after hydrogen plasma treatment) is oxidized to convert the modified layer on its surface into a silicon oxide layer 311.

[0084] For example, the oxidation process may include oxygen plasma treatment, that is, generating a large amount of oxygen plasma by ionizing oxygen (or other suitable oxygen-containing gas, such as ozone), which acts on the hydrogen plasma-treated gate sidewall 300 (i.e., the modified layer) in a combination of chemical reaction and physical bombardment. This plasma reacts with the Si-H bonds in the modified layer, ultimately forming a silicon oxide layer 311. After the silicon oxide layer 311 is formed, the first photoresist layer 500' is removed.

[0085] For example, the oxidation process may include a thermal oxidation process, in which the gate sidewall 300 (i.e., the modified layer) after hydrogen plasma treatment is placed in a high-temperature environment, causing the modified layer to react with an oxidant (oxygen or water vapor) to form a silicon oxide layer 311. After the silicon oxide layer 311 is formed, the first photoresist layer 500' is removed. In some embodiments, the first photoresist layer 500' may be removed first before the thermal oxidation process is performed.

[0086] For example, the oxidation process may include holding the modified layer in an oxygen-containing environment for a preset time. Specifically, the hydrogen plasma-treated gate sidewall 300 (i.e., the modified layer) may be placed in an oxygen atmosphere, an ozone atmosphere, or air for a preset time to allow the modified layer to undergo an oxidation reaction with oxygen or ozone to form a silicon oxide layer 311. After the silicon oxide layer 311 is formed, the first photoresist layer 500' is removed. In some embodiments, the first photoresist layer 500' may be removed first, followed by holding the modified layer in an oxygen-containing environment for a preset time.

[0087] For example, the oxidation process may include an ashing process, through which the first photoresist layer 500' is removed. The ashing process is a dry process that uses plasma to remove photoresist from the surface of a semiconductor wafer. It decomposes the photoresist into volatile byproducts through an oxidation reaction. Simultaneously, it oxidizes the gate sidewall 300 (i.e., the modified layer) after hydrogen plasma treatment, transforming the modified layer into a silicon oxide layer 311. In other words, the ashing process simultaneously removes the first photoresist layer 500' and transforms the modified layer into a silicon oxide layer 311, thereby effectively simplifying the fabrication process.

[0088] In step S23, see Appendix Figure 5E The silicon oxide layer 311 is removed using a wet etching process. For example, the silicon oxide layer 311 can be removed using a wet etching solution containing hydrofluoric acid (HF). After the silicon oxide layer 311 is removed, the gate sidewall 300 is thinned. Thinning the sidewall in this way eliminates the need for a dry etching process, and virtually avoids damage to the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210, effectively preventing them from being etched through during subsequent contact hole formation.

[0089] For example, steps S22 and S23 can be performed once or repeated multiple times (when repeated multiple times, step S22 is performed first and then step S23 is performed each time) to thin the gate sidewall 300 (i.e. the first sidewall layer 310) of silicon nitride material once or multiple times.

[0090] In step S24, see Appendix Figure 5F A contact etch stop layer 600 is deposited conformally on the initial structure, and a dielectric layer 700 is formed on the contact etch stop layer 600.

[0091] For example, in step S24, a contact etch stop layer 600 (CESL) can be conformally deposited on the initial structure (the initial structure after thinning the gate sidewall 300) using a PECVD or ALD process. The material of the contact etch stop layer 600 can be silicon nitride. Then, a dielectric layer 700 is deposited on the contact etch stop layer 600 using a deposition process such as PECVD, and the upper surface of the dielectric layer 700 is planarized using a CMP (Chemical Mechanical Polishing) process. After planarization, the upper surface of the dielectric layer 700 is higher than the upper surface of the contact etch stop layer 600 on the gate structure 200. For example, the material of the dielectric layer 700 can be silicon oxide.

[0092] In step S25, see Appendix Figure 5F , 5G The dielectric layer 700 and the contact etch stop layer 600 are patterned and etched to form a first contact hole 910 exposing the first metal silicide layer 111, a second contact hole 920 exposing the second metal silicide layer 121, and a third contact hole 930 exposing the third metal silicide layer 210. Since the damage to the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210 is significantly reduced when the gate sidewall 300 is thinned, it is effectively prevented that they are etched through during the formation of the first contact hole 910, the second contact hole 920, and the third contact hole 930.

[0093] Specifically, in step S25, please refer to the appendix. Figure 5F A patterned second photoresist layer 800 is formed on the dielectric layer 700. The opening pattern in the second photoresist layer 800 corresponds to the positions of the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210. For example, the second photoresist layer 800 can be formed on the dielectric layer 700 by spin coating and patterned by photolithography. Then, see the appendix... Figure 5GUsing the second photoresist layer 800 as a mask, an anisotropic dry etching process is used to etch the dielectric layer 700 and the contact etch stop layer 600 until the first metal silicide layer 111, the second metal silicide layer 121, and the third metal silicide layer 210 are exposed to form the first contact hole 910, the second contact hole 920, and the third contact hole 930. Afterward, the second photoresist layer 800 is removed.

[0094] For example, after step S25, the preparation method further includes filling the first contact hole 910, the second contact hole 920 and the third contact hole 930 with conductive metal to form a first contact plug, a second contact plug and a third contact plug respectively connected to the first metal silicide layer 111, the second metal silicide layer 121 and the third metal silicide layer 210.

[0095] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0096] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of this application may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0097] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0098] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0099] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0100] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: An initial structure is provided, the initial structure including a substrate, a gate structure and a gate sidewall, wherein a source region and a drain region are formed on the upper part of the substrate, a first metal silicide layer and a second metal silicide layer are formed on the upper part of the source region and the upper part of the drain region respectively, the gate structure is located above the substrate between the source region and the drain region, the upper part of the gate structure has a third metal silicide layer, and the gate sidewall is located on both sides of the gate structure, the gate sidewall being made of silicon nitride; A protective layer is deposited conformally on the initial structure, wherein the material of the protective layer is silicon nitride; A patterned first photoresist layer is formed on the protective layer, wherein the patterned first photoresist layer exposes the protective layer located on the gate sidewall; The exposed protective layer is subjected to hydrogen plasma treatment and oxidation treatment in sequence to convert the exposed protective layer into a silicon oxide layer and remove the first photoresist layer. The silicon oxide layer is removed by a wet etching process; The gate sidewall and the protective layer are etched using a dry etching process to thin the gate sidewall and remove the protective layer. A conformal deposition of a contact etch stop layer is performed on the initial structure, and a dielectric layer is formed on the contact etch stop layer; The dielectric layer and the contact etch stop layer are patterned to form a first contact hole exposing the first metal silicide layer, a second contact hole exposing the second metal silicide layer, and a third contact hole exposing the third metal silicide layer.

2. The preparation method according to claim 1, characterized in that, The oxidation process includes oxygen plasma treatment.

3. The preparation method according to claim 1, characterized in that, The oxidation treatment includes a thermal oxidation process.

4. The preparation method according to claim 1, characterized in that, The oxidation process includes maintaining the sample in an oxygen-containing environment for a predetermined time.

5. The preparation method according to claim 1, characterized in that, Patterning the etching of the dielectric layer and the contact etch stop layer includes: A patterned second photoresist layer is formed on the dielectric layer; Using the second photoresist layer as a mask, the dielectric layer and the contact etch stop layer are etched by an anisotropic dry etching process to form the first contact hole, the second contact hole and the third contact hole; The patterned first photoresist layer and the patterned second photoresist layer are patterned using the same photomask. The first photoresist layer is a negative photoresist layer, and the second photoresist layer is a positive photoresist layer, or the first photoresist layer is a positive photoresist layer and the second photoresist layer is a negative photoresist layer.

6. The preparation method according to claim 1, characterized in that, The gate sidewall includes a first sidewall layer and a second sidewall layer, a first portion of the second sidewall layer is located between the first sidewall layer and the gate structure, and a second portion of the second sidewall layer is located between the first sidewall layer and the substrate. The first sidewall layer is a silicon nitride layer, and the second sidewall layer is a silicon oxide layer.

7. A method for fabricating a semiconductor structure, characterized in that, include: An initial structure is provided, the initial structure including a substrate, a gate structure and a gate sidewall, wherein a source region and a drain region are formed on the upper part of the substrate, a first metal silicide layer and a second metal silicide layer are formed on the upper part of the source region and the upper part of the drain region respectively, the gate structure is located above the substrate between the source region and the drain region, the upper part of the gate structure has a third metal silicide layer, and the gate sidewall is located on both sides of the gate structure, the gate sidewall being made of silicon nitride; A patterned first photoresist layer is formed on the initial structure, wherein the patterned first photoresist layer exposes the gate sidewall; The exposed gate sidewall is subjected to hydrogen plasma treatment and oxidation treatment in sequence to form a silicon oxide layer on the surface of the gate sidewall and remove the first photoresist layer. The silicon oxide layer is removed by a wet etching process; A conformal deposition of a contact etch stop layer is performed on the initial structure, and a dielectric layer is formed on the contact etch stop layer; The dielectric layer and the contact etch stop layer are patterned to form a first contact hole exposing the first metal silicide layer, a second contact hole exposing the second metal silicide layer, and a third contact hole exposing the third metal silicide layer.

8. The preparation method according to claim 7, characterized in that, The oxidation process includes oxygen plasma treatment.

9. The preparation method according to claim 7, characterized in that, The oxidation treatment includes a thermal oxidation process.

10. The preparation method according to claim 7, characterized in that, The oxidation process includes maintaining the sample in an oxygen-containing environment for a predetermined time.

Images