Method for manufacturing single-sided passivated stacked battery and stacked battery

Abstract

This invention discloses a method for single-sided passivation fabrication of a tandem solar cell and the tandem solar cell itself, comprising the following steps: reserving an annular blank area at the edge of the front side of a silicon wafer; depositing a conductive layer on the front side of the silicon wafer, the deposition boundary of the conductive layer being aligned with the outer edge of the annular blank area; fabricating at least one functional layer on the conductive layer; depositing a passivation layer on the front side of the silicon wafer, the passivation layer covering the front side area of ​​the silicon wafer including the annular blank area; and cutting along the annular blank area to form an insulating dead zone surrounding the silicon wafer. This invention, by pre-setting the annular blank area and subsequently cutting along it, removes the annular blank area and all the films above it, physically blocking the plating path that propagates from the front side of the silicon wafer through the sidewalls to the back side, simplifying the process, reducing the breakage rate, and achieving single-sided passivation.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic cell technology, and in particular to a method for preparing single-sided passivation of tandem cells and tandem cells. Background Technology

[0002] As the photovoltaic industry iterates towards higher efficiency, perovskite / crystalline silicon tandem solar cells, with their efficiency advantages, have become the core technology route for the next generation of photovoltaic industrialization. Currently, 210mm half-cell crystalline silicon wafers have become the mainstream specification for pilot and mass production of tandem solar cells due to their suitability for large-scale mass production. In the preparation of the passivation layer of tandem solar cells, atomic layer deposition (ALD) technology, with its advantages such as precise control of film thickness at the atomic level, excellent step conformal performance, and low-temperature compatibility with thermosensitive substrates, is the preferred method for preparing Al2O3 and SiN tandem solar cells. x The optimized process of passivation layers such as SnO2 can effectively suppress interfacial carrier recombination and improve the photoelectric conversion performance of the battery.

[0003] However, regardless of whether it's ALD, chemical vapor deposition (CVD), or other vapor deposition processes, precursor gases can diffuse laterally along the tiny gaps between the silicon wafer and the substrate, as well as along the sidewalls of the wafer. This easily leads to edge-wrap defects: the passivation film can spread from the front to the back of the silicon wafer, causing electrical connection between the films on the front and back of the cell. The full-domain self-contained vapor deposition characteristic of ALD makes this problem particularly prominent. For 210mm textured half-wafer silicon wafers, due to limitations such as surface texture undulations, tooling tolerances, and wafer warpage, it is impossible to achieve a completely sealed fit between the substrate and the carrier. Optimizing process parameters alone can only alleviate the wrap phenomenon, but cannot eliminate the trace lateral diffusion of vapor phase at its source. Ultimately, this results in device performance defects such as edge leakage, open-circuit voltage decay, and fill factor fluctuations, significantly reducing cell conversion efficiency.

[0004] To suppress edge-wrap plating in vapor deposition processes, the industry currently mainly adopts two solutions: one is rigid edge-blocking fixtures, which are prone to mechanical scratches with large-size thin silicon wafers, causing microcracks and increased breakage rates. Furthermore, the textured substrate has blind spots where the sealing is inadequate, making it impossible to completely avoid edge-wrap plating. The other solution is a back-side protective film application process. This solution requires two additional steps: applying and removing the film, significantly lengthening the batch processing time. Residual adhesive residue from the protective film can also contaminate the back of the silicon wafer, introducing interface impurity recombination centers and compromising the passivation effect of the silicon substrate. Additionally, the protective film has limited temperature resistance and precursor corrosion resistance, making it unsuitable for Al2O3 and SiN substrates. x Passivation systems such as SnO2 are commonly used in multilayer batteries, but they have poor versatility and can significantly increase the cost of consumables and labor.

[0005] Furthermore, the 210mm half-wafer silicon wafer has a larger lateral span compared to traditional small-sized silicon wafers, significantly increasing the difficulty of controlling the gas field distribution and tooling clamping uniformity within the deposition chamber. This results in significant differences in the degree of plating around different silicon wafers, and even between the edges and center of the same wafer, leading to high dispersion in the passivation performance of batch cells. Passivation processes that are stable in pilot-scale production experience a rapid decline in yield when scaled up to mass production lines. Simultaneously, the conductive thin film channels formed by edge plating can cause uneven current distribution after module encapsulation, leading to safety failures such as module hot spots, localized overheating aging, and cell burnout, severely hindering the industrialization of perovskite / crystalline silicon tandem solar cells.

[0006] Therefore, how to design a single-sided passivation preparation method with low damage, high uniformity, and high mass production capability is a technical problem that the industry urgently needs to solve. Summary of the Invention

[0007] To address the shortcomings of existing vapor deposition single-sided passivation processes, such as the inability to completely eliminate edge-wrap plating and the tendency of existing anti-wrap plating solutions to cause silicon wafer damage, this invention proposes a single-sided passivation preparation method for tandem solar cells and a tandem solar cell. First, an annular blank area is pre-set at the edge of the front side of the silicon wafer, and then an insulating dead zone is formed by cutting along the blank area. This effectively blocks the conduction path of the passivation layer to the sidewall and back of the silicon wafer, eliminating the need for rigid sealing fixtures or back protective films, significantly reducing process complexity and the risk of breakage. It is especially suitable for the mass production needs of large-size tandem solar cells such as 210mm textured half-cell crystalline silicon wafers.

[0008] The technical solution adopted in this invention is to design a method for single-sided passivation fabrication of tandem solar cells, comprising the following steps:

[0009] A ring-shaped blank area is reserved at the edge of the front side of the silicon wafer;

[0010] A conductive layer is deposited on the front side of the silicon wafer, with the deposition boundary of the conductive layer aligned with the outer edge of the annular blank area;

[0011] At least one functional layer is fabricated on the conductive layer;

[0012] A passivation layer is deposited on the front side of the silicon wafer, covering the front area of ​​the silicon wafer, including the annular blank area.

[0013] The edge of the silicon wafer is cut along the annular blank area to form an insulating dead zone surrounding the silicon wafer.

[0014] This design avoids the extension of the conductive layer to the edge of the silicon wafer by reserving a ring-shaped blank area and defining the deposition boundary of the conductive layer. Combined with the full-coverage deposition of the passivation layer and the subsequent laser cutting process, it can completely remove excess conductive and passivation materials at the edge without relying on rigid sealing fixtures or back protective films, physically blocking the leakage path from the front to the back. This simplifies the process, reduces the breakage rate, and achieves single-sided passivation.

[0015] Furthermore, the conductive layer includes a transparent conductive layer and / or an inorganic hole transport layer.

[0016] This design clarifies the specific composition of the conductive layer, covering hole transport materials such as transparent conductive oxide (TCO) and nickel oxide (NiOx) commonly used in crystalline silicon tandem cells. This allows the edge blanking scheme to flexibly adapt to tandem cell structures with different material systems, improving the versatility and process compatibility of the scheme.

[0017] Furthermore, the transparent conductive layer is made of one or more of ITO, IZO, ICO, IWO, FTO, AZO, NTO, and GZO; the inorganic hole transport layer is a NiOx layer.

[0018] The aforementioned materials exhibit high transmittance and excellent conductivity in the visible light region. Furthermore, the NiOx layer, serving as a hole transport layer, has a mature and stable fabrication process, which helps ensure the photoelectric conversion efficiency and long-term stability of the tandem solar cell.

[0019] Furthermore, at least one functional layer includes an interface modification layer, a perovskite light-absorbing layer, and an electron transport layer arranged sequentially in a direction away from the conductive layer.

[0020] This sequence design facilitates the separation and transport of photogenerated carriers, ensuring the basic photoelectric performance of the battery and providing a technological basis for subsequent passivation and cutting steps.

[0021] Furthermore, the interface modification layer and perovskite light-absorbing layer can be prepared using a patterning process to avoid the annular blank area, or a full coating process can be used to cover the front area of ​​the silicon wafer, including the annular blank area; the electron transport layer is prepared using a full evaporation process to cover the front area of ​​the silicon wafer, including the annular blank area.

[0022] The interface modification layer and perovskite light-absorbing layer can be selected for high-precision patterning (with blank space) or low-cost full-coverage coating, depending on the equipment configuration; at the same time, the electron transport layer (such as C) is forcibly limited. 60 The method employs full vapor deposition, which ensures complete coverage of the perovskite surface and high electron transport efficiency, while also removing excess film from the edges through subsequent cutting steps, thus balancing battery performance with process simplification.

[0023] Furthermore, the passivation layer is deposited using an atomic layer deposition process, and the material of the passivation layer is selected from Al2O3 and SiN. x One or more of SnO2.

[0024] This design employs atomic layer deposition (ALD) to prepare the passivation layer, which leverages the self-limiting reaction properties to form a dense, uniform, and pinhole-free thin film on complex surfaces. The use of materials such as Al2O3 effectively reduces the interface state density on the silicon wafer surface, suppresses carrier recombination, and significantly improves the open-circuit voltage and photoelectric conversion efficiency of the battery.

[0025] Furthermore, the width of the kerf is less than or equal to the width of the annular blank area, and the cutting depth is not less than the thickness of the silicon wafer.

[0026] This design ensures that the annular blank area is completely removed by limiting the slit width to no greater than the width of the blank area, thus avoiding residual conductive channels. By limiting the cutting depth to no less than the thickness of the silicon wafer, it ensures that the silicon substrate and each film layer in the edge area are completely cut off and removed, physically blocking the conduction path of the passivation layer to the sidewalls and back side, thereby improving insulation reliability.

[0027] Furthermore, the width of the annular blank area is 0~50μm.

[0028] This design limits the width of the annular blank area to an optimal range of 0~50μm, which provides sufficient process alignment margin for subsequent film deposition and laser cutting, preventing accidental cutting of the effective cell area, while keeping the proportion of the edge ineffective area at a low level, thereby maximizing the effective power generation area of ​​the silicon wafer and the overall conversion efficiency of the cell.

[0029] Furthermore, the silicon wafer is a 210mm textured half-crystal silicon wafer.

[0030] This type of silicon wafer has a large area and a long total edge length, making edge plating control significantly more difficult than for smaller silicon wafers. This invention, through a structured design of blank spaces and cuts, effectively overcomes the challenges of edge plating in the ALD process for large silicon wafers due to uneven gas field distribution and difficulties in tooling fit, thus exhibiting excellent mass production adaptability.

[0031] The present invention also proposes a stacked battery, comprising:

[0032] A silicon wafer body having a front side, a back side, and an edge side surrounding the silicon wafer body;

[0033] Insulation dead zones are located at the edges of the silicon wafer body;

[0034] A functional layer structure is disposed on the front side of the silicon wafer body. The functional layer structure includes a conductive layer, at least one functional layer and a passivation layer disposed sequentially in a direction away from the front side of the silicon wafer body.

[0035] The outer edge of the conductive layer is aligned with the inner edge of the insulating dead zone. The passivation layer covers the front side of the silicon wafer and the surface of the insulating dead zone, and the passivation layer is interrupted at the insulating dead zone.

[0036] This design utilizes the insulation dead zone to reliably isolate the front passivation layer, fundamentally eliminating the risk of electrical connection between the front and back sides. This allows the cells to effectively suppress edge leakage current and improve the stability of open-circuit voltage and fill factor during long-term use, making it particularly suitable for photovoltaic modules with high reliability requirements.

[0037] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0038] 1. By pre-setting an annular blank area and depositing a passivation layer covering the entire front of the silicon wafer, the risk of microcracks and fragmentation caused by contact and friction between rigid sealing fixtures and thin silicon wafers is eliminated. Subsequently, by cutting along the annular blank area, the annular blank area and all the film layers above it are removed, physically blocking the plating path that spreads from the front of the silicon wafer through the sidewall to the back. At the same time, the process of attaching and removing the back protective film and cleaning residual adhesive is eliminated, which greatly reduces the complexity of the process and the cost of consumables, and ensures the cleanliness of the silicon wafer surface.

[0039] 2. By aligning the deposition boundary of the transparent conductive layer and the inorganic hole transport layer with the outer edge of the annular blank area, and combining the interface modification layer and the perovskite light-absorbing layer with a flexible patterned fabrication process, the problems of misalignment of the multilayer film edge and blurred boundary of the blank area are solved. This provides a clear alignment reference for the subsequent laser cutting process and effectively improves the processing accuracy and yield of the edge insulation structure.

[0040] 3. By using atomic layer deposition (ALD) technology to prepare the passivation layer and adapting it to 210mm large-size half-wafer silicon wafers, the problems of uneven gas field distribution and large differences in deposition rate between the edge and center regions of large-size silicon wafers were solved. The excellent step coverage of the ALD process was utilized to balance the uniformity of the passivation film thickness of the entire silicon wafer, reduce the performance dispersion of different regions in the same batch and the same wafer, and improve the stability of the mass production process. Attached Figure Description

[0041] The present invention will now be described in detail with reference to the embodiments and accompanying drawings, wherein:

[0042] Figure 1 This is a schematic diagram of the structure of the stacked battery of the present invention;

[0043] Figure 2 This is a schematic diagram of the laser cutting direction of the stacked battery of the present invention;

[0044] Figure 3 This is a top view of the stacked battery of the present invention before laser cutting;

[0045] Figure 4 This is a top view of the stacked battery of the present invention after laser cutting;

[0046] Reference numerals: 100, silicon wafer; 200, transparent conductive layer; 300, inorganic hole transport layer; 400, interface modification layer; 500, perovskite light-absorbing layer; 600, electron transport layer; 700, passivation layer. Detailed Implementation

[0047] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0048] The single-sided passivation preparation method for tandem solar cells provided by this invention is particularly suitable for perovskite / crystalline silicon tandem solar cells based on 210mm textured half-wafer crystalline silicon wafers. It can effectively solve the edge-wrap plating problem commonly found in vapor deposition processes, eliminates the need for rigid sealing fixtures or back protective films, significantly reduces process complexity and fragmentation risk, and is suitable for large-scale mass production needs.

[0049] like Figure 1 As shown below, the single-sided passivation preparation method of the stacked battery of the present invention will be described in detail with reference to specific embodiments, which includes steps S1 to S6.

[0050] Step S1: Substrate pretreatment.

[0051] A 210mm textured half-crystalline silicon wafer was selected as the substrate, and the silicon wafer 100 was cleaned and dried.

[0052] In a preferred embodiment of the present invention, the cleaning and drying process includes, in sequence: brush cleaning, ultrasonic cleaning, two-fluid cleaning, conventional spray cleaning, and pure water spray cleaning. The brush cleaning speed is 100~800 r / min, and the spray pressure is 0.05~0.30 MPa. The ultrasonic cleaning frequency is 20~120 kHz, the processing time is 10~180 s, and the temperature is 40℃.

[0053] Based on this, the preferred solution is to perform plasma treatment after cleaning the silicon wafer 100, which includes AK plasma treatment and AP plasma treatment in sequence. The nitrogen flow rate for AP plasma treatment is 368 Lpm, and the dry compressed air flow rate is 0.67 Lpm.

[0054] After the above steps, the surface of silicon wafer 100 is clean, providing a good interface for subsequent film deposition.

[0055] Step S2: Form a ring-shaped blank area at the front edge of the silicon wafer 100.

[0056] By pre-fabricating an edge mask, a ring-shaped blank area with a width of 0-50 μm is reserved on the front edge of the silicon wafer 100. The mask covers the ring-shaped blank area, ensuring that the transparent conductive layer 200 and the inorganic hole transport layer 300 are not deposited in this area during subsequent fabrication. The remaining area is the fabrication area for subsequent stacked functional layers. The width of the ring-shaped blank area can be flexibly adjusted according to the degree of silicon wafer warpage and the uniformity of the deposition process, providing a clear physical boundary for the subsequent passivation layer deposition.

[0057] Step S3: Prepare the stacked functional layers.

[0058] The stacked functional layers, from bottom to top, include a transparent conductive layer 200, an inorganic hole transport layer 300, an interface modification layer 400, a perovskite light-absorbing layer 500, and an electron transport layer 600. The transparent conductive layer 200 and the inorganic hole transport layer 300 are shielded by edge masks during fabrication, and their deposition boundaries are precisely aligned with the outer edge of the annular blank area. Therefore, no functional layers are deposited in the annular blank area. The interface modification layer 400 and the perovskite light-absorbing layer 500 are fabricated using a patterned process to actively avoid the annular blank area, thereby forming a blank structure with clear boundaries without the need for additional masking. The electron transport layer 600 is fabricated using a full-area evaporation process, covering the front area of ​​the silicon wafer, including the annular blank area.

[0059] In some feasible embodiments of the present invention, the transparent conductive layer 200 is selected from one or more of ITO, IZO, ICO, IWO, FTO, AZO, NTO, and GZO, and is prepared by magnetron sputtering process with a thickness of 5~20nm. During sputtering, the oxygen concentration is controlled at 0.10%~1.10% to balance the transmittance and conductivity, and to avoid the resistivity from increasing due to excessive oxygen concentration or the transmittance from decreasing due to excessively low oxygen concentration.

[0060] The inorganic hole transport layer 300 is a NiOx layer prepared by DC magnetron sputtering with a thickness of 5~20nm. During the sputtering process, the oxygen concentration is controlled at 0.0%~10.0% to optimize the hole extraction efficiency and avoid excessive oxygen vacancies that could lead to excessive film conductivity and leakage.

[0061] The interface modification layer 400 is a self-assembled monolayer (SAM) prepared using inkjet printing with an inkjet solution concentration of 0.1–1.0 mg / mL. After printing, the silicon wafer is thermally annealed at 80–150°C for 5–20 min. The annealing process promotes the orientation of SAM molecules on the silicon wafer surface and their chemical bonding with the substrate, effectively passivating surface dangling bonds, reducing interface state density, and improving hole extraction efficiency.

[0062] The perovskite light-absorbing layer 500 is prepared using a slit coating process. During the coating liquid bridge formation process, a 0.0~1.0MPa air knife is applied simultaneously to control the spreading state of the wet film and prevent edge overflow from contaminating the blank areas. After coating, it is placed in a vacuum chamber for vacuum drying (VCD). During the VCD drying step, the opening of the butterfly valve installed on the pipeline between the vacuum chamber and the vacuum pump (adjustment range 0%~100%) is adjusted to control the chamber pumping rate, so that the chamber pressure drops to 5Pa within 0~60s, and is held at this pressure for 50~200s to achieve controllable evaporation of the solvent in the perovskite precursor solution, obtaining a dense and uniform perovskite light-absorbing layer 500. After drying, it is placed in an environment of 80~150℃ for 5~20min for heat annealing to promote the nucleation and growth of perovskite crystals, forming a light-absorbing layer film with high crystallinity and few defects, thereby improving the photoelectric conversion performance.

[0063] Electron transport layer 600 is a C400 fabricated by vapor deposition. 60 A layer, consisting of 1-20 nm thick C layers, is fabricated on a crystalline silicon substrate after the perovskite thin film is prepared using an evaporation process. 60 An electron transport layer ensures efficient electron transport while preventing light absorption loss due to excessive film thickness.

[0064] Step S4: Deposit a passivation layer 700.

[0065] The silicon wafer 100 with the edge blanking pattern completed is placed flat on the carrier station of the vapor deposition equipment. The rigid sealing fixture and the back protective film are abandoned. The vapor deposition process is used to fully cover the front of the silicon wafer 100. The passivation layer 700 covers the front of the silicon wafer 100 and the annular blanking area. Subsequently, by cutting along the annular blanking area, the passivation layer 700 and the electron transport layer 600 deposited in this area are physically removed together with the edge skin, thereby completely avoiding the problems of fixture scratching the silicon wafer and residual adhesive contamination of the protective film.

[0066] In a preferred embodiment of the present invention, a passivation layer 700 is deposited using atomic layer deposition (ALD) technology, and the material of the passivation layer 700 is selected from Al2O3 and SiN. x One or more of SnO2 are used, with a deposition temperature of 60~220℃; the process parameters are controlled as follows: precursor pulse duration 1~10s, carrier gas flow rate 50~1000sccm, purge duration 5~30s, and deposition cycle count 50~300. Utilizing the self-confining characteristics of the ALD process, a dense, pinhole-free passivation film can be formed on the front side, effectively suppressing interfacial carrier recombination and improving the battery open-circuit voltage.

[0067] Step S5: Cut along the annular blank area to form an insulation dead zone.

[0068] Laser cutting is used to cut along the annular blank area at the edge of the silicon wafer 100. The width of the cut is controlled to be less than or equal to the width of the annular blank area, ensuring that the resulting insulating dead zone completely covers the annular blank area. The annular blank area and all the films deposited on it are removed together, completely cutting off any potential conductive paths from the passivation layer 700 to the sidewalls and back of the silicon wafer 100. This step physically transforms the temporarily reserved "annular blank area" in the process into a permanent "insulation dead zone," which is the core step in preventing edge leakage.

[0069] Step S6: Prepare the top transparent conductive layer and metal electrode.

[0070] The top transparent conductive layer is prepared by magnetron sputtering. The material is selected from one or more of ITO, IZO, ICO, IWO, FTO, AZO, NTO, and GZO, with a thickness of 10~40nm. During sputtering, the oxygen concentration is controlled at 0.10%~1.10% to balance light transmittance and conductivity and reduce the series resistance of the battery.

[0071] In some feasible embodiments of the present invention, the metal electrode is prepared by screen printing process to make silver electrode. After printing, it is placed in an environment of 80~150℃ for 10~60min for heat curing to form conductive grid line with good ohmic contact and ensure current collection efficiency.

[0072] To facilitate understanding, the process flow of the preparation method is described using an application example of the present invention.

[0073] A 210mm textured half-wafer crystalline silicon wafer was selected for cleaning and drying. The cleaning process involved brush cleaning (450 r / min, spray pressure 0.18 MPa), ultrasonic cleaning (60 kHz, 90 s, 40 ℃), two-fluid cleaning, conventional spray cleaning, pure water spray cleaning, AK plasma treatment (595 L / min, 88°, 1100 L / min of isolation gas), and AP plasma treatment (368 Lpm of nitrogen, 0.67 Lpm of dry compressed air).

[0074] A 30μm wide annular blank area is reserved at the edge of the front side of silicon wafer 100;

[0075] Subsequently, functional layers were fabricated sequentially: a 15 nm thick ITO transparent conductive layer was prepared by magnetron sputtering with a sputtering oxygen concentration of 0.5%; a 10 nm thick DC magnetron sputtered NiOx hole transport layer was prepared with a sputtering oxygen concentration of 5%; a SAM interface modification layer was prepared by inkjet printing with a reagent concentration of 0.5 mg / mL and annealed at 120 °C for 10 min; a perovskite light-absorbing layer 500 was prepared by slot coating, with 0.5 MPa air knife purging, 5 Pa vacuum pressure held for 100 s, and annealed at 120 °C for 15 min during coating; and a 15 nm thick C layer was prepared by vapor deposition. 60 Electron transport layer;

[0076] Subsequently, an Al2O3 passivation layer was deposited using the ALD process at a deposition temperature of 150℃, a precursor pulse of 5s, a carrier gas flow rate of 500sccm, a purge of 15s, and a cycle of 150 times.

[0077] Then, laser cutting is performed along the blank area, with a kerf width of 25μm, to form an insulating dead zone that completely covers the blank area;

[0078] Finally, a 20nm thick ITO top transparent conductive layer was prepared, and silver electrodes were screen-printed and cured at 120℃ for 30min to obtain the finished tandem battery.

[0079] The tandem solar cell prepared by the above method has an insulating dead zone at the edge of the silicon wafer. The passivation layer on the front side is blocked by the insulating dead zone, eliminating the plating defects that spread to the sidewall and back of the silicon wafer, reducing edge leakage current, and effectively improving the conversion efficiency compared with the traditional tooling shading process. It is suitable for the mass production needs of 210mm large-size silicon wafers, and has excellent long-term operational reliability. It is especially suitable for photovoltaic module scenarios with high stability requirements.

[0080] This invention also proposes a tandem solar cell, comprising: a silicon wafer body, an insulating dead zone, and a functional layer structure. The silicon wafer body has a front side, a back side, and an edge side surrounding the silicon wafer body. The insulating dead zone is disposed at the edge of the silicon wafer body. The functional layer structure is disposed on the front side of the silicon wafer body. The functional layer structure includes a conductive layer, at least one functional layer, and a passivation layer 700 sequentially disposed along a direction away from the front side of the silicon wafer body. The outer edge of the conductive layer is aligned with the inner edge of the insulating dead zone. The passivation layer 700 covers the front side of the silicon wafer body and the surface of the insulating dead zone, and the passivation layer 700 is interrupted at the insulating dead zone. The functional layer structure of the finished tandem solar cell typically also includes a top transparent conductive layer and a metal electrode sequentially disposed. This type of tandem solar cell can be prepared by the single-sided passivation preparation method described above.

[0081] See Figure 1 and Figure 2As shown, in some embodiments of the present invention, the conductive layer includes a transparent conductive layer 200 and / or an inorganic hole transport layer 300. The material of the transparent conductive layer 200 is selected from one or more of ITO, IZO, ICO, IWO, FTO, AZO, NTO, and GZO; the inorganic hole transport layer 300 is a NiOx layer. At least one functional layer includes an interface modification layer 400, a perovskite light-absorbing layer 500, and an electron transport layer 600 sequentially disposed in a direction away from the conductive layer; the outer edges of the interface modification layer 400 and the perovskite light-absorbing layer 500 are aligned with the inner edge of the insulating dead zone, or extend to the surface covering the insulating dead zone; the electron transport layer 600 extends to cover the front area of ​​the silicon wafer, including the annular blank area.

[0082] It should be noted that the terminology used above is for describing specific embodiments only and is not intended to limit the exemplary embodiments of the present invention. When the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof. The order of execution of actions, steps, etc., of the methods shown in the specification can be implemented in any order unless a specific express order is specified, and as long as the output of the preceding process is not used in the subsequent process. Similar sequential terms used for ease of description do not imply that such an order must be followed.

[0083] Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0084] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for preparing a single-sided passivation layer of a tandem battery, characterized in that, Includes the following steps: A ring-shaped blank area is reserved at the edge of the front side of the silicon wafer; A conductive layer is deposited on the front side of the silicon wafer, and the deposition boundary of the conductive layer is aligned with the outer edge of the annular blank area. At least one functional layer is prepared on the conductive layer; A passivation layer is deposited on the front side of the silicon wafer, the passivation layer covering the front area of ​​the silicon wafer including the annular blank area; The edge of the silicon wafer is cut along the annular blank area to form an insulating dead zone surrounding the silicon wafer.

2. The single-sided passivation preparation method according to claim 1, characterized in that, The conductive layer includes a transparent conductive layer and / or an inorganic hole transport layer.

3. The single-sided passivation preparation method according to claim 2, characterized in that, The transparent conductive layer is made of one or more of ITO, IZO, ICO, IWO, FTO, AZO, NTO, and GZO; the inorganic hole transport layer is a NiOx layer.

4. The single-sided passivation preparation method according to claim 1, characterized in that, At least one functional layer includes an interface modification layer, a perovskite light-absorbing layer, and an electron transport layer arranged sequentially in a direction away from the conductive layer.

5. The single-sided passivation preparation method according to claim 4, characterized in that, The interface modification layer and the perovskite light-absorbing layer can be prepared by a patterning process to avoid the annular blank area, or by a full coating process to cover the front area of ​​the silicon wafer, including the annular blank area. The electron transport layer is prepared using a full-area vapor deposition process, covering the front area of ​​the silicon wafer, including the annular blank area.

6. The single-sided passivation preparation method according to claim 1, characterized in that, The passivation layer is deposited using atomic layer deposition (ALD) technology, and the material of the passivation layer is selected from Al2O3 and SiN. x One or more of SnO2.

7. The single-sided passivation preparation method according to claim 1, characterized in that, The width of the cut is less than or equal to the width of the annular blank area, and the cutting depth is not less than the thickness of the silicon wafer.

8. The single-sided passivation preparation method according to claim 1, characterized in that, The width of the annular blank area is 0~50μm.

9. The method for preparing single-sided passivation according to any one of claims 1 to 8, characterized in that, The silicon wafer is a 210mm textured half-crystal silicon wafer.

10. A stacked battery, characterized in that, include: A silicon wafer body having a front side, a back side, and an edge side surrounding the silicon wafer body; An insulation dead zone is provided at the edge of the silicon wafer body; A functional layer structure is disposed on the front side of the silicon wafer body. The functional layer structure includes a conductive layer, at least one functional layer, and a passivation layer disposed sequentially along a direction away from the front side of the silicon wafer body. Wherein, the outer edge of the conductive layer is aligned with the inner edge of the insulating dead zone, the passivation layer covers the front side of the silicon wafer body and the surface of the insulating dead zone, and the passivation layer is interrupted at the insulating dead zone.

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