A p-type positive junction heterojunction solar cell and a preparation method thereof

Abstract

This invention relates to the field of solar cell technology and discloses a p-type positive junction heterojunction solar cell and its fabrication method. The cell structure includes: a p-type silicon wafer with opposing light-receiving and back-lighting surfaces; a first intrinsic amorphous silicon passivation layer and a second intrinsic amorphous silicon passivation layer, respectively disposed on the light-receiving and back-lighting surfaces of the p-type silicon wafer; a first doped layer disposed on the first intrinsic amorphous silicon passivation layer, forming a PN junction with the p-type silicon wafer; a second doped layer disposed on the second intrinsic amorphous silicon passivation layer, forming a back surface field structure; a first conductive film layer disposed on the first doped layer; a second conductive film layer disposed on the second doped layer; a first electrode disposed on the first conductive film layer; and a second electrode disposed on the second conductive film layer. This invention employs a p-type positive junction structure, which can shorten the carrier collection path and improve radiation resistance stability, making it suitable for aerospace missions operating in high-radiation environments for extended periods.

Description

Technical Field

[0001] This invention relates to the field of solar cell technology, and more specifically, to a p-type positive junction heterojunction solar cell suitable for space or ground applications and its fabrication method. Background Technology

[0002] Currently, most mainstream high-efficiency heterojunction solar cells (HJTs) use n-type silicon wafers as the light-absorbing layer, with amorphous silicon thin films deposited on both sides for surface passivation. A heterojunction is then formed and the surface electric field is enhanced by depositing intrinsic amorphous silicon and nanocrystalline silicon thin films of different conductivity types. However, in the field of space photovoltaic applications, this structural approach has the following significant drawbacks: Disadvantage 1: Wide resistivity distribution and inconsistent performance. Due to the low solid solubility of n-type dopants (such as phosphorus) in silicon, the resistivity distribution of n-type silicon wafers is wide (usually dispersed above ±30%), which leads to poor consistency in key parameters such as cell efficiency and open-circuit voltage, affecting the performance and yield of subsequent photovoltaic modules.

[0003] Disadvantage 2: Poor radiation resistance. In space applications such as Low Earth Orbit (LEO), satellites are continuously exposed to high-energy electron radiation (1 MeV electron radiation dose can reach 10). 15 cm -2 (On the order of magnitude). Traditional n-type heterojunction solar cells are prone to efficiency degradation under this environment, and the degradation is difficult to recover. More seriously, under ultra-high radiation accumulation, n-type silicon may even experience a fatal morphological inversion—its electrical properties change from n-type to p-type, causing the PN junction based on the n-type design to fail, and the entire cell function to collapse.

[0004] Disadvantage 3: Insufficient carrier collection efficiency. Traditional n-type HJTs mostly use a back-junction structure (PN junction located on the back surface). After short-wavelength photogenerated carriers are generated near the light-receiving surface, they need to pass through a relatively thick silicon substrate before they can be collected by the PN junction. Under space irradiation, irradiation defects generated in the silicon substrate will significantly increase the carrier recombination probability, reducing short-wavelength response and overall efficiency.

[0005] To address the above shortcomings, existing technologies typically employ the following solutions, but these solutions still have problems.

[0006] Option 1: Triple-junction gallium arsenide (GaInP / GaAs / Ge) solar cells. Triple-junction gallium arsenide (GaInP / GaAs / Ge) solar cells are currently the mainstream solution for space photovoltaics, with initial efficiencies exceeding 30% and excellent radiation resistance. However, their cost is extremely high (approximately 10-50 times that of crystalline silicon solar cells), and their production capacity is limited, making it difficult to meet the needs of large-scale deployment of low-Earth orbit satellite constellations.

[0007] Option 2: n-type HJT cells. n-type HJT cells have achieved efficiencies exceeding 26.5% in the ground-mounted photovoltaic market, but their radiation resistance is relatively poor. Experimental data shows that after 1 MeV electron irradiation (flux of 10... 15 cm -2 After that, the efficiency degradation rate of n-type HJT batteries can reach 25%-35%, and the self-healing rate is only 60%-70%, which cannot meet the requirements of long-term operation in space.

[0008] Option 3: Traditional p-type PERC cells. Traditional p-type PERC cells have low cost and better radiation resistance than n-type cells, but their efficiency ceiling is limited (mass production efficiency is about 23%), and they suffer from light-induced degradation (LID) and insufficient specific power (W / kg), making it difficult to meet the lightweight requirements of space applications.

[0009] Furthermore, in terms of fabrication processes, to meet the lightweight requirements of space applications, the silicon wafer thickness of heterojunction solar cells typically needs to be reduced to 50-70µm. However, under conventional high-temperature, long-duration tubular phosphorus getter processes, ultrathin silicon wafers are highly susceptible to warping or even severe fragmentation due to uneven thermal stress. Simultaneously, to balance the light-trapping requirements of the light-receiving side and the reflection / electrode contact requirements of the back-lighting side, ultrathin silicon wafers require an asymmetric surface structure with a textured light-receiving side and a polished back-lighting side. In existing technologies, a dense protective layer is typically pre-grown on the back-lighting side using chemical vapor deposition or physical masking, and then removed by wet etching after texturing the light-receiving side. This traditional single-sided texturing process is cumbersome, consumes a large amount of auxiliary materials, and has high production costs. Moreover, the multiple deposition and elution processes further increase the fragmentation probability of 50-70µm ultrathin silicon wafers, making large-scale mass production difficult. Summary of the Invention

[0010] The purpose of this invention is to address the technical problems of existing heterojunction solar cells, such as poor radiation resistance, wide resistivity distribution, insufficient carrier collection efficiency, and cumbersome processes and high fragmentation rates in the fabrication of asymmetric surface structures using ultrathin silicon wafers. This invention provides a p-type positive junction heterojunction solar cell and its fabrication method. To achieve the above objective, this invention adopts the following technical solution: A p-type positive junction heterojunction solar cell includes: p-type silicon wafers have opposing light-receiving and back-light-receiving surfaces; The first intrinsic amorphous silicon passivation layer and the second intrinsic amorphous silicon passivation layer are respectively disposed on the light-receiving surface and the backlight surface of the p-type silicon wafer; A first doped layer is disposed on the first intrinsic amorphous silicon passivation layer, and the first doped layer forms a PN junction with the p-type silicon wafer; The second doped layer is disposed on the second intrinsic amorphous silicon passivation layer, and the second doped layer forms a back surface field structure. Both the first doped layer and the second doped layer are hybrid structures of doped amorphous silicon and nanocrystalline silicon. A first conductive film layer is disposed on the first doped layer; A second conductive film layer is disposed on the second doped layer; The first electrode is disposed on the first conductive film layer; The second electrode is disposed on the second conductive film layer.

[0011] Preferably, the thickness of the p-type silicon wafer is 50-70µm, and the p-type silicon wafer is a boron-doped or gallium-doped p-type single crystal silicon wafer.

[0012] Preferably, the light-receiving surface of the p-type silicon wafer has a textured structure with a textured size of 0.5-3µm; the backlighting surface of the p-type silicon wafer has a polished structure; and an asymmetrical surface structure with a textured light-receiving surface and a polished backlighting surface is formed on the p-type silicon wafer.

[0013] Preferably, the thickness of the first intrinsic amorphous silicon passivation layer and the second intrinsic amorphous silicon passivation layer is 8-12 nm; the content of nanocrystalline silicon in the first doped layer and the second doped layer is 40% to 60%; and the doping concentration of the first doped layer is 5 × 10⁻⁶. 19 cm -3 Up to 1.5×10 20 cm -3 The doping concentration of the second doped layer is 1×10⁻⁶. 19 cm -3 Up to 3×10 19 cm -3 .

[0014] Preferably, the first conductive film layer is an ITO layer with a thickness of 80-120 nm; the second conductive film layer is an AZO layer or an ITO / AZO stacked structure with a thickness of 130-220 nm.

[0015] Preferably, the first electrode and the second electrode are silver paste layers or silver-coated copper paste cured layers.

[0016] A method for fabricating a p-type positive junction heterojunction solar cell includes the following steps: S1: Pre-clean the p-type silicon wafer; S2: The p-type silicon wafer is cleaned using a chain phosphorus gettering process, coated with a phosphorus source on both sides, and treated at 700-900℃ for 1-5 minutes to form a phosphorus-silicon glass layer in situ on the light-receiving and back-light-receiving surfaces of the p-type silicon wafer. S3: First, remove the phosphorus silicate glass layer formed after phosphorus gettering on the light-receiving surface, then perform texturing on the light-receiving surface. The phosphorus silicate glass layer on the back-lighting surface is retained during the texturing process on the light-receiving surface. During the final cleaning, the phosphorus silicate glass layer formed after phosphorus gettering on the back-lighting surface is removed simultaneously, forming an asymmetrical surface structure with a textured light-receiving surface and a polished back-lighting surface. S4: After texturing, the first intrinsic amorphous silicon passivation layer and the second intrinsic amorphous silicon passivation layer are deposited sequentially on the p-type silicon wafer. S5: Deposit the first doped layer on the light-receiving surface and deposit the second doped layer on the back-lighting surface; S6: Deposit the first conductive film layer and the second conductive film layer; S7: Print the paste for the first and second electrodes and cure it; S8: Light injection processing.

[0017] Preferably, in step S2, the phosphorus source is selected from at least one of phospho-based polycarboxylic acid, phosphate ester, organophosphorus compound, or phosphorus-containing spin-coating glass source; the coating method is double-sided roller coating.

[0018] Preferably, in step S2, the inlet and outlet of the getter furnace are isolated with nitrogen, and oxygen or filtered compressed air is introduced into the furnace. The transfer speed of the p-type silicon wafer is 3.0-5.0 m / min.

[0019] Preferably, in step S3, after texturing the light-receiving surface, a mixed solution of hydrofluoric acid and ozone is used to clean it at room temperature for 2-3 minutes.

[0020] Compared with the prior art, the present invention provides a p-type positive junction heterojunction solar cell, which has at least the following beneficial effects: Narrow resistivity distribution and good performance consistency. Using p-type silicon wafers, where the p-type dopant (boron) has high solid solubility in silicon, allows for more precise control of the silicon wafer resistivity (dispersion can be controlled within ±10%), resulting in a more concentrated distribution of cell efficiency, which is beneficial for improving module output power and reliability. This solves the problem in existing technologies where the n-type dopant (phosphorus) has low solid solubility in silicon, leading to a wide resistivity distribution (dispersion of over ±30%) in n-type silicon wafers and poor consistency of cell parameters.

[0021] It exhibits excellent radiation resistance and self-healing capability. Using p-type silicon wafers as the light-absorbing layer, the p-type heterojunction solar cell achieves a self-healing rate of over 97% after low-Earth orbit electron irradiation. Defects in p-type silicon have a weaker ability to trap minority carriers, resulting in a higher minority carrier lifetime retention rate after irradiation, making it suitable for long-term operation in high-irradiation environments in aerospace missions. This technology solves the problem of existing n-type HJT cells failing under 1MeV electron irradiation (10... 15 cm -2After that, the efficiency decreases by 25%-35%, and the self-healing rate is only 60%-70%. More seriously, n-type silicon may undergo morphological inversion under ultra-high flux radiation, leading to PN junction failure.

[0022] Optimized short-wavelength carrier collection using a positive junction structure. A positive junction structure (n...) is employed. + The doped layer is located on the front light-receiving side, forming a PN junction with the p-type silicon substrate. Short-wavelength photogenerated carriers, generated near the light-receiving surface, can be rapidly collected by the front PN junction, resulting in a short carrier collection path and significantly reducing the probability of recombination in irradiation defects. Combined with an ultra-thin silicon wafer (50-70μm), the carrier transport distance is further shortened, improving efficiency retention under space irradiation. This solves the problem that traditional n-type HJTs, which often employ a back-junction structure, require short-wavelength photogenerated carriers to pass through a thicker silicon substrate for collection, leading to severe recombination losses under irradiation.

[0023] Double-sided passivation structure reduces recombination losses. Intrinsic amorphous silicon passivation layers (ia-Si:H) are deposited on both sides of the p-type silicon wafer. Utilizing the hydrogen-saturated silicon dangling bonds within these layers, the interface state density and surface recombination rate are significantly reduced, thereby improving open-circuit voltage and overall conversion efficiency. This solves the problem of high surface recombination rates and significant carrier loss at the surface in traditional battery structures.

[0024] A hybrid amorphous / nanocrystalline silicon layer enhances the electric field. The doped layer employs a hybrid structure of amorphous and nanocrystalline silicon. The introduction of nanocrystalline silicon improves the conductivity and carrier mobility of the doped layer while maintaining good surface passivation, thus balancing passivation quality and conductivity. This solves the problem of insufficient conductivity in traditional pure amorphous silicon doped layers, which affects carrier transport efficiency.

[0025] An asymmetric conductive film (TCO) structure optimizes photoelectric performance. The TCO on the light-receiving side uses ITO (preferably no larger than 100nm) to prioritize light transmittance; the TCO on the backlight side uses AZO or an ITO / AZO stack (150-200nm) to emphasize conductivity. This asymmetric structure satisfies the requirements of high light transmittance on the light-receiving side and high conductivity on the backlight side, achieving a better balance in photoelectric performance. This solves the problem that existing symmetrical TCO designs in batteries cannot simultaneously optimize the light transmittance of the light-receiving side and the conductivity of the backlight side.

[0026] The ultra-thin structure meets the lightweight requirements of space applications. The thickness of the p-type silicon wafer can be controlled between 50-70μm, and combined with the shortest carrier collection path of the positive junction structure, it achieves high power specific (413W / kg at a thickness of 60μm) while maintaining high conversion efficiency, thus meeting the lightweight requirements of space photovoltaics. This solves the problem that traditional crystalline silicon cells have excessively thick silicon wafers (typically 150-180μm) and insufficient power specific (W / kg), making it difficult to meet the lightweight requirements of space applications.

[0027] This invention also provides a method for fabricating a p-type positive junction heterojunction solar cell, which has at least the following beneficial effects: Synergistic gettering and asymmetric protection significantly simplify the process flow. In step S2, during gettering, phosphosilicate glass layers are formed in situ on both the light-receiving and back-light-receiving surfaces of the silicon wafer. In step S3, a clever horizontal single-sided wet process is used to remove the phosphosilicate glass layer on only one side, leaving the phosphosilicate glass layer on the back-light-receiving surface as a natural acid-resistant protective layer during texturing of the light-receiving surface. The entire process eliminates the need for additional deposition and removal of auxiliary mask layers such as silica, achieving integrated synergistic manufacturing of gettering, texturing protection, and undercoating polishing. This simplifies the process flow for asymmetric surfaces and saves production costs.

[0028] The chain-type short-time thermal getter process helps reduce the risk of breakage during the processing of ultra-thin silicon wafers. For 50-70µm ultra-thin silicon wafers, a double-sided roller-coated phosphorus source is used in conjunction with a chain-type short-time heat treatment. This extremely short high-temperature process significantly reduces the thermal budget, avoids warping and deformation of the ultra-thin silicon wafers during gettering, and, combined with the horizontal single-sided chain transport in step S3, effectively controls the breakage rate of 50-70µm ultra-thin silicon wafers during production.

[0029] Thermo-optical injection regeneration process stimulates electrical self-healing capability. Step S8 involves placing the cured solar cell in an optical injection device for optical injection treatment, which can passivate crystal defects. Through the synergistic activation of thermal energy and photons, hydrogen atoms in the intrinsic amorphous silicon passivation layer are induced to diffuse into the p-type silicon wafer and passivate deep recombination centers, forming a hydrogen passivation network with radiation-resistant self-healing properties inside the silicon wafer. This results in the finished solar cell exhibiting excellent room-temperature self-healing electrical performance after being exposed to high-energy electron radiation from space.

[0030] The p-type positive junction heterojunction solar cell and its fabrication method described in this invention will have other advantages, objectives and features that will be partly apparent from the following description and partly understood by those skilled in the art through study and practice of the invention. Attached Figure Description

[0031] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of the structure of a p-type positive junction heterojunction solar cell according to the present invention; Figure 2 This is a diagram showing the carrier collection path of a p-type HJT battery with a positive junction structure in this invention. Figure 3 This is a diagram showing the carrier collection path of the p-type HJT battery with a back junction structure in this invention. Figure 4 This is a flowchart illustrating the fabrication process of a p-type positive junction heterojunction solar cell according to the present invention.

[0033] In the figure: 1. p-type silicon wafer; 21. First intrinsic amorphous silicon passivation layer; 22. Second intrinsic amorphous silicon passivation layer; 3. First doped layer; 4. Second doped layer; 51. First conductive film layer; 52. Second conductive film layer; 61. First electrode; 62. Second electrode. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0035] This invention provides a high-efficiency, radiation-resistant p-type positive junction heterojunction solar cell suitable for space or ground applications. For example... Figure 1 As shown, this heterojunction solar cell adopts a forward junction structure, which includes the following layers from the inside out: The central substrate layer of the battery is a p-type silicon wafer 1, which has a light-receiving surface (front) and a back surface (back). A first intrinsic amorphous silicon passivation layer 21 and a second intrinsic amorphous silicon passivation layer 22 for surface passivation are respectively bonded to the light-receiving surface and the back surface of the p-type silicon wafer 1.

[0036] On the light-receiving side, a first doped layer 3 is disposed on the first intrinsic amorphous silicon passivation layer 21. This first doped layer 3 cooperates with the central p-type silicon wafer 1 to form a PN junction near the light-receiving surface of the battery, thereby constituting a positive junction structure. On the backlight side, a second doped layer 4 is disposed on the second intrinsic amorphous silicon passivation layer 22 to form a back surface field (BSF) to enhance the reflection of minority carriers.

[0037] The first doped layer 3 and the second doped layer 4 described above are both hybrid structures of doped amorphous silicon and nanocrystalline silicon. A first conductive film layer 51 and a second conductive film layer 52 are respectively formed on the first doped layer 3 and the second doped layer 4. A first electrode 61 is formed on the first conductive film layer 51, and a second electrode 62 is formed on the second conductive film layer 52.

[0038] The p-type positive junction heterojunction solar cell provided by this invention has the following specific design for each layer: The p-type silicon wafer 1 is a boron-doped or gallium-doped p-type single-crystal silicon wafer. Its resistivity is 0.2-6 Ω·cm, preferably controlled within 0.4-1.1 Ω·cm. Its thickness is 40-120 μm, and for space applications, the thickness of the p-type silicon wafer 1 is further preferably 50-70 μm. Compared to the wider resistivity distribution of traditional n-type silicon wafers, p-type dopants (such as boron) have high solid solubility in silicon, allowing for more precise resistivity control and better consistency in battery performance. The minority carriers (electrons) in the p-type silicon wafer 1 are less sensitive to radiation-induced defects, maintaining a higher minority carrier lifetime after irradiation, laying the physical foundation for radiation resistance.

[0039] The light-receiving surface of the p-type silicon wafer 1 has a textured structure with a texture size of 0.5-3µm, preferably 1-2µm. The texture size refers to the average bottom side length of the micro / nano textured pyramid structure on the light-receiving surface as observed by a scanning electron microscope or an atomic force microscope. The backlighting surface of the p-type silicon wafer 1 has a polished structure. An asymmetric surface structure with a textured light-receiving surface and a polished backlighting surface is formed on the p-type silicon wafer 1.

[0040] The thickness of the first intrinsic amorphous silicon passivation layer 21 and the second intrinsic amorphous silicon passivation layer 22 is 5–15 nm, preferably 8–12 nm. They are deposited on the light-receiving and back-light-receiving surfaces of the p-type silicon wafer 1, respectively, for surface passivation and to reduce the surface recombination rate. The hydrogen atoms in the double-sided passivation layers can effectively saturate silicon dangling bonds, significantly reducing the interface state density and surface recombination rate.

[0041] Both the first doped layer 3 and the second doped layer 4 are hybrid structures of doped amorphous silicon and nanocrystalline silicon. The first doped layer 3 is set to n + Type-doped amorphous and nanocrystalline silicon hybrid layer (n + The second doped layer 4 is set to p-type doped layer 4. + Type-doped amorphous and nanocrystalline silicon hybrid layer (n + The first doped layer 3 has a doping concentration of 40% to 60%. The introduction of nanocrystalline silicon improves the conductivity and carrier mobility of the doped layer while maintaining good surface passivation. 19 cm -3 Up to 2×10 20 cm -3 Preferably 5×10 19 cm -3 Up to 1.5×10 20 cm -3 The doping concentration of the second doped layer 4 is 5 × 10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 Preferably 1×1019 cm -3 Up to 3×10 19 cm -3 The thickness of the first doped layer 3 and the second doped layer 4 is 5-25 nm.

[0042] The first conductive film layer 51 is an ITO layer with a thickness of 80-120 nm, preferably no more than 100 nm, prioritizing front-side light transmittance; the second conductive film layer 52 is preferably an AZO layer or an ITO / AZO stacked structure with a thickness of 130-220 nm, preferably 150-200 nm, emphasizing back-side conductivity. This asymmetric structure achieves a better balance of photoelectric performance.

[0043] The first electrode 61 and the second electrode 62 are each independently selected from either a low-temperature silver paste layer or a silver-coated copper paste curing layer.

[0044] like Figure 4 As shown, the present invention also provides a method for fabricating the p-type positive junction heterojunction solar cell, comprising the following steps: S1: Pre-clean the p-type silicon wafer 1.

[0045] The boron-doped or gallium-doped p-type single-crystal silicon wafer 1, which serves as the substrate, is placed into a cleaning tank for chemical cleaning. The cleaning water can be deionized water, hydrofluoric acid solution, or ozone water to remove impurities and surface oxide layers from the silicon wafer surface.

[0046] S2: The p-type silicon wafer 1 is cleaned using a chain-type phosphorus gettering process, coated with a phosphorus source on both sides, and treated at 700-900℃ for 1-5 minutes to form a phosphorus-silicon glass layer in situ on the light-receiving and back-light-receiving surfaces of the p-type silicon wafer 1.

[0047] In step S2, the phosphorus source is selected from at least one of phospho-based polycarboxylic acid, phosphate ester, organophosphorus compound, or phosphorus-containing spin-coated glass source.

[0048] In terms of process, a getter phosphorus source solution is first prepared, for example, by using deionized water or anhydrous ethanol to prepare the phosphorus source solution. The getter phosphorus source solution is then coated onto the light-receiving surface and the back-light-receiving surface of the p-type monocrystalline silicon wafer 1 using a double-sided roller coating method, with a total coating amount of 15-30 mg on both sides.

[0049] After coating, the silicon wafer is fed into a chain getter furnace. The furnace inlet and outlet are isolated with nitrogen, and oxygen or filtered compressed air is introduced into the furnace. The conveying speed of the p-type silicon wafer 1 is controlled at 3.0-5.0 m / min, and it is heat-treated at 700-900℃ for 1-5 minutes to form a phosphosilicate glass layer in situ on the light-receiving and back-light-receiving surfaces of the p-type silicon wafer 1, and to allow metallic impurities inside the silicon wafer to diffuse into the phosphosilicate glass layer.

[0050] S3: First, remove the phosphorus silicate glass layer formed after phosphorus gettering on the light-receiving surface, then perform texturing on the light-receiving surface. The phosphorus silicate glass layer on the back-lighting surface is retained during the texturing process on the light-receiving surface. During the final cleaning, the phosphorus silicate glass layer formed after phosphorus gettering on the back-lighting surface is removed simultaneously, forming an asymmetrical surface structure with a textured light-receiving surface and a polished back-lighting surface.

[0051] In step S3, the phosphosilicate glass layer formed after phosphorus gettering on the light-receiving side is removed first. This removal can be performed using a horizontal chain-type single-sided wet process: the p-type silicon wafer 1 is placed horizontally on the conveyor rollers of the equipment, with the light-receiving side facing down and the back-lighting side facing up, protected by a water film. The light-receiving side of the p-type silicon wafer 1 is brought into contact with the rollers containing hydrofluoric acid solution in the process tank. The surface tension of the liquid controls the diffusion of the hydrofluoric acid solution to the entire light-receiving side. The reaction lasts for 30-90 seconds to remove the phosphosilicate glass layer on the light-receiving side, while the phosphosilicate glass layer on the back-lighting side remains intact as it does not come into contact with the hydrofluoric acid solution during the reaction on the light-receiving side.

[0052] The light-receiving surface is then texturized to form a textured structure with a size of 0.5-3µm (preferably 1-2µm). During this process, a phosphosilicate glass layer exists on the backlighting surface, which prevents the backlighting surface from being eroded by the texturizing solution.

[0053] After texturing the light-receiving surface, a mixed solution of hydrofluoric acid and ozone is used to smooth the textured surface. The surface is then cleaned at room temperature for 2-3 minutes, removing the phosphosilicate glass layer formed after phosphorus gettering on the back-lighting surface. After final cleaning and drying, the resulting p-type silicon wafer 1 possesses an asymmetric surface structure with a textured light-receiving surface and a polished back-lighting surface.

[0054] S4: After texturing, deposit the first intrinsic amorphous silicon passivation layer 21 and the second intrinsic amorphous silicon passivation layer 22 on both sides of the p-type silicon wafer 1, respectively.

[0055] The silicon wafer is fed into the reaction chamber of a plasma-enhanced chemical vapor deposition (PECVD) apparatus. At 150-200°C, a first intrinsic amorphous silicon passivation layer 21 with a thickness of 8-12 nm is deposited on the light-receiving surface of the p-type monocrystalline silicon wafer 1, and a second intrinsic amorphous silicon passivation layer 22 with a thickness of 8-12 nm is deposited on the back-light-receiving surface of the p-type monocrystalline silicon wafer 1.

[0056] S5: Deposit the first doped layer 3 on the light-receiving surface and deposit the second doped layer 4 on the back-light-receiving surface.

[0057] On the first intrinsic amorphous silicon passivation layer 21 of the light-receiving surface, silane, hydrogen, and phosphine are introduced and reacted to deposit a doping concentration of 5×10⁻⁶. 19 cm -3 Up to 1.5×10 20 cm -3 n +The first doped layer 3 is a hybrid structure of doped amorphous silicon and nanocrystalline silicon, wherein the content of nanocrystalline silicon is 40% to 60%. The first doped layer 3 forms a PN junction with the p-type silicon wafer 1.

[0058] On the second intrinsic amorphous silicon passivation layer 22 on the backlight surface, silane, hydrogen, and diborane are introduced into the reaction deposition to form a doping concentration of 1×10⁻⁶. 19 cm -3 Up to 3×10 19 cm -3 p + Type 4 second doped layer. The second doped layer 4 is also a mixed structure of doped amorphous silicon and nanocrystalline silicon with a nanocrystalline silicon content of 40% to 60%, used to form a back surface field structure.

[0059] S6: Deposit the first conductive film layer 51 and the second conductive film layer 52.

[0060] Using a physical vapor deposition apparatus, an ITO layer with a thickness of 80-120 nm is deposited on the first doped layer 3 to form a first conductive film layer 51; an AZO layer or an ITO / AZO stack structure with a thickness of 130-220 nm is deposited on the second doped layer 4 to form a second conductive film layer 52.

[0061] S7: Print the paste for the first electrode 61 and the second electrode 62 and cure it.

[0062] The corresponding pastes are printed on the first conductive film layer 51 and the second conductive film layer 52 using a screen printing process. The pastes are selected from low-temperature silver paste or silver-coated copper paste. After printing, the battery cells are placed in a curing oven for curing, for example, baking at 150-200°C for 10-30 minutes to obtain the first electrode 61 and the second electrode 62.

[0063] S8: Light injection processing.

[0064] The cured solar cells are placed in a light injection device for light injection treatment to passivate crystal defects and improve the cell's resistance to radiation degradation. For example, a light source with a wavelength of 350-1100nm and an intensity of 3-80 standard solar radiation intensities is used to perform thermo-photoinjection treatment on the solar cells at 150-230℃ for 1-5 minutes.

[0065] Combination Figure 2 and Figure 3 As shown in the figure, black dots represent photogenerated electrons, white dots represent photogenerated holes, triangular elements represent incident sunlight, and arrowed curves represent the migration paths of charge carriers. Figure 2In the shown positive junction structure, the first doped layer 3 is located on the light-receiving side, and the photogenerated electrons excited by incident sunlight are collected at the interface near the first conductive film layer 51; while as Figure 3 In the contrasting back structure shown, the first doped layer 3 is placed on the bottom backlight side, which causes the photogenerated electron primitives to have to longitudinally span the entire thickness of the p-type silicon wafer 1 before they can be collected by the first electrode 61. In this process, the probability of collision recombination with lattice defects is increased.

[0066] This invention employs a positive junction structure (with the first doped layer 3 located on the light-receiving side). Short-wavelength photogenerated carriers, after being generated near the light-receiving surface, can be rapidly collected by the PN junction on the light-receiving surface, resulting in an extremely short carrier collection path. In high-irradiation environments such as space, silicon substrates generate numerous irradiation defects. The combination of the positive junction structure and the ultra-thin p-type silicon wafer further shortens the carrier transport distance, thereby significantly reducing the probability of carriers being trapped and recombinating in irradiation defects and greatly improving efficiency retention.

[0067] To verify the beneficial effects of the above-described structure of the present invention, the following embodiments and comparative examples are provided for illustration.

[0068] Example 1: p-type positive junction heterojunction solar cell suitable for space environment A 60μm thick gallium-doped p-type single-crystal silicon wafer with a resistivity of 0.8Ω·cm is used. The first and second intrinsic amorphous silicon passivation layers are both 10nm thick. The first doped layer is 20nm thick (50% nanocrystalline silicon content), and the second doped layer is 25nm thick. The first conductive film layer on the front side is a 100nm ITO layer, and the second conductive film layer on the back side is a 180nm AZO layer. The electrodes are printed using low-temperature silver-coated copper paste.

[0069] The battery performance test results under AM0 spectrum are as follows: initial conversion efficiency 24.8%, open circuit voltage 735mV, short circuit current density 39.2mA / cm², fill factor 81.5%, and specific power 413W / kg.

[0070] Example 2: p-type positive junction heterojunction solar cell suitable for terrestrial applications The basic structure is the same as in Example 1, except that a 120μm thick p-type silicon wafer is used; and the doping concentration of the first doped layer is 1×10⁻⁶. 20 cm -3 The second conductive film layer on the back is a 200nm ITO / AZO stacked structure.

[0071] The battery performance test results under AM1.5G spectrum are as follows: initial conversion efficiency 25.2%, open circuit voltage 740mV, short circuit current density 39.8mA / cm², fill factor 82.0%, and short-wave response (400nm) EQE 85%.

[0072] Comparative Example 1: Traditional n-type HJT battery (back junction structure) A phosphorus-doped n-type single crystal silicon wafer with a thickness of 120 μm and a resistivity of 1.5 Ω·cm was used. A back junction structure was adopted, and the remaining film layer structure was similar to that in Example 1.

[0073] The AM1.5G battery performance test results are as follows: initial conversion efficiency 25.5%, open-circuit voltage 742mV, and short-circuit current density 40.1mA / cm². 2 The fill factor is 82.3%.

[0074] Comparative Example 2: p-type back junction heterojunction solar cell The battery structure parameters are the same as in Example 2, except that the forward junction structure of the present invention is replaced with a back junction structure (p + On the front surface, n + (On the back).

[0075] The AM1.5G battery performance test results are as follows: initial conversion efficiency 24.5%, short-circuit current density 38.5 mA / cm². 2 Shortwave response (400nm) EQE 78%.

[0076] In addition, 1MeV electrons were also performed with a flux of 10. 15 cm -2 Radiation resistance tests were conducted. The comparison of radiation resistance and carrier collection performance between the above embodiments and the comparative structures (results) is shown in Table 1.

[0077] Table 1: Comparison of radiation resistance and carrier collection performance (Results of examples and comparative examples) Experiments show that the initial conversion efficiency of the n-type HJT in Comparative Example 1 (25.5%) is slightly higher than that in Example 1 (24.8%), but its radiation resistance is significantly worse than that of the p-type positive junction HJT in Example 1. After irradiation, the efficiency retention rate of the p-type positive junction HJT in Example 1 (92%) is far superior to that of the n-type HJT (72%), and its self-healing rate can reach 97%, which can meet the requirements for long-term operation in space. Here, efficiency retention rate = 1 - efficiency decay rate.

[0078] Compared with the p-type back junction structure of Comparative Example 2, the p-type positive junction structure of Example 2 has a 3.3% increase in short-circuit current density and a 7 percentage point increase in short-wavelength response (400nm) EQE, demonstrating that the p-type positive junction structure of Example 2 has a significant advantage in short-wavelength carrier collection.

[0079] In addition, p-type positive junction HJT cell structures with different silicon wafer thicknesses (Structure of Example 2) were tested, and the cell performance test results are shown in Table 2.

[0080] Table 2 Comparison of battery performance test results for different silicon wafer thicknesses As shown in Table 2, under the positive junction structure of the present invention, when the silicon wafer thickness is controlled at 50-70μm, the carrier transport distance is shorter, the irradiation defect capture probability is lower, the efficiency retention rate can reach 92%-93%, and the specific power jumps significantly to over 400W / kg, which is suitable for the lightweight requirements of space photovoltaics.

[0081] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A p-type positive junction heterojunction solar cell, characterized by, include: p-type silicon wafer (1) has a light-receiving surface and a back-lighting surface; The first intrinsic amorphous silicon passivation layer (21) and the second intrinsic amorphous silicon passivation layer (22) are respectively disposed on the light-receiving surface and the backlight surface of the p-type silicon wafer (1); The first doped layer (3) is disposed on the first intrinsic amorphous silicon passivation layer (21), and the first doped layer (3) forms a PN junction with the p-type silicon wafer (1); The second doped layer (4) is disposed on the second intrinsic amorphous silicon passivation layer (22). The second doped layer (4) forms a back surface field structure. The first doped layer (3) and the second doped layer (4) are both mixed structures of doped amorphous silicon and nanocrystalline silicon. The first conductive film layer (51) is disposed on the first doped layer (3); The second conductive film layer (52) is disposed on the second doped layer (4); The first electrode (61) is disposed on the first conductive film layer (51); The second electrode (62) is disposed on the second conductive film layer (52).

2. A p-type positive junction heterojunction solar cell according to claim 1, characterized in that, The thickness of the p-type silicon wafer (1) is 50-70µm, and the p-type silicon wafer (1) is a boron-doped or gallium-doped p-type single crystal silicon wafer.

3. A p-type positive junction heterojunction solar cell according to claim 1, characterized in that, The light-receiving surface of the p-type silicon wafer (1) has a textured surface structure; the backlighting surface of the p-type silicon wafer (1) has a polished surface structure; and an asymmetrical surface structure with a textured light-receiving surface and a polished backlighting surface is formed on the p-type silicon wafer (1).

4. A p-type positive junction heterojunction solar cell according to claim 1, characterized in that, The thickness of the first intrinsic amorphous silicon passivation layer (21) and the second intrinsic amorphous silicon passivation layer (22) is 8-12 nm; the content of nanocrystalline silicon in the first doped layer (3) and the second doped layer (4) is 40% to 60%; the doping concentration of the first doped layer (3) is 5 × 10⁻⁶. 19 cm -3 Up to 1.5×10 20 cm -3 The doping concentration of the second doped layer (4) is 1×10⁻⁶. 19 cm -3 Up to 3×10 19 cm -3 .

5. A p-type positive junction heterojunction solar cell according to claim 1, characterized in that, The first conductive film layer (51) is an ITO layer with a thickness of 80-120nm; the second conductive film layer (52) is an AZO layer or an ITO / AZO stacked structure with a thickness of 130-220nm.

6. A p-type positive junction heterojunction solar cell according to claim 1, characterized in that, The first electrode (61) and the second electrode (62) are silver paste layers or silver-coated copper paste cured layers.

7. A method for fabricating a p-type positive junction heterojunction solar cell as described in any one of claims 1-6, characterized in that, Includes the following steps: S1: Pre-clean the p-type silicon wafer (1); S2: The p-type silicon wafer (1) after cleaning is treated by a chain phosphorus gettering process, and a phosphorus source is coated on both sides. It is then treated at 700-900℃ for 1-5 minutes to form a phosphorus-silicon glass layer in situ on the light-receiving surface and the back-lighting surface of the p-type silicon wafer (1). S3: First, remove the phosphorus silicate glass layer formed after phosphorus gettering on the light-receiving surface, then perform texturing on the light-receiving surface. The phosphorus silicate glass layer on the back-lighting surface is retained during the texturing process on the light-receiving surface. During the final cleaning, the phosphorus silicate glass layer formed after phosphorus gettering on the back-lighting surface is removed simultaneously, forming an asymmetrical surface structure with a textured light-receiving surface and a polished back-lighting surface. S4: Deposit the first intrinsic amorphous silicon passivation layer (21) and the second intrinsic amorphous silicon passivation layer (22) on both sides of the texturized p-type silicon wafer (1). S5: Deposit the first doped layer (3) on the light-receiving surface and deposit the second doped layer (4) on the back-light-receiving surface. S6: Deposit the first conductive film layer (51) and the second conductive film layer (52); S7: Print the paste for the first electrode (61) and the second electrode (62) and cure it; S8: Light injection processing.

8. The method for fabricating a p-type positive junction heterojunction solar cell according to claim 7, characterized in that, In step S2, the phosphorus source is selected from at least one of phospho-based polycarboxylic acid, phosphate ester, organophosphorus compound, or phosphorus-containing spin-coating glass source; the coating method is double-sided roller coating.

9. The method for fabricating a p-type positive junction heterojunction solar cell according to claim 7, characterized in that, In step S2, the inlet and outlet of the getter furnace are isolated with nitrogen, and oxygen or filtered compressed air is introduced into the furnace. The silicon wafer is transported at a speed of 3.0-5.0 m / min.

10. The method for fabricating a p-type positive junction heterojunction solar cell according to claim 7, characterized in that, In step S3, after texturing the light-receiving surface, it is cleaned for 2-3 minutes at room temperature using a mixed solution of hydrofluoric acid and ozone.

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